PIC24H PIC24HJ64GP206 PIC24HJ64GP210 PIC24HJ64GP506 PIC24HJ64GP510 - Datasheet Archive

 

dsPIC33F/PIC24H Flash Programming Specification 1.0 DEVICE OVERVIEW This document defines the programming specification for the

 

dsPIC33F/PIC24H dsPIC33F/PIC24H Flash Programming Specification 1.0 DEVICE OVERVIEW This document defines the programming specification for the dsPIC33F 16-bit Digital Signal Controller (DSC) and PIC24H PIC24H 16-bit Microcontroller (MCU) families. This programming specification is required only for those developing programming support for the dsPIC33F/ PIC24H PIC24H family. Customers only using one of these devices should use development tools that already provide support for device programming. This document includes programming specifications for the following devices: · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · dsPIC33FJ64GP206 dsPIC33FJ64GP306 dsPIC33FJ64GP310 dsPIC33FJ64GP706 dsPIC33FJ64GP708 dsPIC33FJ64GP710 dsPIC33FJ128GP206 dsPIC33FJ128GP306 dsPIC33FJ128GP310 dsPIC33FJ128GP706 dsPIC33FJ128GP708 dsPIC33FJ128GP710 dsPIC33FJ256GP506 dsPIC33FJ256GP510 dsPIC33FJ256GP710 dsPIC33FJ64MC506 dsPIC33FJ64MC508 dsPIC33FJ64MC510 dsPIC33FJ64MC706 dsPIC33FJ64MC710 dsPIC33FJ128MC506 dsPIC33FJ128MC510 dsPIC33FJ128MC706 dsPIC33FJ128MC708 dsPIC33FJ128MC710 dsPIC33FJ256MC510 dsPIC33FJ256MC710 PIC24HJ64GP206 PIC24HJ64GP206 PIC24HJ64GP210 PIC24HJ64GP210 PIC24HJ64GP506 PIC24HJ64GP506 PIC24HJ64GP510 PIC24HJ64GP510 PIC24HJ128GP206 PIC24HJ128GP206 PIC24HJ128GP210 PIC24HJ128GP210 © 2007 Microchip Technology Inc. · · · · · · · · · · · · · PIC24HJ128GP306 PIC24HJ128GP306 PIC24HJ128GP310 PIC24HJ128GP310 PIC24HJ128GP506 PIC24HJ128GP506 PIC24HJ128GP510 PIC24HJ128GP510 PIC24HJ256GP206 PIC24HJ256GP206 PIC24HJ256GP210 PIC24HJ256GP210 PIC24HJ256GP610 PIC24HJ256GP610 dsPIC33FJ12GP201 dsPIC33FJ12GP202 dsPIC33FJ12MC201 dsPIC33FJ12MC202 PIC24HJ12GP201 PIC24HJ12GP201 PIC24HJ12GP202 PIC24HJ12GP202 2.0 PROGRAMMING OVERVIEW OF THE dsPIC33F/PIC24H There are two methods of programming the dsPIC33F/ PIC24H PIC24H family of devices discussed in this programming specification. They are: · In-Circuit Serial ProgrammingTM (ICSPTM) programming capability · Enhanced In-Circuit Serial Programming The ICSP programming method is the most direct method to program the device; however, it is also the slower of the two methods. It provides native, low-level programming capability to erase, program and verify the chip. The Enhanced ICSP protocol uses a faster method that takes advantage of the programming executive, as illustrated in Figure 2-1. The programming executive provides all the necessary functionality to erase, program and verify the chip through a small command set. The command set allows the programmer to program the dsPIC33F/PIC24H Programming Specification devices without having to deal with the low-level programming protocols of the chip. Preliminary DS70152D-page 1 dsPIC33F/PIC24H PROGRAMMING SPECIFICATION FIGURE 2-1: PROGRAMMING SYSTEM OVERVIEW FOR ENHANCED ICSPTM FIGURE 2-2: 3.3V dsPIC33F/PIC24H Programmer CONNECTIONS FOR THE ON-CHIP REGULATOR dsPIC33F/PIC24H Programming Executive VDD VDDCORE CF VSS On-Chip Memory Note 1: This specification is divided into major sections that describe the programming methods independently. Section 3.0 "Device Programming ­ Enhanced ICSP" describes the Enhanced ICSP method. Section 5.0 "Device Programming ­ ICSP" describes the ICSP method. 2.1 Power Requirements All devices in the dsPIC33F/PIC24H family are dual voltage supply designs: one supply for the core and another for the peripherals and I/O pins. A regulator is provided on-chip to alleviate the need for two external voltage supplies. All of the dsPIC33F/PIC24H devices power their core digital logic at a nominal 2.5V. To simplify system design, all devices in the dsPIC33F/PIC24H Programming Specification family incorporate an on-chip regulator that allows the device to run its core logic from VDD. 2.2 Program Memory Write/Erase Requirements The program Flash memory on the dsPIC33F/PIC24H has a specific write/erase requirement that must be adhered to for proper device operation. The rule is that any given word in memory must not be written without first erasing the page in which it is located. Thus, the easiest way to conform to this rule is to write all the data in a programming block within one write cycle. The programming methods specified in this document comply with this requirement. Note: The regulator provides power to the core from the other VDD pins. A low-ESR capacitor (such as tantalum) must be connected to the VDDCORE pin (Figure 2-2). This helps to maintain the stability of the regulator. The specifications for core voltage and capacitance are listed in Section TABLE 8-1: "AC/DC Characteristics and Timing Requirements". DS70152D-page 2 These are typical operating voltages. Refer to Section TABLE 8-1: "AC/DC Characteristics and Timing Requirements" for the full operating ranges of VDD and Preliminary A program memory word can be programmed twice before an erase, but only if (a) the same data is used in both program operations or (b) bits containing `1' are set to `0' but no `0' is set to `1'. © 2007 Microchip Technology Inc. dsPIC33F/PIC24H PROGRAMMING SPECIFICATION 2.3 Pin Diagrams The pin diagrams for the dsPIC33F/PIC24H device family are shown in the following figures. The pins that are required for programming are listed in Table 2-1. The MCLR, PGC1, PGD1, PGC2, PGD2, PGC3 and PGD3 pins are shown in bold letters in the figures. Refer to the appropriate device data sheet for complete pin descriptions. TABLE 2-1: PIN DESCRIPTIONS (PINS USED DURING PROGRAMMING) During Programming Pin Name Pin Name MCLR MCLR VDD and AVDD(1) VSS and AVSS(1) VDDCORE Pin Type Pin Description P Programming Enable VDD P Power Supply VSS P Ground VDDCORE P Regulated Power Supply for Core PGC1 PGC1 I Primary Programming Pin Pair: Serial Clock PGD1 PGD1 I/O Primary Programming Pin Pair: Serial Data PGC2 PGC2 I Secondary Programming Pin Pair: Serial Clock PGD2 PGD2 I/O Secondary Programming Pin Pair: Serial Data PGC3 PGC3 I Tertiary Programming Pin Pair: Serial Clock PGD3 PGD3 I/O Tertiary Programming Pin Pair: Serial Data Legend: I = Input, O = Output, P = Power Note 1: All power supply and ground pins must be connected, including analog supplies (AVDD) and ground (AVSS). © 2007 Microchip Technology Inc. Preliminary DS70152D-page 3 dsPIC33F/PIC24H PROGRAMMING SPECIFICATION Pin Diagrams 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 CSDO/RG13 CSDO/RG13 CSDI/RG12 CSDI/RG12 CSCK/RG14 CSCK/RG14 RG0 RG1 RF1 RF0 VDD VDDCORE OC8/CN16/RD7 OC8/CN16/RD7 OC7/CN15/RD6 OC7/CN15/RD6 OC6/IC6/CN14/RD5 OC6/IC6/CN14/RD5 OC5/IC5/CN13/RD4 OC5/IC5/CN13/RD4 OC4/RD3 OC3/RD2 OC2/RD1 64-Pin TQFP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 dsPIC33FJ64GP206 dsPIC33FJ128GP206 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 PGC2/EMUC2/SOSCO/T1CK/CN0/RC14 PGC2/EMUC2/SOSCO/T1CK/CN0/RC14 PGD2/EMUD2/SOSCI/T4CK/CN1/RC13 PGD2/EMUD2/SOSCI/T4CK/CN1/RC13 OC1/RD0 IC4/INT4/RD11 IC4/INT4/RD11 IC3/INT3/RD10 IC3/INT3/RD10 IC2/U1CTS/INT2/RD9 IC1/INT1/RD8 VSS OSC2/CLKO/RC15 OSC2/CLKO/RC15 OSC1/CLKIN/RC12 OSC1/CLKIN/RC12 VDD SCL1/RG2 SDA1/RG3 U1RTS/SCK1/INT0/RF6 U1RX/SDI1/RF2 U1TX/SDO1/RF3 PGC1/EMUC1/AN6/OCFA/RB6 PGD1/EMUD1/AN7/RB7 AVDD AVSS U2CTS/AN8/RB8 AN9/RB9 TMS/AN10/RB10 TMS/AN10/RB10 TDO/AN11/RB11 TDO/AN11/RB11 VSS VDD TCK/AN12/RB12 TCK/AN12/RB12 TDI/AN13/RB13 TDI/AN13/RB13 U2RTS/AN14/RB14 U2RTS/AN14/RB14 AN15/OCFB/CN12/RB15 AN15/OCFB/CN12/RB15 U2RX/CN17/RF4 U2RX/CN17/RF4 U2TX/CN18/RF5 U2TX/CN18/RF5 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 COFS/RG15 COFS/RG15 AN16/T2CK/T7CK/RC1 AN16/T2CK/T7CK/RC1 AN17/T3CK/T6CK/RC2 AN17/T3CK/T6CK/RC2 SCK2/CN8/RG6 SDI2/CN9/RG7 SDO2/CN10/RG8 SDO2/CN10/RG8 MCLR SS2/T5CK/CN11/RG9 SS2/T5CK/CN11/RG9 VSS VDD AN5/IC8/CN7/RB5 AN4/IC7/CN6/RB4 AN3/CN5/RB3 AN2/SS1/LVDIN/CN4/RB2 PGC3/EMUC3/AN1/VREF-/CN3/RB1 PGD3/EMUD3/AN0/VREF+/CN2/RB0 DS70152D-page 4 Preliminary © 2007 Microchip Technology Inc. dsPIC33F/PIC24H PROGRAMMING SPECIFICATION Pin Diagrams (Continued) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 CSDO/RG13 CSDO/RG13 CSDI/RG12 CSDI/RG12 CSCK/RG14 CSCK/RG14 RG0 RG1 RF1 RF0 VDD VDDCORE OC8/CN16/RD7 OC8/CN16/RD7 OC7/CN15/RD6 OC7/CN15/RD6 OC6/IC6/CN14/RD5 OC6/IC6/CN14/RD5 OC5/IC5/CN13/RD4 OC5/IC5/CN13/RD4 OC4/RD3 OC3/RD2 OC2/RD1 64-Pin TQFP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 dsPIC33FJ64GP306 dsPIC33FJ128GP306 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 PGC2/EMUC2/SOSCO/T1CK/CN0/RC14 PGC2/EMUC2/SOSCO/T1CK/CN0/RC14 PGD2/EMUD2/SOSCI/T4CK/CN1/RC13 PGD2/EMUD2/SOSCI/T4CK/CN1/RC13 OC1/RD0 IC4/INT4/RD11 IC4/INT4/RD11 IC3/INT3/RD10 IC3/INT3/RD10 IC2/U1CTS/INT2/RD9 IC1/INT1/RD8 VSS OSC2/CLKO/RC15 OSC2/CLKO/RC15 OSC1/CLKIN/RC12 OSC1/CLKIN/RC12 VDD SCL1/RG2 SDA1/RG3 U1RTS/SCK1/INT0/RF6 U1RX/SDI1/RF2 U1TX/SDO1/RF3 PGC1/EMUC1/AN6/OCFA/RB6 PGD1/EMUD1/AN7/RB7 AVDD AVSS U2CTS/AN8/RB8 AN9/RB9 TMS/AN10/RB10 TMS/AN10/RB10 TDO/AN11/RB11 TDO/AN11/RB11 VSS VDD TCK/AN12/RB12 TCK/AN12/RB12 TDI/AN13/RB13 TDI/AN13/RB13 U2RTS/AN14/RB14 U2RTS/AN14/RB14 AN15/OCFB/CN12/RB15 AN15/OCFB/CN12/RB15 U2RX/SDA2/CN17/RF4 U2RX/SDA2/CN17/RF4 U2TX/SCL2/CN18/RF5 U2TX/SCL2/CN18/RF5 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 COFS/RG15 COFS/RG15 AN16/T2CK/T7CK/RC1 AN16/T2CK/T7CK/RC1 AN17/T3CK/T6CK/RC2 AN17/T3CK/T6CK/RC2 SCK2/CN8/RG6 SDI2/CN9/RG7 SDO2/CN10/RG8 SDO2/CN10/RG8 MCLR SS2/T5CK/CN11/RG9 SS2/T5CK/CN11/RG9 VSS VDD AN5/IC8/CN7/RB5 AN4/IC7/CN6/RB4 AN3/CN5/RB3 AN2/SS1/LVDIN/CN4/RB2 PGC3/EMUC3/AN1/VREF-/CN3/RB1 PGD3/EMUD3/AN0/VREF+/CN2/RB0 © 2007 Microchip Technology Inc. Preliminary DS70152D-page 5 dsPIC33F/PIC24H PROGRAMMING SPECIFICATION Pin Diagrams (Continued) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 CSDO/RG13 CSDO/RG13 CSDI/RG12 CSDI/RG12 CSCK/RG14 CSCK/RG14 RG0 RG1 C1TX/RF1 C1RX/RF0 VDD VDDCORE OC8/CN16/RD7 OC8/CN16/RD7 OC7/CN15/RD6 OC7/CN15/RD6 OC6/IC6/CN14/RD5 OC6/IC6/CN14/RD5 OC5/IC5/CN13/RD4 OC5/IC5/CN13/RD4 OC4/RD3 OC3/RD2 OC2/RD1 64-Pin TQFP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 dsPIC33FJ256GP506 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 PGC2/EMUC2/SOSCO/T1CK/CN0/RC14 PGC2/EMUC2/SOSCO/T1CK/CN0/RC14 PGD2/EMUD2/SOSCI/T4CK/CN1/RC13 PGD2/EMUD2/SOSCI/T4CK/CN1/RC13 OC1/RD0 IC4/INT4/RD11 IC4/INT4/RD11 IC3/INT3/RD10 IC3/INT3/RD10 IC2/U1CTS/INT2/RD9 IC1/INT1/RD8 VSS OSC2/CLKO/RC15 OSC2/CLKO/RC15 OSC1/CLKIN/RC12 OSC1/CLKIN/RC12 VDD SCL1/RG2 SDA1/RG3 U1RTS/SCK1/INT0/RF6 U1RX/SDI1/RF2 U1TX/SDO1/RF3 PGC1/EMUC1/AN6/OCFA/RB6 PGD1/EMUD1/AN7/RB7 AVDD AVSS U2CTS/AN8/RB8 AN9/RB9 TMS/AN10/RB10 TMS/AN10/RB10 TDO/AN11/RB11 TDO/AN11/RB11 VSS VDD TCK/AN12/RB12 TCK/AN12/RB12 TDI/AN13/RB13 TDI/AN13/RB13 U2RTS/AN14/RB14 U2RTS/AN14/RB14 AN15/OCFB/CN12/RB15 AN15/OCFB/CN12/RB15 U2RX/SDA2/CN17/RF4 U2RX/SDA2/CN17/RF4 U2TX/SCL2/CN18/RF5 U2TX/SCL2/CN18/RF5 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 COFS/RG15 COFS/RG15 AN16/T2CK/T7CK/RC1 AN16/T2CK/T7CK/RC1 AN17/T3CK/T6CK/RC2 AN17/T3CK/T6CK/RC2 SCK2/CN8/RG6 SDI2/CN9/RG7 SDO2/CN10/RG8 SDO2/CN10/RG8 MCLR SS2/T5CK/CN11/RG9 SS2/T5CK/CN11/RG9 VSS VDD AN5/IC8/CN7/RB5 AN4/IC7/CN6/RB4 AN3/CN5/RB3 AN2/SS1/LVDIN/CN4/RB2 PGC3/EMUC3/AN1/VREF-/CN3/RB1 PGD3/EMUD3/AN0/VREF+/CN2/RB0 DS70152D-page 6 Preliminary © 2007 Microchip Technology Inc. dsPIC33F/PIC24H PROGRAMMING SPECIFICATION Pin Diagrams (Continued) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 CSDO/RG13 CSDO/RG13 CSDI/RG12 CSDI/RG12 CSCK/RG14 CSCK/RG14 C2RX/RG0 C2TX/RG1 C1TX/RF1 C1RX/RF0 VDD VDDCORE OC8/CN16/RD7 OC8/CN16/RD7 OC7/CN15/RD6 OC7/CN15/RD6 OC6/IC6/CN14/RD5 OC6/IC6/CN14/RD5 OC5/IC5/CN13/RD4 OC5/IC5/CN13/RD4 OC4/RD3 OC3/RD2 OC2/RD1 64-Pin TQFP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 dsPIC33FJ64GP706 dsPIC33FJ128GP706 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 PGC2/EMUC2/SOSCO/T1CK/CN0/RC14 PGC2/EMUC2/SOSCO/T1CK/CN0/RC14 PGD2/EMUD2/SOSCI/T4CK/CN1/RC13 PGD2/EMUD2/SOSCI/T4CK/CN1/RC13 OC1/RD0 IC4/INT4/RD11 IC4/INT4/RD11 IC3/INT3/RD10 IC3/INT3/RD10 IC2/U1CTS/INT2/RD9 IC1/INT1/RD8 VSS OSC2/CLKO/RC15 OSC2/CLKO/RC15 OSC1/CLKIN/RC12 OSC1/CLKIN/RC12 VDD SCL1/RG2 SDA1/RG3 U1RTS/SCK1/INT0/RF6 U1RX/SDI1/RF2 U1TX/SDO1/RF3 PGC1/EMUC1/AN6/OCFA/RB6 PGD1/EMUD1/AN7/RB7 AVDD AVSS U2CTS/AN8/RB8 AN9/RB9 TMS/AN10/RB10 TMS/AN10/RB10 TDO/AN11/RB11 TDO/AN11/RB11 VSS VDD TCK/AN12/RB12 TCK/AN12/RB12 TDI/AN13/RB13 TDI/AN13/RB13 U2RTS/AN14/RB14 U2RTS/AN14/RB14 AN15/OCFB/CN12/RB15 AN15/OCFB/CN12/RB15 U2RX/SDA2/CN17/RF4 U2RX/SDA2/CN17/RF4 U2TX/SCL2/CN18/RF5 U2TX/SCL2/CN18/RF5 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 COFS/RG15 COFS/RG15 AN16/T2CK/T7CK/RC1 AN16/T2CK/T7CK/RC1 AN17/T3CK/T6CK/RC2 AN17/T3CK/T6CK/RC2 SCK2/CN8/RG6 SDI2/CN9/RG7 SDO2/CN10/RG8 SDO2/CN10/RG8 MCLR SS2/T5CK/CN11/RG9 SS2/T5CK/CN11/RG9 VSS VDD AN5/IC8/CN7/RB5 AN4/IC7/CN6/RB4 AN3/CN5/RB3 AN2/SS1/LVDIN/CN4/RB2 PGC3/EMUC3/AN1/VREF-/CN3/RB1 PGD3/EMUD3/AN0/VREF+/CN2/RB0 © 2007 Microchip Technology Inc. Preliminary DS70152D-page 7 dsPIC33F/PIC24H PROGRAMMING SPECIFICATION Pin Diagrams (Continued) IC5/RD12 IC5/RD12 OC4/RD3 OC3/RD2 OC2/RD1 IC6/CN19/RD13 IC6/CN19/RD13 OC7/CN15/RD6 OC7/CN15/RD6 OC6/CN14/RD5 OC6/CN14/RD5 OC5/CN13/RD4 OC5/CN13/RD4 C1TX/RF1 C1RX/RF0 VDD VDDCORE OC8/CN16/RD7 OC8/CN16/RD7 C2RX/RG0 C2TX/RG1 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 CSCK/RG14 CSCK/RG14 AN23/CN23/RA7 AN23/CN23/RA7 AN22/CN22/RA6 AN22/CN22/RA6 80 79 78 77 76 CSDO/RG13 CSDO/RG13 CSDI/RG12 CSDI/RG12 80-Pin TQFP COFS/RG15 COFS/RG15 1 60 PGC2/EMUC2/SOSCO/T1CK/ CN0/RC14 CN0/RC14 AN16/T2CK/T7CK/RC1 AN16/T2CK/T7CK/RC1 2 59 PGD2/EMUD2/SOSCI/CN1/RC13 PGD2/EMUD2/SOSCI/CN1/RC13 AN17/T3CK/T6CK/RC2 AN17/T3CK/T6CK/RC2 3 58 OC1/RD0 4 57 5 56 IC4/RD11 IC4/RD11 IC3/RD10 IC3/RD10 6 55 IC2/RD9 IC1/RD8 AN18/T4CK/T9CK/RC3 AN18/T4CK/T9CK/RC3 AN19/T5CK/T8CK/RC4 AN19/T5CK/T8CK/RC4 SCK2/CN8/RG6 SDI2/CN9/RG7 7 54 SDO2/CN10/RG8 SDO2/CN10/RG8 8 53 SDA2/INT4/RA3 MCLR 9 52 SCL2/INT3/RA2 VSS SS2/CN11/RG9 SS2/CN11/RG9 VSS 10 VDD 12 TMS/AN20/INT1/RA12 TMS/AN20/INT1/RA12 TDO/AN21/INT2/RA13 TDO/AN21/INT2/RA13 AN5/CN7/RB5 AN4/CN6/RB4 AN3/CN5/RB3 AN2/SS1/LVDIN/CN4/RB2 PGC3/EMUC3/AN1/CN3/RB1 PGD3/EMUD3/AN0/CN2/RB0 44 SCK1/INT0/RF6 SDI1/RF7 18 43 SDO1/RF8 19 42 U1RX/RF2 20 41 U1TX/RF3 24 25 26 27 28 29 30 31 32 33 34 VREF-/RA9 AVDD AVSS U2CTS/AN8/RB8 AN9/RB9 AN10/RB10 AN10/RB10 AN11/RB11 AN11/RB11 VSS VDD TCK/AN12/RB12 TCK/AN12/RB12 TDI/AN13/RB13 TDI/AN13/RB13 22 VREF+/RA10 /RA10 21 PGD1/EMUD1/AN7/RB7 23 Preliminary 40 45 39 16 17 U2TX/CN18/RF5 U2TX/CN18/RF5 SDA1/RG3 U2RX/CN17/RF4 U2RX/CN17/RF4 46 IC8/U1RTS/CN21/RD15 IC8/U1RTS/CN21/RD15 SCL1/RG2 15 38 VDD 47 37 48 14 36 13 35 OSC1/CLKIN/RC12 OSC1/CLKIN/RC12 U2RTS/AN14/RB14 U2RTS/AN14/RB14 OSC2/CLKO/RC15 OSC2/CLKO/RC15 49 AN15/OCFB/CN12/RB15 AN15/OCFB/CN12/RB15 IC7/U1CTS/CN20/RD14 IC7/U1CTS/CN20/RD14 50 11 PGC1/EMUC1/AN6/OCFA/RB6 DS70152D-page 8 51 dsPIC33FJ64GP708 dsPIC33FJ128GP708 © 2007 Microchip Technology Inc. dsPIC33F/PIC24H PROGRAMMING SPECIFICATION Pin Diagrams (Continued) 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 AN28/RE4 AN28/RE4 AN27/RE3 AN27/RE3 AN26/RE2 AN26/RE2 CSDO/RG13 CSDO/RG13 CSDI/RG12 CSDI/RG12 CSCK/RG14 CSCK/RG14 AN25/RE1 AN25/RE1 AN24/RE0 AN24/RE0 AN23/CN23/RA7 AN23/CN23/RA7 AN22/CN22/RA6 AN22/CN22/RA6 RG0 RG1 RF1 RF0 VDD VDDCORE OC8/CN16/RD7 OC8/CN16/RD7 OC7/CN15/RD6 OC7/CN15/RD6 OC6/CN14/RD5 OC6/CN14/RD5 OC5/CN13/RD4 OC5/CN13/RD4 IC6/CN19/RD13 IC6/CN19/RD13 IC5/RD12 IC5/RD12 OC4/RD3 OC3/RD2 OC2/RD1 100-Pin TQFP COFS/RG15 COFS/RG15 VDD AN29/RE5 AN29/RE5 AN30/RE6 AN30/RE6 AN31/RE7 AN31/RE7 AN16/T2CK/T7CK/RC1 AN16/T2CK/T7CK/RC1 AN17/T3CK/T6CK/RC2 AN17/T3CK/T6CK/RC2 AN18/T4CK/T9CK/RC3 AN18/T4CK/T9CK/RC3 AN19/T5CK/T8CK/RC4 AN19/T5CK/T8CK/RC4 SCK2/CN8/RG6 SDI2/CN9/RG7 SDO2/CN10/RG8 SDO2/CN10/RG8 MCLR SS2/CN11/RG9 SS2/CN11/RG9 VSS VDD TMS/RA0 AN20/INT1/RA12 AN20/INT1/RA12 AN21/INT2/RA13 AN21/INT2/RA13 AN5/CN7/RB5 AN4/CN6/RB4 AN3/CN5/RB3 AN2/SS1/LVDIN/CN4/RB2 PGC3/EMUC3/AN1/CN3/RB1 75 2 3 4 5 6 7 8 9 10 11 12 74 VSS PGC2/EMUC2/SOSCO/T1CK/CN0/RC14 PGC2/EMUC2/SOSCO/T1CK/CN0/RC14 73 PGD2/EMUD2/SOSCI/CN1/RC13 PGD2/EMUD2/SOSCI/CN1/RC13 72 OC1/RD0 IC4/RD11 IC4/RD11 IC3/RD10 IC3/RD10 13 14 15 16 17 18 19 20 21 22 23 24 25 71 70 69 68 67 66 dsPIC33FJ64GP310 dsPIC33FJ128GP310 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 IC2/RD9 IC1/RD8 INT4/RA15 INT4/RA15 INT3/RA14 INT3/RA14 VSS OSC2/CLKO/RC15 OSC2/CLKO/RC15 OSC1/CLKIN/RC12 OSC1/CLKIN/RC12 VDD TDO/RA5 TDI/RA4 SDA2/RA3 SCL2/RA2 SCL1/RG2 SDA1/RG3 SCK1/INT0/RF6 SDI1/RF7 SDO1/RF8 U1RX/RF2 U1TX/RF3 PGC1/EMUC1/AN6/OCFA/RB6 PGD1/EMUD1/AN7/RB7 VREF-/RA9 VREF+/RA10 /RA10 AVDD AVSS AN8/RB8 AN9/RB9 AN10/RB10 AN10/RB10 AN11/RB11 AN11/RB11 VSS VDD TCK/RA1 U2RTS/RF13 U2RTS/RF13 U2CTS/RF12 U2CTS/RF12 AN12/RB12 AN12/RB12 AN13/RB13 AN13/RB13 AN14/RB14 AN14/RB14 AN15/OCFB/CN12/RB15 AN15/OCFB/CN12/RB15 VSS VDD IC7/U1CTS/CN20/RD14 IC7/U1CTS/CN20/RD14 IC8/U1RTS/CN21/RD15 IC8/U1RTS/CN21/RD15 U2RX/CN17/RF4 U2RX/CN17/RF4 U2TX/CN18/RF5 U2TX/CN18/RF5 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 PGD3/EMUD3/AN0/CN2/RB0 1 © 2007 Microchip Technology Inc. Preliminary DS70152D-page 9 dsPIC33F/PIC24H PROGRAMMING SPECIFICATION Pin Diagrams (Continued) 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 AN28/RE4 AN28/RE4 AN27/RE3 AN27/RE3 AN26/RE2 AN26/RE2 CSDO/RG13 CSDO/RG13 CSDI/RG12 CSDI/RG12 CSCK/RG14 CSCK/RG14 AN25/RE1 AN25/RE1 AN24/RE0 AN24/RE0 AN23/CN23/RA7 AN23/CN23/RA7 AN22/CN22/RA6 AN22/CN22/RA6 RG0 RG1 C1TX/RF1 C1RX/RF0 VDD VDDCORE OC8/CN16/RD7 OC8/CN16/RD7 OC7/CN15/RD6 OC7/CN15/RD6 OC6/CN14/RD5 OC6/CN14/RD5 OC5/CN13/RD4 OC5/CN13/RD4 IC6/CN19/RD13 IC6/CN19/RD13 IC5/RD12 IC5/RD12 OC4/RD3 OC3/RD2 OC2/RD1 100-Pin TQFP COFS/RG15 COFS/RG15 VDD AN29/RE5 AN29/RE5 AN30/RE6 AN30/RE6 AN31/RE7 AN31/RE7 AN16/T2CK/T7CK/RC1 AN16/T2CK/T7CK/RC1 AN17/T3CK/T6CK/RC2 AN17/T3CK/T6CK/RC2 AN18/T4CK/T9CK/RC3 AN18/T4CK/T9CK/RC3 AN19/T5CK/T8CK/RC4 AN19/T5CK/T8CK/RC4 SCK2/CN8/RG6 SDI2/CN9/RG7 SDO2/CN10/RG8 SDO2/CN10/RG8 MCLR SS2/CN11/RG9 SS2/CN11/RG9 VSS VDD TMS/RA0 AN20/INT1/RA12 AN20/INT1/RA12 AN21/INT2/RA13 AN21/INT2/RA13 AN5/CN7/RB5 AN4/CN6/RB4 AN3/CN5/RB3 AN2/SS1/LVDIN/CN4/RB2 PGC3/EMUC3/AN1/CN3/RB1 75 2 3 4 5 6 7 8 9 10 11 12 74 VSS PGC2/EMUC2/SOSCO/T1CK/CN0/RC14 PGC2/EMUC2/SOSCO/T1CK/CN0/RC14 73 PGD2/EMUD2/SOSCI/CN1/RC13 PGD2/EMUD2/SOSCI/CN1/RC13 72 OC1/RD0 IC4/RD11 IC4/RD11 IC3/RD10 IC3/RD10 13 14 15 16 17 18 19 20 21 22 23 24 25 71 70 69 68 67 66 dsPIC33FJ256GP510 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 IC2/RD9 IC1/RD8 INT4/RA15 INT4/RA15 INT3/RA14 INT3/RA14 VSS OSC2/CLKO/RC15 OSC2/CLKO/RC15 OSC1/CLKIN/RC12 OSC1/CLKIN/RC12 VDD TDO/RA5 TDI/RA4 SDA2/RA3 SCL2/RA2 SCL1/RG2 SDA1/RG3 SCK1/INT0/RF6 SDI1/RF7 SDO1/RF8 U1RX/RF2 U1TX/RF3 PGC1/EMUC1/AN6/OCFA/RB6 PGD1/EMUD1/AN7/RB7 VREF-/RA9 VREF+/RA10 /RA10 AVDD AVSS AN8/RB8 AN9/RB9 AN10/RB10 AN10/RB10 AN11/RB11 AN11/RB11 VSS VDD TCK/RA1 U2RTS/RF13 U2RTS/RF13 U2CTS/RF12 U2CTS/RF12 AN12/RB12 AN12/RB12 AN13/RB13 AN13/RB13 AN14/RB14 AN14/RB14 AN15/OCFB/CN12/RB15 AN15/OCFB/CN12/RB15 VSS VDD IC7/U1CTS/CN20/RD14 IC7/U1CTS/CN20/RD14 IC8/U1RTS/CN21/RD15 IC8/U1RTS/CN21/RD15 U2RX/CN17/RF4 U2RX/CN17/RF4 U2TX/CN18/RF5 U2TX/CN18/RF5 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 PGD3/EMUD3/AN0/CN2/RB0 1 DS70152D-page 10 Preliminary © 2007 Microchip Technology Inc. dsPIC33F/PIC24H PROGRAMMING SPECIFICATION Pin Diagrams (Continued) 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 AN28/RE4 AN28/RE4 AN27/RE3 AN27/RE3 AN26/RE2 AN26/RE2 CSDO/RG13 CSDO/RG13 CSDI/RG12 CSDI/RG12 CSCK/RG14 CSCK/RG14 AN25/RE1 AN25/RE1 AN24/RE0 AN24/RE0 AN23/CN23/RA7 AN23/CN23/RA7 AN22/CN22/RA6 AN22/CN22/RA6 C2RX/RG0 C2TX/RG1 C1TX/RF1 C1RX/RF0 VDD VDDCORE OC8/CN16/RD7 OC8/CN16/RD7 OC7/CN15/RD6 OC7/CN15/RD6 OC6/CN14/RD5 OC6/CN14/RD5 OC5/CN13/RD4 OC5/CN13/RD4 IC6/CN19/RD13 IC6/CN19/RD13 IC5/RD12 IC5/RD12 OC4/RD3 OC3/RD2 OC2/RD1 100-Pin TQFP COFS/RG15 COFS/RG15 VDD AN29/RE5 AN29/RE5 AN30/RE6 AN30/RE6 AN31/RE7 AN31/RE7 AN16/T2CK/T7CK/RC1 AN16/T2CK/T7CK/RC1 AN17/T3CK/T6CK/RC2 AN17/T3CK/T6CK/RC2 AN18/T4CK/T9CK/RC3 AN18/T4CK/T9CK/RC3 AN19/T5CK/T8CK/RC4 AN19/T5CK/T8CK/RC4 SCK2/CN8/RG6 SDI2/CN9/RG7 SDO2/CN10/RG8 SDO2/CN10/RG8 MCLR SS2/CN11/RG9 SS2/CN11/RG9 VSS VDD TMS/RA0 AN20/INT1/RA12 AN20/INT1/RA12 AN21/INT2/RA13 AN21/INT2/RA13 AN5/CN7/RB5 AN4/CN6/RB4 AN3/CN5/RB3 AN2/SS1/LVDIN/CN4/RB2 PGC3/EMUC3/AN1/CN3/RB1 75 2 3 4 5 6 7 8 9 10 11 12 74 VSS PGC2/EMUC2/SOSCO/T1CK/CN0/RC14 PGC2/EMUC2/SOSCO/T1CK/CN0/RC14 73 PGD2/EMUD2/SOSCI/CN1/RC13 PGD2/EMUD2/SOSCI/CN1/RC13 72 OC1/RD0 IC4/RD11 IC4/RD11 IC3/RD10 IC3/RD10 13 14 15 16 17 18 19 20 21 22 23 24 25 71 70 69 68 67 66 dsPIC33FJ64GP710 dsPIC33FJ128GP710 dsPIC33FJ256GP710 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 IC2/RD9 IC1/RD8 INT4/RA15 INT4/RA15 INT3/RA14 INT3/RA14 VSS OSC2/CLKO/RC15 OSC2/CLKO/RC15 OSC1/CLKIN/RC12 OSC1/CLKIN/RC12 VDD TDO/RA5 TDI/RA4 SDA2/RA3 SCL2/RA2 SCL1/RG2 SDA1/RG3 SCK1/INT0/RF6 SDI1/RF7 SDO1/RF8 U1RX/RF2 U1TX/RF3 PGC1/EMUC1/AN6/OCFA/RB6 PGD1/EMUD1/AN7/RB7 VREF-/RA9 VREF+/RA10 /RA10 AVDD AVSS AN8/RB8 AN9/RB9 AN10/RB10 AN10/RB10 AN11/RB11 AN11/RB11 VSS VDD TCK/RA1 U2RTS/RF13 U2RTS/RF13 U2CTS/RF12 U2CTS/RF12 AN12/RB12 AN12/RB12 AN13/RB13 AN13/RB13 AN14/RB14 AN14/RB14 AN15/OCFB/CN12/RB15 AN15/OCFB/CN12/RB15 VSS VDD IC7/U1CTS/CN20/RD14 IC7/U1CTS/CN20/RD14 IC8/U1RTS/CN21/RD15 IC8/U1RTS/CN21/RD15 U2RX/CN17/RF4 U2RX/CN17/RF4 U2TX/CN18/RF5 U2TX/CN18/RF5 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 PGD3/EMUD3/AN0/CN2/RB0 1 © 2007 Microchip Technology Inc. Preliminary DS70152D-page 11 dsPIC33F/PIC24H PROGRAMMING SPECIFICATION Pin Diagrams (Continued) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 PWM3L/RE4 PWM2H/RE3 PWM2L/RE2 PWM1H/RE1 PWM1L/RE0 C1TX/RF1 C1RX/RF0 VDD VDDCORE OC8/UPDN/CN16/RD7 OC8/UPDN/CN16/RD7 OC7/CN15/RD6 OC7/CN15/RD6 OC6/IC6/CN14/RD5 OC6/IC6/CN14/RD5 OC5/IC5/CN13/RD4 OC5/IC5/CN13/RD4 OC4/RD3 OC3/RD2 OC2/RD1 64-Pin TQFP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 dsPIC33FJ64MC506 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 PGC2/EMUC2/SOSCO/T1CK/CN0/RC14 PGC2/EMUC2/SOSCO/T1CK/CN0/RC14 PGD2/EMUD2/SOSCI/T4CK/CN1/RC13 PGD2/EMUD2/SOSCI/T4CK/CN1/RC13 OC1/RD0 IC4/INT4/RD11 IC4/INT4/RD11 IC3/INT3/RD10 IC3/INT3/RD10 IC2/U1CTS/FLTB/INT2/RD9 IC1/FLTA/INT1/RD8 VSS OSC2/CLKO/RC15 OSC2/CLKO/RC15 OSC1/CLKIN/RC12 OSC1/CLKIN/RC12 VDD SCL1/RG2 SDA1/RG3 U1RTS/SCK1/INT0/RF6 U1RX/SDI1/RF2 U1TX/SDO1/RF3 PGC1/EMUC1/AN6/OCFA/RB6 PGD1/EMUD1/AN7/RB7 AVDD AVSS U2CTS/AN8/RB8 AN9/RB9 TMS/AN10/RB10 TMS/AN10/RB10 TDO/AN11/RB11 TDO/AN11/RB11 VSS VDD TCK/AN12/RB12 TCK/AN12/RB12 TDI/AN13/RB13 TDI/AN13/RB13 U2RTS/AN14/RB14 U2RTS/AN14/RB14 AN15/OCFB/CN12/RB15 AN15/OCFB/CN12/RB15 U2RX/CN17/RF4 U2RX/CN17/RF4 U2TX/CN18/RF5 U2TX/CN18/RF5 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 PWM3H/RE5 PWM4L/RE6 PWM4H/RE7 SCK2/CN8/RG6 SDI2/CN9/RG7 SDO2/CN10/RG8 SDO2/CN10/RG8 MCLR SS2/T5CK/CN11/RG9 SS2/T5CK/CN11/RG9 VSS VDD AN5/QEB/IC8/CN7/RB5 AN4/QEA/IC7/CN6/RB4 AN3/INDX/CN5/RB3 AN2/SS1/LVDIN/CN4/RB2 PGC3/EMUC3/AN1/VREF-/CN3/RB1 PGD3/EMUD3/AN0/VREF+/CN2/RB0 DS70152D-page 12 Preliminary © 2007 Microchip Technology Inc. dsPIC33F/PIC24H PROGRAMMING SPECIFICATION Pin Diagrams (Continued) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 PWM3L/RE4 PWM2H/RE3 PWM2L/RE2 PWM1H/RE1 PWM1L/RE0 C1TX/RF1 C1RX/RF0 VDD VDDCORE OC8/UPDN/CN16/RD7 OC8/UPDN/CN16/RD7 OC7/CN15/RD6 OC7/CN15/RD6 OC6/IC6/CN14/RD5 OC6/IC6/CN14/RD5 OC5/IC5/CN13/RD4 OC5/IC5/CN13/RD4 OC4/RD3 OC3/RD2 OC2/RD1 64-Pin TQFP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 dsPIC33FJ128MC506 dsPIC33FJ64MC506 dsPIC33FJ128MC706 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 PGC2/EMUC2/SOSCO/T1CK/CN0/RC14 PGC2/EMUC2/SOSCO/T1CK/CN0/RC14 PGD2/EMUD2/SOSCI/T4CK/CN1/RC13 PGD2/EMUD2/SOSCI/T4CK/CN1/RC13 OC1/RD0 IC4/INT4/RD11 IC4/INT4/RD11 IC3/INT3/RD10 IC3/INT3/RD10 IC2/U1CTS/FLTB/INT2/RD9 IC1/FLTA/INT1/RD8 VSS OSC2/CLKO/RC15 OSC2/CLKO/RC15 OSC1/CLKIN/RC12 OSC1/CLKIN/RC12 VDD SCL1/RG2 SDA1/RG3 U1RTS/SCK1/INT0/RF6 U1RX/SDI1/RF2 U1TX/SDO1/RF3 PGC1/EMUC1/AN6/OCFA/RB6 PGD1/EMUD1/AN7/RB7 AVDD AVSS U2CTS/AN8/RB8 AN9/RB9 TMS/AN10/RB10 TMS/AN10/RB10 TDO/AN11/RB11 TDO/AN11/RB11 VSS VDD TCK/AN12/RB12 TCK/AN12/RB12 TDI/AN13/RB13 TDI/AN13/RB13 U2RTS/AN14/RB14 U2RTS/AN14/RB14 AN15/OCFB/CN12/RB15 AN15/OCFB/CN12/RB15 U2RX/SDA2/CN17/RF4 U2RX/SDA2/CN17/RF4 U2TX/SCL2/CN18/RF5 U2TX/SCL2/CN18/RF5 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 PWM3H/RE5 PWM4L/RE6 PWM4H/RE7 SCK2/CN8/RG6 SDI2/CN9/RG7 SDO2/CN10/RG8 SDO2/CN10/RG8 MCLR SS2/T5CK/CN11/RG9 SS2/T5CK/CN11/RG9 VSS VDD AN5/QEB/IC8/CN7/RB5 AN4/QEA/IC7/CN6/RB4 AN3/INDX/CN5/RB3 AN2/SS1/LVDIN/CN4/RB2 PGC3/EMUC3/AN1/VREF-/CN3/RB1 PGD3/EMUD3/AN0/VREF+/CN2/RB0 © 2007 Microchip Technology Inc. Preliminary DS70152D-page 13 dsPIC33F/PIC24H PROGRAMMING SPECIFICATION Pin Diagrams (Continued) IC5/RD12 IC5/RD12 OC4/RD3 OC3/RD2 OC2/RD1 OC7/CN15/RD6 OC7/CN15/RD6 OC6/CN14/RD5 OC6/CN14/RD5 OC5/CN13/RD4 OC5/CN13/RD4 IC6/CN19/RD13 IC6/CN19/RD13 CRX2/RG0 C2TX/RG1 C1TX/RF1 C1RX/RF0 VDD VDDCORE OC8/CN16/UPDN/RD7 OC8/CN16/UPDN/RD7 PWM1L/RE0 PWM2L/RE2 PWM1H/RE1 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 PWM3L/RE4 PWM2H/RE3 80-Pin TQFP PWM3H/RE5 1 60 PGC2/EMUC2/SOSCO/T1CK/CN0/RC14 PGC2/EMUC2/SOSCO/T1CK/CN0/RC14 PWM4L/RE6 2 59 PGD2/EMUD2/SOSCI/CN1/RC13 PGD2/EMUD2/SOSCI/CN1/RC13 OC1/RD0 PWM4H/RE7 3 58 AN16/T2CK/T7CK/RC1 AN16/T2CK/T7CK/RC1 AN17/T3CK/T6CK/RC2 AN17/T3CK/T6CK/RC2 SCK2/CN8/RG6 4 57 5 56 IC4/RD11 IC4/RD11 IC3/RD10 IC3/RD10 6 55 IC2/RD9 SDI2/CN9/RG7 7 54 IC1/RD8 SDO2/CN10/RG8 SDO2/CN10/RG8 MCLR 8 53 INT4/RA3 INT3/RA2 VSS 9 52 SS2/CN11/RG9 SS2/CN11/RG9 VSS 10 51 VDD 12 49 OSC2/CLKO/RC15 OSC2/CLKO/RC15 OSC1/CLKIN/RC12 OSC1/CLKIN/RC12 TMS/FLTA/INT1/RE8 13 48 VDD TDO/FLTB/INT2/RE9 14 47 SCL1/RG2 AN5/QEB/CN7/RB5 AN4/QEA/CN6/RB4 15 46 SDA1/RG3 16 45 SCK1/INT0/RF6 AN3/INDX/CN5/RB3 17 44 SDI1/RF7 AN2/SS1/LVDIN/CN4/RB2 PGC3/EMUC3/AN1/CN3/RB1 18 43 SDO1/RF8 19 42 U1RX/RF2 PGD3/EMUD3/AN0/CN2/RB0 20 41 U1TX/RF3 dsPIC33FJ64MC508 DS70152D-page 14 34 40 33 TDI/AN13/RB13 TDI/AN13/RB13 39 32 TCK/AN12/RB12 TCK/AN12/RB12 U2TX/CN18/RF5 U2TX/CN18/RF5 31 VDD U2RX/CN17/RF4 U2RX/CN17/RF4 30 VSS 38 29 AN11/RB11 AN11/RB11 37 28 AN9/RB9 AN10/RB10 AN10/RB10 IC8/U1RTS/CN21/RD15 IC8/U1RTS/CN21/RD15 27 U2CTS/AN8/RB8 36 26 AVSS 35 25 AVDD U2RTS/AN14/RB14 U2RTS/AN14/RB14 24 Preliminary 50 AN15/OCFB/CN12/RB15 AN15/OCFB/CN12/RB15 IC7/U1CTS/CN20/RD14 IC7/U1CTS/CN20/RD14 23 VREF-/RA9 22 PGD1/EMUD1/AN7/RB7 VREF+/RA10 /RA10 21 PGC1/EMUC1/AN6/OCFA/RB6 11 © 2007 Microchip Technology Inc. dsPIC33F/PIC24H PROGRAMMING SPECIFICATION Pin Diagrams (Continued) IC5/RD12 IC5/RD12 OC4/RD3 OC3/RD2 OC2/RD1 OC6/CN14/RD5 OC6/CN14/RD5 OC5/CN13/RD4 OC5/CN13/RD4 IC6/CN19/RD13 IC6/CN19/RD13 CRX2/RG0 C2TX/RG1 C1TX/RF1 C1RX/RF0 VDD VDDCORE OC8/CN16/UPDN/RD7 OC8/CN16/UPDN/RD7 OC7/CN15/RD6 OC7/CN15/RD6 PWM2L/RE2 PWM1H/RE1 PWM1L/RE0 PWM2H/RE3 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 PWM3L/RE4 80-Pin TQFP PWM3H/RE5 1 60 PGC2/EMUC2/SOSCO/T1CK/CN0/RC14 PGC2/EMUC2/SOSCO/T1CK/CN0/RC14 PWM4L/RE6 2 59 PGD2/EMUD2/SOSCI/CN1/RC13 PGD2/EMUD2/SOSCI/CN1/RC13 PWM4H/RE7 3 58 OC1/RD0 AN16/T2CK/T7CK/RC1 AN16/T2CK/T7CK/RC1 AN17/T3CK/T6CK/RC2 AN17/T3CK/T6CK/RC2 SCK2/CN8/RG6 4 57 5 56 IC4/RD11 IC4/RD11 IC3/RD10 IC3/RD10 6 55 IC2/RD9 SDI2/CN9/RG7 7 54 IC1/RD8 8 53 SDA2/INT4/RA3 SCL2/INT3/RA2 VSS SDO2/CN10/RG8 SDO2/CN10/RG8 MCLR 9 52 SS2/CN11/RG9 SS2/CN11/RG9 VSS 10 51 VDD 12 49 OSC2/CLKO/RC15 OSC2/CLKO/RC15 OSC1/CLKIN/RC12 OSC1/CLKIN/RC12 VDD dsPIC33FJ128MC708 11 50 © 2007 Microchip Technology Inc. 29 30 31 32 33 34 35 36 37 38 39 40 VSS VDD TCK/AN12/RB12 TCK/AN12/RB12 TDI/AN13/RB13 TDI/AN13/RB13 U2RTS/AN14/RB14 U2RTS/AN14/RB14 AN15/OCFB/CN12/RB15 AN15/OCFB/CN12/RB15 IC7/U1CTS/CN20/RD14 IC7/U1CTS/CN20/RD14 IC8/U1RTS/CN21/RD15 IC8/U1RTS/CN21/RD15 U2RX/CN17/RF4 U2RX/CN17/RF4 U2TX/CN18/RF5 U2TX/CN18/RF5 U1TX/RF3 AN11/RB11 AN11/RB11 41 28 20 AN9/RB9 U1RX/RF2 PGD3/EMUD3/AN0/CN2/RB0 AN10/RB10 AN10/RB10 SDO1/RF8 42 27 43 19 26 18 U2CTS/AN8/RB8 AN2/SS1/LVDIN/CN4/RB2 PGC3/EMUC3/AN1/CN3/RB1 25 SDI1/RF7 AVSS SCK1/INT0/RF6 44 AVDD 45 17 24 16 AN3/INDX/CN5/RB3 VREF+/RA10 /RA10 SDA1/RG3 23 46 VREF-/RA9 SCL1/RG2 15 22 47 21 48 14 PGD1/EMUD1/AN7/RB7 13 PGC1/EMUC1/AN6/OCFA/RB6 TMS/FLTA/INT1/RE8 TDO/FLTB/INT2/RE9 AN5/QEB/CN7/RB5 AN4/QEA/CN6/RB4 Preliminary DS70152D-page 15 dsPIC33F/PIC24H PROGRAMMING SPECIFICATION Pin Diagrams (Continued) 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 PWM3L/RE4 PWM2H/RE3 PWM2L/RE2 CSDO/RG13 CSDO/RG13 CSDI/RG12 CSDI/RG12 CSCK/RG14 CSCK/RG14 PWM1H/RE1 PWM1L/RE0 AN23/CN23/RA7 AN23/CN23/RA7 AN22/CN22/RA6 AN22/CN22/RA6 RG0 RG1 C1TX/RF1 C1RX/RF0 VDD VDDCORE OC8/UPDN//CN16/RD7 OC8/UPDN//CN16/RD7 OC7/CN15/RD6 OC7/CN15/RD6 OC6/CN14/RD5 OC6/CN14/RD5 OC5/CN13/RD4 OC5/CN13/RD4 IC6/CN19/RD13 IC6/CN19/RD13 IC5/RD12 IC5/RD12 OC4/RD3 OC3/RD2 OC2/RD1 100-Pin TQFP COFS/RG15 COFS/RG15 VDD PWM3H/RE5 PWM4L/RE6 PWM4H/RE7 AN16/T2CK/T7CK/RC1 AN16/T2CK/T7CK/RC1 AN17/T3CK/T6CK/RC2 AN17/T3CK/T6CK/RC2 AN18/T4CK/T9CK/RC3 AN18/T4CK/T9CK/RC3 AN19/T5CK/T8CK/RC4 AN19/T5CK/T8CK/RC4 SCK2/CN8/RG6 SDI2/CN9/RG7 SDO2/CN10/RG8 SDO2/CN10/RG8 MCLR SS2/CN11/RG9 SS2/CN11/RG9 VSS VDD TMS/RA0 AN20/FLTA/INT1/RE8 AN20/FLTA/INT1/RE8 AN21/FLTB/INT2/RE9 AN21/FLTB/INT2/RE9 AN5/QEB/CN7/RB5 AN4/QEA/CN6/RB4 AN3/INDX/CN5/RB3 AN2/SS1/LVDIN/CN4/RB2 PGC3/EMUC3/AN1/CN3/RB1 75 2 3 4 5 6 7 8 9 10 11 12 74 VSS PGC2/EMUC2/SOSCO/T1CK/CN0/RC14 PGC2/EMUC2/SOSCO/T1CK/CN0/RC14 73 PGD2/EMUD2/SOSCI/CN1/RC13 PGD2/EMUD2/SOSCI/CN1/RC13 72 OC1/RD0 IC4/RD11 IC4/RD11 IC3/RD10 IC3/RD10 IC2/RD9 71 70 69 68 67 66 13 14 15 16 17 18 19 20 21 22 23 24 25 dsPIC33FJ64MC510 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 IC1/RD8 INT4/RA15 INT4/RA15 INT3/RA14 INT3/RA14 VSS OSC2/CLKO/RC15 OSC2/CLKO/RC15 OSC1/CLKIN/RC12 OSC1/CLKIN/RC12 VDD TDO/RA5 TDI/RA4 RA3 RA2 SCL1/RG2 SDA1/RG3 SCK1/INT0/RF6 SDI1/RF7 SDO1/RF8 U1RX/RF2 U1TX/RF3 PGC1/EMUC1/AN6/OCFA/RB6 PGD1/EMUD1/AN7/RB7 VREF-/RA9 VREF+/RA10 /RA10 AVDD AVSS AN8/RB8 AN9/RB9 AN10/RB10 AN10/RB10 AN11/RB11 AN11/RB11 VSS VDD TCK/RA1 U2RTS/RF13 U2RTS/RF13 U2CTS/RF12 U2CTS/RF12 AN12/RB12 AN12/RB12 AN13/RB13 AN13/RB13 AN14/RB14 AN14/RB14 AN15/OCFB/CN12/RB15 AN15/OCFB/CN12/RB15 VSS VDD IC7/U1CTS/CN20/RD14 IC7/U1CTS/CN20/RD14 IC8/U1RTS/CN21/RD15 IC8/U1RTS/CN21/RD15 U2RX/CN17/RF4 U2RX/CN17/RF4 U2TX/CN18/RF5 U2TX/CN18/RF5 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 PGD3/EMUD3/AN0/CN2/RB0 1 DS70152D-page 16 Preliminary © 2007 Microchip Technology Inc. dsPIC33F/PIC24H PROGRAMMING SPECIFICATION Pin Diagrams (Continued) 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 PWM3L/RE4 PWM2H/RE3 PWM2L/RE2 CSDO/RG13 CSDO/RG13 CSDI/RG12 CSDI/RG12 CSCK/RG14 CSCK/RG14 PWM1H/RE1 PWM1L/RE0 AN23/CN23/RA7 AN23/CN23/RA7 AN22/CN22/RA6 AN22/CN22/RA6 RG0 RG1 C1TX/RF1 C1RX/RF0 VDD VDDCORE OC8/UPDN//CN16/RD7 OC8/UPDN//CN16/RD7 OC7/CN15/RD6 OC7/CN15/RD6 OC6/CN14/RD5 OC6/CN14/RD5 OC5/CN13/RD4 OC5/CN13/RD4 IC6/CN19/RD13 IC6/CN19/RD13 IC5/RD12 IC5/RD12 OC4/RD3 OC3/RD2 OC2/RD1 100-Pin TQFP COFS/RG15 COFS/RG15 VDD PWM3H/RE5 PWM4L/RE6 PWM4H/RE7 AN16/T2CK/T7CK/RC1 AN16/T2CK/T7CK/RC1 AN17/T3CK/T6CK/RC2 AN17/T3CK/T6CK/RC2 AN18/T4CK/T9CK/RC3 AN18/T4CK/T9CK/RC3 AN19/T5CK/T8CK/RC4 AN19/T5CK/T8CK/RC4 SCK2/CN8/RG6 SDI2/CN9/RG7 SDO2/CN10/RG8 SDO2/CN10/RG8 MCLR SS2/CN11/RG9 SS2/CN11/RG9 VSS VDD TMS/RA0 AN20/FLTA/INT1/RE8 AN20/FLTA/INT1/RE8 AN21/FLTB/INT2/RE9 AN21/FLTB/INT2/RE9 AN5/QEB/CN7/RB5 AN4/QEA/CN6/RB4 AN3/INDX/CN5/RB3 AN2/SS1/LVDIN/CN4/RB2 PGC3/EMUC3/AN1/CN3/RB1 75 2 3 4 5 6 7 8 9 10 11 12 74 VSS PGC2/EMUC2/SOSCO/T1CK/CN0/RC14 PGC2/EMUC2/SOSCO/T1CK/CN0/RC14 73 PGD2/EMUD2/SOSCI/CN1/RC13 PGD2/EMUD2/SOSCI/CN1/RC13 72 OC1/RD0 IC4/RD11 IC4/RD11 IC3/RD10 IC3/RD10 IC2/RD9 71 70 69 68 67 66 13 14 15 16 17 18 19 20 21 22 23 24 25 dsPIC33FJ128MC510 dsPIC33FJ256MC510 65 64 63 62 61 60 59 58 57 56 IC1/RD8 INT4/RA15 INT4/RA15 INT3/RA14 INT3/RA14 VSS OSC2/CLKO/RC15 OSC2/CLKO/RC15 OSC1/CLKIN/RC12 OSC1/CLKIN/RC12 VDD TDO/RA5 TDI/RA4 SDA2/RA3 SCL2/RA2 SCL1/RG2 SDA1/RG3 55 54 53 52 SCK1/INT0/RF6 51 U1TX/RF3 SDI1/RF7 SDO1/RF8 U1RX/RF2 PGC1/EMUC1/AN6/OCFA/RB6 PGD1/EMUD1/AN7/RB7 VREF-/RA9 VREF+/RA10 /RA10 AVDD AVSS AN8/RB8 AN9/RB9 AN10/RB10 AN10/RB10 AN11/RB11 AN11/RB11 VSS VDD TCK/RA1 U2RTS/RF13 U2RTS/RF13 U2CTS/RF12 U2CTS/RF12 AN12/RB12 AN12/RB12 AN13/RB13 AN13/RB13 AN14/RB14 AN14/RB14 AN15/OCFB/CN12/RB15 AN15/OCFB/CN12/RB15 VSS VDD IC7/U1CTS/CN20/RD14 IC7/U1CTS/CN20/RD14 IC8/U1RTS/CN21/RD15 IC8/U1RTS/CN21/RD15 U2RX/CN17/RF4 U2RX/CN17/RF4 U2TX/CN18/RF5 U2TX/CN18/RF5 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 PGD3/EMUD3/AN0/CN2/RB0 1 © 2007 Microchip Technology Inc. Preliminary DS70152D-page 17 dsPIC33F/PIC24H PROGRAMMING SPECIFICATION Pin Diagrams (Continued) 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 PWM3L/RE4 PWM2H/RE3 PWM2L/RE2 CSDO/RG13 CSDO/RG13 CSDI/RG12 CSDI/RG12 CSCK/RG14 CSCK/RG14 PWM1H/RE1 PWM1L/RE0 AN23/CN23/RA7 AN23/CN23/RA7 AN22/CN22/RA6 AN22/CN22/RA6 C2RX/RG0 C2TX/RG1 C1TX/RF1 C1RX/RF0 VDD VDDCORE OC8/UPDN//CN16/RD7 OC8/UPDN//CN16/RD7 OC7/CN15/RD6 OC7/CN15/RD6 OC6/CN14/RD5 OC6/CN14/RD5 OC5/CN13/RD4 OC5/CN13/RD4 IC6/CN19/RD13 IC6/CN19/RD13 IC5/RD12 IC5/RD12 OC4/RD3 OC3/RD2 OC2/RD1 100-Pin TQFP COFS/RG15 COFS/RG15 VDD PWM3H/RE5 PWM4L/RE6 PWM4H/RE7 AN16/T2CK/T7CK/RC1 AN16/T2CK/T7CK/RC1 AN17/T3CK/T6CK/RC2 AN17/T3CK/T6CK/RC2 AN18/T4CK/T9CK/RC3 AN18/T4CK/T9CK/RC3 AN19/T5CK/T8CK/RC4 AN19/T5CK/T8CK/RC4 SCK2/CN8/RG6 SDI2/CN9/RG7 SDO2/CN10/RG8 SDO2/CN10/RG8 MCLR SS2/CN11/RG9 SS2/CN11/RG9 VSS VDD TMS/RA0 AN20/FLTA/INT1/RE8 AN20/FLTA/INT1/RE8 AN21/FLTB/INT2/RE9 AN21/FLTB/INT2/RE9 AN5/QEB/CN7/RB5 AN4/QEA/CN6/RB4 AN3/INDX/CN5/RB3 AN2/SS1/LVDIN/CN4/RB2 PGC3/EMUC3/AN1/CN3/RB1 75 2 3 4 5 6 7 8 9 10 11 12 74 VSS PGC2/EMUC2/SOSCO/T1CK/CN0/RC14 PGC2/EMUC2/SOSCO/T1CK/CN0/RC14 73 PGD2/EMUD2/SOSCI/CN1/RC13 PGD2/EMUD2/SOSCI/CN1/RC13 72 OC1/RD0 IC4/RD11 IC4/RD11 IC3/RD10 IC3/RD10 IC2/RD9 71 70 69 68 67 66 13 14 15 16 17 18 19 20 21 22 23 24 25 dsPIC33FJ64MC710 dsPIC33FJ128MC710 dsPIC33FJ256MC710 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 IC1/RD8 INT4/RA15 INT4/RA15 INT3/RA14 INT3/RA14 VSS OSC2/CLKO/RC15 OSC2/CLKO/RC15 OSC1/CLKIN/RC12 OSC1/CLKIN/RC12 VDD TDO/RA5 TDI/RA4 SDA2/RA3 SCL2/RA2 SCL1/RG2 SDA1/RG3 SCK1/INT0/RF6 SDI1/RF7 SDO1/RF8 U1RX/RF2 U1TX/RF3 PGC1/EMUC1/AN6/OCFA/RB6 PGD1/EMUD1/AN7/RB7 VREF-/RA9 VREF+/RA10 /RA10 AVDD AVSS AN8/RB8 AN9/RB9 AN10/RB10 AN10/RB10 AN11/RB11 AN11/RB11 VSS VDD TCK/RA1 U2RTS/RF13 U2RTS/RF13 U2CTS/RF12 U2CTS/RF12 AN12/RB12 AN12/RB12 AN13/RB13 AN13/RB13 AN14/RB14 AN14/RB14 AN15/OCFB/CN12/RB15 AN15/OCFB/CN12/RB15 VSS VDD IC7/U1CTS/CN20/RD14 IC7/U1CTS/CN20/RD14 IC8/U1RTS/CN21/RD15 IC8/U1RTS/CN21/RD15 U2RX/CN17/RF4 U2RX/CN17/RF4 U2TX/CN18/RF5 U2TX/CN18/RF5 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 PGD3/EMUD3/AN0/CN2/RB0 1 DS70152D-page 18 Preliminary © 2007 Microchip Technology Inc. dsPIC33F/PIC24H PROGRAMMING SPECIFICATION Pin Diagrams (Continued) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 RG13 RG12 RG14 RG0 RG1 RF1 RF0 VDD VDDCORE OC8/CN16/RD7 OC8/CN16/RD7 OC7/CN15/RD6 OC7/CN15/RD6 OC6/IC6/CN14/RD5 OC6/IC6/CN14/RD5 OC5/IC5/CN13/RD4 OC5/IC5/CN13/RD4 OC4/RD3 OC3/RD2 OC2/RD1 64-Pin TQFP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PIC24HJ64GP206 PIC24HJ64GP206 PIC24HJ128GP206 PIC24HJ128GP206 PIC24HJ256GP206 PIC24HJ256GP206 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 PGC2/EMUC2/SOSCO/T1CK/CN0/RC14 PGC2/EMUC2/SOSCO/T1CK/CN0/RC14 PGD2/EMUD2/SOSCI/T4CK/CN1/RC13 PGD2/EMUD2/SOSCI/T4CK/CN1/RC13 OC1/RD0 IC4/INT4/RD11 IC4/INT4/RD11 IC3/INT3/RD10 IC3/INT3/RD10 IC2/U1CTS/INT2/RD9 IC1/INT1/RD8 VSS OSC2/CLKO/RC15 OSC2/CLKO/RC15 OSC1/CLKIN/RC12 OSC1/CLKIN/RC12 VDD SCL1/RG2 SDA1/RG3 U1RTS/SCK1/INT0/RF6 U1RX/SDI1/RF2 U1TX/SDO1/RF3 PGC1/EMUC1/AN6/OCFA/RB6 PGD1/EMUD1/AN7/RB7 AVDD AVSS U2CTS/AN8/RB8 AN9/RB9 TMS/AN10/RB10 TMS/AN10/RB10 TDO/AN11/RB11 TDO/AN11/RB11 VSS VDD TCK/AN12/RB12 TCK/AN12/RB12 TDI/AN13/RB13 TDI/AN13/RB13 U2RTS/AN14/RB14 U2RTS/AN14/RB14 AN15/OCFB/CN12/RB15 AN15/OCFB/CN12/RB15 U2RX/CN17/RF4 U2RX/CN17/RF4 U2TX/CN18/RF5 U2TX/CN18/RF5 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 RG15 AN16/T2CK/T7CK/RC1 AN16/T2CK/T7CK/RC1 AN17/T3CK/T6CK/RC2 AN17/T3CK/T6CK/RC2 SCK2/CN8/RG6 SDI2/CN9/RG7 SDO2/CN10/RG8 SDO2/CN10/RG8 MCLR SS2/T5CK/CN11/RG9 SS2/T5CK/CN11/RG9 VSS VDD AN5/IC8/CN7/RB5 AN4/IC7/CN6/RB4 AN3/CN5/RB3 AN2/SS1/CN4/RB2 PGC3/EMUC3/AN1/VREF-/CN3/RB1 PGD3/EMUD3/AN0/VREF+/CN2/RB0 Note: The PIC24HJ64GP206 PIC24HJ64GP206 device does not have the SCL2 and SDA2 pins. © 2007 Microchip Technology Inc. Preliminary DS70152D-page 19 dsPIC33F/PIC24H PROGRAMMING SPECIFICATION Pin Diagrams (Continued) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 RG13 RG12 RG14 RG0 RG1 RF1 RF0 VDD VDDCORE OC8/CN16/RD7 OC8/CN16/RD7 OC7/CN15/RD6 OC7/CN15/RD6 OC6/IC6/CN14/RD5 OC6/IC6/CN14/RD5 OC5/IC5/CN13/RD4 OC5/IC5/CN13/RD4 OC4/RD3 OC3/RD2 OC2/RD1 64-Pin TQFP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PIC24HJ128GP306 PIC24HJ128GP306 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 PGC2/EMUC2/SOSCO/T1CK/CN0/RC14 PGC2/EMUC2/SOSCO/T1CK/CN0/RC14 PGD2/EMUD2/SOSCI/T4CK/CN1/RC13 PGD2/EMUD2/SOSCI/T4CK/CN1/RC13 OC1/RD0 IC4/INT4/RD11 IC4/INT4/RD11 IC3/INT3/RD10 IC3/INT3/RD10 IC2/U1CTS/INT2/RD9 IC1/INT1/RD8 VSS OSC2/CLKO/RC15 OSC2/CLKO/RC15 OSC1/CLKIN/RC12 OSC1/CLKIN/RC12 VDD SCL1/RG2 SDA1/RG3 U1RTS/SCK1/INT0/RF6 U1RX/SDI1/RF2 U1TX/SDO1/RF3 PGC1/EMUC1/AN6/OCFA/RB6 PGD1/EMUD1/AN7/RB7 AVDD AVSS U2CTS/AN8/RB8 AN9/RB9 TMS/AN10/RB10 TMS/AN10/RB10 TDO/AN11/RB11 TDO/AN11/RB11 VSS VDD TCK/AN12/RB12 TCK/AN12/RB12 TDI/AN13/RB13 TDI/AN13/RB13 U2RTS/AN14/RB14 U2RTS/AN14/RB14 AN15/OCFB/CN12/RB15 AN15/OCFB/CN12/RB15 U2RX/SDA2/CN17/RF4 U2RX/SDA2/CN17/RF4 U2TX/SCL2/CN18/RF5 U2TX/SCL2/CN18/RF5 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 RG15 AN16/T2CK/T7CK/RC1 AN16/T2CK/T7CK/RC1 AN17/T3CK/T6CK/RC2 AN17/T3CK/T6CK/RC2 SCK2/CN8/RG6 SDI2/CN9/RG7 SDO2/CN10/RG8 SDO2/CN10/RG8 MCLR SS2/T5CK/CN11/RG9 SS2/T5CK/CN11/RG9 VSS VDD AN5/IC8/CN7/RB5 AN4/IC7/CN6/RB4 AN3/CN5/RB3 AN2/SS1/CN4/RB2 PGC3/EMUC3/AN1/VREF-/CN3/RB1 PGD3/EMUD3/AN0/VREF+/CN2/RB0 DS70152D-page 20 Preliminary © 2007 Microchip Technology Inc. dsPIC33F/PIC24H PROGRAMMING SPECIFICATION Pin Diagrams (Continued) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 CSDO/RG13 CSDO/RG13 CSDI/RG12 CSDI/RG12 CSCK/RG14 CSCK/RG14 RG0 RG1 C1TX/RF1 C1RX/RF0 VDD VDDCORE OC8/CN16/RD7 OC8/CN16/RD7 OC7/CN15/RD6 OC7/CN15/RD6 OC6/IC6/CN14/RD5 OC6/IC6/CN14/RD5 OC5/IC5/CN13/RD4 OC5/IC5/CN13/RD4 OC4/RD3 OC3/RD2 OC2/RD1 64-Pin TQFP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PIC24HJ64GP506 PIC24HJ64GP506 PIC24HJ128GP506 PIC24HJ128GP506 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 PGC2/EMUC2/SOSCO/T1CK/CN0/RC14 PGC2/EMUC2/SOSCO/T1CK/CN0/RC14 PGD2/EMUD2/SOSCI/T4CK/CN1/RC13 PGD2/EMUD2/SOSCI/T4CK/CN1/RC13 OC1/RD0 IC4/INT4/RD11 IC4/INT4/RD11 IC3/INT3/RD10 IC3/INT3/RD10 IC2/U1CTS/INT2/RD9 IC1/INT1/RD8 VSS OSC2/CLKO/RC15 OSC2/CLKO/RC15 OSC1/CLKIN/RC12 OSC1/CLKIN/RC12 VDD SCL1/RG2 SDA1/RG3 U1RTS/SCK1/INT0/RF6 U1RX/SDI1/RF2 U1TX/SDO1/RF3 PGC1/EMUC1/AN6/OCFA/RB6 PGD1/EMUD1/AN7/RB7 AVDD AVSS U2CTS/AN8/RB8 AN9/RB9 TMS/AN10/RB10 TMS/AN10/RB10 TDO/AN11/RB11 TDO/AN11/RB11 VSS VDD TCK/AN12/RB12 TCK/AN12/RB12 TDI/AN13/RB13 TDI/AN13/RB13 U2RTS/AN14/RB14 U2RTS/AN14/RB14 AN15/OCFB/CN12/RB15 AN15/OCFB/CN12/RB15 U2RX/SDA2/CN17/RF4 U2RX/SDA2/CN17/RF4 U2TX/SCL2/CN18/RF5 U2TX/SCL2/CN18/RF5 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 COFS/RG15 COFS/RG15 AN16/T2CK/T7CK/RC1 AN16/T2CK/T7CK/RC1 AN17/T3CK/T6CK/RC2 AN17/T3CK/T6CK/RC2 SCK2/CN8/RG6 SDI2/CN9/RG7 SDO2/CN10/RG8 SDO2/CN10/RG8 MCLR SS2/T5CK/CN11/RG9 SS2/T5CK/CN11/RG9 VSS VDD AN5/IC8/CN7/RB5 AN4/IC7/CN6/RB4 AN3/CN5/RB3 AN2/SS1/CN4/RB2 PGC3/EMUC3/AN1/VREF-/CN3/RB1 PGD3/EMUD3/AN0/VREF+/CN2/RB0 © 2007 Microchip Technology Inc. Preliminary DS70152D-page 21 dsPIC33F/PIC24H PROGRAMMING SPECIFICATION Pin Diagrams (Continued) 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 AN28/RE4 AN28/RE4 AN27/RE3 AN27/RE3 AN26/RE2 AN26/RE2 RG13 RG12 RG14 AN25/RE1 AN25/RE1 AN24/RE0 AN24/RE0 AN23/CN23/RA7 AN23/CN23/RA7 AN22/CN22/RA6 AN22/CN22/RA6 RG0 RG1 RF1 RF0 VDD VDDCORE OC8/CN16/RD7 OC8/CN16/RD7 OC7/CN15/RD6 OC7/CN15/RD6 OC6/CN14/RD5 OC6/CN14/RD5 OC5/CN13/RD4 OC5/CN13/RD4 IC6/CN19/RD13 IC6/CN19/RD13 IC5/RD12 IC5/RD12 OC4/RD3 OC3/RD2 OC2/RD1 100-Pin TQFP RG15 VDD AN29/RE5 AN29/RE5 AN30/RE6 AN30/RE6 AN31/RE7 AN31/RE7 AN16/T2CK/T7CK/RC1 AN16/T2CK/T7CK/RC1 AN17/T3CK/T6CK/RC2 AN17/T3CK/T6CK/RC2 AN18/T4CK/T9CK/RC3 AN18/T4CK/T9CK/RC3 AN19/T5CK/T8CK/RC4 AN19/T5CK/T8CK/RC4 SCK2/CN8/RG6 SDI2/CN9/RG7 SDO2/CN10/RG8 SDO2/CN10/RG8 MCLR SS2/CN11/RG9 SS2/CN11/RG9 VSS VDD TMS/RA0 AN20/INT1/RA12 AN20/INT1/RA12 AN21/INT2/RA13 AN21/INT2/RA13 AN5/CN7/RB5 AN4/CN6/RB4 AN3/CN5/RB3 AN2/SS1/CN4/RB2 75 74 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 71 70 69 68 67 66 65 64 63 62 IC3/RD10 IC3/RD10 IC2/RD9 IC1/RD8 INT4/RA15 INT4/RA15 INT3/RA14 INT3/RA14 VSS 59 58 SDA2/RA3 SCL2/RA2 SCL1/RG2 SDA1/RG3 SCK1/INT0/RF6 54 53 52 51 25 61 60 OSC2/CLKO/RC15 OSC2/CLKO/RC15 OSC1/CLKIN/RC12 OSC1/CLKIN/RC12 VDD TDO/RA5 TDI/RA4 57 56 55 PIC24HJ64GP210 PIC24HJ64GP210 PIC24HJ128GP210 PIC24HJ128GP210 PIC24HJ128GP310 PIC24HJ128GP310 PIC24HJ256GP210 PIC24HJ256GP210 23 24 PGD3/EMUD3/AN0/CN2/RB0 PGD2/EMUD2/SOSCI/CN1/RC13 PGD2/EMUD2/SOSCI/CN1/RC13 OC1/RD0 IC4/RD11 IC4/RD11 72 PGC2/EMUC2/SOSCO/T1CK/CN0/RC14 PGC2/EMUC2/SOSCO/T1CK/CN0/RC14 SDI1/RF7 SDO1/RF8 U1RX/RF2 U1TX/RF3 PGC1/EMUC1/AN6/OCFA/RB6 PGD1/EMUD1/AN7/RB7 VREF-/RA9 VREF+/RA10 /RA10 AVDD AVSS AN8/RB8 AN9/RB9 AN10/RB10 AN10/RB10 AN11/RB11 AN11/RB11 VSS VDD TCK/RA1 U2RTS/RF13 U2RTS/RF13 U2CTS/RF12 U2CTS/RF12 AN12/RB12 AN12/RB12 AN13/RB13 AN13/RB13 AN14/RB14 AN14/RB14 AN15/OCFB/CN12/RB15 AN15/OCFB/CN12/RB15 VSS VDD IC7/U1CTS/CN20/RD14 IC7/U1CTS/CN20/RD14 IC8/U1RTS/CN21/RD15 IC8/U1RTS/CN21/RD15 U2RX/CN17/RF4 U2RX/CN17/RF4 U2TX/CN18/RF5 U2TX/CN18/RF5 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 PGC3/EMUC3/AN1/CN3/RB1 VSS 73 1 DS70152D-page 22 Preliminary © 2007 Microchip Technology Inc. dsPIC33F/PIC24H PROGRAMMING SPECIFICATION Pin Diagrams (Continued) 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 AN28/RE4 AN28/RE4 AN27/RE3 AN27/RE3 AN26/RE2 AN26/RE2 RG13 RG12 RG14 AN25/RE1 AN25/RE1 AN24/RE0 AN24/RE0 AN23/CN23/RA7 AN23/CN23/RA7 AN22/CN22/RA6 AN22/CN22/RA6 RG0 RG1 C1TX/RF1 C1RX/RF0 VDD VDDCORE OC8/CN16/RD7 OC8/CN16/RD7 OC7/CN15/RD6 OC7/CN15/RD6 OC6/CN14/RD5 OC6/CN14/RD5 OC5/CN13/RD4 OC5/CN13/RD4 IC6/CN19/RD13 IC6/CN19/RD13 IC5/RD12 IC5/RD12 OC4/RD3 OC3/RD2 OC2/RD1 100-Pin TQFP RG15 VDD AN29/RE5 AN29/RE5 AN30/RE6 AN30/RE6 AN31/RE7 AN31/RE7 AN16/T2CK/T7CK/RC1 AN16/T2CK/T7CK/RC1 AN17/T3CK/T6CK/RC2 AN17/T3CK/T6CK/RC2 AN18/T4CK/T9CK/RC3 AN18/T4CK/T9CK/RC3 AN19/T5CK/T8CK/RC4 AN19/T5CK/T8CK/RC4 SCK2/CN8/RG6 SDI2/CN9/RG7 SDO2/CN10/RG8 SDO2/CN10/RG8 MCLR SS2/CN11/RG9 SS2/CN11/RG9 VSS VDD TMS/RA0 AN20/INT1/RA12 AN20/INT1/RA12 AN21/INT2/RA13 AN21/INT2/RA13 AN5/CN7/RB5 AN4/CN6/RB4 AN3/CN5/RB3 AN2/SS1/CN4/RB2 PGC3/EMUC3/AN1/CN3/RB1 75 74 VSS PGC2/EMUC2/SOSCO/T1CK/CN0/RC14 PGC2/EMUC2/SOSCO/T1CK/CN0/RC14 73 PGD2/EMUD2/SOSCI/CN1/RC13 PGD2/EMUD2/SOSCI/CN1/RC13 OC1/RD0 5 6 7 8 9 71 70 69 68 67 66 72 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 65 64 PIC24HJ64GP510 PIC24HJ64GP510 PIC24HJ128GP510 PIC24HJ128GP510 63 62 61 60 59 58 57 56 55 54 53 52 51 IC4/RD11 IC4/RD11 IC3/RD10 IC3/RD10 IC2/RD9 IC1/RD8 INT4/RA15 INT4/RA15 INT3/RA14 INT3/RA14 VSS OSC2/CLKO/RC15 OSC2/CLKO/RC15 OSC1/CLKIN/RC12 OSC1/CLKIN/RC12 VDD TDO/RA5 TDI/RA4 SDA2/RA3 SCL2/RA2 SCL1/RG2 SDA1/RG3 SCK1/INT0/RF6 SDI1/RF7 SDO1/RF8 U1RX/RF2 U1TX/RF3 PGC1/EMUC1/AN6/OCFA/RB6 PGD1/EMUD1/AN7/RB7 VREF-/RA9 VREF+/RA10 /RA10 AVDD AVSS AN8/RB8 AN9/RB9 AN10/RB10 AN10/RB10 AN11/RB11 AN11/RB11 VSS VDD TCK/RA1 U2RTS/RF13 U2RTS/RF13 U2CTS/RF12 U2CTS/RF12 AN12/RB12 AN12/RB12 AN13/RB13 AN13/RB13 AN14/RB14 AN14/RB14 AN15/OCFB/CN12/RB15 AN15/OCFB/CN12/RB15 VSS VDD IC7/U1CTS/CN20/RD14 IC7/U1CTS/CN20/RD14 IC8/U1RTS/CN21/RD15 IC8/U1RTS/CN21/RD15 U2RX/CN17/RF4 U2RX/CN17/RF4 U2TX/CN18/RF5 U2TX/CN18/RF5 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 PGD3/EMUD3/AN0/CN2/RB0 1 2 3 4 © 2007 Microchip Technology Inc. Preliminary DS70152D-page 23 dsPIC33F/PIC24H PROGRAMMING SPECIFICATION Pin Diagrams (Continued) 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 AN28/RE4 AN28/RE4 AN27/RE3 AN27/RE3 AN26/RE2 AN26/RE2 RG13 RG12 RG14 AN25/RE1 AN25/RE1 AN24/RE0 AN24/RE0 AN23/CN23/RA7 AN23/CN23/RA7 AN22/CN22/RA6 AN22/CN22/RA6 C2RX/RG0 C2TX/RG1 C1TX/RF1 C1RX/RF0 VDD VDDCORE OC8/CN16/RD7 OC8/CN16/RD7 OC7/CN15/RD6 OC7/CN15/RD6 OC6/CN14/RD5 OC6/CN14/RD5 OC5/CN13/RD4 OC5/CN13/RD4 IC6/CN19/RD13 IC6/CN19/RD13 IC5/RD12 IC5/RD12 OC4/RD3 OC3/RD2 OC2/RD1 100-Pin TQFP RG15 VDD AN29/RE5 AN29/RE5 AN30/RE6 AN30/RE6 AN31/RE7 AN31/RE7 AN16/T2CK/T7CK/RC1 AN16/T2CK/T7CK/RC1 AN17/T3CK/T6CK/RC2 AN17/T3CK/T6CK/RC2 AN18/T4CK/T9CK/RC3 AN18/T4CK/T9CK/RC3 AN19/T5CK/T8CK/RC4 AN19/T5CK/T8CK/RC4 SCK2/CN8/RG6 SDI2/CN9/RG7 SDO2/CN10/RG8 SDO2/CN10/RG8 MCLR SS2/CN11/RG9 SS2/CN11/RG9 VSS VDD TMS/RA0 AN20/INT1/RA12 AN20/INT1/RA12 AN21/INT2/RA13 AN21/INT2/RA13 AN5/CN7/RB5 AN4/CN6/RB4 75 VSS 2 3 4 5 6 7 8 9 10 11 12 74 73 PGC2/EMUC2/SOSCO/T1CK/CN0/RC14 PGC2/EMUC2/SOSCO/T1CK/CN0/RC14 PGD2/EMUD2/SOSCI/CN1/RC13 PGD2/EMUD2/SOSCI/CN1/RC13 72 OC1/RD0 71 70 69 IC4/RD11 IC4/RD11 IC3/RD10 IC3/RD10 IC2/RD9 68 67 66 IC1/RD8 INT4/RA15 INT4/RA15 PIC24HJ256GP610 PIC24HJ256GP610 13 14 15 16 17 18 19 20 21 22 23 24 25 65 64 63 62 61 60 59 58 INT3/RA14 INT3/RA14 VSS OSC2/CLKO/RC15 OSC2/CLKO/RC15 OSC1/CLKIN/RC12 OSC1/CLKIN/RC12 VDD TDO/RA5 TDI/RA4 SDA2/RA3 SCL2/RA2 57 56 55 54 SCL1/RG2 SDA1/RG3 SCK1/INT0/RF6 53 52 51 SDO1/RF8 U1RX/RF2 SDI1/RF7 U1TX/RF3 PGC1/EMUC1/AN6/OCFA/RB6 PGD1/EMUD1/AN7/RB7 VREF-/RA9 VREF+/RA10 /RA10 AVDD AVSS AN8/RB8 AN9/RB9 AN10/RB10 AN10/RB10 AN11/RB11 AN11/RB11 VSS VDD TCK/RA1 U2RTS/RF13 U2RTS/RF13 U2CTS/RF12 U2CTS/RF12 AN12/RB12 AN12/RB12 AN13/RB13 AN13/RB13 AN14/RB14 AN14/RB14 AN15/OCFB/CN12/RB15 AN15/OCFB/CN12/RB15 VSS VDD IC7/U1CTS/CN20/RD14 IC7/U1CTS/CN20/RD14 IC8/U1RTS/CN21/RD15 IC8/U1RTS/CN21/RD15 U2RX/CN17/RF4 U2RX/CN17/RF4 U2TX/CN18/RF5 U2TX/CN18/RF5 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 AN3/CN5/RB3 AN2/SS1/CN4/RB2 PGC3/EMUC3/AN1/CN3/RB1 PGD3/EMUD3/AN0/CN2/RB0 1 DS70152D-page 24 Preliminary © 2007 Microchip Technology Inc. dsPIC33F/PIC24H PROGRAMMING SPECIFICATION Pin Diagrams (Continued) 18-PIN 18-PIN SDIP 18-PIN 18-PIN SOIC 1 18 VDD PGD2/EMUD2/AN0/VREF+/CN2/RA0 2 17 VSS PGC2/EMUC2/AN1/VREF-/CN3/RA1 3 16 AN6/RP15/CN11/RB15 AN6/RP15/CN11/RB15 PGD1/EMUD1/AN2/RP0/CN4/RB0 4 15 AN7/RP14/CN12/RB14 AN7/RP14/CN12/RB14 PGC1/EMUC1/AN3/RP1/CN5/RB1 5 14 VDDCORE OSCI/CLKI/CN30/RA2 OSCI/CLKI/CN30/RA2 6 13 VSS OSCO/CLKO/CN29/RA3 OSCO/CLKO/CN29/RA3 7 12 SCL1/RP9/CN21/RB9 SCL1/RP9/CN21/RB9 PGD3/EMUD3/SOSCI/RP4/CN1/RB4 8 11 SDA1/RP8/CN22/RB8 SDA1/RP8/CN22/RB8 PGC3/EMUC3/SOSCO/T1CK/CN0/RA4 9 10 INT0/RP7/CN23/RB7 INT0/RP7/CN23/RB7 © 2007 Microchip Technology Inc. dsPIC33FJ12GP201 PIC24HJ12GP201 PIC24HJ12GP201 MCLR Preliminary DS70152D-page 25 dsPIC33F/PIC24H PROGRAMMING SPECIFICATION Pin Diagrams (Continued) 20-PIN 20-PIN SDIP 20-PIN 20-PIN SSOP 1 20 VDD PGD2/EMUD2/AN0/VREF+/CN2/RA0 2 19 s sV PGC2/EMC2/AN1/VREF-/CN3/RA1 3 18 PWM1L1/RP15/CN11/RB15 PWM1L1/RP15/CN11/RB15 PGD1/EMUD1/AN2/RP0/CN4/RB0 4 17 PWM1H1/RP14/CN12/RB14 PWM1H1/RP14/CN12/RB14 PGC1/EMUC1/AN3/RP1/CN5/RB1 5 16 PWM1L2/RP13/CN13/RB13 PWM1L2/RP13/CN13/RB13 VSS 6 15 PWM1H2/RP12/CN14/RB12 PWM1H2/RP12/CN14/RB12 OSCI/CLKI/CN30/RA2 OSCI/CLKI/CN30/RA2 7 14 VDDCORE OSCO/CLKO/CN29/RA3 OSCO/CLKO/CN29/RA3 8 13 PWM2L1/SDA1/RP9/CN21/RB9 PWM2L1/SDA1/RP9/CN21/RB9 PGD3/EMUD3/SOSCI/RP4/CN1/RB4 9 12 PWM2H1/SCL1/RP8/CN22/RB8 PWM2H1/SCL1/RP8/CN22/RB8 10 11 INT0/RP7/CN23/RB7 INT0/RP7/CN23/RB7 PGC3/EMUC3/SOSCO/T1CK/CN0/RA4 dsPIC33FJ12MC201 MCLR Pin Diagrams (Continued) 28-PIN 28-PIN SDIP 28-PIN 28-PIN SOIC 1 28 PGD2/EMUD2/AN0/VREF+/CN2/RA0 2 27 ss VA PGC2/EMUC2/AN1/VREF-/CN3/RA1 3 26 AN6/RP15/CN11/RB15 AN6/RP15/CN11/RB15 PGD1/EMUD1/AN2/RP0/CN4/RB0 4 25 AN7/RP14/CN12/RB14 AN7/RP14/CN12/RB14 PGC1/EMUC1/AN3/RP1/CN5/RB1 5 24 AN8/RP13/CN13/RB13 AN8/RP13/CN13/RB13 AN4/RP2/CN6/RB2 6 23 AN9/RP12/CN14/RB12 AN9/RP12/CN14/RB12 AN5/RP3/CN7/RB3 7 22 TMS/RP11/CN15/RB11 TMS/RP11/CN15/RB11 ssV 8 21 TDI/RP10/CN16/RB10 TDI/RP10/CN16/RB10 20 EROCDDV 9 DD VA OSCO/CLK1/CN30/RA2 OSCO/CLK1/CN30/RA2 dsPIC33FJ12GP202 PIC24HJ12GP202 PIC24HJ12GP202 MCLR OSCI/CLKI/CN29/RA3 OSCI/CLKI/CN29/RA3 19 PGD3/EMUD3/SOSC/RP4/CN1/RB4 11 18 TDO/SDA1/RP9/CN21/RB9 TDO/SDA1/RP9/CN21/RB9 PGC3/EMUC3/SOSCO/T1CK/CN0/RA4 12 17 TCK/SCL1/RP8/CN22/RB8 TCK/SCL1/RP8/CN22/RB8 DDV 13 16 INT0/RP7/CN23/RB7 INT0/RP7/CN23/RB7 ASDA1/RP5/CN27/RB5 ASDA1/RP5/CN27/RB5 14 15 ASCL1/RP6/CN24/RB6 ASCL1/RP6/CN24/RB6 Preliminary ssV DS70152D-page 26 10 © 2007 Microchip Technology Inc. dsPIC33F/PIC24H PROGRAMMING SPECIFICATION Pin Diagrams (Continued) 28-PIN 28-PIN SDIP 28-PIN 28-PIN SOIC 1 28 AV DD PGD2/EMUD2/AN0/VREF+/CN2/RA0 2 27 AV PGC2/EMUC2/AN1/VREF-/CN3/RA1 3 26 PWM1L1/RP15/CN11/RB15 PWM1L1/RP15/CN11/RB15 PGD1/EMUD1/AN2/RP0/CN4/RB0 4 25 PWM1H1/RP14/CN12/RB14 PWM1H1/RP14/CN12/RB14 PGC1/EMUC1/AN3/RP1/CN5/RB1 5 24 PWM1L2/RP13/CN13/RB13 PWM1L2/RP13/CN13/RB13 AN4/RP2/CN6/RB2 6 23 PWM1H2/RP12/CN14/RB12 PWM1H2/RP12/CN14/RB12 AN5/RP3/CN7/RB3 7 22 TMS/PWM1L3/RP11/CN15/RB11 TMS/PWM1L3/RP11/CN15/RB11 ssV 8 21 TDI/PWM1H3/RP10/CN16/RB10 TDI/PWM1H3/RP10/CN16/RB10 OSCI/CLKI/CN30/RA2 OSCI/CLKI/CN30/RA2 9 V 20 ss dsPIC33FJ12MC202 MCLR DDCORE 19 Vss 11 18 TDO/PWM2L1/SDA1/RP9/CN21/RB9 TDO/PWM2L1/SDA1/RP9/CN21/RB9 PGC3/EMUC3/SOSCO/T1CK/CN0/RA4 12 17 TCK/PWM2H1/SCL1/RP8/CN22/RB8 TCK/PWM2H1/SCL1/RP8/CN22/RB8 V DD 13 16 INT0/RP7/CN23/RB7 INT0/RP7/CN23/RB7 ASDA1/RP5/CN27/RB5 ASDA1/RP5/CN27/RB5 14 15 ASCL1/RP6/CN24/RB6 ASCL1/RP6/CN24/RB6 OSCO/CLKO/CN29/RA3 OSCO/CLKO/CN29/RA3 10 PGD3/EMUD3/SOSCI/RP4/CN1/RB4 © 2007 Microchip Technology Inc. Preliminary DS70152D-page 27 dsPIC33F/PIC24H PROGRAMMING SPECIFICATION Pin Diagrams (Continued) 28 27 26 25 24 23 AN7/RP14/CN12/RB14 AN7/RP14/CN12/RB14 AN6/RP15/CN11/RB15 AN6/RP15/CN11/RB15 AVSS AVDD MCLR PGD2/EMUD2/AN0/VREF+/CN2/RA0 PGC2/EMUC2/AN1/VREF-/CN3/RA1 28-Pin QFN 6*6mm 22 PGD1/EMUD1/AN2/RP0/CN4/RB0 1 21 AN8/RP13/CN13/RB13 AN8/RP13/CN13/RB13 PGC1/EMUC1/AN3/RP1/CN5/RB1 2 20 AN9/RP12/CN14/RB12 AN9/RP12/CN14/RB12 AN4/RP2/CN6/RB2 3 19 TMS/RP11/CN15/RB11 TMS/RP11/CN15/RB11 18 TDI/RP10/CN16/RB10 TDI/RP10/CN16/RB10 dsPIC33FJ12GP202 PIC24HJ12GP202 PIC24HJ12GP202 V DDCORE OSCI/CLKI/CN30/RA2 OSCI/CLKI/CN30/RA2 6 16 V SS OSCO/CLKO/CN29/RA3 OSCO/CLKO/CN29/RA3 7 15 DS70152D-page 28 9 10 11 12 13 TDO/SDA1/RP9/CN21/RB9 TDO/SDA1/RP9/CN21/RB9 14 TCK/SCL1/RP8/CN22/RB8 TCK/SCL1/RP8/CN22/RB8 PGD3/EMUD3/SOSCI/RP4/CN1/RB4 8 INT0/RP7/CN23/RB7 INT0/RP7/CN23/RB7 17 ASCL1/RP6/CN24/RB6 ASCL1/RP6/CN24/RB6 5 ASDA1/RP5/CN27/RB5 ASDA1/RP5/CN27/RB5 VSS V DD 4 PGC3/EMUC3/SOSCO/T1CK/CN0/RA4 AN5/RP3/CN7/RB3 Preliminary © 2007 Microchip Technology Inc. dsPIC33F/PIC24H PROGRAMMING SPECIFICATION Pin Diagrams (Continued) 25 23 22 AV ss AVDD MCLR 26 PWM1H1/ RP14/CN12/RB14 RP14/CN12/RB14 27 PWM1L1/RP15/CN11/RB15 PWM1L1/RP15/CN11/RB15 28 PGD2/EMUD2/AN0/VREF+/CN2/RA0 PGC2/EMUC2/AN1/VREF-/CN3/RA1 28-Pin QFN 6*6mm 24 PGD1/EMUD1/AN2/RP0/CN4/RB0 1 21 PWM1L2/RP13/CN13/RB13 PWM1L2/RP13/CN13/RB13 PGC1/EMUC1/AN3/RP1/CN5/RB1 2 20 PWM1H2/RP12/CN14/RB12 PWM1H2/RP12/CN14/RB12 AN4/RP2/CN6/RB2 3 19 TMS/PWM1L3/RP11/CN15/RB11 TMS/PWM1L3/RP11/CN15/RB11 AN5/RP3/CN7/RB3 4 18 TDI/PWM1H3/RP10/CN16/RB10 TDI/PWM1H3/RP10/CN16/RB10 VSS 5 17 V DDCORE OSCI/CLKI/CN30/RA2 OSCI/CLKI/CN30/RA2 6 16 VSS OSCO/CLKO/CN29/RA3 OSCO/CLKO/CN29/RA3 7 15 TDO/PWM2L1/SDA1/RP9/CN21/RB9 TDO/PWM2L1/SDA1/RP9/CN21/RB9 © 2007 Microchip Technology Inc. 11 12 13 14 ASCL1/RP6/CN24/RB6 ASCL1/RP6/CN24/RB6 INT0/RP7/CN23/RB7 INT0/RP7/CN23/RB7 TCK/PWM2H1/SCL1/RP8/CN22/RB8 TCK/PWM2H1/SCL1/RP8/CN22/RB8 PGC3/EMUC3/SOSCO/T1CK/CN0/RA4 10 ASDA1/RP5/CN27/RB5 ASDA1/RP5/CN27/RB5 9 VDD 8 PGD3/EMUD3/SOSCI/RP4/CN1/RB4 dsPIC33FJ12MC202 Preliminary DS70152D-page 29 dsPIC33F/PIC24H PROGRAMMING SPECIFICATION 2.4 Memory Map The program memory map extends from 0x0 to 0xFFFFFE. Code storage is located at the base of the memory map and supports up to 88K instructions (about 256 Kbytes). Table 2-2 shows the program memory size and number of erase and program blocks present in each device variant. Each erase block, or page, contains 512 instructions and each program block, or row, contains 64 instructions. Locations 0x800000 through 0x800FFE are reserved for executive code memory. This region stores the programming executive and the debugging executive. The programming executive is used for device pro- TABLE 2-2: gramming and the debug executive is used for in-circuit debugging. This region of memory can not be used to store user code. Locations 0xF80000 through 0xF80017 are reserved for the device Configuration registers. Locations 0xFF0000 and 0xFF0002 are reserved for the Device ID Word registers. These bits can be used by the programmer to identify what device type is being programmed. They are described in Section 7.0 "Device ID". The Device ID registers read out normally, even after code protection is applied. Figure 2-3 shows the memory map for the dsPIC33F/ PIC24H PIC24H family variants. CODE MEMORY SIZE User Memory Address Limit (Instruction Words) Write Blocks Erase Blocks Executive Memory Address Limit (Instruction Words) dsPIC33FJ64GP206 0x00ABFE (22K) 344 43 0x800FFE (2K) dsPIC33FJ64GP306 0x00ABFE (22K) 344 43 0x800FFE (2K) dsPIC33FJ64GP310 0x00ABFE (22K) 344 43 0x800FFE (2K) dsPIC33FJ64GP706 0x00ABFE (22K) 344 43 0x800FFE (2K) dsPIC33FJ64GP708 0x00ABFE (22K) 344 43 0x800FFE (2K) dsPIC33FJ64GP710 0x00ABFE (22K) 344 43 0x800FFE (2K) dsPIC33FJ128GP206 0x0157FE (44K) 688 86 0x800FFE (2K) dsPIC33FJ128GP306 0x0157FE (44K) 688 86 0x800FFE (2K) dsPIC33FJ128GP310 0x0157FE (44K) 688 86 0x800FFE (2K) dsPIC33FJ128GP706 0x0157FE (44K) 688 86 0x800FFE (2K) dsPIC33FJ128GP708 0x0157FE (44K) 688 86 0x800FFE (2K) dsPIC33F/PIC24H Device dsPIC33FJ128GP710 0x0157FE (44K) 688 86 0x800FFE (2K) dsPIC33FJ256GP506 0x02ABFE (88K) 1368 171 0x800FFE (2K) dsPIC33FJ256GP510 0x02ABFE (88K) 1368 171 0x800FFE (2K) dsPIC33FJ256GP710 0x02ABFE (88K) 1368 171 0x800FFE (2K) dsPIC33FJ64MC506 0x00ABFE (22K) 344 43 0x800FFE (2K) dsPIC33FJ64MC508 0x00ABFE (22K) 344 43 0x800FFE (2K) dsPIC33FJ64MC510 0x00ABFE (22K) 344 43 0x800FFE (2K) dsPIC33FJ64MC706 0x00ABFE (22K) 344 43 0x800FFE (2K) dsPIC33FJ64MC710 0x00ABFE (22K) 344 43 0x800FFE (2K) dsPIC33FJ128MC506 0x0157FE (44K) 688 86 0x800FFE (2K) dsPIC33FJ128MC510 0x0157FE (44K) 688 86 0x800FFE (2K) dsPIC33FJ128MC706 0x0157FE (44K) 688 86 0x800FFE (2K) dsPIC33FJ128MC708 0x0157FE (44K) 688 86 0x800FFE (2K) dsPIC33FJ128MC710 0x0157FE (44K) 688 86 0x800FFE (2K) dsPIC33FJ256MC510 0x02ABFE (88K) 1368 171 0x800FFE (2K) dsPIC33FJ256MC710 0x02ABFE (88K) 1368 171 0x800FFE (2K) PIC24HJ64GP206 PIC24HJ64GP206 0x00ABFE (22K) 344 43 0x800FFE (2K) PIC24HJ64GP210 PIC24HJ64GP210 0x00ABFE (22K) 344 43 0x800FFE (2K) PIC24HJ64GP506 PIC24HJ64GP506 0x00ABFE (22K) 344 43 0x800FFE (2K) PIC24HJ64GP510 PIC24HJ64GP510 0x00ABFE (22K) 344 43 0x800FFE (2K) PIC24HJ128GP206 PIC24HJ128GP206 0x0157FE (44K) 688 86 0x800FFE (2K) PIC24HJ128GP210 PIC24HJ128GP210 0x0157FE (44K) 688 86 0x800FFE (2K) DS70152D-page 30 Preliminary © 2007 Microchip Technology Inc. dsPIC33F/PIC24H PROGRAMMING SPECIFICATION TABLE 2-2: CODE MEMORY SIZE (CONTINUED) PIC24HJ128GP306 PIC24HJ128GP306 0x0157FE (44K) 688 86 0x800FFE (2K) PIC24HJ128GP310 PIC24HJ128GP310 0x0157FE (44K) 688 86 0x800FFE (2K) PIC24HJ128GP506 PIC24HJ128GP506 0x0157FE (44K) 688 86 0x800FFE (2K) PIC24HJ128GP510 PIC24HJ128GP510 0x0157FE (44K) 688 86 0x800FFE (2K) PIC24HJ256GP206 PIC24HJ256GP206 0x02ABFE (88K) 1368 171 0x800FFE (2K) PIC24HJ256GP210 PIC24HJ256GP210 0x02ABFE (88K) 1368 171 0x800FFE (2K) PIC24HJ256GP610 PIC24HJ256GP610 0x02ABFE (88K) 1368 171 0x800FFE (2K) dsPIC33FJ12GP201 0x001FFE (4K) 64 8 0x8007FE (1K) dsPIC33FJ12GP202 0x001FFE (4K) 64 8 0x8007FE (1K) dsPIC33FJ12MC201 0x001FFE (4K) 64 8 0x8007FE (1K) dsPIC33FJ12MC202 0x001FFE (4K) 64 8 0x8007FE (1K) PIC24HJ12GP201 PIC24HJ12GP201 0x001FFE (4K) 64 8 0x8007FE (1K) PIC24HJ12GP202 PIC24HJ12GP202 0x001FFE (4K) 64 8 0x8007FE (1K) © 2007 Microchip Technology Inc. Preliminary DS70152D-page 31 dsPIC33F/PIC24H PROGRAMMING SPECIFICATION FIGURE 2-3: PROGRAM MEMORY MAP 0x000000 User Flash Code Memory (87552 x 24-bit) User Memory Space 0x02ABFE 0x02AC00 Reserved 0x7FFFFE 0x800000 Executive Code Memory (2048 x 24-bit) 0x800FFE 0x801000 Configuration Memory Space Reserved Configuration Registers (12 x 8-bit) 0xF7FFFE 0xF80000 0xF80017 0xF80018 Reserved Device ID (2 x 16-bit) Reserved Note: 0xFEFFFE 0xFF0000 0xFF0002 0xFF0004 0xFFFFFE The address boundaries for user Flash and Executive code memory are device dependent. DS70152D-page 32 Preliminary © 2007 Microchip Technology Inc. dsPIC33F/PIC24H PROGRAMMING SPECIFICATION 3.0 DEVICE PROGRAMMING ­ ENHANCED ICSP 3.1 This section discusses programming the device through Enhanced ICSP and the programming executive. The programming executive resides in executive memory (separate from code memory) and is executed when Enhanced ICSP Programming mode is entered. The programming executive provides the mechanism for the programmer (host device) to program and verify the dsPIC33F/PIC24H Programming Specification family devices using a simple command set and communication protocol. There are several basic functions provided by the programming executive: · · · · · Read Memory Erase Memory Program Memory Blank Check Read Executive Firmware Revision Overview of the Programming Process Figure 3-1 shows the high-level overview of the programming process. After entering Enhanced ICSP mode, the programming executive is verified. Next, the device is erased. Then, the code memory is programmed, followed by the nonvolatile device Configuration registers. Code memory (including the Configuration registers) is then verified to ensure that programming was successful. After the programming executive has been verified in memory (or loaded if not present), the dsPIC33F/ PIC24H PIC24H Programming Specification can be programmed using the command set shown in Table 3-1. FIGURE 3-1: The programming executive performs the low-level tasks required for erasing, programming and verifying a device. This allows the programmer to program the device by issuing the appropriate commands and data. Table 3-1 summarizes the commands. A detailed description for each command is provided in Section 4.2 "Programming Executive Commands". TABLE 3-1: Description Start Enter Enhanced ICSPTM Perform Bulk Erase COMMAND SET SUMMARY Command HIGH-LEVEL ENHANCED ICSPTM PROGRAMMING FLOW Program Memory SCHECK Sanity check READC Read Configuration registers or Device ID registers READP Read code memory PROGC Program a Configuration register and verify PROGP Program one row of code memory and verify PROGW Program one word of code memory and verify QBLANK Query if the code memory is blank QVER Verify Program Query the software version Verify Configuration Bits Exit Enhanced ICSP The programming executive uses the device's data RAM for variable storage and program execution. After the programming executive has run, no assumptions should be made about the contents of data RAM. © 2007 Microchip Technology Inc. Program Configuration Bits Preliminary Done DS70152D-page 33 dsPIC33F/PIC24H PROGRAMMING SPECIFICATION 3.2 Confirming the Presence of the Programming Executive 3.3 Before programming can begin, the programmer must confirm that the programming executive is stored in executive memory. The procedure for this task is shown in Figure 3-2. First, ICSP mode is entered. Then, the unique Application ID Word stored in executive memory is read. If the programming executive is resident, the Application ID Word is 0xBB, which means programming can resume as normal. However, if the Application ID Word is not 0xBB, the programming executive must be programmed to executive code memory using the method described in Section 6.0 "Programming the Programming Executive to Memory". Section 5.0 "Device Programming ­ ICSP" describes the ICSP programming method. Section 5.11 "Reading the Application ID Word" describes the procedure for reading the Application ID Word in ICSP mode. FIGURE 3-2: CONFIRMING PRESENCE OF PROGRAMMING EXECUTIVE Start As shown in Figure 3-3, entering Enhanced ICSP Program/Verify mode requires three steps: 1. 2. 3. The MCLR pin is briefly driven high then low. A 32-bit key sequence is clocked into PGD. MCLR is then driven high within a specified period of time and held. The programming voltage applied to MCLR is VIH, which is essentially VDD in the case of dsPIC33F/ PIC24H PIC24H devices. There is no minimum time requirement for holding at VIH. After VIH is removed, an interval of at least P18 must elapse before presenting the key sequence on PGD. The key sequence is a specific 32-bit pattern, `0100 1101 0100 0011 0100 1000 0101 0000' (more easily remembered as 0x4D434850 in hexadecimal format). The device will enter Program/Verify mode only if the key sequence is valid. The Most Significant bit (MSb) of the most significant nibble must be shifted in first. Once the key sequence is complete, VIH must be applied to MCLR and held at that level for as long as Program/Verify mode is to be maintained. An interval time of at least P19 and P7 must elapse before presenting data on PGD. Signals appearing on PGD before P7 has elapsed will not be interpreted as valid. On successful entry, the program memory can be accessed and programmed in serial fashion. While in the Program/Verify mode, all unused I/Os are placed in the high-impedance state. Enter ICSPTM Mode Read the Application ID from Address 0x807F0 Is Application ID 0xBB? Entering Enhanced ICSP Mode No Yes Prog. Executive is Resident in Memory Prog. Executive must be Programmed Finish DS70152D-page 34 Preliminary © 2007 Microchip Technology Inc. dsPIC33F/PIC24H PROGRAMMING SPECIFICATION FIGURE 3-3: ENTERING ENHANCED ICSPTM MODE P6 P14 MCLR P19 VDD P7 VIH VIH Program/Verify Entry Code = 0x4D434850 0 b31 PGD 1 b30 0 b29 0 b28 1 b27 . 0 b3 0 b2 0 b1 0 b0 PGC P1A P1B P18 3.4 Blank Check 3.5 The term "Blank Check" implies verifying that the device has been successfully erased and has no programmed memory locations. A blank or erased memory location is always read as a `1'. The Device ID registers (0xFF0000:0xFF0002) can be ignored by the Blank Check since this region stores device information that cannot be erased. The device Configuration registers are also ignored by the Blank Check. Additionally, all unimplemented memory space should be ignored from the Blank Check. The QBLANK command is used for the Blank Check. It determines if the code memory is erased by testing these memory regions. A `BLANK' or `NOT BLANK' response is returned. If it is determined that the device is not blank, it must be erased before attempting to program the chip. 3.5.1 Code Memory Programming PROGRAMMING METHODOLOGY Code memory is programmed with the PROGP command. PROGP programs one row of code memory starting from the memory address specified in the command. The number of PROGP commands required to program a device depends on the number of write blocks that must be programmed in the device. A flowchart for programming code memory is shown in Figure 3-4. In this example, all 88K instruction words of a dsPIC33F/PIC24H device are programmed. First, the number of commands to send (called `RemainingCmds' in the flowchart) is set to 1368 and the destination address (called `BaseAddress') is set to `0'. Next, one write block in the device is programmed with a PROGP command. Each PROGP command contains data for one row of code memory of the dsPIC33F/PIC24H. After the first command is processed successfully, `RemainingCmds' is decremented by `1' and compared with `0'. Since there are more PROGP commands to send, `BaseAddress' is incremented by 0x80 to point to the next row of memory. On the second PROGP command, the second row is programmed. This process is repeated until the entire device is programmed. Note: © 2007 Microchip Technology Inc. Preliminary If a bootloader needs to be programmed, the bootloader code must not be programmed into the first page of code memory. For example, if a bootloader located at address 0x200 attempts to erase the first page, it would inadvertently erase itself. Instead, program the bootloader into the second page, e.g. 0x400. DS70152D-page 35 dsPIC33F/PIC24H PROGRAMMING SPECIFICATION FIGURE 3-4: FLOWCHART FOR PROGRAMMING CODE MEMORY 3.5.2 After code memory is programmed, the contents of memory can be verified to ensure that programming was successful. Verification requires code memory to be read back and compared against the copy held in the programmer's buffer. Start The READP command can be used to read back all the programmed code memory. BaseAddress = 0x0 RemainingCmds = 1368 Alternatively, you can have the programmer perform the verification after the entire device is programmed, using a checksum computation. Send PROGP Command to Program BaseAddress Is PROGP response PASS? 3.5.3 CHECKSUM COMPUTATION Only the Configuration registers are included in the checksum computation. The Device ID and Unit ID are not included in the checksum computation. No Table 3-2 shows how this 16-bit computation can be made for each dsPIC33F and PIC24H PIC24H device. Computations for read code protection are shown both enabled and disabled. The checksum values shown here assume that the Configuration registers are also erased. However, when code protection is enabled, the value of the FGS register is assumed to be 0x5. Yes RemainingCmds = RemainingCmds ­ 1 BaseAddress = BaseAddress + 0x80 No PROGRAMMING VERIFICATION Is RemainingCmds `0'? Yes Finish DS70152D-page 36 Failure Report Error Preliminary © 2007 Microchip Technology Inc. dsPIC33F/PIC24H PROGRAMMING SPECIFICATION TABLE 3-2: CHECKSUM COMPUTATION Device dsPIC33FJ64GP206 Read Code Protection Disabled Checksum Computation CFGB + SUM(0:00ABFF 00ABFF) Erased Value Value with 0xAAAAAA at 0x0 and Last Code Address 0x03BC 0x01BE Enabled dsPIC33FJ64GP306 CFGB 0x05BA 0x05BA Disabled CFGB + SUM(0:00ABFF 00ABFF) 0x03BC 0x01BE Enabled dsPIC33FJ64GP310 CFGB 0x05BA 0x05BA Disabled CFGB + SUM(0:00ABFF 00ABFF) 0x03BC 0x01BE Enabled dsPIC33FJ64GP706 CFGB 0x05BA 0x05BA Disabled CFGB + SUM(0:00ABFF 00ABFF) 0x03BC 0x01BE Enabled dsPIC33FJ64GP708 CFGB 0x05BA 0x05BA Disabled CFGB + SUM(0:00ABFF 00ABFF) 0x03BC 0x01BE Enabled dsPIC33FJ64GP710 CFGB 0x05BA 0x05BA Disabled CFGB + SUM(0:00ABFF 00ABFF) 0x03BC 0x01BE Enabled dsPIC33FJ128GP206 Disabled Enabled dsPIC33FJ128GP306 Disabled Enabled dsPIC33FJ128GP310 Disabled Enabled dsPIC33FJ128GP706 Disabled Enabled dsPIC33FJ128GP708 Disabled Enabled dsPIC33FJ128GP710 Disabled Enabled dsPIC33FJ256GP506 Disabled Enabled dsPIC33FJ256GP510 Disabled Enabled dsPIC33FJ256GP710 Disabled Enabled CFGB 0x05BA 0x05BA CFGB + SUM(0:0157FF 0157FF) 0x01BC 0xFFBE CFGB 0x05BA 0x05BA CFGB + SUM(0:0157FF 0157FF) 0x01BC 0xFFBE CFGB 0x05BA 0x05BA CFGB + SUM(0:0157FF 0157FF) 0x01BC 0xFFBE CFGB 0x05BA 0x05BA CFGB + SUM(0:0157FF 0157FF) 0x01BC 0xFFBE CFGB 0x05BA 0x05BA CFGB + SUM(0:0157FF 0157FF) 0x01BC 0xFFBE CFGB 0x05BA 0x05BA CFGB + SUM(0:0157FF 0157FF) 0x01BC 0xFFBE CFGB 0x05BA 0x05BA CFGB + SUM(0:02ABFF 02ABFF) 0x03BC 0x01BE CFGB 0x05BA 0x05BA CFGB + SUM(0:02ABFF 02ABFF) 0x03BC 0x01BE CFGB 0x05BA 0x05BA CFGB + SUM(0:02ABFF 02ABFF) 0x03BC 0x01BE CFGB 0x05BA 0x05BA Item Description: SUM(a:b) = Byte sum of locations a to b inclusive (all 3 bytes of code memory) CFGB = Configuration Block (masked) = Byte sum of (FBS & 0xCF) + (FSS & 0xFF) + (FGS & 0x07) + (FOSCSEL & 0xA7) + (FOSC & 0xE7) + (FWDT & 0xDF) + (FPOR & 0xE7) + (FICD & 0xE3) (for dsPIC33FJ12GP201/202, dsPIC33FJ12MC201/202 and PIC24HJ12GP201/202 PIC24HJ12GP201/202) = Byte sum of (FBS & 0xCF) + (FSS & 0xCF) + (FGS & 0x07) + (FOSCSEL & 0xA7) + (FOSC & 0xC7) + (FWDT & 0xDF) + (FPOR & 0xE7) + (FICD & 0xE3) (for all other devices) © 2007 Microchip Technology Inc. Preliminary DS70152D-page 37 dsPIC33F/PIC24H PROGRAMMING SPECIFICATION TABLE 3-2: CHECKSUM COMPUTATION (CONTINUED) Device dsPIC33FJ64MC506 Read Code Protection Checksum Computation Erased Value Value with 0xAAAAAA at 0x0 and Last Code Address 0x05BA Disabled CFGB + SUM(0:00ABFF 00ABFF) 0x03BC 0x01BE CFGB 0x05BA 0x05BA Disabled CFGB + SUM(0:00ABFF 00ABFF) 0x03BC 0x01BE CFGB 0x05BA 0x05BA Disabled CFGB + SUM(0:00ABFF 00ABFF) 0x03BC 0x01BE Enabled CFGB 0x05BA 0x05BA Disabled CFGB + SUM(0:00ABFF 00ABFF) 0x03BC 0x01BE Enabled dsPIC33FJ64MC710 0x01BE 0x05BA Enabled dsPIC33FJ64MC706 0x03BC CFGB Enabled dsPIC33FJ64MC510 CFGB + SUM(0:00ABFF 00ABFF) Enabled dsPIC33FJ64MC508 Disabled CFGB 0x05BA 0x05BA CFGB + SUM(0:0157FF 0157FF) 0x01BC 0xFFBE CFGB 0x05BA 0x05BA CFGB + SUM(0:0157FF 0157FF) 0x01BC 0xFFBE CFGB 0x05BA 0x05BA CFGB + SUM(0:0157FF 0157FF) 0x01BC 0xFFBE CFGB 0x05BA 0x05BA CFGB + SUM(0:0157FF 0157FF) 0x01BC 0xFFBE CFGB 0x05BA 0x05BA CFGB + SUM(0:0157FF 0157FF) 0x01BC 0xFFBE CFGB 0x05BA 0x05BA CFGB + SUM(0:02ABFF 02ABFF) 0x03BC 0x01BE CFGB 0x05BA 0x05BA dsPIC33FJ128MC506 Disabled Enabled dsPIC33FJ128MC510 Disabled Enabled dsPIC33FJ128MC706 Disabled Enabled dsPIC33FJ128MC708 Disabled Enabled dsPIC33FJ128MC710 Disabled Enabled dsPIC33FJ256MC510 Disabled Enabled dsPIC33FJ256MC710 Disabled PIC24HJ64GP206 PIC24HJ64GP206 CFGB + SUM(0:02ABFF 02ABFF) 0x03BC 0x01BE Enabled CFGB 0x05BA 0x05BA PIC24HJ64GP210 PIC24HJ64GP210 Disabled CFGB + SUM(0:00ABFF 00ABFF) 0x03BC 0x01BE Enabled CFGB 0x05BA 0x05BA CFGB + SUM(0:00ABFF 00ABFF) 0x03BC 0x01BE CFGB 0x05BA 0x05BA Disabled CFGB + SUM(0:00ABFF 00ABFF) 0x03BC 0x01BE Enabled PIC24HJ64GP506 PIC24HJ64GP506 Disabled Enabled CFGB 0x05BA 0x05BA Item Description: SUM(a:b) = Byte sum of locations a to b inclusive (all 3 bytes of code memory) CFGB = Configuration Block (masked) = Byte sum of (FBS & 0xCF) + (FSS & 0xFF) + (FGS & 0x07) + (FOSCSEL & 0xA7) + (FOSC & 0xE7) + (FWDT & 0xDF) + (FPOR & 0xE7) + (FICD & 0xE3) (for dsPIC33FJ12GP201/202, dsPIC33FJ12MC201/202 and PIC24HJ12GP201/202 PIC24HJ12GP201/202) = Byte sum of (FBS & 0xCF) + (FSS & 0xCF) + (FGS & 0x07) + (FOSCSEL & 0xA7) + (FOSC & 0xC7) + (FWDT & 0xDF) + (FPOR & 0xE7) + (FICD & 0xE3) (for all other devices) DS70152D-page 38 Preliminary © 2007 Microchip Technology Inc. dsPIC33F/PIC24H PROGRAMMING SPECIFICATION TABLE 3-2: CHECKSUM COMPUTATION (CONTINUED) Device PIC24HJ64GP510 PIC24HJ64GP510 Read Code Protection Checksum Computation Erased Value Value with 0xAAAAAA at 0x0 and Last Code Address dsPIC33FJ12GP201 0x05BA Disabled CFGB + SUM(0:0157FF 0157FF) 0x01BC 0xFFBE CFGB 0x05BA 0x05BA Disabled CFGB + SUM(0:0157FF 0157FF) 0x01BC 0xFFBE CFGB 0x05BA 0x05BA Disabled CFGB + SUM(0:0157FF 0157FF) 0x01BC 0xFFBE CFGB 0x05BA 0x05BA Disabled CFGB + SUM(0:0157FF 0157FF) 0x01BC 0xFFBE CFGB 0x05BA 0x05BA Disabled CFGB + SUM(0:0157FF 0157FF) 0x01BC 0xFFBE CFGB 0x05BA 0x05BA Disabled CFGB + SUM(0:02ABFF 02ABFF) 0x03BC 0x01BE CFGB 0x05BA 0x05BA Disabled CFGB + SUM(0:02ABFF 02ABFF) 0x03BC 0x01BE CFGB 0x05BA 0x05BA Disabled CFGB + SUM(0:02ABFF 02ABFF) 0x03BC 0x01BE Enabled PIC24HJ256GP610 PIC24HJ256GP610 0xFFBE 0x05BA Enabled PIC24HJ256GP210 PIC24HJ256GP210 0x01BC CFGB Enabled PIC24HJ256GP206 PIC24HJ256GP206 CFGB + SUM(0:0157FF 0157FF) Enabled PIC24HJ128GP510 PIC24HJ128GP510 Disabled Enabled PIC24HJ128GP506 PIC24HJ128GP506 0x05BA Enabled PIC24HJ128GP310 PIC24HJ128GP310 0x01BE 0x05BA Enabled PIC24HJ128GP306 PIC24HJ128GP306 0x03BC CFGB Enabled PIC24HJ128GP210 PIC24HJ128GP210 CFGB + SUM(0:00ABFF 00ABFF) Enabled PIC24HJ128GP206 PIC24HJ128GP206 Disabled Enabled CFGB 0x05BA 0x05BA dsPIC33FJ12GP202 Disabled CFGB + SUM(0:001FFF 001FFF) 0xD60C 0xD40E Enabled CFGB 0x060A 0x060A dsPIC33FJ12MC201 Disabled CFGB + SUM(0:001FFF 001FFF) 0xD60C 0xD40E Enabled CFGB 0x060A 0x060A dsPIC33FJ12MC202 Disabled CFGB + SUM(0:001FFF 001FFF) 0xD60C 0xD40E Enabled CFGB 0x060A 0x060A PIC24HJ12GP201 PIC24HJ12GP201 Disabled CFGB + SUM(0:001FFF 001FFF) 0xD60C 0xD40E Enabled CFGB 0x060A 0x060A CFGB + SUM(0:001FFF 001FFF) 0xD60C 0xD40E CFGB 0x060A 0x060A Disabled CFGB + SUM(0:001FFF 001FFF) 0xD60C 0xD40E Enabled PIC24HJ12GP202 PIC24HJ12GP202 Disabled Enabled CFGB 0x060A 0x060A Item Description: SUM(a:b) = Byte sum of locations a to b inclusive (all 3 bytes of code memory) CFGB = Configuration Block (masked) = Byte sum of (FBS & 0xCF) + (FSS & 0xFF) + (FGS & 0x07) + (FOSCSEL & 0xA7) + (FOSC & 0xE7) + (FWDT & 0xDF) + (FPOR & 0xE7) + (FICD & 0xE3) (for dsPIC33FJ12GP201/202, dsPIC33FJ12MC201/202 and PIC24HJ12GP201/202 PIC24HJ12GP201/202) = Byte sum of (FBS & 0xCF) + (FSS & 0xCF) + (FGS & 0x07) + (FOSCSEL & 0xA7) + (FOSC & 0xC7) + (FWDT & 0xDF) + (FPOR & 0xE7) + (FICD & 0xE3) (for all other devices) © 2007 Microchip Technology Inc. Preliminary DS70152D-page 39 dsPIC33F/PIC24H PROGRAMMING SPECIFICATION 3.6 3.6.1 Configuration Bits Programming OVERVIEW The dsPIC33F/PIC24H has Configuration bits stored in twelve 8-bit Configuration registers, aligned on even configuration memory address boundaries. These bits can be set or cleared to select various device configurations. There are three types of Configuration bits: system operation bits, code-protect bits and unit ID bits. The system operation bits determine the power-on settings for system level components, such as oscillator and Watchdog Timer. The code-protect bits prevent program memory from being read and written. The register descriptions for the FBS, FSS, FGS, FOSCSEL, FOSC, FWDT, FPOR and FICD Configuration registers are shown in Table 3-3. The Configuration register map is shown in Table 3-4. Note: If any of the code-protect bits in FBS, FSS or FGS is clear, then the entire device must be erased before it can be reprogrammed. DS70152D-page 40 Preliminary © 2007 Microchip Technology Inc. dsPIC33F/PIC24H PROGRAMMING SPECIFICATION TABLE 3-3: dsPIC33F/PIC24H CONFIGURATION BITS DESCRIPTION Bit Field Register RBS FBS Description Boot Segment Data RAM Code Protection 11 = No RAM is reserved for Boot Segment 10 = Small-sized Boot RAM [128 bytes of RAM are reserved for Boot Segment] 01 = Medium-sized Boot RAM [256 bytes of RAM are reserved for Boot Segment] 00 = Large-sized Boot RAM [1024 bytes of RAM are reserved for Boot Segment] [Note: This bit is Reserved in dsPIC33FJ12GP201/202, dsPIC33FJ12MC201/202 and PIC24HJ12GP201/202 PIC24HJ12GP201/202.] BSS FBS Boot Segment Program Memory Code Protection 111 = No Boot Segment 110 = Standard security, Small-sized Boot Program Flash [Boot Segment ends at 0x0003FF in dsPIC33FJ12GP201/202, dsPIC33FJ12MC201/202 and PIC24HJ12GP201/202 PIC24HJ12GP201/202. Boot Segment ends at 0x0007FF in other all other devices.] 101 = Standard security, Medium-sized Boot Program Flash [Boot Segment ends at 0x0007FF in dsPIC33FJ12GP201/202, dsPIC33FJ12MC201/202 and PIC24HJ12GP201/202 PIC24HJ12GP201/202. Boot Segment ends at 0x001FFF in all other devices.] 100 = Standard security, Large-sized Boot Program Flash [Boot Segment ends at 0x000FFF in dsPIC33FJ12GP201/202, dsPIC33FJ12MC201/202 and PIC24HJ12GP201/202 PIC24HJ12GP201/202. Boot Segment ends at 0x003FFF in all other devices.] 011 = No Boot Segment 010 = High security, Small-sized Boot Program Flash [Reserved in dsPIC33FJ12GP201/202, dsPIC33FJ12MC201/202 and PIC24HJ12GP201/202 PIC24HJ12GP201/202. Boot Segment ends at 0x0007FF in all other devices.] 001 = High security, Medium-sized Boot Program Flash [Reserved in dsPIC33FJ12GP201/202, dsPIC33FJ12MC201/202 and PIC24HJ12GP201/202 PIC24HJ12GP201/202. Boot Segment ends at 0x001FFF in all other devices.] 000 = High security, Large-sized Boot Program Flash [Reserved in dsPIC33FJ12GP201/202, dsPIC33FJ12MC201/202 and PIC24HJ12GP201/202 PIC24HJ12GP201/202. Boot Segment ends at 0x003FFF in all other devices.] BWRP FBS Boot Segment Program Memory Write Protection 1 = Boot Segment program memory is not write-protected 0 = Boot program memory is write-protected © 2007 Microchip Technology Inc. Preliminary DS70152D-page 41 dsPIC33F/PIC24H PROGRAMMING SPECIFICATION TABLE 3-3: dsPIC33F/PIC24H CONFIGURATION BITS DESCRIPTION (CONTINUED) Bit Field Register Description RSS FSS Secure Segment Data RAM Code Protection 11 = No Data RAM is reserved for Secure Segment 10 = Small-sized Secure RAM [(256 ­ N) bytes of RAM are reserved for Secure Segment in all other devices.] 01 = Medium-sized Secure RAM [(2048 ­ N) bytes of RAM are reserved for Secure Segment in all other devices.] 00 = Large-sized Secure RAM [(4096 ­ N) bytes of RAM are reserved for Secure Segment in all other devices.] where N = Number of bytes of RAM reserved for Boot Sector. Note 1: This bit is Reserved in dsPIC33FJ12GP201/202, dsPIC33FJ12MC201/202 and PIC24HJ12GP201/202 PIC24HJ12GP201/202.] 2: If the defined Boot Segment size is greater than or equal to the defined Secure Segment, then the Secure Segment size selection has no effect and the Secure Segment is disabled. SSS FSS Secure Segment Program Memory Code Protection 111 = No Secure Segment 110 = Standard security, Small-sized Secure Program Flash [Secure Segment ends at 0x001FFF for dsPIC33FJ64GPxxx/ dsPIC33FJ64MCxxx/PIC24HJ64GPxxx devices, and at 0x003FFF in other devices.] 101 = Standard security, Medium-sized Secure Program Flash [Secure Segment ends at 0x003FFF for dsPIC33FJ64GPxxx/ dsPIC33FJ64MCxxx/PIC24HJ64GPxxx devices, and at 0x007FFF in other devices.] 100 = Standard security, Large-sized Secure Program Flash [Secure Segment ends at 0x007FFF for dsPIC33FJ64GPxxx/ dsPIC33FJ64MCxxx/PIC24HJ64GPxxx devices, and at 0x00FFFF in other devices.] 011 = No Secure Segment 010 = High security, Small-sized Secure Program Flash [Secure Segment ends at 0x001FFF for dsPIC33FJ64GPxxx/ dsPIC33FJ64MCxxx/PIC24HJ64GPxxx devices, and at 0x003FFF in other devices.] 001 = High security, Medium-sized Secure Program Flash [Secure Segment ends at 0x003FFF for dsPIC33FJ64GPxxx/ dsPIC33FJ64MCxxx/PIC24HJ64GPxxx devices, and at 0x007FFF in other devices.] 000 = High security, Large-sized Secure Program Flash [Secure Segment ends at 0x007FFF for dsPIC33FJ64GPxxx/ dsPIC33FJ64MCxxx/PIC24HJ64GPxxx devices, and at 0x00FFFF in other devices.] [Note: This bit is Reserved in dsPIC33FJ12GP201/202, dsPIC33FJ12MC201/202 and PIC24HJ12GP201/202 PIC24HJ12GP201/202.] SWRP DS70152D-page 42 FSS Secure Segment Program Memory Write Protection 1 = Secure Segment program memory is not write-protected 0 = Secure program memory is write-protected [Note: This bit is Reserved in dsPIC33FJ12GP201/202, dsPIC33FJ12MC201/202 and PIC24HJ12GP201/202 PIC24HJ12GP201/202.] Preliminary © 2007 Microchip Technology Inc. dsPIC33F/PIC24H PROGRAMMING SPECIFICATION TABLE 3-3: dsPIC33F/PIC24H CONFIGURATION BITS DESCRIPTION (CONTINUED) Bit Field Register Description GSS FGS General Segment Code-Protect bit 11 = Code protection is disabled 10 = Standard security code protection is enabled 0x = Reserved in dsPIC33FJ12GP201/202, dsPIC33FJ12MC201/202 and PIC24HJ12GP201/202 PIC24HJ12GP201/202. In all other devices, high security code protection is enabled. GWRP FGS General Segment Write-Protect bit 1 = General Segment program memory is not write-protected 0 = General Segment program memory is write-protected IESO FOSCSEL Two-speed Oscillator Start-Up Enable bit 1 = Start up device with FRC, then automatically switch to the user-selected oscillator source when ready 0 = Start up device with user-selected oscillator source TEMP FOSCSEL Temperature Protection Enable bit 1 = Temperature protection disabled 0 = Temperature protection enabled FNOSC FOSCSEL Initial Oscillator Source Selection bits 111 = Internal Fast RC (FRC) oscillator 110 = Reserved 101 = LPRC oscillator 100 = Secondary (LP) oscillator 011 = Primary (XT, HS, EC) oscillator with PLL 010 = Primary (XT, HS, EC) oscillator 001 = Internal Fast RC (FRC) oscillator with PLL 000 = Reserved FCKSM FOSC Clock Switching Mode bits 1x = Clock switching is disabled, Fail-Safe Clock Monitor is disabled 01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled 00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled IOL1WAY FOSC Peripheral Pin Select Configuration 1 = Allow only one reconfiguration 0 = Allow multiple reconfigurations [Note: This bit is only present in the dsPIC33FJ12GP201/202, dsPIC33FJ12MC201/202 and PIC24HJ12GP201/202 PIC24HJ12GP201/202 devices.] OSCIOFNC FOSC OSC2 Pin Function bit (except in XT and HS modes) 1 = OSC2 is clock output 0 = OSC2 is general purpose digital I/O pin POSCMD FOSC Primary Oscillator Mode Select bits 11 = Primary oscillator disabled 10 = HS crystal oscillator mode 01 = XT crystal oscillator mode 00 = EC (external clock) mode FWDTEN FWDT Watchdog Enable bit 1 = Watchdog always enabled (LPRC oscillator cannot be disabled. Clearing the SWDTEN bit in the RCON register will have no effect) 0 = Watchdog enabled/disabled by user software (LPRC can be disabled by clearing the SWDTEN bit in the RCON register) WINDIS FWDT Watchdog Timer Window Enable bit 1 = Watchdog Timer in Non-Window mode 0 = Watchdog Timer in Window mode WDTPRE FWDT Watchdog Timer Prescaler bit 1 = 1:128 0 = 1:32 © 2007 Microchip Technology Inc. Preliminary DS70152D-page 43 dsPIC33F/PIC24H PROGRAMMING SPECIFICATION TABLE 3-3: dsPIC33F/PIC24H CONFIGURATION BITS DESCRIPTION (CONTINUED) Bit Field Register WDTPOST FWDT Watchdog Timer Postscaler bits 1111 = 1:32,768 1110 = 1:16,384 . . . 0001 = 1:2 0000 = 1:1 PWMPIN FPOR Motor Control PWM Module Pin mode 1 = PWM module pins controlled by PORT register at device Reset (tri-stated) 0 = PWM module pins controlled by PWM module at device Reset (configured as output pins) HPOL FPOR Motor Control PWM High-side Polarity bit 1 = PWM module high-side output pins have active-high output polarity 0 = PWM module high-side output pins have active-low output polarity LPOL FPOR Motor Control PWM Low-side Polarity bit 1 = PWM module low-side output pins have active-high output polarity 0 = PWM module low-side output pins have active-low output polarity ALTI2C FPOR Alternate I2CTM pins 1 = I2C mapped to SDA1/SCL1 pins 0 = I2C mapped to ASDA1/SACL1 pins [Note: This bit is only present in the dsPIC33FJ12GP201/202, dsPIC33FJ12MC201/202 and PIC24HJ12GP201/202 PIC24HJ12GP201/202 devices.] FPWRT FPOR Power-on Reset Timer Value Select bits 111 = PWRT = 128 ms 110 = PWRT = 64 ms 101 = PWRT = 32 ms 100 = PWRT = 16 ms 011 = PWRT = 8 ms 010 = PWRT = 4 ms 001 = PWRT = 2 ms 000 = PWRT Disabled BKBUG FICD Background Debug Enable bit 1 = Device will reset in User mode 0 = Device will reset in Debug mode COE FICD Debugger/Emulator Enable bit 1 = Device will reset in Operational mode 0 = Device will reset in Clip-On Emulation mode JTAGEN FICD JTAG Enable bit 1 = JTAG enabled 0 = JTAG disabled ICS FICD ICD Communication Channel Select bits 11 = Communicate on PGC1/EMUC1 and PGD1/EMUD1 10 = Communicate on PGC2/EMUC2 and PGD2/EMUD2 01 = Communicate on PGC3/EMUC3 and PGD3/EMUD3 00 = Reserved, do not use - All DS70152D-page 44 Description Unimplemented (read as `0', write as `0') Preliminary © 2007 Microchip Technology Inc. dsPIC33F/PIC24H PROGRAMMING SPECIFICATION TABLE 3-4: Address dsPIC33F/PIC24H DEVICE CONFIGURATION REGISTER MAP Name Bit 7 Bit 6 Bit 5 (3) FBS RBS 0xF80002 FSS RSS(3) 0xF80004 FGS 0xF80000 0xF80006 FOSCSEL Bit 4 Bit 3 GSS - IOL1WAY(2) GWRP FNOSC - OSCIOFNC 0xF80008 FOSC 0xF8000A FWDT 0xF8000C FPOR 0xF8000E FICD 0xF80010 FUID0 FUID1 User Unit ID Byte 1 0xF80014 FUID2 User Unit ID Byte 2 0xF80016 FUID3 POSCMD User Unit ID Byte 0 0xF80012 User Unit ID Byte 3 Note 1: 2: 3: 3.6.2 FCKSM SWRP(3) SSS TEMP Bit 0 BWRP (3) - - Bit 1 BSS - - IESO Bit 2 FWDTEN WINDIS PWMPIN(1) HPOL(1) BKBUG COE - WDTPRE LPOL(1) ALTI2C(2) JTAGEN PROGRAMMING METHODOLOGY Twelve PROGC commands are required to program all the Configuration bits. A flowchart for Configuration bit programming is shown in Figure 3-5. 3.6.3 - FPWRT - ICS On the dsPIC33F General Purpose Family devices (dsPIC33FJXXXGPXXX) and PIC24H PIC24H devices, these bits are reserved (read as `1' and must be programmed as `1'). These bits are only present in the dsPIC33FJ12GP201/202, dsPIC33FJ12MC201/202 and PIC24HJ12GP201/202 PIC24HJ12GP201/202 devices. In all other devices, they are unimplemented (read as `0'). In the dsPIC33FJ12GP201/202, dsPIC33FJ12MC201/202 and PIC24HJ12GP201/202 PIC24HJ12GP201/202 devices, these bits are reserved (read as `1' and must be programmed as `1'). Configuration bits may be programmed a single byte at a time using the PROGC command. This command specifies the configuration data and Configuration register address. When Configuration bits are programmed, any unimplemented bits must be programmed with a `0' and any reserved bits must be programmed with a `1'. Note: WDTPOST If the General Code Segment CodeProtect bit (GCP) is programmed to `0', code memory is code-protected and can not be read. Code memory must be verified before enabling read protection. See Section 3.6.4 "CodeGuard Security Configuration Bits" for more information about code-protect Configuration bits. PROGRAMMING VERIFICATION After the Configuration bits are programmed, the contents of memory should be verified to ensure that the programming was successful. Verification requires the Configuration bits to be read back and compared against the copy held in the programmer's buffer. The READC command reads back the programmed Configuration bits and verifies that the programming was successful. 3.6.4 CODEGUARD SECURITY CONFIGURATION BITS The FBS, FSS and FGS Configuration registers are special Configuration registers that control the size and level of code protection for the Boot Segment, Secure Segment and General Segment, respectively. For each segment, two main forms of code protection are provided. One form prevents code memory from being written (write protection), while the other prevents code memory from being read (read protection). BWRP, SWRP and GWRP bits control write protection and BSS, SSS and GSS bits controls read protection. The Chip Erase ERASEB command sets all the code protection bits to `1', which allows the device to be programmed. When write protection is enabled, any programming operation to code memory will fail. When read protection is enabled, any read from code memory will cause a `0x0' to be read, regardless of the actual contents of code memory. Since the programming executive always verifies what it programs, attempting to program code memory with read protection enabled will also result in failure. It is imperative that all code protection bits are `1' while the device is being programmed and verified. Only after the device is programmed and verified should any of the above bits be programmed to `0'. Any unimplemented Configuration bits are read-only and read as `0'. The reserved bits are read-only and read as `1'. © 2007 Microchip Technology Inc. Preliminary DS70152D-page 45 dsPIC33F/PIC24H PROGRAMMING SPECIFICATION In addition to code memory protection, a part of Data RAM can be configured to be accessible only by code resident in the Boot Segment and/or Secure Segment. The sizes of these "reserved" sections are user-configurable, using the RBS and RSS bits. Note: 3.6.5 USER UNIT ID The dsPIC33F/PIC24H devices provide four 8-bit Configuration registers (FUID0 through FUID3) for the user to store product-specific information, such as unit serial numbers and other product manufacturing data. All bits in the FBS, FSS and FGS Configuration registers can only be programmed to a value of `0'. the ERASEB command is the only way to reprogram code-protect bits from ON (`0') to OFF (`1'). FIGURE 3-5: CONFIGURATION BIT PROGRAMMING FLOW Start ConfigAddress = 0xF80000 Send PROGC Command Is PROGC response PASS? No Yes ConfigAddress = ConfigAddress + 2 No Is ConfigAddress 0xF80018? Yes Failure Report Error Finish 3.7 Exiting Enhanced ICSP Mode FIGURE 3-6: Exiting Program/Verify mode is done by removing VIH from MCLR, as shown in Figure 3-6. The only requirement for exit is that an interval P16 should elapse between the last clock and program signals on PGC and PGD before removing VIH. EXITING ENHANCED ICSPTM MODE P16 P17 VIH MCLR VDD PGD VIH PGC PGD = Input DS70152D-page 46 Preliminary © 2007 Microchip Technology Inc. dsPIC33F/PIC24H PROGRAMMING SPECIFICATION 4.0 THE PROGRAMMING EXECUTIVE 4.1 Programming Executive Communication The programmer and programming executive have a master-slave relationship, where the programmer is the master programming device and the programming executive is the slave. All communication is initiated by the programmer in the form of a command. Only one command at a time can be sent to the programming executive. In turn, the programming executive only sends one response to the programmer after receiving and processing a command. The programming executive command set is described in Section 4.2 "Programming Executive Commands". The response set is described in Section 4.3 "Programming Executive Responses". 4.1.1 COMMUNICATION INTERFACE AND PROTOCOL The ICSP/Enhanced ICSP interface is a 2 wire SPI implemented using the PGC and PGD pins. The PGC pin is used as a clock input pin and the clock source must be provided by the programmer. The PGD pin is used for sending command data to and receiving response data from the programming executive. All serial data is transmitted on the falling edge of PGC and latched on the rising edge of PGC. All data transmissions are sent to the Most Significant bit (MSb) first using 16-bit mode (see Figure 4-1). FIGURE 4-1: 2 3 4 5 6 11 12 13 14 After the entire response is clocked out, the programmer should terminate the clock on PGC until it is time to send another command to the programming executive. This protocol is shown in Figure 4-2. 4.1.2 SPI RATE In Enhanced ICSP mode, the dsPIC33F/PIC24H family devices operate from the Fast Internal RC oscillator, which has a nominal frequency of 7.3728 MHz. This oscillator frequency yields an effective system clock frequency of 1.8432 MHz. To ensure that the programmer does not clock too fast, it is recommended that a 7.35 MHz clock be provided by the programmer. 4.1.3 TIME OUTS The programming executive uses no Watchdog or time out for transmitting responses to the programmer. If the programmer does not follow the flow control mechanism using PGC as described in Section 4.1.1 "Communication Interface and Protocol", it is possible that the programming executive will behave unexpectedly while trying to send a response to the programmer. Since the programming executive has no time out, it is imperative that the programmer correctly follow the described communication protocol. As a safety measure, the programmer should use the command time outs identified in Table 4-1. If the command time out expires, the programmer should reset the programming executive and start programming the device again. PROGRAMMING EXECUTIVE SERIAL TIMING P1 1 After the programming executive has processed the command, it brings PGD low for 15 sec to indicate to the programmer that the response is available to be clocked out. The programmer can begin to clock out the response 23 sec after PGD is brought low and it must provide the necessary amount of clock pulses to receive the entire response from the programming executive. 15 16 PGC P1A P3 P1B P2 PGD MSb 14 13 12 11 . 5 4 3 2 1 LSb Since a 2 wire SPI is used, and data transmissions are bidirectional, a simple protocol is used to control the direction of PGD. When the programmer completes a command transmission, it releases the PGD line and allows the programming executive to drive this line high. The programming executive keeps the PGD line high to indicate that it is processing the command. © 2007 Microchip Technology Inc. Preliminary DS70152D-page 47 dsPIC33F/PIC24H PROGRAMMING SPECIFICATION FIGURE 4-2: PROGRAMMING EXECUTIVE ­ PROGRAMMER COMMUNICATION PROTOCOL Host Transmits Last Command Word 1 2 Programming Executive Processes Command Host Clocks Out Response 1 15 16 2 15 16 1 2 15 16 PGC PGD MSB X X X LSB MSB X X X LSB 1 P8 0 P9a P9b MSB X X X LSB 8ns 23 µs PGC = Input PGD = Input 4.2 PGC = Input (Idle) PGD = Output 4.2.2 Programming Executive Commands The programming executive command set is shown in Table 4-1. This table contains the opcode, mnemonic, length, time out and description for each command. Functional details on each command are provided in the command descriptions (Section 4.2.4 "Command Descriptions"). 4.2.1 PACKED DATA FORMAT When 24-bit instruction words are transferred across the 16-bit SPI interface, they are packed to conserve space using the format shown in Figure 4-4. This format minimizes traffic over the SPI and provides the programming executive with data that is properly aligned for performing table write operations. FIGURE 4-4: COMMAND FORMAT All programming executive commands have a general format consisting of a 16-bit header and any required data for the command (see Figure 4-3). The 16-bit header consists of a 4-bit opcode field, which is used to identify the command, followed by a 12-bit command length field. FIGURE 4-3: 15 PGC = Input PGD = Output 12 COMMAND FORMAT 11 15 PACKED INSTRUCTION WORD FORMAT 8 7 0 LSW1 MSB2 MSB1 LSW2 LSWx: Least Significant 16 bits of instruction word MSBx: Most Significant Byte of instruction word 0 Opcode Note: Length Command Data First Word (if required) When the number of instruction words transferred is odd, MSB2 is zero and LSW2 can not be transmitted. · 4.2.3 · Command Data Last Word (if required) The command opcode must match one of those in the command set. Any command that is received which does not match the list in Table 4-1 will return a "NACK" response (see Section 5.3.1.1 "Opcode Field"). The command length is represented in 16-bit words since the SPI operates in 16-bit mode. The programming executive uses the command length field to determine the number of words to read from the SPI port. If the value of this field is incorrect, the command will not be properly received by the programming executive. DS70152D-page 48 PROGRAMMING EXECUTIVE ERROR HANDLING The programming executive will "NACK" all unsupported commands. Additionally, due to the memory constraints of the programming executive, no checking is performed on the data contained in the programmer command. It is the responsibility of the programmer to command the programming executive with valid command arguments or the programming operation may fail. Additional information on error handling is provided in Section 5.3.1.3 "QE_Code Field". Preliminary © 2007 Microchip Technology Inc. dsPIC33F/PIC24H PROGRAMMING SPECIFICATION TABLE 4-1: Opcode PROGRAMMING EXECUTIVE COMMAND SET Mnemonic Length (16-bit words) Time Out Description 0x0 SCHECK 1 1 msec Sanity check. 0x1 READC 3 1 msec Read an 8-bit word from the specified Configuration register or Device ID register. 0x2 READP 4 0x3 RESERVED 0x4 PROGC 4 5 msec Write an 8-bit word to the specified Configuration register. 0x5 PROGP 99 5 msec Program one row of code memory at the specified address, then verify. 0x6 PROGW 5 5 msec Program one instruction word of code memory at the specified address, then verify. 0x7 RESERVED N/A N/A This command is reserved. It will return a NACK. 0x8 RESERVED N/A N/A This command is reserved. It will return a NACK. N/A N/A This command is reserved. It will return a NACK. 2 TBD Query if the code memory is blank. 0x9 RESERVED 0xA 1 msec/row Read `N' 24-bit instruction words of code memory starting from the specified address. N/A QBLANK N/A This command is reserved. It will return a NACK. 0xB QVER 1 1 msec 0xC RESERVED N/A N/A Query the programming executive software version. This command is reserved. It will return a NACK. 0xD RESERVED N/A N/A This command is reserved. It will return a NACK. Legend: TBD = To Be Determined Note: One row of code memory consists of (64) 24-bit words. Refer to Table 2-2 for device-specific information. 4.2.4 COMMAND DESCRIPTIONS All commands supported by the programming executive are described in Section 5.2.5 "SCHECK Command" through Section 4.2.12 "QVER Command". 4.2.5 SCHECK COMMAND 15 12 11 0 Opcode Length Field Description Opcode 0x0 Length 0x1 The SCHECK command instructs the programming executive to do nothing but generate a response. This command is used as a "Sanity Check" to verify that the programming executive is operational. Expected Response (2 words): 0x1000 0x0002 Note: This instruction is not required programming, but is provided development purposes only. © 2007 Microchip Technology Inc. for for Preliminary DS70152D-page 49 dsPIC33F/PIC24H PROGRAMMING SPECIFICATION 4.2.6 15 READC COMMAND 12 11 Opcode 4.2.7 8 7 0 15 12 11 8 7 Opcode Length N READP COMMAND 0 Length N Addr_MSB Reserved Addr_LS Addr_MSB Addr_LS Field Description Field Description Opcode 0x1 Length 0x3 Opcode N Number of 8-bit Configuration registers or Device ID registers to read (max of 256) Length 0x4 N Number of 24-bit instructions to read (max of 32768) Addr_MSB MSB of 24-bit source address Reserved 0x0 Addr_LS Least Significant 16 bits of 24-bit source address Addr_MSB MSB of 24-bit source address Addr_LS Least Significant 16 bits of 24-bit source address The READC command instructs the programming executive to read N Configuration registers or Device ID registers, starting from the 24-bit address specified by Addr_MSB and Addr_LS. This command can only be used to read 8-bit or 16-bit data. When this command is used to read Configuration registers, the upper byte in every data word returned by the programming executive is 0x00 and the lower byte contains the Configuration register value. Expected Response (4 + 3 * (N ­ 1)/2 words for N odd): 0x1100 2+N Configuration register or Device ID Register 1 . Configuration register or Device ID Register N Note: Reading unimplemented memory will cause the programming executive to reset. Please ensure that only memory locations present on a particular device are accessed. The READP command instructs the programming executive to read N 24-bit words of code memory, starting from the 24-bit address specified by Addr_MSB and Addr_LS. This command can only be used to read 24bit data. All data returned in the response to this command uses the packed data format described in Section 4.2.2 "Packed Data Format". Expected Response (2 + 3 * N/2 words for N even): 0x1200 2 + 3 * N/2 Least significant program memory word 1 . Least significant data word N Expected Response (4 + 3 * (N ­ 1)/2 words for N odd): 0x1200 4 + 3 * (N ­ 1)/2 Least significant program memory word 1 . MSB of program memory word N (zero padded) Note: DS70152D-page 50 0x2 Preliminary Reading unimplemented memory will cause the programming executive to reset. Please ensure that only memory locations present on a particular device are accessed. © 2007 Microchip Technology Inc. dsPIC33F/PIC24H PROGRAMMING SPECIFICATION 4.2.8 PROGC COMMAND 15 12 11 4.2.9 8 7 Opcode 0 15 12 11 8 7 Opcode Length Reserved PROGP COMMAND 0 Length Reserved Addr_MSB Addr_MSB Addr_LS Addr_LS Data D_1 D_2 Field Opcode . Description D_N 0x4 Length 0x4 Reserved 0x0 Field Description Addr_MSB MSB of 24-bit destination address Opcode 0x5 Addr_LS Least Significant 16 bits of 24-bit destination address Length 0x63 Reserved 0x0 Data 8-bit data word Addr_MSB MSB of 24-bit destination address The PROGC command instructs the programming executive to program a single Configuration register, located at the specified memory address. Addr_LS Least Significant 16 bits of 24-bit destination address D_1 16-bit data word 1 After the specified data word has been programmed to code memory, the programming executive verifies the programmed data against the data in the command. D_2 16-bit data word 2 Expected Response (2 words): 0x1400 0x0002 . 16-bit data word 3 through 95 D_96 16-bit data word 96 The PROGP command instructs the programming executive to program one row of code memory (64 instruction words) to the specified memory address. Programming begins with the row address specified in the command. The destination address should be a multiple of 0x80. The data to program to memory, located in command words D_1 through D_96, must be arranged using the packed instruction word format shown in Figure 4-4. After all data has been programmed to code memory, the programming executive verifies the programmed data against the data in the command. Expected Response (2 words): 0x1500 0x0002 Note: © 2007 Microchip Technology Inc. Preliminary Refer to Table 2-2 for code memory size information. DS70152D-page 51 dsPIC33F/PIC24H PROGRAMMING SPECIFICATION 4.2.10 PROGW COMMAND 15 12 11 Opcode 4.2.11 8 7 0 12 11 0 Opcode Length Reserved 15 QBLANK COMMAND Length PSize Addr_MSB Addr_LS Data_LS Reserved Field Data_MSB Description Opcode 0x5 Reserved 0x0 Addr_MSB MSB of 24-bit destination address Addr_LS Least Significant 16 bits of 24-bit destination address Data_MSB MSB of 24-bit data Data_LS Least Significant 16 bits of 24-bit data Length of program memory to check (in 24-bit words) +1, up to a max of 49152 0x6 Length 0x2 PSize Description 0xA Length Field Opcode The QBLANK command queries the programming executive to determine if the contents of code memory are blank (contains all `1's). The size of code memory to check must be specified in the command. The Blank Check for code memory begins at 0x0 and advances toward larger addresses for the specified number of instruction words. The PROGW command instructs the programming executive to program one word of code memory (3 bytes) to the specified memory address. After the word has been programmed to code memory, the programming executive verifies the programmed data against the data in the command. Expected Response (2 words): 0x1600 0x0002 DS70152D-page 52 QBLANK returns a QE_Code of 0xF0 if the specified code memory and code-protect bits are blank; otherwise, QBLANK returns a QE_Code of 0x0F. Expected Response (2 words for blank device): 0x1AF0 0x0002 Expected Response (2 words for non-blank device): 0x1A0F 0x0002 Note: Preliminary The QBLANK command does not check the system operation Configuration bits since these bits are not set to `1' when a Chip Erase is performed. © 2007 Microchip Technology Inc. dsPIC33F/PIC24H PROGRAMMING SPECIFICATION 4.2.12 4.3.1 QVER COMMAND 15 12 11 0 Opco