PIC24FJ256GB110 DS39897B PIC32 ISO/TS-16949 PIC24FJ64GB106 PIC24FJ128GB106 - Datasheet Archive

 

Data Sheet 64/80/100-Pin, 16-Bit Flash Microcontrollers with USB On-The-Go (OTG) © 2008 Microchip Technology Inc.

 

PIC24FJ256GB110 PIC24FJ256GB110 Family Data Sheet 64/80/100-Pin, 16-Bit Flash Microcontrollers with USB On-The-Go (OTG) © 2008 Microchip Technology Inc. Preliminary DS39897B DS39897B Note the following details of the code protection feature on Microchip devices: · Microchip products meet the specification contained in their particular Microchip Data Sheet. · Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. · There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. · Microchip is willing to work with the customer who is concerned about the integrity of their code. · Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, rfPIC and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, PICkit, PICDEM, PICDEM.net, PICtail, PIC32 PIC32 logo, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2008, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949 ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company's quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified. DS39897B-page ii Preliminary © 2008 Microchip Technology Inc. PIC24FJ256GB110 PIC24FJ256GB110 FAMILY 64/80/100-Pin, 16-Bit Flash Microcontrollers with USB On-The-Go (OTG) Power Management: High-Performance CPU: · On-Chip 2.5V Voltage Regulator · Switch between Clock Sources in Real Time · Idle, Sleep and Doze modes with Fast Wake-up and Two-Speed Start-up · Run mode: 1 mA/MIPS, 2.0V Typical · Sleep mode Current Down to 100 nA Typical · Standby Current with 32 kHz Oscillator: 2.5 A, 2.0V typical · · · · · · · Modified Harvard Architecture Up to 16 MIPS Operation at 32 MHz 8 MHz Internal Oscillator 17-Bit x 17-Bit Single-Cycle Hardware Multiplier 32-Bit by 16-Bit Hardware Divider 16 x 16-Bit Working Register Array C Compiler Optimized Instruction Set Architecture with Flexible Addressing modes · Linear Program Memory Addressing, Up to 12 Mbytes · Linear Data Memory Addressing, Up to 64 Kbytes · Two Address Generation Units for Separate Read and Write Addressing of Data Memory Universal Serial Bus Features: Analog Features: USBOTG CTMU JTAG PMP/PSP Comparators I2CTM SPI UART w/IrDA® Compare/ PWM Output Capture Input Timers 16-Bit 10-Bit A/D (ch) · 10-Bit, Up to 16-Channel Analog-to-Digital (A/D) Converter at 500 ksps: - Conversions available in Sleep mode · Three Analog Comparators with Programmable Input/ Output Configuration · Charge Time Measurement Unit (CTMU) Remappable Peripherals Remappable Pins SRAM (Bytes) Program Memory (Bytes) Device Pins · USB v2.0 On-The-Go (OTG) Compliant · Dual Role Capable ­ can act as either Host or Peripheral · Low-Speed (1.5 Mb/s) and Full-Speed (12 Mb/s) USB Operation in Host mode · Full-Speed USB Operation in Device mode · High-Precision PLL for USB · Internal Voltage Boost Assist for USB Bus Voltage Generation · Interface for Off-Chip Charge Pump for USB Bus Voltage Generation · Supports up to 32 Endpoints (16 bidirectional): - USB Module can use any RAM location on the device as USB endpoint buffers · On-Chip USB Transceiver with On-Chip Voltage Regulator · Interface for Off-Chip USB Transceiver · Supports Control, Interrupt, Isochronous and Bulk Transfers · On-Chip Pull-up and Pull-Down Resistors PIC24FJ64GB106 PIC24FJ64GB106 64 64K 16K 29 5 9 9 4 3 3 16 3 Y Y Y Y PIC24FJ128GB106 PIC24FJ128GB106 64 128K 16K 29 5 9 9 4 3 3 16 3 Y Y Y Y PIC24FJ192GB106 PIC24FJ192GB106 64 192K 16K 29 5 9 9 4 3 3 16 3 Y Y Y Y PIC24FJ256GB106 PIC24FJ256GB106 64 256K 16K 29 5 9 9 4 3 3 16 3 Y Y Y Y PIC24FJ64GB108 PIC24FJ64GB108 80 64K 16K 40 5 9 9 4 3 3 16 3 Y Y Y Y PIC24FJ128GB108 PIC24FJ128GB108 80 128K 16K 40 5 9 9 4 3 3 16 3 Y Y Y Y PIC24FJ192GB108 PIC24FJ192GB108 80 192K 16K 40 5 9 9 4 3 3 16 3 Y Y Y Y PIC24FJ256GB108 PIC24FJ256GB108 80 256K 16K 40 5 9 9 4 3 3 16 3 Y Y Y Y PIC24FJ64GB110 PIC24FJ64GB110 100 64K 16K 44 5 9 9 4 3 3 16 3 Y Y Y Y PIC24FJ128GB110 PIC24FJ128GB110 100 128K 16K 44 5 9 9 4 3 3 16 3 Y Y Y Y PIC24FJ192GB110 PIC24FJ192GB110 100 192K 16K 44 5 9 9 4 3 3 16 3 Y Y Y Y PIC24FJ256GB110 PIC24FJ256GB110 100 256K 16K 44 5 9 9 4 3 3 16 3 Y Y Y Y © 2008 Microchip Technology Inc. Preliminary DS39897B-page 1 PIC24FJ256GB110 PIC24FJ256GB110 FAMILY Peripheral Features: Special Microcontroller Features: · Peripheral Pin Select: - Allows independent I/O mapping of many peripherals at run time - Continuous hardware integrity checking and safety interlocks prevent unintentional configuration changes - Up to 44 available pins (100-pin devices) · Three 3-Wire/4-Wire SPI modules (supports 4 Frame modes) with 8-Level FIFO Buffer · Three I2CTM modules support Multi-Master/Slave modes and 7-Bit/10-Bit Addressing · Four UART modules: - Supports RS-485 RS-485, RS-232 RS-232, LIN/J6202 LIN/J6202 protocols and IrDA® - On-chip hardware encoder/decoder for IrDA - Auto-wake-up and Auto-Baud Detect (ABD) - 4-level deep FIFO buffer · Five 16-Bit Timers/Counters with Programmable Prescaler · Nine 16-Bit Capture Inputs, each with a Dedicated Time Base · Nine 16-Bit Compare/PWM Outputs, each with a Dedicated Time Base · 8-Bit Parallel Master Port (PMP/PSP): - Up to 16 address pins - Programmable polarity on control lines · Hardware Real-Time Clock/Calendar (RTCC): - Provides clock, calendar and alarm functions · Programmable Cyclic Redundancy Check (CRC) Generator · Up to 5 External Interrupt Sources · · · · · · DS39897B-page 2 · · · · · · · · Operating Voltage Range of 2.0V to 3.6V Self-Reprogrammable under Software Control 5.5V Tolerant Input (digital pins only) Configurable Open-Drain Outputs on Digital I/O High-Current Sink/Source (18 mA/18 mA) on all I/O Selectable Power Management modes: - Sleep, Idle and Doze modes with fast wake-up Fail-Safe Clock Monitor Operation: - Detects clock failure and switches to on-chip, low-power RC oscillator On-Chip LDO Regulator Power-on Reset (POR), Power-up Timer (PWRT), Low-Voltage Detect (LVD) and Oscillator Start-up Timer (OST) Flexible Watchdog Timer (WDT) with On-Chip. Low-Power RC Oscillator for Reliable Operation In-Circuit Serial ProgrammingTM (ICSPTM) and In-Circuit Debug (ICD) via 2 Pins JTAG Boundary Scan and Programming Support Brown-out Reset (BOR) Flash Program Memory: - 10,000 erase/write cycle endurance (minimum) - 20-year data retention minimum - Selectable write protection boundary - Write protection option for Flash Configuration Words Preliminary © 2008 Microchip Technology Inc. PIC24FJ256GB110 PIC24FJ256GB110 FAMILY 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 PMD4/CN62/RE4 PMD4/CN62/RE4 PMD3/CN61/RE3 PMD3/CN61/RE3 PMD2/CN60/RE2 PMD2/CN60/RE2 PMD1/CN59/RE1 PMD1/CN59/RE1 PMD0/CN58/RE0 PMD0/CN58/RE0 VCMPST2/CN69/RF1 VCMPST2/CN69/RF1 VBUSST/VCMPST1/CN68/RF0 VBUSST/VCMPST1/CN68/RF0 ENVREG VCAP/VDDCORE C3INA/CN16/RD7 C3INA/CN16/RD7 C3INB/CN15/RD6 C3INB/CN15/RD6 PMRD/RP20/CN14/RD5 PMRD/RP20/CN14/RD5 PMWR/RP25/CN13/RD4 PMWR/RP25/CN13/RD4 RP22/PMBE/CN52/RD3 RP22/PMBE/CN52/RD3 DPH/RP23/CN51/RD2 DPH/RP23/CN51/RD2 RP24/VCPCON/CN50/RD1 RP24/VCPCON/CN50/RD1 Pin Diagram (64-Pin TQFP) 48 1 2 3 4 5 6 7 8 9 10 11 12 47 46 45 PIC24FJXXXGB106 PIC24FJXXXGB106 44 43 42 41 40 RPI37/SOSCO/C3INC/TICK/ RPI37/SOSCO/C3INC/TICK/ CN0/RC14 CN0/RC14 SOSCI/C3IND/CN1/RC13 SOSCI/C3IND/CN1/RC13 RP11/DMH/CN49/INT0/RD0 RP11/DMH/CN49/INT0/RD0 RP12/PMCS1/CN56/RD11 RP12/PMCS1/CN56/RD11 RP3/SCL1/PMCS2/CN55/RD10 RP3/SCL1/PMCS2/CN55/RD10 RP4/DPLN/SDA1/CN54/RD9 RP4/DPLN/SDA1/CN54/RD9 RP2/DMLN/RTCC/CN53/RD8 RP2/DMLN/RTCC/CN53/RD8 VSS OSCO/CLKO/CN22/RC15 OSCO/CLKO/CN22/RC15 39 38 37 36 35 34 33 13 14 15 16 OSCI/CLKI/CN23/RC12 OSCI/CLKI/CN23/RC12 VDD D+/RG2 D-/RG3 VUSB VBUS RP16/USBID/CN71/RF3 RP16/USBID/CN71/RF3 Legend: TCK/PMA11/AN12/CTED2/CN30/RB12 TCK/PMA11/AN12/CTED2/CN30/RB12 TDI/PMA10/AN13/CTED1/CN31/RB13 TDI/PMA10/AN13/CTED1/CN31/RB13 CTPLS/RP14/PMA1/AN14/CN32/RB14 CTPLS/RP14/PMA1/AN14/CN32/RB14 RP29/PMA0/AN15/REFO/CN12/RB15 RP29/PMA0/AN15/REFO/CN12/RB15 PMA9/RP10/SDA2/CN17/RF4 PMA9/RP10/SDA2/CN17/RF4 PMA8/RP17/SCL2/CN18/RF5 PMA8/RP17/SCL2/CN18/RF5 PGEC2/AN6/RP6/CN24/RB6 PGEC2/AN6/RP6/CN24/RB6 PGED2/RCV/RP7/AN7/CN25/RB7 PGED2/RCV/RP7/AN7/CN25/RB7 AVDD AVSS RP8/AN8/CN26/RB8 RP8/AN8/CN26/RB8 PMA7/RP9/AN9/CN27/RB9 PMA7/RP9/AN9/CN27/RB9 TMS/PMA13/AN10/CVREF/CN28/RB10 TMS/PMA13/AN10/CVREF/CN28/RB10 TDO/AN11/PMA12/CN29/RB11 TDO/AN11/PMA12/CN29/RB11 VSS VDD 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 PMD5/CN63/RE5 PMD5/CN63/RE5 PMD6/SCL3/CN64/RE6 PMD6/SCL3/CN64/RE6 PMD7/SDA3/CN65/RE7 PMD7/SDA3/CN65/RE7 PMA5/RP21/C1IND/CN8/RG6 PMA5/RP21/C1IND/CN8/RG6 RP26/PMA4/C1INC/CN9/RG7 RP26/PMA4/C1INC/CN9/RG7 PMA3/RP19/C2IND/CN10/RG8 PMA3/RP19/C2IND/CN10/RG8 MCLR RP27/PMA2/C2INC/CN11/RG9 RP27/PMA2/C2INC/CN11/RG9 VSS VDD PGEC3/RP18/VBUSON/C1INA/AN5/CN7/RB5 PGEC3/RP18/VBUSON/C1INA/AN5/CN7/RB5 PGED3/RP28/USBOEN/C1INB/AN4/CN6/RB4 PGED3/RP28/USBOEN/C1INB/AN4/CN6/RB4 VPIO/C2INA/AN3/CN5/RB3 VMIO/RP13/C2INB/AN2/CN4/RB2 VMIO/RP13/C2INB/AN2/CN4/RB2 PGEC1/RP1/VREF-/AN1/CN3/RB1 PGED1/RP0/PMA6/VREF+/AN0/CN2/RB0 RPn represents remappable pins for Peripheral Pin Select feature. © 2008 Microchip Technology Inc. Preliminary DS39897B-page 3 PIC24FJ256GB110 PIC24FJ256GB110 FAMILY PMD5/CN63/RE5 PMD5/CN63/RE5 RP22/PMBE/CN52/RD3 RP22/PMBE/CN52/RD3 DPH/RP23/CN51/RD2 DPH/RP23/CN51/RD2 RP24/VCPCON/CN50/RD1 RP24/VCPCON/CN50/RD1 65 64 63 62 61 PMRD/RP20/CN14/RD5 PMRD/RP20/CN14/RD5 PMWR/RP25/CN13/RD4 PMWR/RP25/CN13/RD4 CN19/RD13 CN19/RD13 RPI42/CN57/RD12 RPI42/CN57/RD12 ENVREG VCAP/VDDCORE C3INA/CN16/RD7 C3INA/CN16/RD7 C3INB/CN15/RD6 C3INB/CN15/RD6 75 74 73 72 71 70 69 68 67 66 PMD1/CN59/RE1 PMD1/CN59/RE1 PMD0/CN58/RE0 PMD0/CN58/RE0 CN77/RG0 CN77/RG0 CN78/RG1 CN78/RG1 VCMPST2/CN69/RF1 VCMPST2/CN69/RF1 VBUSST/VCMPST1/CN68/RF0 VBUSST/VCMPST1/CN68/RF0 PMD2/CN60/RE2 PMD2/CN60/RE2 80 79 78 77 76 PMD4/CN62/RE4 PMD4/CN62/RE4 PMD3/CN61/RE3 PMD3/CN61/RE3 Pin Diagram (80-Pin TQFP) 60 RPI37/SOSCO/C3INC/T1CK/CN0/RC14 RPI37/SOSCO/C3INC/T1CK/CN0/RC14 59 SOSCI/C3IND/CN1/RC13 SOSCI/C3IND/CN1/RC13 58 RP11/DMH/CN49/INT0/RD0 RP11/DMH/CN49/INT0/RD0 57 RP12/PMCS1/CN56/RD11 RP12/PMCS1/CN56/RD11 56 1 RP3/PMCS2/SCL1/CN55/RD10 RP3/PMCS2/SCL1/CN55/RD10 PMD6/SCL3/CN64/RE6 PMD6/SCL3/CN64/RE6 2 PMD7/SDA3/CN65/RE7 PMD7/SDA3/CN65/RE7 3 RPI38/CN45/RC1 RPI38/CN45/RC1 RPI40/CN47/RC3 RPI40/CN47/RC3 4 PMA5/RP21/C1IND/CN8/RG6 PMA5/RP21/C1IND/CN8/RG6 6 55 RP4/DPLN/SDA1/CN54/RD9 RP4/DPLN/SDA1/CN54/RD9 RP26/PMA4/C1INC/CN9/RG7 RP26/PMA4/C1INC/CN9/RG7 7 54 RP2/DMLN/RTCC/CN53/RD8 RP2/DMLN/RTCC/CN53/RD8 PMA3/RP19/C2IND/CN10/RG8 PMA3/RP19/C2IND/CN10/RG8 8 53 RPI35/SDA2/CN44/RA15 RPI35/SDA2/CN44/RA15 MCLR 9 52 RPI36/SCL2/CN43/RA14 RPI36/SCL2/CN43/RA14 10 51 VSS 50 OSCO/CLKO/CN22/RC15 OSCO/CLKO/CN22/RC15 OSCI/CLKI/CN23/RC12 OSCI/CLKI/CN23/RC12 RP27/PMA2/C2INC/CN11/RG9 RP27/PMA2/C2INC/CN11/RG9 5 PIC24FJXXXGB108 PIC24FJXXXGB108 VSS 11 VDD 12 49 TMS/RPI33/CN66/RE8 TMS/RPI33/CN66/RE8 13 48 VDD TDO/RPI34/CN67/RE9 TDO/RPI34/CN67/RE9 14 47 D+/RG2 30 31 32 33 34 35 36 37 38 39 40 VDD TCK/AN12/CTED2/PMA11/CN30/RB12 TCK/AN12/CTED2/PMA11/CN30/RB12 TDI/AN13/CTED1/PMA10/CN31/RB13 TDI/AN13/CTED1/PMA10/CN31/RB13 CTPLS/RP14/PMA1/AN14/CN32/RB14 CTPLS/RP14/PMA1/AN14/CN32/RB14 RP29/PMA0/AN15/REFO/CN12/RB15 RP29/PMA0/AN15/REFO/CN12/RB15 RPI43/CN20/RD14 RPI43/CN20/RD14 RP5/CN21/RD15 RP5/CN21/RD15 RP10/PMA9/CN17/RF4 RP10/PMA9/CN17/RF4 RP17/PMA8/CN18/RF5 RP17/PMA8/CN18/RF5 21 PGEC2/AN6/RP6/CN24/RB6 PGEC2/AN6/RP6/CN24/RB6 Legend: 29 RP16/USBID/CN71/RF3 RP16/USBID/CN71/RF3 AN11/PMA12/CN29/RB11 AN11/PMA12/CN29/RB11 Vss 20 28 RP30/CN70/RF2 RP30/CN70/RF2 41 PGED1/RP0/AN0/CN2/RB0 RP9/AN9/CN27/RB9 RP9/AN9/CN27/RB9 42 AN10/CVREF/PMA13/CN28/RB10 AN10/CVREF/PMA13/CN28/RB10 19 27 RP15/CN74/RF8 RP15/CN74/RF8 PGEC1/RP1/AN1/CN3/RB1 AVSS RP8/AN8/CN26/RB8 RP8/AN8/CN26/RB8 18 43 25 26 VBUS VMIO/RP13/C2INB/AN2/CN4/RB2 VMIO/RP13/C2INB/AN2/CN4/RB2 AVDD 44 24 17 23 VUSB VPIO/C2INA/AN3/CN5/RB3 PMA7/VREF-/CN41/RA9 PMA7/VREF-/CN41/RA9 D-/RG3 45 PMA6/VREF+/CN42/RA10 /CN42/RA10 46 16 22 15 PGED2/RCV/RP7/AN7/CN25/RB7 PGED2/RCV/RP7/AN7/CN25/RB7 PGEC3/RP18/VBUSON/C1INA/AN5/CN7/RB5 PGEC3/RP18/VBUSON/C1INA/AN5/CN7/RB5 PGED3/RP28/USBOEN/C1INB/AN4/CN6/RB4 PGED3/RP28/USBOEN/C1INB/AN4/CN6/RB4 RPn and RPIn represent remappable pins for Peripheral Pin Select feature. DS39897B-page 4 Preliminary © 2008 Microchip Technology Inc. PIC24FJ256GB110 PIC24FJ256GB110 FAMILY PMD2/CN60/RE2 PMD2/CN60/RE2 CN80/RG13 CN80/RG13 CN79/RG12 CN79/RG12 CN81/RG14 CN81/RG14 PMD1/CN59/RE1 PMD1/CN59/RE1 PMD0/CN58/RE0 PMD0/CN58/RE0 CN40/RA7 CN40/RA7 CN39/RA6 CN39/RA6 CN77/RG0 CN77/RG0 CN78/RG1 CN78/RG1 VCMPST2/CN69/RF1 VCMPST2/CN69/RF1 VBUSST/VCMPST1/CN68/RF0 VBUSST/VCMPST1/CN68/RF0 ENVREG VCAP/VDDCORE C3INA/CN16/RD7 C3INA/CN16/RD7 C3INB/CN15/RD6 C3INB/CN15/RD6 PMRD/RP20/CN14/RD5 PMRD/RP20/CN14/RD5 PMWR/RP25/CN13/RD4 PMWR/RP25/CN13/RD4 CN19/RD13 CN19/RD13 RPI42/CN57/RD12 RPI42/CN57/RD12 RP22/PMBE/CN52/RD3 RP22/PMBE/CN52/RD3 DPH/RP23/CN51/RD2 DPH/RP23/CN51/RD2 RP24/VCPCON/CN50/RD1 RP24/VCPCON/CN50/RD1 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 PMD4/CN62/RE4 PMD4/CN62/RE4 PMD3/CN61/RE3 PMD3/CN61/RE3 Pin Diagram (100-Pin TQFP) 1 75 VDD 2 74 PMD5/CN63/RE5 PMD5/CN63/RE5 3 73 PMD6/SCL3/CN64/RE6 PMD6/SCL3/CN64/RE6 PMD7/SDA3/CN65/RE7 PMD7/SDA3/CN65/RE7 4 72 VSS RPI37/SOSCO/C3INC/T1CK/ RPI37/SOSCO/C3INC/T1CK/ CN0/RC14 CN0/RC14 SOSCI/C3IND/CN1/RC13 SOSCI/C3IND/CN1/RC13 RP11/DMH/CN49/INT0/RD0 RP11/DMH/CN49/INT0/RD0 5 71 RP12/PMCS1/CN56/RD11 RP12/PMCS1/CN56/RD11 RPI38/CN45/RC1 RPI38/CN45/RC1 6 70 RP3/PMCS2/CN55/RD10 RP3/PMCS2/CN55/RD10 RPI39/CN46/RC2 RPI39/CN46/RC2 7 69 RP4/DPLN/CN54/RD9 RP4/DPLN/CN54/RD9 RPI40/CN47/RC3 RPI40/CN47/RC3 8 68 RP2/DMLN/RTCC/CN53/RD8 RP2/DMLN/RTCC/CN53/RD8 RPI41/CN48/RC4 RPI41/CN48/RC4 9 67 RPI35/SDA1/CN44/RA15 RPI35/SDA1/CN44/RA15 PMA5/RP21/C1IND/CN8/RG6 PMA5/RP21/C1IND/CN8/RG6 10 66 RPI36/SCL1/CN43/RA14 RPI36/SCL1/CN43/RA14 RP26/PMA4/C1INC/CN9/RG7 RP26/PMA4/C1INC/CN9/RG7 11 65 RP19/PMA3/C2IND/CN10/RG8 RP19/PMA3/C2IND/CN10/RG8 12 64 VSS OSCO/CLKO/CN22/RC15 OSCO/CLKO/CN22/RC15 MCLR 13 63 OSCI/CLKI/CN23/RC12 OSCI/CLKI/CN23/RC12 RP27/PMA2/C2INC/CN11/RG9 RP27/PMA2/C2INC/CN11/RG9 14 62 VDD VSS 15 61 TDO/CN38/RA5 TDO/CN38/RA5 CN82/RG15 CN82/RG15 PIC24FJXXXGB110 PIC24FJXXXGB110 16 60 TDI/CN37/RA4 TDI/CN37/RA4 17 59 SDA2/CN36/RA3 SDA2/CN36/RA3 RPI33/CN66/RE8 RPI33/CN66/RE8 18 58 SCL2/CN35/RA2 SCL2/CN35/RA2 RPI34/CN67/RE9 RPI34/CN67/RE9 PGEC3/RP18/VBUSON/C1INA/AN5/CN7/RB5 PGEC3/RP18/VBUSON/C1INA/AN5/CN7/RB5 19 57 D+/RG2 20 56 D-/RG3 PGED3/RP28/USBOEN/C1INB/AN4/CN6/RB4 PGED3/RP28/USBOEN/C1INB/AN4/CN6/RB4 21 55 VUSB VPIO/C2INA/AN3/CN5/RB3 VMIO/RP13/C2INB/AN2/CN4/RB2 VMIO/RP13/C2INB/AN2/CN4/RB2 22 54 VBUS 23 53 RP15/CN74/RF8 RP15/CN74/RF8 PGEC1/RP1/AN1/CN3/RB1 24 52 RP30/CN70/RF2 RP30/CN70/RF2 PGED1/RP0/AN0/CN2/RB0 25 51 RP16/USBID/CN71/RF3 RP16/USBID/CN71/RF3 Legend: VSS VDD RPI43/CN20/RD14 RPI43/CN20/RD14 RP5/CN21/RD15 RP5/CN21/RD15 RP10/PMA9/CN17/RF4 RP10/PMA9/CN17/RF4 RP17/PMA8/CN18/RF5 RP17/PMA8/CN18/RF5 PGEC2/AN6/RP6/CN24/RB6 PGEC2/AN6/RP6/CN24/RB6 PGED2/RCV/RP7/AN7/CN25/RB7 PGED2/RCV/RP7/AN7/CN25/RB7 PMA7/VREF-/CN41/RA9 PMA7/VREF-/CN41/RA9 PMA6/VREF+/CN42/RA10 /CN42/RA10 AVDD AVSS RP8/AN8/CN26/RB8 RP8/AN8/CN26/RB8 RP9/AN9/CN27/RB9 RP9/AN9/CN27/RB9 AN10/CVREF/PMA13/CN28/RB10 AN10/CVREF/PMA13/CN28/RB10 AN11/PMA12/CN29/RB11 AN11/PMA12/CN29/RB11 VSS VDD TCK/CN34/RA1 TCK/CN34/RA1 RP31/CN76/RF13 RP31/CN76/RF13 RPI32/CN75/RF12 RPI32/CN75/RF12 AN12/CTED2/PMA11/CN30/RB12 AN12/CTED2/PMA11/CN30/RB12 AN13/CTED1/PMA10/CN31/RB13 AN13/CTED1/PMA10/CN31/RB13 CTPLS/RP14/PMA1/AN14/CN32/RB14 CTPLS/RP14/PMA1/AN14/CN32/RB14 RP29/PMA0/AN15/REFO/CN12/RB15 RP29/PMA0/AN15/REFO/CN12/RB15 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 VDD TMS/CN33/RA0 TMS/CN33/RA0 RPn and RPIn represent remappable pins for Peripheral Pin Select feature. © 2008 Microchip Technology Inc. Preliminary DS39897B-page 5 PIC24FJ256GB110 PIC24FJ256GB110 FAMILY Table of Contents 1.0 Device Overview . 9 2.0 CPU . 25 3.0 Memory Organization . 31 4.0 Flash Program Memory . 55 5.0 Resets . 61 6.0 Interrupt Controller . 67 7.0 Oscillator Configuration . 109 8.0 Power-Saving Features . 119 9.0 I/O Ports . 121 10.0 Timer1 . 147 11.0 Timer2/3 and Timer4/5 . 149 12.0 Input Capture with Dedicated Timers . 155 13.0 Output Compare with Dedicated Timers . 159 14.0 Serial Peripheral Interface (SPI). 169 15.0 Inter-Integrated Circuit (I2CTM) . 179 16.0 Universal Asynchronous Receiver Transmitter (UART) . 187 17.0 Universal Serial Bus with On-The-Go Support (USB OTG) . 195 18.0 Parallel Master Port (PMP). 225 19.0 Real-Time Clock and Calendar (RTCC) . 235 20.0 Programmable Cyclic Redundancy Check (CRC) Generator . 245 21.0 10-bit High-Speed A/D Converter. 249 22.0 Triple Comparator Module. 259 23.0 Comparator Voltage Reference. 263 24.0 Charge Time Measurement Unit (CTMU) . 265 25.0 Special Features . 269 26.0 Development Support. 281 27.0 Instruction Set Summary . 285 28.0 Electrical Characteristics . 293 29.0 Packaging Information. 307 Appendix A: Revision History. 317 Index . 319 The Microchip Web Site . 323 Customer Change Notification Service . 323 Customer Support . 323 Reader Response . 324 Product Identification System. 325 DS39897B-page 6 Preliminary © 2008 Microchip Technology Inc. PIC24FJ256GB110 PIC24FJ256GB110 FAMILY TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A DS30000A is version A of document DS30000 DS30000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: · Microchip's Worldwide Web site; http://www.microchip.com · Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. © 2008 Microchip Technology Inc. Preliminary DS39897B-page 7 PIC24FJ256GB110 PIC24FJ256GB110 FAMILY NOTES: DS39897B-page 8 Preliminary © 2008 Microchip Technology Inc. PIC24FJ256GB110 PIC24FJ256GB110 FAMILY 1.0 DEVICE OVERVIEW This document contains device-specific information for the following devices: · PIC24FJ64GB106 PIC24FJ64GB106 · PIC24FJ192GB108 PIC24FJ192GB108 · PIC24FJ128GB106 PIC24FJ128GB106 · PIC24FJ256GB108 PIC24FJ256GB108 · PIC24FJ192GB106 PIC24FJ192GB106 · PIC24FJ64GB110 PIC24FJ64GB110 · PIC24FJ256GB106 PIC24FJ256GB106 · PIC24FJ128GB110 PIC24FJ128GB110 · PIC24FJ64GB108 PIC24FJ64GB108 · PIC24FJ192GB110 PIC24FJ192GB110 · PIC24FJ128GB108 PIC24FJ128GB108 · PIC24FJ256GB110 PIC24FJ256GB110 · Doze Mode Operation: When timing-sensitive applications, such as serial communications, require the uninterrupted operation of peripherals, the CPU clock speed can be selectively reduced, allowing incremental power savings without missing a beat. · Instruction-Based Power-Saving Modes: The microcontroller can suspend all operations, or selectively shut down its core while leaving its peripherals active, with a single instruction in software. 1.1.3 This expands on the existing line of Microchip`s 16-bit microcontrollers, combining an expanded peripheral feature set and enhanced computational performance with a new connectivity option: USB On-The-Go. The PIC24FJ256GB110 PIC24FJ256GB110 family provides a new platform for high-performance USB applications which may need more than an 8-bit platform, but don't require the power of a digital signal processor. 1.1 1.1.1 Core Features 16-BIT 16-BIT ARCHITECTURE Central to all PIC24F PIC24F devices is the 16-bit modified Harvard architecture, first introduced with Microchip's dsPIC® digital signal controllers. The PIC24F PIC24F CPU core offers a wide range of enhancements, such as: · 16-bit data and 24-bit address paths with the ability to move information between data and memory spaces · Linear addressing of up to 12 Mbytes (program space) and 64 Kbytes (data) · A 16-element working register array with built-in software stack support · A 17 x 17 hardware multiplier with support for integer math · Hardware support for 32 by 16-bit division · An instruction set that supports multiple addressing modes and is optimized for high-level languages such as `C' · Operational performance up to 16 MIPS 1.1.2 POWER-SAVING TECHNOLOGY All of the devices in the PIC24FJ256GB110 PIC24FJ256GB110 family incorporate a range of features that can significantly reduce power consumption during operation. Key items include: · On-the-Fly Clock Switching: The device clock can be changed under software control to the Timer1 source or the internal, low-power RC oscillator during operation, allowing the user to incorporate power-saving ideas into their software designs. © 2008 Microchip Technology Inc. OSCILLATOR OPTIONS AND FEATURES All of the devices in the PIC24FJ256GB110 PIC24FJ256GB110 family offer five different oscillator options, allowing users a range of choices in developing application hardware. These include: · Two Crystal modes using crystals or ceramic resonators. · Two External Clock modes offering the option of a divide-by-2 clock output. · A Fast Internal Oscillator (FRC) with a nominal 8 MHz output, which can also be divided under software control to provide clock speeds as low as 31 kHz. · A Phase Lock Loop (PLL) frequency multiplier, available to the external oscillator modes and the FRC oscillator, which allows clock speeds of up to 32 MHz. · A separate internal RC oscillator (LPRC) with a fixed 31 kHz output, which provides a low-power option for timing-insensitive applications. The internal oscillator block also provides a stable reference source for the Fail-Safe Clock Monitor. This option constantly monitors the main clock source against a reference signal provided by the internal oscillator and enables the controller to switch to the internal oscillator, allowing for continued low-speed operation or a safe application shutdown. 1.1.4 EASY MIGRATION Regardless of the memory size, all devices share the same rich set of peripherals, allowing for a smooth migration path as applications grow and evolve. The consistent pinout scheme used throughout the entire family also aids in migrating from one device to the next larger, or even in jumping from 64-pin to 100-pin devices. The PIC24F PIC24F family is pin-compatible with devices in the dsPIC33 family, and shares some compatibility with the pinout schema for PIC18 PIC18 and dsPIC30. This extends the ability of applications to grow from the relatively simple, to the powerful and complex, yet still selecting a Microchip device. Preliminary DS39897B-page 9 PIC24FJ256GB110 PIC24FJ256GB110 FAMILY 1.2 USB On-The-Go With the PIC24FJ256GB110 PIC24FJ256GB110 family of devices, Microchip introduces USB On-The-Go functionality on a single chip to its product line. This new module provides on-chip functionality as a target device compatible with the USB 2.0 standard, as well as limited stand-alone functionality as a USB embedded host. By implementing USB Host Negotiation Protocol (HNP), the module can also dynamically switch between device and host operation, allowing for a much wider range of versatile USB-enabled applications on a microcontroller platform. · Parallel Master/Enhanced Parallel Slave Port: One of the general purpose I/O ports can be reconfigured for enhanced parallel data communications. In this mode, the port can be configured for both master and slave operations, and supports 8-bit and 16-bit data transfers with up to 16 external address lines in Master modes. · Real-Time Clock/Calendar: This module implements a full-featured clock and calendar with alarm functions in hardware, freeing up timer resources and program memory space for use of the core application. In addition to USB host functionality, PIC24FJ256GB110 PIC24FJ256GB110 family devices provide a true single-chip USB solution, including an on-chip transceiver and voltage regulator, and a voltage boost generator for sourcing bus power during host operations. 1.4 1.3 The devices are differentiated from each other in four ways: Other Special Features · Peripheral Pin Select: The peripheral pin select feature allows most digital peripherals to be mapped over a fixed set of digital I/O pins. Users may independently map the input and/or output of any one of the many digital peripherals to any one of the I/O pins. · Communications: The PIC24FJ256GB110 PIC24FJ256GB110 family incorporates a range of serial communication peripherals to handle a range of application requirements. There are three independent I2C modules that support both Master and Slave modes of operation. Devices also have, through the peripheral pin select feature, four independent UARTs with built-in IrDA encoder/decoders and three SPI modules. · Analog Features: All members of the PIC24FJ256GB110 PIC24FJ256GB110 family include a 10-bit A/D Converter module and a triple comparator module. The A/D module incorporates programmable acquisition time, allowing for a channel to be selected and a conversion to be initiated without waiting for a sampling period, as well as faster sampling speeds. The comparator module includes three analog comparators that are configurable for a wide range of operations. · CTMU Interface: In addition to their other analog features, members of the PIC24FJ256GB110 PIC24FJ256GB110 family include the brand new CTMU interface module. This provides a convenient method for precision time measurement and pulse generation, and can serve as an interface for capacitive sensors. DS39897B-page 10 Details on Individual Family Members Devices in the PIC24FJ256GB110 PIC24FJ256GB110 family are available in 64-pin, 80-pin and 100-pin packages. The general block diagram for all devices is shown in Figure 1-1. 1. 2. 3. 4. Flash program memory (64 Kbytes for PIC24FJ64GB1 PIC24FJ64GB1 devices, 128 Kbytes for PIC24FJ128GB1 PIC24FJ128GB1 devices, 192 Kbytes for PIC24FJ192GB1 PIC24FJ192GB1 devices and 256 Kbytes for PIC24FJ256GB1 PIC24FJ256GB1 devices). Available I/O pins and ports (51 pins on 6 ports for 64-pin devices, 65 pins on 7 ports for 80-pin devices and 83 pins on 7 ports for 100-pin devices). Available Interrupt-on-Change Notification (ICN) inputs (49 on 64-pin devices, 63 on 80-pin devices, and 81 on 100-pin devices). Available remappable pins (29 pins on 64-pin devices, 40 pins on 80-pin devices and 44 pins on 100-pin devices) All other features for devices in this family are identical. These are summarized in Table 1-1. A list of the pin features available on the PIC24FJ256GB110 PIC24FJ256GB110 family devices, sorted by function, is shown in Table 1-4. Note that this table shows the pin location of individual peripheral features and not how they are multiplexed on the same pin. This information is provided in the pinout diagrams in the beginning of the data sheet. Multiplexed features are sorted by the priority given to a feature, with the highest priority peripheral being listed first. Preliminary © 2008 Microchip Technology Inc. PIC24FJ256GB110 PIC24FJ256GB110 FAMILY TABLE 1-1: DEVICE FEATURES FOR THE PIC24FJ256GB110 PIC24FJ256GB110 FAMILY: 64-PIN 64-PIN DEVICES Features 64GB106 64GB106 Operating Frequency Program Memory (bytes) Program Memory (instructions) 128GB106 128GB106 192GB106 192GB106 256GB106 256GB106 DC ­ 32 MHz 64K 128K 22,016 44,032 Data Memory (bytes) 192K 256K 67,072 87,552 16,384 Interrupt Sources (soft vectors/NMI traps) 66 (62/4) I/O Ports Ports B, C, D, E, F, G Total I/O Pins 51 Remappable Pins 29 (28 I/O, 1 Input only) Timers: 5(1) Total Number (16-bit) 32-Bit (from paired 16-bit timers) 2 Input Capture Channels 9(1) Output Compare/PWM Channels 9(1) Input Change Notification Interrupt 49 Serial Communications: UART 4(1) SPI (3-wire/4-wire) 3(1) I2CTM 3 Parallel Communications (PMP/PSP) Yes JTAG Boundary Scan/Programming Yes 10-Bit Analog-to-Digital Module (input channels) 16 Analog Comparators 3 CTMU Interface Resets (and delays) Instruction Set Yes POR, BOR, RESET Instruction, MCLR, WDT; Illegal Opcode, REPEAT Instruction, Hardware Traps, Configuration Word Mismatch (PWRT, OST, PLL Lock) 76 Base Instructions, Multiple Addressing Mode Variations Packages Note 1: 64-Pin TQFP Peripherals are accessible through remappable pins. © 2008 Microchip Technology Inc. Preliminary DS39897B-page 11 PIC24FJ256GB110 PIC24FJ256GB110 FAMILY TABLE 1-2: DEVICE FEATURES FOR THE PIC24FJ256GB110 PIC24FJ256GB110 FAMILY: 80-PIN 80-PIN DEVICES Features 64GB108 64GB108 Operating Frequency Program Memory (bytes) Program Memory (instructions) 128GB108 128GB108 192GB108 192GB108 256GB108 256GB108 DC ­ 32 MHz 64K 128K 22,016 44,032 Data Memory (bytes) 192K 256K 67,072 87,552 16,384 Interrupt Sources (soft vectors/NMI traps) 66 (62/4) I/O Ports Ports A, B, C, D, E, F, G Total I/O Pins 65 Remappable Pins 40 (31 I/O, 9 Input only) Timers: 5(1) Total Number (16-bit) 32-Bit (from paired 16-bit timers) 2 Input Capture Channels 9(1) Output Compare/PWM Channels 9(1) Input Change Notification Interrupt 63 Serial Communications: UART 4(1) SPI (3-wire/4-wire) 3(1) I2CTM 3 Parallel Communications (PMP/PSP) Yes JTAG Boundary Scan/Programming Yes 10-Bit Analog-to-Digital Module (input channels) 16 Analog Comparators 3 CTMU Interface Resets (and delays) Instruction Set Yes POR, BOR, RESET Instruction, MCLR, WDT; Illegal Opcode, REPEAT Instruction, Hardware Traps, Configuration Word Mismatch (PWRT, OST, PLL Lock) 76 Base Instructions, Multiple Addressing Mode Variations Packages Note 1: 80-Pin TQFP Peripherals are accessible through remappable pins. DS39897B-page 12 Preliminary © 2008 Microchip Technology Inc. PIC24FJ256GB110 PIC24FJ256GB110 FAMILY TABLE 1-3: DEVICE FEATURES FOR THE PIC24FJ256GB110 PIC24FJ256GB110 FAMILY: 100-PIN 100-PIN DEVICES Features 64GB110 64GB110 Operating Frequency Program Memory (bytes) Program Memory (instructions) 128GB110 128GB110 192GB110 192GB110 256GB110 256GB110 DC ­ 32 MHz 64K 128K 192K 256K 22,016 44,032 67,072 87,552 Data Memory (bytes) 16,384 Interrupt Sources (soft vectors/NMI traps) 66 (62/4) I/O Ports Ports A, B, C, D, E, F, G Total I/O Pins 83 Remappable Pins 44 (32 I/O, 12 Input only) Timers: 5(1) Total Number (16-bit) 32-Bit (from paired 16-bit timers) 2 Input Capture Channels 9(1) Output Compare/PWM Channels 9(1) Input Change Notification Interrupt 81 Serial Communications: UART 4(1) SPI (3-wire/4-wire) 3(1) I2CTM 3 Parallel Communications (PMP/PSP) Yes JTAG Boundary Scan/Programming Yes 10-Bit Analog-to-Digital Module (input channels) 16 Analog Comparators 3 CTMU Interface Resets (and delays) Instruction Set Yes POR, BOR, RESET Instruction, MCLR, WDT; Illegal Opcode, REPEAT Instruction, Hardware Traps, Configuration Word Mismatch (PWRT, OST, PLL Lock) 76 Base Instructions, Multiple Addressing Mode Variations Packages Note 1: 100-Pin TQFP Peripherals are accessible through remappable pins. © 2008 Microchip Technology Inc. Preliminary DS39897B-page 13 PIC24FJ256GB110 PIC24FJ256GB110 FAMILY FIGURE 1-1: PIC24FJ256GB110 PIC24FJ256GB110 FAMILY GENERAL BLOCK DIAGRAM Data Bus Interrupt Controller PORTA(1) 16 (13 I/O) 16 16 8 Data Latch PSV & Table Data Access Control Block Data RAM PCH PCL Program Counter Repeat Stack Control Control Logic Logic 23 Address Latch PORTB (16 I/O) 16 23 16 Read AGU Write AGU Address Latch PORTC(1) Program Memory (8 I/O) Data Latch 16 EA MUX Literal Data Address Bus 24 Inst Latch 16 16 PORTD(1) (16 I/O) Inst Register Instruction Decode & Control PORTE(1) Control Signals OSCO/CLKO OSCI/CLKI Timing Generation FRC/LPRC Oscillators REFO (10 I/O) 16 x 16 W Reg Array 17x17 Multiplier Power-up Timer Oscillator Start-up Timer (9 I/O) 16 Watchdog Timer Voltage Regulator PORTF(1) 16-Bit ALU Power-on Reset Precision Band Gap Reference ENVREG Divide Support BOR and LVD(2) PORTG(1) (12 I/O) VDDCORE/VCAP Timer1 Timer2/3(3) VDD, VSS Timer4/5(3) MCLR RTCC 10-Bit ADC Comparators(3) USB OTG PMP/PSP IC 1-9(3) Note 1: 2: 3: PWM/OC 1-9(3) ICNs(1) SPI 1/2/3(3) I2C 1/2/3 UART 1/2/3/4(3) CTMU Not all I/O pins or features are implemented on all device pinout configurations. See Table 1-4 for specific implementations by pin count. BOR functionality is provided when the on-board voltage regulator is enabled. These peripheral I/Os are only accessible through remappable pins. DS39897B-page 14 Preliminary © 2008 Microchip Technology Inc. PIC24FJ256GB110 PIC24FJ256GB110 FAMILY TABLE 1-4: PIC24FJ256GB110 PIC24FJ256GB110 FAMILY PINOUT DESCRIPTIONS Pin Number Function 64-Pin TQFP 80-Pin TQFP 100-Pin TQFP I/O Input Buffer AN0 16 20 25 I ANA AN1 15 19 24 I ANA AN2 14 18 23 I ANA AN3 13 17 22 I ANA AN4 12 16 21 I ANA AN5 11 15 20 I ANA AN6 17 21 26 I ANA AN7 18 22 27 I ANA AN8 21 27 32 I ANA AN9 22 28 33 I ANA AN10 23 29 34 I ANA AN11 24 30 35 I ANA AN12 27 33 41 I ANA AN13 28 34 42 I ANA AN14 29 35 43 I ANA AN15 30 36 44 I Description A/D Analog Inputs. ANA AVDD 19 25 30 P - AVSS 20 26 31 P - C1INA 11 15 20 I ANA Comparator 1 Input A. C1INB 12 16 21 I ANA Comparator 1 Input B. C1INC 5 7 11 I ANA Comparator 1 Input C. C1IND 4 6 10 I ANA Comparator 1 Input D. C2INA 13 17 22 I ANA Comparator 2 Input A. C2INB 14 18 23 I ANA Comparator 2 Input B. C2INC 8 10 14 I ANA Comparator 2 Input C. C2IND 6 8 12 I ANA Comparator 2 Input D. C3INA 55 69 84 I ANA Comparator 3 Input A. C3INB 54 68 83 I ANA Comparator 3 Input B. C3INC 48 60 74 I ANA Comparator 3 Input C. C3IND 47 59 73 I ANA Comparator 3 Input D. CLKI 39 49 63 I ANA CLKO 40 50 64 O - Legend: TTL = TTL input buffer ANA = Analog level input/output © 2008 Microchip Technology Inc. Positive Supply for Analog modules. Ground Reference for Analog modules. Main Clock Input Connection. System Clock Output. ST = Schmitt Trigger input buffer I2CTM = I2C/SMBus input buffer Preliminary DS39897B-page 15 PIC24FJ256GB110 PIC24FJ256GB110 FAMILY TABLE 1-4: PIC24FJ256GB110 PIC24FJ256GB110 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number 64-Pin TQFP 80-Pin TQFP 100-Pin TQFP I/O Input Buffer CN0 48 60 74 I ST CN1 47 59 73 I ST CN2 16 20 25 I ST CN3 15 19 24 I ST CN4 14 18 23 I ST CN5 13 17 22 I ST CN6 12 16 21 I ST CN7 11 15 20 I ST CN8 4 6 10 I ST CN9 5 7 11 I ST CN10 6 8 12 I ST CN11 8 10 14 I ST CN12 30 36 44 I ST CN13 52 66 81 I ST CN14 53 67 82 I ST CN15 54 68 83 I ST CN16 55 69 84 I ST CN17 31 39 49 I ST CN18 32 40 50 I ST CN19 - 65 80 I ST CN20 - 37 47 I ST CN21 - 38 48 I ST CN22 40 50 64 I ST CN23 39 49 63 I ST CN24 17 21 26 I ST CN25 18 22 27 I ST CN26 21 27 32 I ST CN27 22 28 33 I ST CN28 23 29 34 I ST CN29 24 30 35 I ST CN30 27 33 41 I ST CN31 28 34 42 I ST CN32 29 35 43 I ST CN33 - - 17 I ST CN34 - - 38 I ST CN35 - - 58 I ST CN36 - - 59 I ST CN37 - - 60 I ST CN38 - - 61 I ST CN39 - - 91 I ST Function CN40 - - 92 I - 23 28 I ST - 24 29 I Interrupt-on-Change Inputs. ST CN41 Description ST CN42 Legend: TTL = TTL input buffer ANA = Analog level input/output DS39897B-page 16 ST = Schmitt Trigger input buffer I2CTM = I2C/SMBus input buffer Preliminary © 2008 Microchip Technology Inc. PIC24FJ256GB110 PIC24FJ256GB110 FAMILY TABLE 1-4: PIC24FJ256GB110 PIC24FJ256GB110 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number 64-Pin TQFP 80-Pin TQFP 100-Pin TQFP I/O Input Buffer CN43 - 52 66 I ST CN44 - 53 67 I ST CN45 - 4 6 I ST CN46 - - 7 I ST CN47 - 5 8 I ST CN48 - - 9 I ST CN49 46 58 72 I ST CN50 49 61 76 I ST CN51 50 62 77 I ST CN52 51 63 78 I ST CN53 42 54 68 I ST CN54 43 55 69 I ST CN55 44 56 70 I ST CN56 45 57 71 I ST CN57 - 64 79 I ST CN58 60 76 93 I ST CN59 61 77 94 I ST CN60 62 78 98 I ST CN61 63 79 99 I ST CN62 64 80 100 I ST CN63 1 1 3 I ST CN64 2 2 4 I ST CN65 3 3 5 I ST CN66 - 13 18 I ST CN67 - 14 19 I ST CN68 58 72 87 I ST CN69 59 73 88 I ST CN70 - 42 52 I ST CN71 33 41 51 I ST CN74 - 43 53 I ST CN75 - - 40 I ST CN76 - - 39 I ST CN77 - 75 90 I ST CN78 - 74 89 I ST CN79 - - 96 I ST CN80 - - 97 I ST CN81 - - 95 I ST CN82 - - 1 I ST CTED1 28 34 42 I ANA CTMU External Edge Input 1. CTED2 27 33 41 I ANA CTMU External Edge Input 2. Function Description Interrupt-on-Change Inputs. CTPLS 29 35 43 O - CTMU Pulse Output. CVREF 23 29 34 O - Comparator Voltage Reference Output. Legend: TTL = TTL input buffer ANA = Analog level input/output © 2008 Microchip Technology Inc. ST = Schmitt Trigger input buffer I2CTM = I2C/SMBus input buffer Preliminary DS39897B-page 17 PIC24FJ256GB110 PIC24FJ256GB110 FAMILY TABLE 1-4: PIC24FJ256GB110 PIC24FJ256GB110 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number 64-Pin TQFP 80-Pin TQFP 100-Pin TQFP I/O Input Buffer D+ 37 47 57 I/O - USB Differential Plus line (internal transceiver). D- 36 46 56 I/O - USB Differential Minus line (internal transceiver). DMH 46 58 72 O - D- External Pull-up Control Output. DMLN 42 54 68 O - D- External Pull-down Control Output. DPH 50 62 77 O - D+ External Pull-up Control Output. DPLN 43 55 69 O - D+ External Pull-down Control Output. ENVREG 57 71 86 I ST Voltage Regulator Enable. INT0 46 58 72 I ST External Interrupt Input. MCLR 7 9 13 I ST Master Clear (device Reset) Input. This line is brought low to cause a Reset. OSCI 39 49 63 I ANA Main Oscillator Input Connection. OSCO 40 50 64 O ANA Main Oscillator Output Connection. PGEC1 15 19 24 I/O ST In-Circuit Debugger/Emulator/ICSPTM Programming Clock. PGED1 16 20 25 I/O ST In-Circuit Debugger/Emulator/ICSP Programming Data. PGEC2 17 21 26 I/O ST In-Circuit Debugger/Emulator/ICSP Programming Clock. PGED2 18 22 27 I/O ST In-Circuit Debugger/Emulator/ICSP Programming Data. PGEC3 11 15 20 I/O ST In-Circuit Debugger/Emulator/ICSP Programming Clock. PGED3 12 16 21 I/O ST In-Circuit Debugger/Emulator/ICSP Programming Data. PMA0 30 36 44 I/O ST Parallel Master Port Address Bit 0 Input (Buffered Slave modes) and Output (Master modes). PMA1 29 35 43 I/O ST Parallel Master Port Address Bit 1 Input (Buffered Slave modes) and Output (Master modes). PMA2 8 10 14 O - PMA3 6 8 12 O - Parallel Master Port Address (Demultiplexed Master modes). PMA4 5 7 11 O - PMA5 4 6 10 O - PMA6 16 24 29 O - PMA7 22 23 28 O - PMA8 32 40 50 O - PMA9 31 39 49 O - PMA10 PMA10 28 34 42 O - PMA11 PMA11 27 33 41 O - PMA12 PMA12 24 30 35 O - PMA13 PMA13 23 29 34 O - PMCS1 45 57 71 I/O ST/TTL Parallel Master Port Chip Select 1 Strobe/Address Bit 15. PMCS2 44 56 70 O ST Parallel Master Port Chip Select 2 Strobe/Address Bit 14. 51 63 78 O - Parallel Master Port Byte Enable Strobe. Function PMBE Legend: TTL = TTL input buffer ANA = Analog level input/output DS39897B-page 18 Description ST = Schmitt Trigger input buffer I2CTM = I2C/SMBus input buffer Preliminary © 2008 Microchip Technology Inc. PIC24FJ256GB110 PIC24FJ256GB110 FAMILY TABLE 1-4: PIC24FJ256GB110 PIC24FJ256GB110 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number 64-Pin TQFP 80-Pin TQFP 100-Pin TQFP I/O Input Buffer PMD0 60 76 93 I/O ST/TTL PMD1 61 77 94 I/O ST/TTL PMD2 62 78 98 I/O ST/TTL PMD3 63 79 99 I/O ST/TTL PMD4 64 80 100 I/O ST/TTL PMD5 1 1 3 I/O ST/TTL PMD6 2 2 4 I/O ST/TTL PMD7 3 3 5 I/O ST/TTL PMRD 53 67 82 O - PMWR 52 66 81 O - Parallel Master Port Write Strobe. RA0 - - 17 I/O ST PORTA Digital I/O. RA1 - - 38 I/O ST RA2 - - 58 I/O ST RA3 - - 59 I/O ST RA4 - - 60 I/O ST RA5 - - 61 I/O ST RA6 - - 91 I/O ST RA7 - - 92 I/O ST RA9 - 23 28 I/O ST RA10 - 24 29 I/O ST RA14 - 52 66 I/O ST RA15 - 53 67 I/O ST RB0 16 20 25 I/O ST RB1 15 19 24 I/O ST RB2 14 18 23 I/O ST RB3 13 17 22 I/O ST RB4 12 16 21 I/O ST RB5 11 15 20 I/O ST RB6 17 21 26 I/O ST RB7 18 22 27 I/O ST RB8 21 27 32 I/O ST RB9 22 28 33 I/O ST RB10 23 29 34 I/O ST RB11 24 30 35 I/O ST RB12 27 33 41 I/O ST RB13 28 34 42 I/O ST RB14 29 35 43 I/O ST RB15 30 36 44 I/O ST Function Legend: TTL = TTL input buffer ANA = Analog level input/output © 2008 Microchip Technology Inc. Description Parallel Master Port Data (Demultiplexed Master mode) or Address/Data (Multiplexed Master modes). Parallel Master Port Read Strobe. PORTB Digital I/O. ST = Schmitt Trigger input buffer I2CTM = I2C/SMBus input buffer Preliminary DS39897B-page 19 PIC24FJ256GB110 PIC24FJ256GB110 FAMILY TABLE 1-4: PIC24FJ256GB110 PIC24FJ256GB110 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number Function 64-Pin TQFP 80-Pin TQFP 100-Pin TQFP I/O Input Buffer Description RC1 - 4 6 I/O ST RC2 - - 7 I/O ST RC3 - 5 8 I/O ST RC4 - - 9 I/O ST RC12 39 49 63 I/O ST RC13 47 59 73 I/O ST RC14 48 60 74 I/O ST RC15 40 50 64 I/O ST RCV 18 22 27 I ST USB Receive Input (from external transceiver). RD0 46 58 72 I/O ST PORTD Digital I/O. RD1 49 61 76 I/O ST RD2 50 62 77 I/O ST RD3 51 63 78 I/O ST RD4 52 66 81 I/O ST RD5 53 67 82 I/O ST RD6 54 68 83 I/O ST RD7 55 69 84 I/O ST RD8 42 54 68 I/O ST RD9 43 55 69 I/O ST RD10 44 56 70 I/O ST RD11 45 57 71 I/O ST RD12 - 64 79 I/O ST RD13 - 65 80 I/O ST RD14 - 37 47 I/O ST RD15 - 38 48 I/O ST RE0 60 76 93 I/O ST RE1 61 77 94 I/O ST RE2 62 78 98 I/O ST RE3 63 79 99 I/O ST RE4 64 80 100 I/O ST RE5 1 1 3 I/O ST RE6 2 2 4 I/O ST RE7 3 3 5 I/O - 13 18 I/O ST RE9 - 14 19 I/O ST REFO 30 36 44 O - PORTE Digital I/O. ST RE8 PORTC Digital I/O. Legend: TTL = TTL input buffer ANA = Analog level input/output DS39897B-page 20 Reference Clock Output. ST = Schmitt Trigger input buffer I2CTM = I2C/SMBus input buffer Preliminary © 2008 Microchip Technology Inc. PIC24FJ256GB110 PIC24FJ256GB110 FAMILY TABLE 1-4: PIC24FJ256GB110 PIC24FJ256GB110 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number 64-Pin TQFP 80-Pin TQFP 100-Pin TQFP I/O Input Buffer RF0 58 72 87 I/O ST RF1 59 73 88 I/O ST RF2 - 42 52 I/O ST RF3 33 41 51 I/O ST RF4 31 39 49 I/O ST RF5 32 40 50 I/O ST RF8 - 43 53 I/O ST RF12 - - 40 I/O ST ST Function RF13 - - 39 I/O RG0 - 75 90 I/O ST RG1 - 74 89 I/O 37 47 57 I/O ST RG3 36 46 56 I/O ST RG6 4 6 10 I/O ST RG7 5 7 11 I/O ST RG8 6 8 12 I/O ST RG9 8 10 14 I/O ST RG12 - - 96 I/O ST RG13 - - 97 I/O ST RG14 - - 95 I/O PORTF Digital I/O. ST RG2 Description ST ST RG15 - - 1 I/O RP0 16 20 25 I/O ST RP1 15 19 24 I/O ST RP2 42 54 68 I/O ST RP3 44 56 70 I/O ST RP4 43 55 69 I/O ST RP5 - 38 48 I/O ST RP6 17 21 26 I/O ST RP7 18 22 27 I/O ST RP8 21 27 32 I/O ST RP9 22 28 33 I/O ST RP10 31 39 49 I/O ST RP11 46 58 72 I/O ST RP12 45 57 71 I/O ST RP13 14 18 23 I/O ST RP14 29 35 43 I/O PORTG Digital I/O. ST RP15 - 43 53 I/O ST RP16 33 41 51 I/O ST RP17 32 40 50 I/O ST RP18 11 15 20 I/O ST 6 8 12 I/O Remappable Peripheral (input or output). ST RP19 Legend: TTL = TTL input buffer ANA = Analog level input/output © 2008 Microchip Technology Inc. ST = Schmitt Trigger input buffer I2CTM = I2C/SMBus input buffer Preliminary DS39897B-page 21 PIC24FJ256GB110 PIC24FJ256GB110 FAMILY TABLE 1-4: PIC24FJ256GB110 PIC24FJ256GB110 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number Function 100-Pin TQFP I/O Input Buffer 64-Pin TQFP 80-Pin TQFP RP20 53 67 82 I/O ST RP21 4 6 10 I/O ST RP22 51 63 78 I/O ST RP23 50 62 77 I/O ST RP24 49 61 76 I/O ST RP25 52 66 81 I/O ST RP26 5 7 11 I/O ST RP27 8 10 14 I/O ST RP28 12 16 21 I/O ST RP29 30 36 44 I/O ST RP30 - 42 52 I/O ST RP31 - - 39 I/O Description ST Remappable Peripheral (input or output). RPI32 RPI32 - - 40 I ST RPI33 RPI33 - 13 18 I ST Remappable Peripheral (input only). RPI34 RPI34 - 14 19 I ST RPI35 RPI35 - 53 67 I ST RPI36 RPI36 - 52 66 I ST RPI37 RPI37 48 60 74 I ST RPI38 RPI38 - 4 6 I ST RPI39 RPI39 - - 7 I ST RPI40 RPI40 - 5 8 I ST RPI41 RPI41 - - 9 I ST RPI42 RPI42 - 64 79 I ST RPI43 RPI43 - 37 47 I ST RTCC 42 54 68 O - Real-Time Clock Alarm/Seconds Pulse Output. SCL1 44 56 66 I/O I2C I2C1 Synchronous Serial Clock Input/Output. SCL2 32 52 58 I/O I2C I2C2 Synchronous Serial Clock Input/Output. SCL3 2 2 4 I/O I2C I2C3 Synchronous Serial Clock Input/Output. I2C1 Data Input/Output. SDA1 43 55 67 I/O I2C SDA2 31 53 59 I/O I2C I2C2 Data Input/Output. SDA3 3 3 5 I/O I2C I2C3 Data Input/Output. SOSCI 47 59 73 I ANA Secondary Oscillator/Timer1 Clock Input. SOSCO 48 60 74 O ANA T1CK 48 60 74 I ST Timer1 Clock. Secondary Oscillator/Timer1 Clock Output. TCK 27 33 38 I ST JTAG Test Clock/Programming Clock Input. TDI 28 34 60 I ST JTAG Test Data/Programming Data Input. JTAG Test Data Output. TDO 24 14 61 O - TMS 23 13 17 I ST JTAG Test Mode Select Input. USBID 33 41 51 I ST USB OTG ID (OTG mode only). USBOEN 12 16 21 O - USB Output Enable Control (for external transceiver). Legend: TTL = TTL input buffer ANA = Analog level input/output DS39897B-page 22 ST = Schmitt Trigger input buffer I2CTM = I2C/SMBus input buffer Preliminary © 2008 Microchip Technology Inc. PIC24FJ256GB110 PIC24FJ256GB110 FAMILY TABLE 1-4: PIC24FJ256GB110 PIC24FJ256GB110 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number Function 64-Pin TQFP 80-Pin TQFP 100-Pin TQFP I/O Input Buffer Description VBUS 34 44 54 P - VBUSON 11 15 20 O - USB Voltage, Host mode (5V). VBUSST 58 72 87 I ANA VCAP 56 70 85 P - External Filter Capacitor Connection (regulator enabled). USB VBUS Boost Generator, Comparator Input 1. USB OTG External Charge Pump Control. USB OTG Internal Charge Pump Feedback Control. VCMPST1 58 72 87 I ST VCMPST2 59 73 88 I ST USB VBUS Boost Generator, Comparator Input 2. VCPCON 49 61 76 O - USB OTG VBUS PWM/Charge Output. 10, 26, 38 12, 32, 48 2, 16, 37, 46, 62 P - Positive Supply for Peripheral Digital Logic and I/O Pins. VDDCORE 56 70 85 P - Positive Supply for Microcontroller Core Logic (regulator disabled). VMIO 14 18 23 I/O ST USB Differential Minus Input/Output (external transceiver). VPIO 13 17 22 I/O ST VREF- 15 23 28 I ANA VDD VREF+ VSS VUSB Legend: USB Differential Plus Input/Output (external transceiver). A/D and Comparator Reference Voltage (low) Input. 16 24 29 I ANA 9, 25, 41 11, 31, 51 15, 36, 45, 65, 75 P - Ground Reference for Logic and I/O Pins. 35 45 55 P - USB Voltage (3.3V) TTL = TTL input buffer ANA = Analog level input/output © 2008 Microchip Technology Inc. A/D and Comparator Reference Voltage (high) Input. ST = Schmitt Trigger input buffer I2CTM = I2C/SMBus input buffer Preliminary DS39897B-page 23 PIC24FJ256GB110 PIC24FJ256GB110 FAMILY NOTES: DS39897B-page 24 Preliminary © 2008 Microchip Technology Inc. PIC24FJ256GB110 PIC24FJ256GB110 FAMILY 2.0 Note: CPU This data sheet summarizes the features of this group of PIC24F PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the "PIC24F PIC24F Family Reference Manual", "Section 2. CPU" (DS39703 DS39703). The PIC24F PIC24F CPU has a 16-bit (data) modified Harvard architecture with an enhanced instruction set and a 24-bit instruction word with a variable length opcode field. The Program Counter (PC) is 23 bits wide and addresses up to 4M instructions of user program memory space. A single-cycle instruction prefetch mechanism is used to help maintain throughput and provides predictable execution. All instructions execute in a single cycle, with the exception of instructions that change the program flow, the double-word move (MOV.D) instruction and the table instructions. Overhead-free program loop constructs are supported using the REPEAT instructions, which are interruptible at any point. PIC24F PIC24F devices have sixteen, 16-bit working registers in the programmer's model. Each of the working registers can act as a data, address or address offset register. The 16th working register (W15) operates as a Software Stack Pointer for interrupts and calls. The upper 32 Kbytes of the data space memory map can optionally be mapped into program space at any 16K word boundary defined by the 8-bit Program Space Visibility Page Address (PSVPAG) register. The program to data space mapping feature lets any instruction access program space as if it were data space. The Instruction Set Architecture (ISA) has been significantly enhanced beyond that of the PIC18 PIC18, but maintains an acceptable level of backward compatibility. All PIC18 PIC18 instructions and addressing modes are supported, either directly, or through simple macros. Many of the ISA enhancements have been driven by compiler efficiency needs. For most instructions, the core is capable of executing a data (or program data) memory read, a working register (data) read, a data memory write and a program (instruction) memory read per instruction cycle. As a result, three parameter instructions can be supported, allowing trinary operations (that is, A + B = C) to be executed in a single cycle. A high-speed, 17-bit by 17-bit multiplier has been included to significantly enhance the core arithmetic capability and throughput. The multiplier supports Signed, Unsigned and Mixed mode, 16-bit by 16-bit or 8-bit by 8-bit, integer multiplication. All multiply instructions execute in a single cycle. The 16-bit ALU has been enhanced with integer divide assist hardware that supports an iterative non-restoring divide algorithm. It operates in conjunction with the REPEAT instruction looping mechanism and a selection of iterative divide instructions to support 32-bit (or 16-bit), divided by 16-bit, integer signed and unsigned division. All divide operations require 19 cycles to complete but are interruptible at any cycle boundary. The PIC24F PIC24F has a vectored exception scheme with up to 8 sources of non-maskable traps and up to 118 interrupt sources. Each interrupt source can be assigned to one of seven priority levels. A block diagram of the CPU is shown in Figure 2-1. 2.1 Programmer's Model The programmer's model for the PIC24F PIC24F is shown in Figure 2-2. All registers in the programmer's model are memory mapped and can be manipulated directly by instructions. A description of each register is provided in Table 2-1. All registers associated with the programmer's model are memory mapped. The core supports Inherent (no operand), Relative, Literal, Memory Direct and three groups of addressing modes. All modes support Register Direct and various Register Indirect modes. Each group offers up to seven addressing modes. Instructions are associated with predefined addressing modes depending upon their functional requirements. © 2008 Microchip Technology Inc. Preliminary DS39897B-page 25 PIC24FJ256GB110 PIC24FJ256GB110 FAMILY FIGURE 2-1: PIC24F PIC24F CPU CORE BLOCK DIAGRAM PSV & Table Data Access Control Block Data Bus Interrupt Controller 16 8 16 16 Data Latch 23 23 PCH PCL Program Counter Loop Stack Control Control Logic Logic 16 Data RAM Address Latch 23 16 RAGU WAGU Address Latch Program Memory EA MUX Address Bus Data Latch ROM Latch 24 Control Signals to Various Blocks Instruction Reg Hardware Multiplier Divide Support 16 Literal Data Instruction Decode & Control 16 16 x 16 W Register Array 16 16-Bit ALU 16 To Peripheral Modules DS39897B-page 26 Preliminary © 2008 Microchip Technology Inc. PIC24FJ256GB110 PIC24FJ256GB110 FAMILY TABLE 2-1: CPU CORE REGISTERS Register(s) Name Description W0 through W15 Working Register Array PC 23-Bit Program Counter SR ALU STATUS Register SPLIM Stack Pointer Limit Value Register TBLPAG Table Memory Page Address Register PSVPAG Program Space Visibility Page Address Register RCOUNT Repeat Loop Counter Register CORCON CPU Control Register FIGURE 2-2: PROGRAMMER'S MODEL 15 Divider Working Registers 0 W0 (WREG) W1 W2 Multiplier Registers W3 W4 W5 W6 W7 Working/Address Registers W8 W9 W10 W11 W12 W13 W14 Frame Pointer W15 Stack Pointer 0 SPLIM 0 22 0 0 PC 7 0 TBLPAG 7 0 PSVPAG 15 0 RCOUNT SRH SRL - - - - - - - DC IPL 2 1 0 RA N OV Z C 15 15 Stack Pointer Limit Value Register Program Counter Table Memory Page Address Register Program Space Visibility Page Address Register Repeat Loop Counter Register 0 ALU STATUS Register (SR) 0 - - - - - - - - - - - - IPL3 PSV - - CPU Control Register (CORCON) Registers or bits shadowed for PUSH.S and POP.S instructions. © 2008 Microchip Technology Inc. Preliminary DS39897B-page 27 PIC24FJ256GB110 PIC24FJ256GB110 FAMILY 2.2 CPU Control Registers REGISTER 2-1: SR: ALU STATUS REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 - - - - - - - DC bit 15 bit 8 R/W-0(1) IPL2 R/W-0(1) (2) IPL1 (2) R/W-0(1) IPL0 (2) R-0 R/W-0 R/W-0 R/W-0 R/W-0 RA N OV Z C bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 15-9 Unimplemented: Read as `0' bit 8 DC: ALU Half Carry/Borrow bit 1 = A carry out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized data) of the result occurred 0 = No carry out from the 4th or 8th low-order bit of the result has occurred bit 7-5 IPL2:IPL0: CPU Interrupt Priority Level Status bits(1,2) 111 = CPU interrupt priority level is 7 (15); user interrupts disabled 110 = CPU interrupt priority level is 6 (14) 101 = CPU interrupt priority Level is 5 (13) 100 = CPU interrupt priority level is 4 (12) 011 = CPU interrupt priority level is 3 (11) 010 = CPU interrupt priority level is 2 (10) 001 = CPU interrupt priority level is 1 (9) 000 = CPU interrupt priority level is 0 (8) bit 4 RA: REPEAT Loop Active bit 1 = REPEAT loop in progress 0 = REPEAT loop not in progress bit 3 N: ALU Negative bit 1 = Result was negative 0 = Result was non-negative (zero or positive) bit 2 OV: ALU Overflow bit 1 = Overflow occurred for signed (2's complement) arithmetic in this arithmetic operation 0 = No overflow has occurred bit 1 Z: ALU Zero bit 1 = An operation which effects the Z bit has set it at some time in the past 0 = The most recent operation which effects the Z bit has cleared it (i.e., a non-zero result) bit 0 C: ALU Carry/Borrow bit 1 = A carry out from the Most Significant bit of the result occurred 0 = No carry out from the Most Significant bit of the result occurred Note 1: 2: The IPL Status bits are read-only when NSTDIS (INTCON1) = 1. The IPL Status bits are concatenated with the IPL3 bit (CORCON) to form the CPU Interrupt Priority Level (IPL). The value in parentheses indicates the IPL when IPL3 = 1. DS39897B-page 28 Preliminary © 2008 Microchip Technology Inc. PIC24FJ256GB110 PIC24FJ256GB110 FAMILY REGISTER 2-2: CORCON: CPU CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 - - - - - - - - bit 15 bit 8 U-0 U-0 - U-0 - - U-0 R/C-0 R/W-0 - IPL3 U-0 U-0 PSV (1) - - bit 7 bit 0 Legend: C = Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 15-4 Unimplemented: Read as `0' bit 3 IPL3: CPU Interrupt Priority Level Status bit(1) 1 = CPU interrupt priority level is greater than 7 0 = CPU interrupt priority level is 7 or less bit 2 PSV: Program Space Visibility in Data Space Enable bit 1 = Program space visible in data space 0 = Program space not visible in data space bit 1-0 x = Bit is unknown Unimplemented: Read as `0' Note 1: 2.3 User interrupts are disabled when IPL3 = 1. Arithmetic Logic Unit (ALU) The PIC24F PIC24F ALU is 16 bits wide and is capable of addition, subtraction, bit shifts and logic operations. Unless otherwise mentioned, arithmetic operations are 2's complement in nature. Depending on the operation, the ALU may affect the values of the Carry (C), Zero (Z), Negative (N), Overflow (OV) and Digit Carry (DC) Status bits in the SR register. The C and DC Status bits operate as Borrow and Digit Borrow bits, respectively, for subtraction operations. The ALU can perform 8-bit or 16-bit operations, depending on the mode of the instruction that is used. Data for the ALU operation can come from the W register array, or data memory, depending on the addressing mode of the instruction. Likewise, output data from the ALU can be written to the W register array or a data memory location. © 2008 Microchip Technology Inc. The PIC24F PIC24F CPU incorporates hardware support for both multiplication and division. This includes a dedicated hardware multiplier and support hardware for 16-bit divisor division. 2.3.1 MULTIPLIER The ALU contains a high-speed, 17-bit x 17-bit multiplier. It supports unsigned, signed or mixed sign operation in several multiplication modes: 1. 2. 3. 4. 5. 6. 7. Preliminary 16-bit x 16-bit signed 16-bit x 16-bit unsigned 16-bit signed x 5-bit (literal) unsigned 16-bit unsigned x 16-bit unsigned 16-bit unsigned x 5-bit (literal) unsigned 16-bit unsigned x 16-bit signed 8-bit unsigned x 8-bit unsigned DS39897B-page 29 PIC24FJ256GB110 PIC24FJ256GB110 FAMILY 2.3.2 DIVIDER 2.3.3 The divide block supports signed and unsigned integer divide operations with the following data sizes: 1. 2. 3. 4. 32-bit signed/16-bit signed divide 32-bit unsigned/16-bit unsigned divide 16-bit signed/16-bit signed divide 16-bit unsigned/16-bit unsigned divide The quotient for all divide instructions ends up in W0 and the remainder in W1. Sixteen-bit signed and unsigned DIV instructions can specify any W register for both the 16-bit divisor (Wn), and any W register (aligned) pair (W(m + 1):Wm) for the 32-bit dividend. The divide algorithm takes one cycle per bit of divisor, so both 32-bit/16-bit and 16-bit/16-bit instructions take the same number of cycles to execute. TABLE 2-2: Instruction MULTI-BIT SHIFT SUPPORT The PIC24F PIC24F ALU supports both single bit and single-cycle, multi-bit arithmetic and logic shifts. Multi-bit shifts are implemented using a shifter block, capable of performing up to a 15-bit arithmetic right shift, or up to a 15-bit left shift, in a single cycle. All multi-bit shift instructions only support Register Direct Addressing for both the operand source and result destination. A full summary of instructions that use the shift operation is provided below in Table 2-2. INSTRUCTIONS THAT USE THE SINGLE AND MULTI-BIT SHIFT OPERATION Description ASR Arithmetic shift right source register by one or more bits. SL Shift left source register by one or more bits. LSR Logical shift right source register by one or more bits. DS39897B-page 30 Preliminary © 2008 Microchip Technology Inc. PIC24FJ256GB110 PIC24FJ256GB110 FAMILY 3.0 MEMORY ORGANIZATION As Harvard architecture devices, PIC24F PIC24F microcontrollers feature separate program and data memory spaces and busses. This architecture also allows the direct access of program memory from the data space during code execution. 3.1 Program Address Space The program address memory space of the PIC24FJ256GB110 PIC24FJ256GB110 family devices is 4M instructions. The space is addressable by a 24-bit value derived FIGURE 3-1: from either the 23-bit Program Counter (PC) during program execution, or from table operation or data space remapping, as described in Section 3.3 "Interfacing Program and Data Memory Spaces". User access to the program memory space is restricted to the lower half of the address range (000000h to 7FFFFFh). The exception is the use of TBLRD/TBLWT operations which use TBLPAG to permit access to the Configuration bits and Device ID sections of the configuration memory space. Memory maps for the PIC24FJ256GB110 PIC24FJ256GB110 family of devices are shown in Figure 3-1. PROGRAM SPACE MEMORY MAP FOR PIC24FJ256GB110 PIC24FJ256GB110 FAMILY DEVICES PIC24FJ64GB1XX PIC24FJ64GB1XX PIC24FJ128GB1XX PIC24FJ128GB1XX PIC24FJ192GB1XX PIC24FJ192GB1XX PIC24FJ256GB1XX PIC24FJ256GB1XX GOTO Instruction Reset Address Interrupt Vector Table GOTO Instruction Reset Address Interrupt Vector Table GOTO Instruction Reset Address Interrupt Vector Table GOTO Instruction Reset Address Interrupt Vector Table Reserved Reserved Reserved Reserved Alternate Vector Table Alternate Vector Table Alternate Vector Table Alternate Vector Table User Flash Program Memory (22K instructions) User Memory Space Flash Config Words User Flash Program Memory (44K instructions) User Flash Program Memory (67K instructions) Flash Config Words User Flash Program Memory (87K instructions) Flash Config Words Unimplemented Read `0' Unimplemented Read `0' 0000FEh 000100h 000104h 0001FEh 000200h 00ABFEh 00AC00h 0157FEh 015800h 020BFEh 020C00h Flash Config Words Unimplemented Read `0' 000000h 000002h 000004h 02ABFEh 02AC00h Unimplemented Read `0' 7FFFFFh 800000h Reserved Reserved Reserved Device Config Registers Device Config Registers Device Config Registers Device Config Registers Reserved Reserved Reserved Reserved DEVID (2) Configuration Memory Space Reserved DEVID (2) DEVID (2) DEVID (2) F7FFFEh F80000h F8000Eh F80010h FEFFFEh FF0000h FFFFFFh Note: Memory areas are not shown to scale. © 2008 Microchip Technology Inc. Preliminary DS39897B-page 31 PIC24FJ256GB110 PIC24FJ256GB110 FAMILY 3.1.1 PROGRAM MEMORY ORGANIZATION 3.1.3 In PIC24FJ256GB110 PIC24FJ256GB110 family devices, the top three words of on-chip program memory are reserved for configuration information. On device Reset, the configuration information is copied into the appropriate Configuration registers. The addresses of the Flash Configuration Word for devices in the PIC24FJ256GB110 PIC24FJ256GB110 family are shown in Table 3-1. Their location in the memory map is shown with the other memory vectors in Figure 3-1. The program memory space is organized in word-addressable blocks. Although it is treated as 24 bits wide, it is more appropriate to think of each address of the program memory as a lower and upper word, with the upper byte of the upper word being unimplemented. The lower word always has an even address, while the upper word has an odd address (Figure 3-2). The Configuration Words in program memory are a compact format. The actual Configuration bits are mapped in several different registers in the configuration memory space. Their order in the Flash Configuration Words do not reflect a corresponding arrangement in the configuration space. Additional details on the device Configuration Words are provided in Section 25.1 "Configuration Bits". Program memory addresses are always word-aligned on the lower word, and addresses are incremented or decremented by two during code execution. This arrangement also provides compatibility with data memory space addressing and makes it possible to access data in the program memory space. 3.1.2 FLASH CONFIGURATION WORDS HARD MEMORY VECTORS All PIC24F PIC24F devices reserve the addresses between 00000h and 000200h for hard coded program execution vectors. A hardware Reset vector is provided to redirect code execution from the default value of the PC on device Reset to the actual start of code. A GOTO instruction is programmed by the user at 000000h with the actual address for the start of code at 000002h. TABLE 3-1: FLASH CONFIGURATION WORDS FOR PIC24FJ256GB110 PIC24FJ256GB110 FAMILY DEVICES PIC24FJ128GB PIC24FJ128GB 44,032 0157FAh: 0157FEh PIC24FJ192GB PIC24FJ192GB 67,072 020BFAh: 020BFEh 87,552 02ABFAh: 02ABFEh least significant word most significant word 16 8 PC Address (LSW Address) 0 000000h 000002h 000004h 000006h 00000000 00000000 00000000 00000000 Program Memory `Phantom' Byte (read as `0') DS39897B-page 32 00ABFAh: 00ABFEh PROGRAM MEMORY ORGANIZATION 23 000001h 000003h 000005h 000007h 22,016 PIC24FJ256GB PIC24FJ256GB MSW Address Configuration Word Addresses PIC24FJ64GB PIC24FJ64GB PIC24F PIC24F devices also have two interrupt vector tables, located from 000004h to 0000FFh and 000100h to 0001FFh. These vector tables allow each of the many device interrupt sources to be handled by separate ISRs. A more detailed discussion of the interrupt vector tables is provided in Section 6.1 "Interrupt Vector Table". FIGURE 3-2: Program Memory (Words) Device Instruction Width Preliminary © 2008 Microchip Technology Inc. PIC24FJ256GB110 PIC24FJ256GB110 FAMILY 3.2 Data Address Space The PIC24F PIC24F core has a separate, 16-bit wide data memory space, addressable as a single linear range. The data space is accessed using two Address Generation Units (AGUs), one each for read and write operations. The data space memory map is shown in Figure 3-3. All Effective Addresses (EAs) in the data memory space are 16 bits wide and point to bytes within the data space. This gives a data space address range of 64 Kbytes or 32K words. The lower half of the data memory space (that is, when EA = 0) is used for implemented memory addresses, while the upper half (EA = 1) is reserved for the program space visibility area (see Section 3.3.3 "Reading Data from Program Memory Using Program Space Visibility"). FIGURE 3-3: PIC24FJ256GB110 PIC24FJ256GB110 family devices implement a total of 16 Kbytes of data memory. Should an EA point to a location outside of this area, an all zero word or byte will be returned. 3.2.1 DATA SPACE WIDTH The data memory space is organized in byte-addressable, 16-bit wide blocks. Data is aligned in data memory and registers as 16-bit words, but all data space EAs resolve to bytes. The Least Significant Bytes of each word have even addresses, while the Most Significant Bytes have odd addresses. DATA SPACE MEMORY MAP FOR PIC24FJ256GB110 PIC24FJ256GB110 FAMILY DEVICES MSB Address 0001h 07FFh 0801h Implemented Data RAM MSB LSB SFR Space 1FFFh 2001h Data RAM 47FFh 4801h LSB Address 0000h 07FEh 0800h SFR Space Near Data Space 1FFEh 2000h 47FEh 4800h Unimplemented Read as `0' 7FFFh 8001h 7FFFh 8000h Program Space Visibility Area FFFFh Note: FFFEh Data memory areas are not shown to scale. © 2008 Microchip Technology Inc. Preliminary DS39897B-page 33 PIC24FJ256GB110 PIC24FJ256GB110 FAMILY 3.2.2 DATA MEMORY ORGANIZATION AND ALIGNMENT A sign-extend instruction (SE) is provided to allow users to translate 8-bit signed data to 16-bit signed values. Alternatively, for 16-bit unsigned data, users can clear the MSB of any W register by executing a zero-extend (ZE) instruction on the appropriate address. To maintain backward compatibility with PIC® devices and improve data space memory usage efficiency, the PIC24F PIC24F instruction set supports both word and byte operations. As a consequence of byte accessibility, all Effective Address calculations are internally scaled to step through word-aligned memory. For example, the core recognizes that Post-Modified Register Indirect Addressing mode [Ws+] will result in a value of Ws + 1 for byte operations and Ws + 2 for word operations. Although most instructions are capable of operating on word or byte data sizes, it should be noted that some instructions operate only on words. 3.2.3 The 8-Kbyte area between 0000h and 1FFFh is referred to as the near data space. Locations in this space are directly addressable via a 13-bit absolute address field within all memory direct instructions. The remainder of the data space is addressable indirectly. Additionally, the whole data space is addressable using MOV instructions, which support Memory Direct Addressing with a 16-bit address field. Data byte reads will read the complete word which contains the byte, using the LSb of any EA to determine which byte to select. The selected byte is placed onto the LSB of the data path. That is, data memory and registers are organized as two parallel, byte-wide entities with shared (word) address decode but separate write lines. Data byte writes only write to the corresponding side of the array or register which matches the byte address. 3.2.4 All word accesses must be aligned to an even address. Misaligned word data fetches are not supported, so care must be taken when mixing byte and word operations, or translating from 8-bit MCU code. If a misaligned read or write is attempted, an address error trap will be generated. If the error occurred on a read, the instruction underway is completed; if it occurred on a write, the instruction will be executed but the write will not occur. In either case, a trap is then executed, allowing the system and/or user to examine the machine state prior to execution of the address Fault. SFR SPACE The first 2 Kbytes of the near data space, from 0000h to 07FFh, are primarily occupied with Special Function Registers (SFRs). These are used by the PIC24F PIC24F core and peripheral modules for controlling the operation of the device. SFRs are distributed among the modules that they control and are generally grouped together by module. Much of the SFR space contains unused addresses; these are read as `0'. A diagram of the SFR space, showing where SFRs are actually implemented, is shown in Table 3-2. Each implemented area indicates a 32-byte region where at least one address is implemented as an SFR. A complete listing of implemented SFRs, including their addresses, is shown in Tables 3-3 through 3-30. All byte loads into any W register are loaded into the Least Significant Byte. The Most Significant Byte is not modified. TABLE 3-2: NEAR DATA SPACE IMPLEMENTED REGIONS OF SFR DATA SPACE SFR Space Address xx00 xx20 000h xx40 xx60 Core 100h xx80 ICN Timers xxA0 xxC0 xxE0 Interrupts Capture - Compare 200h I2CTM UART SPI/UART SPI/I2C SPI UART 300h A/D A/D/CTMU - - - - 400h - - - - 500h - - - - 600h PMP RTC/Comp CRC - 700h - - System NVM/PMD I/O - USB - - - - PPS - - - - - - - Legend: - = No implemented SFRs in this block DS39897B-page 34 Preliminary © 2008 Microchip Technology Inc. © 2008 Microchip Technology Inc. Preliminary 0012 0014 0016 0018 001A 001C 001E 0020 002E 0030 0032 0034 0036 WREG9 WREG10 WREG10 WREG11 WREG11 WREG12 WREG12 WREG13 WREG13 WREG14 WREG14 WREG15 WREG15 SPLIM PCL PCH TBLPAG PSVPAG RCOUNT - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - = unimplemented, read as `0'. Reset values are shown in hexadecimal. 0010 WREG8 Legend: 000E WREG7 Bit 10 0052 000C WREG6 Bit 11 DISICNT 000A WREG5 Bit 12 0044 0008 WREG4 Bit 13 0042 0006 WREG3 Bit 14 SR 0004 WREG2 Bit 15 CPU CORE REGISTERS MAP CORCON 0000 0002 WREG0 WREG1 Addr File Name TABLE 3-3: Bit 7 Working Register 15 Working Register 14 Working Register 13 Working Register 12 Working Register 11 Working Register 10 Working Register 9 Working Register 8 Working Register 7 Working Register 6 Working Register 5 Working Register 4 Working Register 3 Working Register 2 Working Register 1 Working Register 0 Bit 8 Bit 6 - - - - - - IPL2 - IPL1 Bit 4 Bit 3 Bit 2 - IPL0 - RA IPL3 N PSV OV Program Space Visibility Page Address Register Table Memory Page Address Register Program Counter Register High Byte Bit 5 Disable Interrupts Counter Register - DC Repeat Loop Counter Register - - - Program Counter Low Word Register Stack Pointer Limit Value Register Bit 9 - Z Bit 1 - C Bit 0 xxxx 0000 0000 xxxx 0000 0000 0000 0000 xxxx 0800 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 All Resets PIC24FJ256GB110 PIC24FJ256GB110 FAMILY DS39897B-page 35 DS39897B-page 36 0064 0066 0068 CNEN3 CNEN4 CNEN5 Legend: Note 1: 2: - - - - CN59PUE CN59PUE - = unimplemented, read as `0'. Reset values are shown in hexadecimal. Unimplemented in 64-pin devices; read as `0'. Unimplemented in 64-pin and 80-pin devices; read as `0'. - CN60PUE CN60PUE CN25PUE CN25PUE CN24PUE CN24PUE - - - - - CN58PUE CN58PUE CN57PUE CN57PUE(1) CN56PUE CN56PUE 0074 CN79PUE CN79PUE(2) CN78PUE CN78PUE(1) CN77PUE CN77PUE(1) CN76PUE CN76PUE(2) CN75PUE CN75PUE(2) CN74PUE CN74PUE(1) CNPU6(2) 0076 CN61PUE CN61PUE CNPU5 CN62PUE CN62PUE 0072 CNPU4 CN63PUE CN63PUE CN26PUE CN26PUE - CN71PUE CN71PUE CN55PUE CN55PUE CN23PUE CN23PUE CN7PUE - CN70PUE CN70PUE(1) CN54PUE CN54PUE CN22PUE CN22PUE CN6PUE - CN4PUE - CN68IE CN68IE CN52IE CN52IE CN36IE CN36IE(2) CN3PUE - CN67IE CN67IE(1) CN51IE CN51IE CN35IE CN35IE(2) CN19IE CN19IE(1) CN3IE - - CN69PUE CN69PUE CN53PUE CN53PUE CN65PDE CN65PDE CN49PDE CN49PDE CN64PDE CN64PDE CN51PUE CN51PUE - - 0000 CN48PDE CN48PDE(2) 0000 0000 0000 0000 All Resets CN50PUE CN50PUE CN18PUE CN18PUE CN2PUE CN82IE CN82IE(2) CN66IE CN66IE(1) CN50IE CN50IE CN34IE CN34IE(2) CN18IE CN18IE CN2IE CN0IE 0000 0000 0000 0000 0000 0000 0000 0000 0000 CN64PUE CN64PUE 0000 CN48PUE CN48PUE(2) 0000 CN0PUE CN80IE CN80IE(2) CN64IE CN64IE CN48IE CN48IE(2) CN32IE CN32IE CN16IE CN16IE CN82PUE CN82PUE(2) CN81PUE CN81PUE(2) CN80PUE CN80PUE(2) 0000 CN65PUE CN65PUE CN49PUE CN49PUE CN1PUE CN81IE CN81IE(2) CN65IE CN65IE CN49IE CN49IE CN33IE CN33IE(2) CN17IE CN17IE CN1IE CN82PDE CN82PDE(2) CN81PDE CN81PDE(2) CN80PDE CN80PDE(2) 0000 CN68PUE CN68PUE CN67PUE CN67PUE(1) CN66PUE CN66PUE(1) CN52PUE CN52PUE CN21PUE CN21PUE(1) CN20PUE CN20PUE(1) CN19PUE CN19PUE(1) CN5PUE - CN69IE CN69IE CN53IE CN53IE CN37IE CN37IE(2) CN4IE CN20IE CN20IE(1) CN5IE - CN21IE CN21IE(1) - CN50PDE CN50PDE CN0PDE CN32PUE CN32PUE CN27PUE CN27PUE CN8PUE - CN70IE CN70IE(1) CN54IE CN54IE CN38IE CN38IE(2) CN22IE CN22IE CN6IE - CN51PDE CN51PDE CN68PDE CN68PDE CN67PDE CN67PDE(1) CN66PDE CN66PDE(1) CN52PDE CN52PDE CN1PDE 0070 CN47PUE CN47PUE(1) CN46PUE CN46PUE(2) CN45PUE CN45PUE(1) CN44PUE CN44PUE(1) CN43PUE CN43PUE(1) CN42PUE CN42PUE(1) CN41PUE CN41PUE(1) CN40PUE CN40PUE(2) CN39PUE CN39PUE(2) CN38PUE CN38PUE(2) CN37PUE CN37PUE(2) CN36PUE CN36PUE(2) CN35PUE CN35PUE(2) CN34PUE CN34PUE(2) CN33PUE CN33PUE(2) CN28PUE CN28PUE CN9PUE - CN71IE CN71IE CN55IE CN55IE CN39IE CN39IE(2) CN23IE CN23IE CN7IE - CN69PDE CN69PDE CN53PDE CN53PDE CN18PDE CN18PDE CN2PDE Bit 0 CNPU3 CN29PUE CN29PUE CN10PUE CN10PUE - - CN56IE CN56IE CN57IE CN57IE(1) - CN40IE CN40IE(2) CN24IE CN24IE CN8IE - CN41IE CN41IE(1) CN25IE CN25IE CN9IE - CN3PDE Bit 1 CN16PUE CN16PUE CN30PUE CN30PUE CN11PUE CN11PUE - CN74IE CN74IE(1) CN58IE CN58IE CN42IE CN42IE(1) CN26IE CN26IE CN10IE CN10IE - CN70PDE CN70PDE(1) CN4PDE CN21PDE CN21PDE(1) CN20PDE CN20PDE(1) CN19PDE CN19PDE(1) CN5PDE Bit 2 CN17PUE CN17PUE CN31PUE CN31PUE CN12PUE CN12PUE - CN75IE CN75IE(2) CN59IE CN59IE CN43IE CN43IE(1) CN27IE CN27IE CN11IE CN11IE - CN71PDE CN71PDE CN54PDE CN54PDE CN22PDE CN22PDE CN6PDE Bit 3 006E CN13PUE CN13PUE - CN76IE CN76IE(2) CN60IE CN60IE CN44IE CN44IE(1) CN28IE CN28IE CN12IE CN12IE - - CN55PDE CN55PDE CN23PDE CN23PDE CN7PDE Bit 4 CNPU2 CN14PUE CN14PUE - CN77IE CN77IE(1) CN61IE CN61IE CN45IE CN45IE(1) CN29IE CN29IE CN13IE CN13IE - - CN58PDE CN58PDE CN57PDE CN57PDE(1) CN56PDE CN56PDE CN24PDE CN24PDE CN8PDE Bit 5 006C CN15PUE CN15PUE - CN78IE CN78IE(1) CN79IE CN79IE(2) - CN62IE CN62IE CN46IE CN46IE(2) CN47IE CN47IE(1) CN63IE CN63IE CN30IE CN30IE CN14IE CN14IE - CN31IE CN31IE CN15IE CN15IE - CN59PDE CN59PDE CN25PDE CN25PDE CN9PDE Bit 6 CNPU1 CNEN6(2) 006A 0060 0062 CNEN2 005E CNEN1 CNPD6 CN60PDE CN60PDE 005C CN79PDE CN79PDE(2) CN78PDE CN78PDE(1) CN77PDE CN77PDE(1) CN76PDE CN76PDE(2) CN75PDE CN75PDE(2) CN74PDE CN74PDE(1) (2) CN61PDE CN61PDE CNPD5 CN62PDE CN62PDE 005A CNPD4 CN63PDE CN63PDE CN26PDE CN26PDE CN10PDE CN10PDE Bit 7 CN32PDE CN32PDE CN27PDE CN27PDE CN11PDE CN11PDE Bit 8 0058 CN47PDE CN47PDE(1) CN46PDE CN46PDE(2) CN45PDE CN45PDE(1) CN44PDE CN44PDE(1) CN43PDE CN43PDE(1) CN42PDE CN42PDE(1) CN41PDE CN41PDE(1) CN40PDE CN40PDE(2) CN39PDE CN39PDE(2) CN38PDE CN38PDE(2) CN37PDE CN37PDE(2) CN36PDE CN36PDE(2) CN35PDE CN35PDE(2) CN34PDE CN34PDE(2) CN33PDE CN33PDE(2) CN28PDE CN28PDE CN12PDE CN12PDE Bit 9 CNPD3 CN29PDE CN29PDE CN13PDE CN13PDE Bit 10 CN16PDE CN16PDE CN30PDE CN30PDE CN14PDE CN14PDE Bit 11 CN17PDE CN17PDE CN31PDE CN31PDE CN15PDE CN15PDE Bit 12 0054 Bit 13 0056 Bit 14 CNPD2 Bit 15 ICN REGISTER MAP CNPD1 Addr File Name TABLE 3-4: PIC24FJ256GB110 PIC24FJ256GB110 FAMILY Preliminary © 2008 Microchip Technology Inc. © 2008 Microchip Technology Inc. Preliminary 00C4 00C8 00CA 00CC IPC16 IPC16 IPC18 IPC18 IPC19 IPC19 IPC20 IPC20 00CE 00C2 IPC15 IPC15 IPC23 IPC23 - RTCIF - - - - T1IP2 - - T4IP2 IC5IP2 - - - - - - - - - - T2IP0 T1IP0 OC9IE - - OC8IE T5IE U1TXIE OC9IF - - OC8IF T5IF U1TXIF - - Bit 12 U3TXIP1 - - CRCIP1 - - - - OC7IP1 IC5IP1 - U2TXIP1 T4IP1 IC8IP1 CNIP1 - U3TXIP0 - - CRCIP0 - - - - OC7IP0 IC5IP0 - U2TXIP0 T4IP0 IC8IP0 CNIP0 - SPI3IP2 - - - - SPI3IP1 - SPI3IP0 U4ERIP2 U4ERIP1 U4ERIP0 - - U3TXIP2 - CRCIP2 - - - OC7IP2 - - - - U2TXIP2 - IC8IP2 CNIP2 - - T2IP1 T1IP1 IC9IE CTMUIE - PMPIE INT2IE AD1IE IC9IF CTMUIF - PMPIF INT2IF AD1IF - - Bit 13 U1RXIP2 U1RXIP1 U1RXIP0 - - T2IP2 - - - - - RTCIE - U2RXIE - U2TXIE - - - - - U2RXIF - - U2TXIF DISI - Bit 14 ALTIVT NSTDIS Bit 15 - - - - - - - - - - - - - - - - - - - - - - SPI3IE - - OC7IE T4IE U1RXIE SPI3IF - - OC7IF T4IF U1RXIF - - Bit 11 OC4IP1 IC7IP1 CMIP1 - SPI1IP1 OC2IP1 OC1IP1 U4TXIE - - OC5IE OC3IE SPF1IE U4TXIF - - OC5IF OC3IF SPF1IF - - Bit 9 OC4IP0 IC7IP0 CMIP0 - SPI1IP0 OC2IP0 OC1IP0 U4RXIE LVDIE - - OC6IP1 IC4IP1 - - OC6IP0 IC4IP0 - RTCIP1 INT4IP1 RTCIP0 INT4IP0 - - - - - SPF3IP2 - SPF3IP1 - SPF3IP0 USB1IP2 USB1IP1 USB1IP0 U3RXIP2 U3RXIP1 U3RXIP0 - - U2ERIP2 U2ERIP1 U2ERIP0 RTCIP2 INT4IP2 MI2C2P2 MI2C2P1 MI2C2P0 - OC6IP2 IC4IP2 - - - - - - - - - - - - - - - - - - - - - - - U4ERIE - - IC5IE IC8IE - IC6IE T2IE U4ERIF - - T3IE U4RXIF LVDIF - IC5IF IC8IF - IC6IF T2IF - - Bit 7 T3IF - - Bit 8 U2RXIP2 U2RXIP1 U2RXIP0 OC4IP2 IC7IP2 CMIP2 - SPI1IP2 OC2IP2 OC1IP2 SPF3IE - - OC6IE OC4IE SPI1IE SPF3IF - - OC6IF OC4IF SPI1IF - - Bit 10 INTERRUPT CONTROLLER REGISTER MAP - = unimplemented, read as `0'. Reset values are shown in hexadecimal. 00D2 IPC22 IPC22 Legend: 00D0 IPC21 IPC21 00BE IPC13 IPC13 00B6 IPC9 00BC 00B4 IPC8 IPC12 IPC12 00B2 IPC7 00B8 00B0 IPC6 00BA 00AE IPC5 IPC11 IPC11 00AC IPC4 IPC10 IPC10 00A8 00A6 IPC1 00AA 00A4 IPC0 IPC3 009E IEC5 IPC2 009C IEC4 0096 IEC1 0098 0094 IEC0 009A 008E IFS5 IEC3 008C IFS4 IEC2 0088 008A 0086 IFS1 IFS3 0084 IFS0 IFS2 0080 0082 INTCON1 INTCON2 Addr File Name TABLE 3-5: AD1IP1 SPF1IP1 IC2IP1 IC1IP1 MI2C3IE - INT3IE IC3IE - IC2IE MI2C3IF - INT3IF IC3IF - IC2IF - - Bit 5 - INT3IP1 SI2C2P1 PMPIP1 OC5IP1 IC3IP1 SPI2IP1 INT2IP1 OC3IP1 - - IC9IP2 U4TXIP2 IC9IP1 U4TXIP1 MI2C3P2 MI2C3P1 U3ERIP2 U3ERIP1 Bit 3 Bit 2 Bit 1 - U1ERIP0 - INT3IP0 SI2C2P0 PMPIP0 OC5IP0 IC3IP0 SPI2IP0 INT2IP0 OC3IP0 - MI2C1P0 AD1IP0 SPF1IP0 IC2IP0 IC1IP0 SI2C3IE - - - INT1IE - SI2C3IF - - - INT1IF - - U3ERIP0 IC9IP0 U4TXIP0 MI2C3P0 - - - - - - - - - - - - - - - - - - - - - - U3TXIE CRCIE - - CNIE T1IE U3TXIF CRCIF - - CNIF T1IF - SI2C3P1 - - LVDIP1 - - - - OC8IP1 IC6IP1 - SPF2IP1 T5IP1 - INT1IP1 SI2C1P1 U1TXIP1 T3IP1 - INT0IP1 U3ERIE U1ERIE SI2C2IE SPI2IE MI2C1IE IC1IE U3ERIF U1ERIF SI2C2IF SPI2IF MI2C1IF IC1IF INT1EP SI2C3P0 - - LVDIP0 - - - - OC8IP0 IC6IP0 - SPF2IP0 T5IP0 - INT1IP0 SI2C1P0 U1TXIP0 T3IP0 - INT0IP0 - - - SPF2IE SI2C1IE INT0IE - - - SPF2IF SI2C1IF INT0IF INT0EP - Bit 0 OC9IP2 OC9IP1 OC9IP0 U4RXIP2 U4RXIP1 U4RXIP0 SI2C3P2 - - LVDIP2 - - - - OC8IP2 IC6IP2 - SPF2IP2 T5IP2 - INT1IP2 SI2C1P2 U1TXIP2 T3IP2 - INT0IP2 U3RXIE U2ERIE MI2C2IE - CMIE OC1IE U3RXIF U2ERIF MI2C2IF - CMIF OC1IF INT2EP MATHERR ADDRERR STKERR OSCFAIL Bit 4 CTMUIP2 CTMUIP1 CTMUIP0 - U1ERIP2 U1ERIP1 - INT3IP2 SI2C2P2 PMPIP2 OC5IP2 IC3IP2 SPI2IP2 INT2IP2 OC3IP2 - MI2C1P2 MI2C1P1 AD1IP2 SPF1IP2 IC2IP2 IC1IP2 USB1IE - INT4IE IC4IE IC7IE OC2IE USB1IF - INT4IF IC4IF IC7IF OC2IF - - Bit 6 0044 4444 4444 4440 0040 0004 4440 0400 0440 0440 0044 4444 4440 0044 4444 4440 4404 4444 0044 4444 4440 4444 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 All Resets PIC24FJ256GB110 PIC24FJ256GB110 FAMILY DS39897B-page 37 DS39897B-page 38 010C 010E 0110 0112 0114 0116 0118 011A PR2 PR3 T2CON T3CON TMR4 TMR5HLD TMR5 PR4 TON TON TON - - - - Bit 14 TSIDL TSIDL TSIDL TSIDL Bit 13 - - - - Bit 12 - - - - Bit 11 - - - - - Legend: - 0120 - = unimplemented, read as `0'. Reset values are shown in hexadecimal. T5CON TSIDL 011E - Bit 7 - Timer2 Register - Timer1 Period Register Timer1 Register Bit 8 TGATE Bit 6 Bit 5 TCKPS1 - - - - Timer4 Register - - Timer3 Period Register Timer2 Period Register Timer3 Register TGATE TGATE TCKPS1 TCKPS1 - - - - - - Timer5 Period Register Timer4 Period Register Timer5 Register TGATE TGATE TCKPS1 TCKPS1 Timer5 Holding Register (for 32-bit operations only) T4CON TON - Bit 9 Timer3 Holding Register (for 32-bit timer operations only) - Bit 10 011C 010A TMR3 TON Bit 15 TIMER REGISTER MAP PR5 0106 0108 T1CON TMR3HLD 0104 PR1 TMR2 0100 0102 TMR1 Addr File Name TABLE 3-6: TCKPS0 TCKPS0 TCKPS0 TCKPS0 TCKPS0 Bit 4 - T32 - T32 - Bit 3 - - - - TSYNC Bit 2 TCS TCS TCS TCS TCS Bit 1 - - - - - Bit 0 0000 0000 FFFF FFFF 0000 0000 0000 0000 0000 FFFF FFFF 0000 0000 0000 0000 FFFF 0000 All Resets PIC24FJ256GB110 PIC24FJ256GB110 FAMILY Preliminary © 2008 Microchip Technology Inc. © 2008 Microchip Technology Inc. Preliminary 0180 IC9CON1 Legend: - Bit 14 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Bit 15 - ICSIDL - ICSIDL - ICSIDL - ICSIDL - ICSIDL - ICSIDL - ICSIDL - ICSIDL - ICSIDL Bit 13 Bit 11 Bit 10 - - - - - - - - - - - - - - - - - - - ICTSEL2 ICTSEL1 ICTSEL0 - ICTSEL2 ICTSEL1 ICTSEL0 - ICTSEL2 ICTSEL1 ICTSEL0 - ICTSEL2 ICTSEL1 ICTSEL0 - ICTSEL2 ICTSEL1 ICTSEL0 - ICTSEL2 ICTSEL1 ICTSEL0 - ICTSEL2 ICTSEL1 ICTSEL0 - ICTSEL2 ICTSEL1 ICTSEL0 - ICTSEL2 ICTSEL1 ICTSEL0 Bit 12 INPUT CAPTURE REGISTER MAP - = unimplemented, read as `0'. Reset values are shown in hexadecimal. 0184 0186 IC9BUF IC9TMR 0182 017E IC9CON2 017C IC8CON2 IC8BUF 0178 017A IC8CON1 IC8TMR 0174 0172 IC7CON2 0176 0170 IC7CON1 IC7BUF 016E IC7TMR 016C IC6CON2 IC6BUF 0168 016A IC6CON1 IC6TMR 0164 0162 IC5CON2 0166 0160 IC5CON1 IC5BUF 015E IC5TMR 015C IC4CON2 IC4BUF 0158 015A IC4CON1 IC4TMR 0154 0156 0152 IC3CON2 IC3BUF 0150 IC3CON1 IC3TMR 014E IC2CON2 014C 0148 014A IC2CON1 IC2BUF 0146 IC2TMR 0144 IC1BUF 0140 0142 IC1CON1 IC1CON2 IC1TMR Addr File Name TABLE 3-7: - - - - - - - - - - - - - - - - - - Bit 9 ICTRIG - Bit 7 TRIGSTAT ICI1 Bit 6 - ICTRIG ICI1 TRIGSTAT - ICTRIG ICI1 TRIGSTA