PIC24FJ128GA DS39747C ISO/TS-16949 RS-232 RS-485 PIC24FJ64GA006 PIC24FJ96GA006 - Datasheet Archive

 

Data Sheet General Purpose, 16-Bit Flash Microcontrollers © 2006 Microchip Technology Inc. Preliminary DS39747C Note the

 

PIC24FJ128GA PIC24FJ128GA Family Data Sheet General Purpose, 16-Bit Flash Microcontrollers © 2006 Microchip Technology Inc. Preliminary DS39747C DS39747C Note the following details of the code protection feature on Microchip devices: · Microchip products meet the specification contained in their particular Microchip Data Sheet. · Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. · There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. · Microchip is willing to work with the customer who is concerned about the integrity of their code. · Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Linear Active Thermistor, Mindi, MiWi, MPASM, MPLIB, MPLINK, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2006, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949 ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona, Gresham, Oregon and Mountain View, California. The Company's quality system processes and procedures are for its PICmicro® 8-bit MCUs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified. DS39747C-page ii Preliminary © 2006 Microchip Technology Inc. PIC24FJ128GA PIC24FJ128GA FAMILY General Purpose, 16-bit Flash Microcontrollers High-Performance CPU: Analog Features: · Modified Harvard Architecture · Up to 16 MIPS operation @ 32 MHz · 8 MHz internal oscillator: - 4x PLL option - Multiple divide options · 17-bit x 17-bit Single-Cycle Hardware Fractional/Integer Multiplier · 32-bit by 16-bit Hardware Divider · 16 x 16-bit Working Register Array · C compiler Optimized Instruction Set Architecture: - 76 base instructions - Flexible addressing modes · Linear Program Memory Addressing up to 12 Mbytes · Linear Data Memory Addressing up to 64 Kbytes · Two Address Generation Units for separate Read and Write Addressing of Data Memory · 10-bit, up to 16-channel Analog-to-Digital Converter (A/D): - 500 ksps conversion rate - Conversion available during Sleep and Idle · Dual Analog Comparators with Programmable Input/Output Configuration Peripheral Features: · Two 3-wire/4-wire SPI modules, supporting 4 Frame modes with 4-level FIFO Buffer · Two I2CTM modules support Multi-Master/Slave mode and 7-bit/10-bit Addressing · Two UART modules: - Supports RS-232 RS-232, RS-485 RS-485 and LIN 1.2 - Supports IrDA® with on-chip hardware endec - Auto-Wake-up on Start bit - Auto-Baud Detect - 4-level FIFO buffer · Parallel Master Slave Port (PMP/PSP): - Supports 8-bit or 16-bit data - Supports 16 address lines · Hardware Real-Time Clock/Calendar (RTCC): - Provides clock, calendar and alarm functions · Five 16-bit Timers/Counters with Programmable prescaler · Five 16-bit Capture Inputs · Five 16-bit Compare/PWM Outputs · High-Current Sink/Source on select I/O pins: 18 mA/18 mA · Configurable Open-Drain Output on Digital I/O pins · Up to 5 External Interrupt Sources Special Microcontroller Features: UART SPI I2CTM 10-bit A/D (ch) Comparators PMP/PSP JTAG 5 2 2 2 16 2 Y Y 2 2 2 16 2 Y Y 5 2 2 2 16 2 Y Y 5 5 2 2 2 16 2 Y Y 5 5 2 2 2 16 2 Y Y 5 5 5 2 2 2 16 2 Y Y 8K 5 5 5 2 2 2 16 2 Y Y 8K 5 5 5 2 2 2 16 2 Y Y 8K 5 5 5 2 2 2 16 2 Y Y Pins Program Memory (Bytes) SRAM (Bytes) Timers 16-bit Capture Input Compare/ PWM Output · Operating Voltage Range of 2.0V to 3.6V · Flash Program Memory: - 1000 erase/write cycles, typical - Flash retention 20 years, typical · Self-Reprogrammable under Software Control · Selectable Power Management modes: - Sleep, Idle and Alternate Clock modes · Fail-Safe Clock Monitor operation: - Detects clock failure and switches to on-chip, low-power RC oscillator · On-Chip LDO Regulator · JTAG Boundary Scan and Programming Support · Power-on Reset (POR), Power-up Timer (PWRT) and Oscillator Start-up Timer (OST) · Flexible Watchdog Timer (WDT) with On-Chip, Low-Power RC Oscillator for reliable operation · In-Circuit Serial ProgrammingTM (ICSPTM) and In-Circuit Emulation (ICE) via 2 pins PIC24FJ64GA006 PIC24FJ64GA006 64 64K 8K 5 5 PIC24FJ96GA006 PIC24FJ96GA006 64 96K 8K 5 5 5 PIC24FJ128GA006 PIC24FJ128GA006 64 128K 8K 5 5 PIC24FJ64GA008 PIC24FJ64GA008 80 64K 8K 5 PIC24FJ96GA008 PIC24FJ96GA008 80 96K 8K 5 PIC24FJ128GA008 PIC24FJ128GA008 80 128K 8K PIC24FJ64GA010 PIC24FJ64GA010 100 64K PIC24FJ96GA010 PIC24FJ96GA010 100 96K PIC24FJ128GA010 PIC24FJ128GA010 100 128K Device © 2006 Microchip Technology Inc. Preliminary DS39747C-page 1 PIC24FJ128GA PIC24FJ128GA FAMILY Pin Diagrams 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 PMD4/RE4 PMD3/RE3 PMD2/RE2 PMD1/RE1 PMD0/RE0 RF1 RF0 ENVREG VCAP/VDDCORE CN16/RD7 CN16/RD7 CN15/RD6 CN15/RD6 PMRD/CN14/RD5 PMRD/CN14/RD5 PMWR/OC5/IC5/CN13/RD4 PMWR/OC5/IC5/CN13/RD4 PMBE/OC4/RD3 OC3/RD2 OC2/RD1 64-Pin TQFP PMD5/RE5 PMD6/RE6 PMD7/RE7 PMA5/SCK2/CN8/RG6 PMA4/SDI2/CN9/RG7 PMA3/SDO2/CN10/RG8 PMA3/SDO2/CN10/RG8 MCLR PMA2/SS2/CN11/RG9 PMA2/SS2/CN11/RG9 VSS VDD C1IN+/AN5/CN7/RB5 C1IN-/AN4/CN6/RB4 C2IN+/AN3/CN5/RB3 C2IN-/AN2/SS1/CN4/RB2 PGC1/EMUC1/VREF-/AN1/CN3/RB1 2 3 4 5 6 7 8 9 10 11 12 SOSCO/T1CK/CN0/RC14 SOSCO/T1CK/CN0/RC14 47 SOSCI/CN1/RC13 SOSCI/CN1/RC13 46 OC1/RD0 IC4/PMCS1/INT4/RD11 IC4/PMCS1/INT4/RD11 IC3/PMCS2/INT3/RD10 IC3/PMCS2/INT3/RD10 IC2/U1CTS//INT2/RD9 45 44 43 42 PIC24FJXXGA006 PIC24FJXXGA006 PIC24FJXXXGA006 PIC24FJXXXGA006 41 40 39 38 37 36 35 13 14 15 16 34 33 IC1/RTCC/INT1/RD8 Vss OSC2/CLKO/RC15 OSC2/CLKO/RC15 OSC1/CLKI/RC12 OSC1/CLKI/RC12 VDD SCL1/RG2 SDA1/RG3 U1RTS/BCLK1/SCK1/INT0/RF6 U1RX/SDI1/RF2 U1TX/SDO1/RF3 PGC2/EMUC2/AN6/OCFA/RB6 PGD2/EMUD2/AN7/RB7 AVDD AVSS U2CTS/C1OUT/AN8/RB8 PMA7/C2OUT/AN9/RB9 TMS/PMA13/CVREF/AN10/RB10 TMS/PMA13/CVREF/AN10/RB10 TDO/PMA12/AN11/RB11 TDO/PMA12/AN11/RB11 VSS VDD TCK/PMA11/AN12/RB12 TCK/PMA11/AN12/RB12 TDI/PMA10/AN13/RB13 TDI/PMA10/AN13/RB13 PMA1/U2RTS/BCLK2/AN14/RB14 PMA1/U2RTS/BCLK2/AN14/RB14 PMA0/AN15/OCFB/CN12/RB15 PMA0/AN15/OCFB/CN12/RB15 PMA9/U2RX/SDA2/CN17/RF4 PMA9/U2RX/SDA2/CN17/RF4 PMA8/U2TX/SCL2/CN18/RF5 PMA8/U2TX/SCL2/CN18/RF5 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 PGD1/EMUD1/PMA6/VREF+/AN0/CN2/RB0 48 1 DS39747C-page 2 Preliminary © 2006 Microchip Technology Inc. PIC24FJ128GA PIC24FJ128GA FAMILY Pin Diagrams (Continued) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 PMD4/RE4 PMD3/RE3 PMD2/RE2 PMD1/RE1 PMD0/RE0 RG0 RG1 RF1 RF0 ENVREG VCAP/VDDCORE CN16/RD7 CN16/RD7 CN15/RD6 CN15/RD6 PMRD/CN14/RD5 PMRD/CN14/RD5 PMWR/OC5/CN13/RD4 PMWR/OC5/CN13/RD4 CN19/RD13 CN19/RD13 IC5/RD12 IC5/RD12 PMBE/OC4/RD3 OC3/RD2 OC2/RD1 80-Pin TQFP PMD5/RE5 PMD6/RE6 PMD7/RE7 T2CK/RC1 T4CK/RC3 PMA5/SCK2/CN8/RG6 PMA4/SDI2/CN9/RG7 PMA3/SDO2/CN10/RG8 PMA3/SDO2/CN10/RG8 MCLR PMA2/SS2/CN11/RG9 PMA2/SS2/CN11/RG9 VSS VDD TMS/INT1/RE8 TDO/INT2/RE9 2 3 4 5 6 7 8 9 10 11 12 PIC24FJXXGA008 PIC24FJXXGA008 PIC24FJXXXGA008 PIC24FJXXXGA008 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 SOSCO/T1CK/CN0/RC14 SOSCO/T1CK/CN0/RC14 SOSCI/CN1/RC13 SOSCI/CN1/RC13 OC1/RD0 IC4/PMCS1/RD11 IC4/PMCS1/RD11 IC3/PMCS2/RD10 IC3/PMCS2/RD10 IC2/RD9 IC1/RTCC/RD8 SDA2/INT4/RA15 SDA2/INT4/RA15 SCL2/INT3/RA14 SCL2/INT3/RA14 VSS OSC2/CLKO/RC15 OSC2/CLKO/RC15 OSC1/CLKI/RC12 OSC1/CLKI/RC12 VDD SCL1/RG2 SDA1/RG3 SCK1/INT0/RF6 SDI1/RF7 SDO1/RF8 U1RX/RF2 U1TX/RF3 PGC2/EMUC2/AN6/OCFA/RB6 PGD2/EMUD2/AN7/RB7 PMA7/VREF-/RA9 PMA6/VREF+/RA10 /RA10 AVDD AVSS U2CTS/C1OUT/AN8/RB8 C2OUT/AN9/RB9 PMA13/CVREF/AN10/RB10 PMA13/CVREF/AN10/RB10 PMA12/AN11/RB11 PMA12/AN11/RB11 VSS VDD TCK/PMA11/AN12/RB12 TCK/PMA11/AN12/RB12 TDI/PMA10/AN13/RB13 TDI/PMA10/AN13/RB13 PMA1/U2RTS/BCLK2/AN14/RB14 PMA1/U2RTS/BCLK2/AN14/RB14 PMA0/AN15/OCFB/CN12/RB15 PMA0/AN15/OCFB/CN12/RB15 CN20/U1CTS/RD14 CN20/U1CTS/RD14 CN21/U1RTS/BCLK1/RD15 CN21/U1RTS/BCLK1/RD15 PMA9/U2RX/CN17/RF4 PMA9/U2RX/CN17/RF4 PMA8/U2TX/CN18/RF5 PMA8/U2TX/CN18/RF5 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 C1IN+/AN5/CN7/RB5 C1IN-/AN4/CN6/RB4 C2IN+/AN3/CN5/RB3 C2IN-/AN2/SS1/CN4/RB2 PGC1/EMUC1/AN1/CN3/RB1 PGD1/EMUD1/AN0/CN2/RB0 1 © 2006 Microchip Technology Inc. Preliminary DS39747C-page 3 PIC24FJ128GA PIC24FJ128GA FAMILY Pin Diagrams (Continued) 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 PMD4/RE4 PMD3/RE3 PMD2/RE2 RG13 RG12 RG14 PMD1/RE1 PMD0/RE0 RA7 RA6 RG0 RG1 RF1 RF0 ENVREG VCAP/VDDCORE CN16/RD7 CN16/RD7 CN15/RD6 CN15/RD6 PMRD/CN14/RD5 PMRD/CN14/RD5 PMWR/OC5/CN13/RD4 PMWR/OC5/CN13/RD4 CN19/RD13 CN19/RD13 IC5/RD12 IC5/RD12 PMBE/OC4/RD3 OC3/RD2 OC2/RD1 100-Pin TQFP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 PIC24FJXXGA010 PIC24FJXXGA010 PIC24FJXXXGA010 PIC24FJXXXGA010 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 VSS SOSCO/T1CK/CN0/RC14 SOSCO/T1CK/CN0/RC14 SOSCI/CN1/RC13 SOSCI/CN1/RC13 OC1/RD0 IC4/PMCS1/RD11 IC4/PMCS1/RD11 IC3/PMCS2/RD10 IC3/PMCS2/RD10 IC2/RD9 IC1/RTCC/RD8 INT4/RA15 INT4/RA15 INT3/RA14 INT3/RA14 VSS OSC2/CLKO/RC15 OSC2/CLKO/RC15 OSC1/CLKI/RC12 OSC1/CLKI/RC12 VDD TDO/RA5 TDI/RA4 SDA2/RA3 SCL2/RA2 SCL1/RG2 SDA1/RG3 SCK1/INT0/RF6 SDI1/RF7 SDO1/RF8 U1RX/RF2 U1TX/RF3 PGC2/EMUC2/AN6/OCFA/RB6 PGD2/EMUD2/AN7/RB7 PMA7/VREF-/RA9 PMA6/VREF+/RA10 /RA10 AVDD AVSS C1OUT/AN8/RB8 C2OUT/AN9/RB9 PMA13/CVREF/AN10/RB10 PMA13/CVREF/AN10/RB10 PMA12/AN11/RB11 PMA12/AN11/RB11 VSS VDD TCK/RA1 U2RTS/BCLK2/RF13 U2RTS/BCLK2/RF13 U2CTS/RF12 U2CTS/RF12 PMA11/AN12/RB12 PMA11/AN12/RB12 PMA10/AN13/RB13 PMA10/AN13/RB13 PMA1/AN14/RB14 PMA1/AN14/RB14 PMA0/AN15/OCFB/CN12/RB15 PMA0/AN15/OCFB/CN12/RB15 VSS VDD CN20/U1CTS/RD14 CN20/U1CTS/RD14 CN21/U1RTS/BCLK1/RD15 CN21/U1RTS/BCLK1/RD15 PMA9/U2RX/CN17/RF4 PMA9/U2RX/CN17/RF4 PMA8/U2TX/CN18/RF5 PMA8/U2TX/CN18/RF5 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 RG15 VDD PMD5/RE5 PMD6/RE6 PMD7/RE7 T2CK/RC1 T3CK/RC2 T4CK/RC3 T5CK/RC4 PMA5/SCK2/CN8/RG6 PMA4/SDI2/CN9/RG7 PMA3/SDO2/CN10/RG8 PMA3/SDO2/CN10/RG8 MCLR PMA2/SS2/CN11/RG9 PMA2/SS2/CN11/RG9 VSS VDD TMS/RA0 INT1/RE8 INT2/RE9 C1IN+/AN5/CN7/RB5 C1IN-/AN4/CN6/RB4 C2IN+/AN3/CN5/RB3 C2IN-/AN2/SS1/CN4/RB2 PGC1/EMUC1/AN1/CN3/RB1 PGD1/EMUD1/AN0/CN2/RB0 DS39747C-page 4 Preliminary © 2006 Microchip Technology Inc. PIC24FJ128GA PIC24FJ128GA FAMILY Table of Contents 1.0 Device Overview . 7 2.0 CPU. 19 3.0 Memory Organization . 25 4.0 Flash Program Memory. 45 5.0 Resets . 51 6.0 Interrupt Controller . 57 7.0 Oscillator Configuration . 91 8.0 Power-Saving Features. 97 9.0 I/O Ports . 99 10.0 Timer1 . 101 11.0 Timer2/3 and Timer4/5 . 103 12.0 Input Capture. 109 13.0 Output Compare. 111 14.0 Serial Peripheral Interface (SPI). 115 15.0 Inter-Integrated Circuit (I2CTM) . 123 16.0 Universal Asynchronous Receiver Transmitter (UART) . 131 17.0 Parallel Master Port. 139 18.0 Real-Time Clock and Calendar . 149 19.0 Programmable Cyclic Redundancy Check (CRC) Generator . 161 20.0 10-bit High-Speed A/D Converter. 165 21.0 Comparator Module. 173 22.0 Comparator Voltage Reference. 177 23.0 Special Features . 179 24.0 Instruction Set Summary . 189 25.0 Development Support. 197 26.0 Electrical Characteristics . 201 27.0 Packaging Information. 213 Appendix A: Revision History. 219 Index . 221 The Microchip Web Site . 225 Customer Change Notification Service . 225 Customer Support . 225 Reader Response . 226 Product Identification System . 227 © 2006 Microchip Technology Inc. Preliminary DS39747C-page 5 PIC24FJ128GA PIC24FJ128GA FAMILY TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A DS30000A is version A of document DS30000 DS30000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: · Microchip's Worldwide Web site; http://www.microchip.com · Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. DS39747C-page 6 Preliminary © 2006 Microchip Technology Inc. PIC24FJ128GA PIC24FJ128GA FAMILY 1.0 DEVICE OVERVIEW 1.1.2 This document contains device specific information for the following devices: · · · · · · · · · PIC24FJ64GA006 PIC24FJ64GA006 PIC24FJ64GA008 PIC24FJ64GA008 PIC24FJ64GA010 PIC24FJ64GA010 PIC24FJ96GA006 PIC24FJ96GA006 PIC24FJ96GA008 PIC24FJ96GA008 PIC24FJ96GA010 PIC24FJ96GA010 PIC24FJ128GA006 PIC24FJ128GA006 PIC24FJ128GA008 PIC24FJ128GA008 PIC24FJ128GA010 PIC24FJ128GA010 POWER-SAVING TECHNOLOGY All of the devices in the PIC24FJ128GA PIC24FJ128GA family incorporate a range of features that can significantly reduce power consumption during operation. Key items include: This family introduces a new line of Microchip devices: a 16-bit RISC microcontroller family with a broad peripheral feature set and enhanced computational performance. The PIC24FJ128GA PIC24FJ128GA family offers a new migration option for those high-performance applications which may be outgrowing their 8-bit platforms, but don't require the numerical processing power of a digital signal processor. · On-the-Fly Clock Switching: The device clock can be changed under software control to the Timer1 source or the internal low-power RC oscillator during operation, allowing the user to incorporate power-saving ideas into their software designs. · Doze Mode Operation: When timing-sensitive applications, such as serial communications, require the uninterrupted operation of peripherals, the CPU clock speed can be selectively reduced, allowing incremental power savings without missing a beat. · Instruction-Based Power-Saving Modes: The microcontroller can suspend all operations, or selectively shut down its core while leaving its peripherals active, with a single instruction in software. 1.1 1.1.3 1.1.1 Core Features 16-BIT 16-BIT ARCHITECTURE Central to all PIC24 PIC24 devices is the 16-bit modified Harvard architecture, first introduced with Microchip's dsPIC® digital signal controllers. The PIC24 PIC24 CPU core offers a wide range of enhancements, such as: · 16-bit data and 24-bit address paths, with the ability to move information between data and memory spaces · Linear addressing of up to 8 Mbytes (program space) and 64 Kbytes (data) · A 16-element working register array with built-in software stack support · A 17 x 17 hardware multiplier with support for integer math · Hardware support for 32 by 16-bit division · An instruction set that supports multiple addressing modes and is optimized for high-level languages such as `C' · Operational performance up to 16 MIPS OSCILLATOR OPTIONS AND FEATURES All of the devices in the PIC24FJ128GA PIC24FJ128GA family offer five different oscillator options, allowing users a range of choices in developing application hardware. These include: · Two Crystal modes, using crystals or ceramic resonators. · Two External Clock modes, offering the option of a divide-by-2 clock output. · A Fast Internal Oscillator (FRC) with a nominal 8 MHz output, which can also be divided under software control to provide clock speeds as low as 31 kHz. · A Phase Lock Loop (PLL) frequency multiplier, available to the external oscillator modes and the FRC oscillator, which allows clock speeds of up to 32 MHz. · A separate internal RC oscillator (LPRC) with a fixed 31 kHz output, which provides a low-power option for timing-insensitive applications. The internal oscillator block also provides a stable reference source for the Fail-Safe Clock Monitor. This option constantly monitors the main clock source against a reference signal provided by the internal oscillator and enables the controller to switch to the internal oscillator, allowing for continued low-speed operation or a safe application shutdown. © 2006 Microchip Technology Inc. Preliminary DS39747C-page 7 PIC24FJ128GA PIC24FJ128GA FAMILY 1.1.4 1.3 EASY MIGRATION Regardless of the memory size, all devices share the same rich set of peripherals, allowing for a smooth migration path as applications grow and evolve. The consistent pinout scheme used throughout the entire family also aids in migrating to the next larger device. This is true when moving between devices with the same pin count, or even jumping from 64-pin to 80-pin to 100-pin devices. Details on Individual Family Members Devices in the PIC24FJ128GA PIC24FJ128GA family are available in 64-pin, 80-pin and 100-pin packages. The general block diagram for all devices is shown in Figure 1-1. The devices are differentiated from each other in two ways: 1. Flash program memory (64 Kbytes for PIC24FJ64GA PIC24FJ64GA devices, 96 Kbytes for PIC24FJ96GA PIC24FJ96GA devices and 128 Kbytes for PIC24FJ128GA PIC24FJ128GA devices). Available I/O pins and ports (53 pins on 6 ports for 64-pin devices, 69 pins on 7 ports for 80-pin devices and 84 pins on 7 ports for 100-pin devices). The PIC24 PIC24 family is pin-compatible with devices in the dsPIC33 family, and shares some compatibility with the pinout schema for PIC18 PIC18 and dsPIC30. This extends the ability of applications to grow from the relatively simple to the powerful and complex, yet still select a Microchip device. 2. 1.2 All other features for devices in this family are identical. These are summarized in Table 1-1. Other Special Features · Communications: The PIC24FJ128GA PIC24FJ128GA family incorporates a range of serial communication peripherals to handle a range of application requirements. All devices are equipped with two independent UARTs with built-in IrDA encoder/decoders. There are also two independent SPI modules, and two independent I2C modules that support both Master and Slave modes of operation. · Parallel Master/Enhanced Parallel Slave Port: One of the general purpose I/O ports can be reconfigured for enhanced parallel data communications. In this mode, the port can be configured for both master and slave operations, and supports 8-bit and 16-bit data transfers with up to 16 external address lines in Master modes. · Real-Time Clock/Calendar: This module implements a full-featured clock and calendar with alarm functions in hardware, freeing up timer resources and program memory space for use of the core application. · 10-Bit A/D Converter: This module incorporates programmable acquisition time, allowing for a channel to be selected and a conversion to be initiated without waiting for a sampling period, as well as faster sampling speeds. DS39747C-page 8 A list of the pin features available on the PIC24FJ128GA PIC24FJ128GA family devices, sorted by function, is shown in Table 1-2. Note that this table shows the pin location of individual peripheral features and not how they are multiplexed on the same pin. This information is provided in the pinout diagrams in the beginning of the data sheet. Multiplexed features are sorted by the priority given to a feature, with the highest priority peripheral being listed first. Preliminary © 2006 Microchip Technology Inc. PIC24FJ128GA PIC24FJ128GA FAMILY Operating Frequency Program Memory (Bytes) Program Memory (Instructions) PIC24FJ128GA010 PIC24FJ128GA010 PIC24FJ96GA010 PIC24FJ96GA010 PIC24FJ64GA010 PIC24FJ64GA010 PIC24FJ128GA008 PIC24FJ128GA008 PIC24FJ96GA008 PIC24FJ96GA008 PIC24FJ64GA008 PIC24FJ64GA008 PIC24FJ96GA006 PIC24FJ96GA006 Features PIC24FJ128GA006 PIC24FJ128GA006 DEVICE FEATURES FOR THE PIC24FJ128GA PIC24FJ128GA FAMILY PIC24FJ64GA006 PIC24FJ64GA006 TABLE 1-1: DC ­ 32 MHz 64K 96K 128K 64K 96K 128K 64K 96K 128K 22,016 32,768 44,032 22,016 32,768 44,032 22,016 32,768 44,032 Data Memory (Bytes) 8192 Interrupt Sources (Soft Vectors/NMI Traps) 43 (39/4) I/O Ports Total I/O Pins Ports B, C, D, E, F, G Ports A, B, C, D, E, F, G Ports A, B, C, D, E, F, G 53 69 84 Timers: Total number (16-bit) 5 32-bit (from paired 16-bit timers) 2 Input Capture Channels 5 Output Compare/PWM Channels 5 Input Change Notification Interrupt 19 22 Serial Communications: Enhanced UART 2 SPI (3-wire/4-wire) 2 I2CTM 2 Parallel Communications (PMP/PSP) Yes JTAG Boundary Scan Yes 10-bit Analog-to-Digital Module (input channels) 16 Analog Comparators 2 Resets (and Delays) POR, BOR, RESET Instruction, MCLR, WDT; Illegal Opcode, Repeat Hardware Traps, (PWRT, OST, PLL Lock) Instruction Set Packages © 2006 Microchip Technology Inc. 76 Base Instructions, Multiple Addressing Mode Variations 64-pin TQFP Preliminary 80-pin TQFP 100-pin TQFP DS39747C-page 9 PIC24FJ128GA PIC24FJ128GA FAMILY FIGURE 1-1: PIC24FJ128GA PIC24FJ128GA FAMILY GENERAL BLOCK DIAGRAM Data Bus Interrupt Controller PORTA(1) RA0:RA7, RA9:RA10, RA14:15 16 16 8 16 Data Latch PSV & Table Data Access Control Block Data RAM PCU PCH PCL Program Counter Repeat Stack Control Control Logic Logic 23 PORTB Address Latch RB0:RB15 16 23 16 Read AGU Write AGU Address Latch 16 PORTC(1) RC1:RC4, RC12:RC15 Program Memory Data Latch EA MUX 24 Inst Latch Literal Data Address Bus 16 PORTD(1) 16 RD0:RD15 Inst Register Instruction Decode & Control RE0:RE9 Control Signals OSC2/CLKO OSC1/CLKI Timing Generation FRC/LPRC Oscillators Precision Band Gap Reference ENVREG Voltage Regulator VDDCORE/VCAP Timer1 PORTE(1) Divide Support 16 x 16 W Reg Array 17x17 Multiplier Power-up Timer PORTF(1) RF0:RF8, RF12:RF13 Oscillator Start-up Timer 16-bit ALU Power-on Reset 16 Watchdog Timer PORTG(1) Brown-out Reset(2) RG0:RG9, RG12:RG15 VDD, VSS Timer2/3 MCLR Timer4/5 RTCC 10-bit ADC Comparators PMP/PSP IC1-5 Note PWM/ OC1-5 CN1-22 CN1-22(1) SPI1/2 I2C1/2 UART1/2 1: Not all pins or features are implemented on all device pinout configurations. See Table 1-2 for I/O port pin descriptions. 2: BOR functionality is provided when the on-board voltage regulator is enabled. DS39747C-page 10 Preliminary © 2006 Microchip Technology Inc. PIC24FJ128GA PIC24FJ128GA FAMILY TABLE 1-2: PIC24FJ128GA PIC24FJ128GA FAMILY PINOUT DESCRIPTIONS Pin Number I/O Input Buffer 25 I ANA 24 I ANA 18 23 I ANA 17 22 I ANA 12 16 21 I ANA AN5 11 15 20 I ANA AN6 17 21 26 I ANA AN7 18 22 27 I ANA AN8 21 27 32 I ANA AN9 22 28 33 I ANA AN10 23 29 34 I ANA AN11 24 30 35 I ANA AN12 27 33 41 I ANA AN13 28 34 42 I ANA AN14 29 35 43 I ANA AN15 30 36 44 I ANA AVDD 19 25 30 P - Positive Supply for Analog Modules. AVSS 20 26 31 P - Ground Reference for Analog Modules. BCLK1 35 38 48 O - UART1 IrDA® Baud Clock. BCLK2 29 35 39 O - UART2 IrDA® Baud Clock. C1IN- 12 16 21 I ANA Comparator 1 Negative Input. C1IN+ 11 15 20 I ANA Comparator 1 Positive Input. Function 64-pin 80-pin 100-pin AN0 16 20 AN1 15 19 AN2 14 AN3 13 AN4 Description A/D Analog Inputs. C1OUT 21 27 32 O - C2IN- 14 18 23 I ANA Comparator 2 Negative Input. Comparator 2 Positive Input. C2IN+ 13 17 22 I ANA C2OUT 22 28 33 O - Comparator 1 Output. Comparator 2 Output. CLKI 39 49 63 I ANA CLKO 40 50 64 O - System Clock Output. CN0 48 60 74 I ST Interrupt-on-Change Inputs. CN1 47 59 73 I ST CN2 16 20 25 I ST CN3 15 19 24 I ST CN4 14 18 23 I ST CN5 13 17 22 I ST CN6 12 16 21 I ST CN7 11 15 20 I ST CN8 4 6 10 I ST CN9 5 7 11 I ST CN10 6 8 12 I ST CN11 8 10 14 I ST CN12 30 36 44 I ST CN13 52 66 81 I ST CN14 53 67 82 I ST CN15 54 68 83 I ST CN16 55 69 84 I ST CN17 31 39 49 I Main Clock Input Connection. ST Legend: TTL = TTL input buffer ANA = Analog level input/output © 2006 Microchip Technology Inc. ST = Schmitt Trigger input buffer I2CTM = I2C/SMBus input buffer Preliminary DS39747C-page 11 PIC24FJ128GA PIC24FJ128GA FAMILY TABLE 1-2: PIC24FJ128GA PIC24FJ128GA FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number Function I/O 100-pin Input Buffer Description 64-pin 80-pin CN18 32 40 50 I ST CN19 - 65 80 I ST CN20 - 37 47 I ST CN21 - 38 48 I ST CVREF 23 29 34 O ANA Comparator Voltage Reference Output. EMUC1 15 19 24 I/O ST In-Circuit Emulator Clock Input/Output. EMUD1 16 20 25 I/O ST In-Circuit Emulator Data Input/Output. EMUC2 17 21 26 I/O ST In-Circuit Emulator Clock Input/Output. EMUD2 18 22 27 I/O ST In-Circuit Emulator Data Input/Output. ENVREG 57 71 86 I ST Enable for On-Chip Voltage Regulator. Input Capture Inputs. IC1 42 54 68 I ST IC2 43 55 69 I ST IC3 44 56 70 I ST IC4 45 57 71 I Interrupt-on-Change Inputs. ST ST IC5 52 64 79 I INT0 35 45 55 I ST INT1 42 13 18 I ST INT2 43 14 19 I ST INT3 44 52 66 I ST INT4 45 53 67 I ST MCLR 7 9 13 I ST Master Clear (Device Reset) Input. This line is brought low to cause a Reset. OC1 46 58 72 O - Output Compare/PWM Outputs. OC2 49 61 76 O - OC3 50 62 77 O - OC4 51 63 78 O - OC5 52 66 81 O - OCFA 17 21 26 I ST Output Compare Fault A Input. Output Compare Fault B Input. External Interrupt Inputs. OCFB 30 36 44 I ST OSC1 39 49 63 I ANA Main Oscillator Input Connection. OSC2 40 50 64 O ANA Main Oscillator Output Connection. PGC1 15 19 24 I/O ST In-Circuit Debugger and ICSPTM Programming Clock PGD1 16 20 25 I/O ST In-Circuit Debugger and ICSP Programming Data. PGC2 17 21 26 I/O ST In-Circuit Debugger and ICSPTM Programming Clock. PGD2 18 22 27 I/O ST In-Circuit Debugger and ICSP Programming Data. Legend: TTL = TTL input buffer ANA = Analog level input/output DS39747C-page 12 ST = Schmitt Trigger input buffer I2CTM = I2C/SMBus input buffer Preliminary © 2006 Microchip Technology Inc. PIC24FJ128GA PIC24FJ128GA FAMILY TABLE 1-2: PIC24FJ128GA PIC24FJ128GA FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number I/O Input Buffer 44 I/O ST Parallel Master Port Address Bit 0 Input (Buffered Slave modes) and Output (Master modes). 35 43 I/O ST Parallel Master Port Address Bit 1 Input (Buffered Slave modes) and Output (Master modes). 8 10 14 O - 6 8 12 O - Parallel Master Port Address (Demultiplexed Master modes). PMA4 5 7 11 O - PMA5 4 6 10 O - PMA6 16 24 29 O - PMA7 22 23 28 O - PMA8 32 40 50 O - PMA9 31 39 49 O - PMA10 PMA10 28 34 42 O - PMA11 PMA11 27 33 41 O - PMA12 PMA12 24 30 35 O - PMA13 PMA13 23 29 34 O - Function 64-pin 80-pin 100-pin PMA0 30 36 PMA1 29 PMA2 PMA3 Description PMBE 51 63 78 O - Parallel Master Port Byte Enable Strobe. PMCS1 45 57 71 O - Parallel Master Port Chip Select 1 Strobe/Address bit 14. PMCS2 44 56 70 O - Parallel Master Port Chip Select 2 Strobe/Address bit 15. PMD0 60 76 93 I/O ST PMD1 61 77 94 I/O ST Parallel Master Port Data (Demultiplexed Master mode) or Address/Data (Multiplexed Master modes). PMD2 62 78 98 I/O ST PMD3 63 79 99 I/O ST PMD4 64 80 100 I/O ST PMD5 1 1 3 I/O ST PMD6 2 2 4 I/O ST PMD7 3 3 5 I/O ST PMRD 53 67 82 O - Parallel Master Port Read Strobe. 52 66 81 O - Parallel Master Port Write Strobe. PMWR Legend: TTL = TTL input buffer ANA = Analog level input/output © 2006 Microchip Technology Inc. ST = Schmitt Trigger input buffer I2CTM = I2C/SMBus input buffer Preliminary DS39747C-page 13 PIC24FJ128GA PIC24FJ128GA FAMILY TABLE 1-2: PIC24FJ128GA PIC24FJ128GA FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number Function I/O 64-pin 80-pin 100-pin Input Buffer RA0 - - 17 I/O ST RA1 - - 38 I/O ST RA2 - - 58 I/O ST RA3 - - 59 I/O ST RA4 - - 60 I/O ST RA5 - - 61 I/O ST RA6 - - 91 I/O ST RA7 - - 92 I/O ST RA9 - 23 28 I/O ST RA10 - 24 29 I/O ST RA14 - 52 66 I/O ST RA15 - 53 67 I/O ST RB0 16 20 25 I/O ST RB1 15 19 24 I/O ST RB2 14 18 23 I/O ST RB3 13 17 22 I/O ST RB4 12 16 21 I/O ST RB5 11 15 20 I/O ST RB6 17 21 26 I/O ST RB7 18 22 27 I/O ST RB8 21 27 32 I/O ST RB9 22 28 33 I/O Description ST RB10 23 29 34 I/O 24 30 35 I/O ST RB12 27 33 41 I/O ST RB13 28 34 42 I/O ST RB14 29 35 43 I/O ST RB15 30 36 44 I/O ST RC1 - 4 6 I/O ST RC2 - - 7 I/O ST RC3 - 5 8 I/O ST RC4 - - 9 I/O ST RC12 39 49 63 I/O ST RC13 47 59 73 I/O ST RC14 48 60 74 I/O ST RC15 40 50 64 I/O PORTB Digital I/O. ST RB11 PORTA Digital I/O. Legend: TTL = TTL input buffer ANA = Analog level input/output DS39747C-page 14 PORTC Digital I/O. ST ST = Schmitt Trigger input buffer I2CTM = I2C/SMBus input buffer Preliminary © 2006 Microchip Technology Inc. PIC24FJ128GA PIC24FJ128GA FAMILY TABLE 1-2: PIC24FJ128GA PIC24FJ128GA FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number Function I/O 64-pin 80-pin 100-pin Input Buffer RD0 46 58 72 I/O ST RD1 49 61 76 I/O ST RD2 50 62 77 I/O ST RD3 51 63 78 I/O ST RD4 52 66 81 I/O ST RD5 53 67 82 I/O ST RD6 54 68 83 I/O ST RD7 55 69 84 I/O ST RD8 42 54 68 I/O ST RD9 43 55 69 I/O ST RD10 44 56 70 I/O ST RD11 45 57 71 I/O ST RD12 - 64 79 I/O ST RD13 - 65 80 I/O ST RD14 - 37 47 I/O ST RD15 - 38 48 I/O ST RE0 60 76 93 I/O ST RE1 61 77 94 I/O ST RE2 62 78 98 I/O ST RE3 63 79 99 I/O ST RE4 64 80 100 I/O ST RE5 1 1 3 I/O ST RE6 2 2 4 I/O ST RE7 3 3 5 I/O ST RE8 - 13 18 I/O ST RE9 - 14 19 I/O ST RF0 58 72 87 I/O ST RF1 59 73 88 I/O ST RF2 34 42 52 I/O ST RF3 33 41 51 I/O ST RF4 31 39 49 I/O ST RF5 32 40 50 I/O ST RF6 35 45 55 I/O ST RF7 - 44 54 I/O Description ST RF8 - 43 53 I/O - - 40 I/O - - 39 I/O PORTF Digital I/O. ST RF13 PORTE Digital I/O. ST RF12 PORTD Digital I/O. Legend: TTL = TTL input buffer ANA = Analog level input/output © 2006 Microchip Technology Inc. ST ST = Schmitt Trigger input buffer I2CTM = I2C/SMBus input buffer Preliminary DS39747C-page 15 PIC24FJ128GA PIC24FJ128GA FAMILY TABLE 1-2: PIC24FJ128GA PIC24FJ128GA FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number I/O Input Buffer 90 I/O ST 89 I/O ST 47 57 I/O ST 46 56 I/O ST 4 6 10 I/O ST RG7 5 7 11 I/O ST RG8 6 8 12 I/O ST RG9 8 10 14 I/O ST RG12 - - 96 I/O ST RG13 - - 97 I/O ST RG14 - - 95 I/O ST RG15 - - 1 I/O ST RTCC 42 54 68 O - Real-Time Clock Alarm Output. SCK1 35 45 55 O - SPI1 Serial Clock Output. Function 64-pin 80-pin 100-pin RG0 - 75 RG1 - 74 RG2 37 RG3 36 RG6 Description PORTG Digital I/O. SCK2 4 6 10 I/O ST SPI2 Serial Clock Output. SCL1 37 47 57 I/O I 2C I2C1 Synchronous Serial Clock Input/Output. SCL2 32 52 58 I/O I 2C I2C2 Synchronous Serial Clock Input/Output. SDA1 36 46 56 I/O I 2C I2C1 Data Input/Output. 2 SDA2 31 53 59 I/O I C I2C2 Data Input/Output. SDI1 34 44 54 I ST SPI1 Serial Data Input. SDI2 5 7 11 I ST SPI2 Serial Data Input. SDO1 33 43 53 O - SPI1 Serial Data Output. SDO2 6 8 12 O - SOSCI 47 59 73 I ANA Secondary Oscillator/Timer1 Clock Input. SPI2 Serial Data Output. SOSCO 48 60 74 O ANA Secondary Oscillator/Timer1 Clock Output. SS1 14 18 23 I/O ST Slave Select Input/Frame Select Output (SPI1). SS2 8 10 14 I/O ST Slave Select Input/Frame Select Output (SPI2). T1CK 48 60 74 I ST Timer1 Clock. T2CK - 4 6 I ST Timer2 External Clock Input. T3CK - - 7 I ST Timer3 External Clock Input. T4CK - 5 8 I ST Timer4 External Clock Input. T5CK - - 9 I ST Timer5 External Clock Input. TCK 27 33 38 I ST JTAG Test Clock/Programming Clock Input. TDI 28 34 60 I ST JTAG Test Data/Programming Data Input. TDO 24 14 61 O - JTAG Test Data Output. TMS 23 13 17 I ST JTAG Test Mode Select Input. Legend: TTL = TTL input buffer ANA = Analog level input/output DS39747C-page 16 ST = Schmitt Trigger input buffer I2CTM = I2C/SMBus input buffer Preliminary © 2006 Microchip Technology Inc. PIC24FJ128GA PIC24FJ128GA FAMILY TABLE 1-2: PIC24FJ128GA PIC24FJ128GA FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number I/O Input Buffer 47 I ST 38 48 O - UART1 Request to Send Output. 42 52 I ST UART1 Receive. 33 41 51 O DIG UART1 Transmit Output. U2CTS 21 27 40 I ST UART2 Clear to Send Input. U2RTS 29 35 39 O - UART2 Request to Send Output. U2RX 31 39 49 I ST UART 2 Receive Input. U2TX 32 40 50 O - UART2 Transmit Output. VDD 10, 26, 38 12, 32, 48 2, 16, 37, 46, 62 P - Positive Supply for Peripheral Digital Logic and I/O pins. VDDCAP 56 70 85 P - External Filter Capacitor Connection (regulator enabled). VDDCORE 56 70 85 P - Positive Supply for Microcontroller Core Logic (regulator disabled). Function 64-pin 80-pin 100-pin U1CTS 43 37 U1RTS 35 U1RX 34 U1TX Description UART1 Clear to Send Input. VREF- 15 23 28 I ANA A/D and Comparator Reference Voltage (Low) Input. VREF+ 16 24 29 I ANA A/D and Comparator Reference Voltage (High) Input. VSS 9, 25, 41 11, 31, 51 15, 36, 45, 65, 75 P - Legend: TTL = TTL input buffer ANA = Analog level input/output © 2006 Microchip Technology Inc. Ground Reference for Logic and I/O pins. ST = Schmitt Trigger input buffer I2CTM = I2C/SMBus input buffer Preliminary DS39747C-page 17 PIC24FJ128GA PIC24FJ128GA FAMILY NOTES: DS39747C-page 18 Preliminary © 2006 Microchip Technology Inc. PIC24FJ128GA PIC24FJ128GA FAMILY 2.0 CPU The PIC24 PIC24 CPU has a 16-bit (data) modified Harvard architecture with an enhanced instruction set, and a 23-bit instruction word with a variable length opcode field. The Program Counter (PC) is 24 bits wide and addresses up to 4M instructions of user program memory space. A single-cycle instruction prefetch mechanism is used to help maintain throughput and provides predictable execution. All instructions execute in a single cycle, with the exception of instructions that change the program flow, the double-word move (MOV.D) instruction and the table instructions. Overhead-free program loop constructs are supported using the REPEAT instructions, which are interruptible at any point. PIC24 PIC24 devices have sixteen 16-bit working registers in the programmer's model. Each of the working registers can act as a data, address or address offset register. The 16th working register (W15) operates as a software Stack Pointer for interrupts and calls. The upper 32 Kbytes of the data space memory map can optionally be mapped into program space at any 16K word boundary defined by the 8-bit Program Space Visibility Page (PSVPAG) register. The program to data space mapping feature lets any instruction access program space as if it were data space. The Instruction Set Architecture (ISA) has been significantly enhanced beyond that of the PIC18 PIC18, but maintains an acceptable level of backward compatibility. All PIC18 PIC18 instructions and addressing modes are supported either directly or through simple macros. Many of the ISA enhancements have been driven by compiler efficiency needs. The core supports Inherent (no operand), Relative, Literal, Memory Direct and three groups of addressing modes. All modes support Register Direct and various Register Indirect modes. Each group offers up to 7 addressing modes. Instructions are associated with predefined addressing modes depending upon their functional requirements. © 2006 Microchip Technology Inc. For most instructions, the core is capable of executing a data (or program data) memory read, a working register (data) read, a data memory write and a program (instruction) memory read per instruction cycle. As a result, three-parameter instructions can be supported, allowing trinary operations (that is, A + B = C) to be executed in a single cycle. A high-speed 17-bit by 17-bit multiplier has been included to significantly enhance the core arithmetic capability and throughput. The multiplier supports signed, unsigned and mixed mode 16-bit by 16-bit or 8-bit by 8-bit integer multiplication. All multiply instructions execute in a single cycle. The 16-bit ALU has been enhanced with integer divide assist hardware that supports an iterative non-restoring divide algorithm. It operates in conjunction with the REPEAT instruction looping mechanism, and a selection of iterative divide instructions, to support 32-bit (or 16-bit) divided by 16-bit integer signed and unsigned division. All divide operations require 19 cycles to complete but are interruptible at any cycle boundary. The PIC24 PIC24 has a vectored exception scheme with up to 8 sources of non-maskable traps and up to 118 interrupt sources. Each interrupt source can be assigned to one of seven priority levels. A block diagram of the CPU is shown in Figure 2-1. 2.1 Programmer's Model The programmer's model for the PIC24 PIC24 is shown in Figure 2-2. All registers in the programmer's model are memory mapped and can be manipulated directly by instructions. A description of each register is provided in Table 2-1. All registers associated with the programmer's model are memory mapped. Preliminary DS39747C-page 19 PIC24FJ128GA PIC24FJ128GA FAMILY FIGURE 2-1: PIC24 PIC24 CPU CORE BLOCK DIAGRAM PSV & Table Data Access Control Block Data Bus Interrupt Controller 16 8 16 16 Data Latch 23 23 PCU PCH PCL Program Counter Loop Stack Control Control Logic Logic 16 Data RAM Address Latch 23 16 RAGU WAGU Address Latch Program Memory EA MUX Address Bus Data Latch ROM Latch 24 Control Signals to Various Blocks Instruction Reg Hardware Multiplier Divide Support 16 Literal Data Instruction Decode & Control 16 16 x 16 W Register Array 16 16-Bit ALU 16 To Peripheral Modules DS39747C-page 20 Preliminary © 2006 Microchip Technology Inc. PIC24FJ128GA PIC24FJ128GA FAMILY TABLE 2-1: CPU CORE REGISTERS Register(s) Name Description W0 through W15 Working register array PC 23-bit Program Counter SR ALU STATUS register SPLIM Stack Pointer Limit Value register TBLPAG Table Memory Page Address register PSVPAG Program Space Visibility Page Address register RCOUNT Repeat Loop Counter register CORCON CPU Control Register FIGURE 2-2: PROGRAMMER'S MODEL 15 Divider Working Registers 0 W0 (WREG) W1 W2 Multiplier Registers W3 W4 W5 W6 W7 Working/Address Registers W8 W9 W10 W11 W12 W13 W14 Frame Pointer W15 Stack Pointer 0 SPLIM 0 Stack Pointer Limit 0 0 Program Counter 22 PC 7 0 TBLPAG 7 Data Table Page Address 0 Program Space Visibility Page Address PSVPAG 15 0 RCOUNT 15 SRH REPEAT Loop Counter SRL 0 - - - - - - - DC IPL RA N OV Z C 2 1 0 STATUS Register (SR) 0 15 - - - - - - - - - - - - IPL3 PSV - - Core Control Register (CORCON) Registers or bits shadowed for PUSH.S and POP.S instructions. © 2006 Microchip Technology Inc. Preliminary DS39747C-page 21 PIC24FJ128GA PIC24FJ128GA FAMILY 2.2 CPU Control Registers REGISTER 2-1: SR: CPU STATUS REGISTER Upper Byte: U-0 U-0 U-0 U-0 U-0 U-0 U -0 R/W-0 - - - - - - - DC bit 15 bit 8 Lower Byte: R/W-0(1) IPL2(2) R/W-0(1) R/W-0(1) (2) (2) IPL1 IPL0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 RA N OV Z C bit 7 bit 0 bit 15-9 Unimplemented: Read as `0' bit 8 DC: ALU Half Carry/Borrow bit 1 = A carry-out from the 4th low-order bit (for byte sized data) or 8th low-order bit (for word sized data) of the result occurred 0 = No carry-out from the 4th or 8th low-order bit of the result has occurred bit 7-5 IPL2:IPL0: CPU Interrupt Priority Level Status bits(2) 111 = CPU interrupt priority level is 7 (15). User interrupts disabled. 110 = CPU interrupt priority level is 6 (14) 101 = CPU Interrupt Priority Level is 5 (13) 100 = CPU interrupt priority level is 4 (12) 011 = CPU interrupt priority level is 3 (11) 010 = CPU interrupt priority level is 2 (10) 001 = CPU interrupt priority level is 1 (9) 000 = CPU interrupt priority level is 0 (8) Note 1: The IPL Status bits are read-only when NSTDIS (INTCON1) = 1. 2: The IPL bits are concatenated with the IPL3 bit (CORCON) to form the CPU interrupt priority level. The value in parentheses indicates the IPL when IPL3 = 1. bit 4 RA: REPEAT Loop Active bit 1 = REPEAT loop in progress 0 = REPEAT loop not in progress bit 3 N: ALU Negative bit 1 = Result was negative 0 = Result was non-negative (zero or positive) bit 2 OV: ALU Overflow bit 1 = Overflow occurred for signed (2's complement) arithmetic in this arithmetic operation 0 = No overflow has occurred bit 1 Z: ALU Zero bit 1 = An operation which effects the Z bit has set it at some time in the past 0 = The most recent operation which effects the Z bit has cleared it (i.e., a non-zero result) bit 0 C: ALU Carry/Borrow bit 1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared DS39747C-page 22 Preliminary x = Bit is unknown © 2006 Microchip Technology Inc. PIC24FJ128GA PIC24FJ128GA FAMILY REGISTER 2-2: Upper Byte: U-0 - bit 15 CORCON: CORE CONTROL REGISTER U-0 - U-0 - Lower Byte: U-0 - bit 7 U-0 - U-0 - U-0 - U-0 - U-0 - U-0 - bit 15-4 U-0 - U-0 - bit 0 PSV: Program Space Visibility in Data Space Enable bit 1 = Program space visible in data space 0 = Program space not visible in data space bit 1-0 R/W-0 PSV IPL3: CPU Interrupt Priority Level Status bit 1 = CPU interrupt priority level is greater than 7 0 = CPU interrupt priority level is 7 or less bit 2 R/C-0 IPL3 U-0 - bit 8 Unimplemented: Read as `0' bit 3 U-0 - Unimplemented: Read as `0' Note: User interrupts are disabled when IPL3 = 1. Legend: R = Readable bit 2.3 W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared Arithmetic Logic Unit (ALU) The PIC24 PIC24 ALU is 16 bits wide and is capable of addition, subtraction, bit shifts and logic operations. Unless otherwise mentioned, arithmetic operations are 2's complement in nature. Depending on the operation, the ALU may affect the values of the Carry (C), Zero (Z), Negative (N), Overflow (OV) and Digit Carry (DC) Status bits in the SR register. The C and DC Status bits operate as Borrow and Digit Borrow bits, respectively, for subtraction operations. The ALU can perform 8-bit or 16-bit operations, depending on the mode of the instruction that is used. Data for the ALU operation can come from the W register array, or data memory, depending on the addressing mode of the instruction. Likewise, output data from the ALU can be written to the W register array or a data memory location. © 2006 Microchip Technology Inc. x = Bit is unknown The PIC24 PIC24 CPU incorporates hardware support for both multiplication and division. This includes a dedicated hardware multiplier and support hardware for 16-bit divisor division. 2.3.1 MULTIPLIER The ALU contains a high-speed 17-bit x 17-bit multiplier. It supports unsigned, signed or mixed sign operation in several multiplication modes: 1. 2. 3. 4. 5. 6. 7. Preliminary 16-bit x 16-bit signed 16-bit x 16-bit unsigned 16-bit signed x 5-bit (literal) unsigned 16-bit unsigned x 16-bit unsigned 16-bit unsigned x 5-bit (literal) unsigned 16-bit unsigned x 16-bit signed 8-bit unsigned x 8-bit unsigned DS39747C-page 23 PIC24FJ128GA PIC24FJ128GA FAMILY 2.3.2 DIVIDER 2.3.3 The divide block supports 32-bit/16-bit and 16-bit/16-bit signed and unsigned integer divide operation with the following data sizes: 1. 2. 3. 4. 32-bit signed/16-bit signed divide 32-bit unsigned/16-bit unsigned divide 16-bit signed/16-bit signed divide 16-bit unsigned/16-bit unsigned divide The quotient for all divide instructions ends up in W0 and the remainder in W1. 16-bit signed and unsigned DIV instructions can specify any W register for both the 16-bit divisor (Wn) and any W register (aligned) pair (W(m+1):Wm) for the 32-bit dividend. The divide algorithm takes one cycle per bit of divisor, so both 32-bit/16-bit and 16-bit/16-bit instructions take the same number of cycles to execute. TABLE 2-2: The PIC24 PIC24 ALU supports both single-bit and single-cycle, multi-bit arithmetic and logic shifts. Multi-bit shifts are implemented using a shifter block, capable of performing up to a 15-bit arithmetic right shift, or up to a 15-bit left shift, in a single cycle. All multi-bit shift instructions only support register direct addressing for both the operand source and result destination. A full summary of instructions that use the shift operation is provided below in Table 2-2. INSTRUCTIONS THAT USE THE SINGLE AND MULTI-BIT SHIFT OPERATION Instruction ASR MULTI-BIT SHIFT SUPPORT Description Arithmetic shift right source register by one bit. ASRF Arithmetic shift right the content of the register by one bit. ASRW Arithmetic shift right source register by up to 15 bits, value held in the W register referenced within instruction. ASRK Arithmetic shift right source register up to 15 bits. Shift value is literal. SL Shift left source register by one bit. SLF Shift left the content of the file register by one bit. SLW Shift left source register by up to 15 bits, value held in the W register referenced instruction. SLK Shift left source register up to 15 bits. Shift value is literal. LSR Logical shift right source register by one bit. LSRF Logical shift right the content of the register by one bit. LSRW Logical shift right source register by up to 15 bits, value held in the W register referenced within instruction. LSRK Logical shift right source register up to 15 bits. Shift value is literal. DS39747C-page 24 Preliminary © 2006 Microchip Technology Inc. PIC24FJ128GA PIC24FJ128GA FAMILY 3.0 MEMORY ORGANIZATION As Harvard architecture devices, PIC24 PIC24 microcontrollers feature separate program and data memory spaces and busses. This architecture also allows the direct access of program memory from the data space during code execution. 3.1 Program Address Space The program address memory space of PIC24FJ128GA PIC24FJ128GA family devices is 4M instructions. The space is addressable by a 24-bit value derived from FIGURE 3-1: either the 23-bit Program Counter (PC) during program execution, or from table operation or data space remapping, as described in Section 3.3 "Interfacing Program and Data Memory Spaces". User access to the program memory space is restricted to the lower half of the address range (000000h to 7FFFFFh). The exception is the use of TBLRD/TBLWT operations, which use TBLPAG to permit access to the Configuration bits and Device ID sections of the configuration memory space. Memory maps for the PIC24FJ128GA PIC24FJ128GA family of devices are shown in Figure 3-1. PROGRAM SPACE MEMORY MAP FOR PIC24FJ128GA PIC24FJ128GA FAMILY DEVICES PIC24FJ96GA PIC24FJ96GA PIC24FJ128GA PIC24FJ128GA GOTO Instruction Reset Address Interrupt Vector Table GOTO Instruction Reset Address Interrupt Vector Table GOTO Instruction Reset Address Interrupt Vector Table Reserved Reserved Reserved Alternate Vector Table User Memory Space PIC24FJ64GA PIC24FJ64GA Alternate Vector Table Alternate Vector Table User Flash Program Memory (22K instructions) User Flash Program Memory (32K instructions) Flash Config Words User Flash Program Memory (44K instructions) 000000h 000002h 000004h 0000FEh 000100h 000104h 0001FEh 000200h 00ABFEh 00AC00h 00FFFEh 010000h Flash Config Words Flash Config Words 0157FEh 015800h Unimplemented (Read `0's) Unimplemented (Read `0's) Unimplemented (Read `0's) 7FFFFEh 800000h Reserved Reserved Device Configuration Registers Device Configuration Registers Device Configuration Registers Reserved Reserved Reserved DEVID (2) DEVID (2) DEVID (2) Configuration Memory Space Reserved Note: F7FFFEh F80000h F8000Eh F80010h FEFFFEh FF0000h FFFFFEh Memory areas are not shown to scale. © 2006 Microchip Technology Inc. Preliminary DS39747C-page 25 PIC24FJ128GA PIC24FJ128GA FAMILY 3.1.1 PROGRAM MEMORY ORGANIZATION 3.1.3 In PIC24FJ128GA PIC24FJ128GA family devices, the top two words of on-chip program memory are reserved for configuration information. On device Reset, the configuration information is copied into the appropriate Configuration registers. The addresses of the Flash Configuration Word for devices in the PIC24FJ128GA PIC24FJ128GA family are shown in Table 3-1. Their location in the memory map is shown with the other memory vectors in Figure 3-1. The program memory space is organized in word addressable blocks. Although it is treated as 24 bits wide, it is more appropriate to think of each address of the program memory as a lower and upper word, with the upper byte of the upper word being unimplemented. The lower word always has an even address, while the upper word has an odd address (Figure 3-2). The Configuration Words in program memory are a compact format. The actual Configuration bits are mapped in several different registers in the configuration memory space. Their order in the Flash Configuration Words do not reflect a corresponding arrangement in the configuration space. Additional details on the device Configuration Words are provided in Section 23.1 "Configuration Bits". Program memory addresses are always word-aligned on the lower word, and addresses are incremented or decremented by two during code execution. This arrangement also provides compatibility with data memory space addressing and makes it possible to access data in the program memory space. 3.1.2 HARD MEMORY VECTORS All PIC24 PIC24 devices reserve the addresses between 00000h and 000200h for hard coded program execution vectors. A hardware Reset vector is provided to redirect code execution from the default value of the PC on device Reset to the actual start of code. A GOTO instruction is programmed by the user at 000000h, with the actual address for the start of code at 000002h. TABLE 3-1: msw Address Configuration Word Addresses PIC24FJ64GA PIC24FJ64GA 22 00ABFCh: 00ABFEh PIC24FJ96GA PIC24FJ96GA 32 00FFFCh: 00FFFEh PIC24FJ128GA PIC24FJ128GA 44 0157FCh: 0157FEh least significant word most significant word 16 8 PC Address (lsw Address) 0 000000h 000002h 000004h 000006h 00000000 00000000 00000000 00000000 Program Memory `Phantom' Byte (read as `0') DS39747C-page 26 Program Memory (K words) PROGRAM MEMORY ORGANIZATION 23 000001h 000003h 000005h 000007h FLASH CONFIGURATION WORDS FOR PIC24FJ128GA PIC24FJ128GA FAMILY DEVICES Device PIC24 PIC24 devices also have two interrupt vector tables, located from 000004h to 0000FFh and 000100h to 0001FFh. These vector tables allow each of the many device interrupt sources to be handled by separate ISRs. A more detailed discussion of the interrupt vector tables is provided in Section 6.1 "Interrupt Vector Table". FIGURE 3-2: FLASH CONFIGURATION WORDS Instruction Width Preliminary © 2006 Microchip Technology Inc. PIC24FJ128GA PIC24FJ128GA FAMILY 3.2 Data Address Space The PIC24 PIC24 core has a separate 16-bit wide data memory space, addressable as a single linear range. The data space is accessed using two Address Generation Units (AGUs), one each for read and write operations. The data space memory map is shown in Figure 3-3. All Effective Addresses (EAs) in the data memory space are 16 bits wide, and point to bytes within the data space. This gives a data space address range of 64 Kbytes, or 32K words. The lower half of the data memory space (that is, when EA = 0) is used for implemented memory addresses, while the upper half (EA = 1) is reserved for the Program Space Visibility area (see Section 3.3.3 "Reading Data from Program Memory Using Program Space Visibility"). FIGURE 3-3: PIC24FJ128GA PIC24FJ128GA family devices implement a total of 8 Kbytes of data memory. Should an EA point to a location outside of this area, an all zero word or byte will be returned. 3.2.1 DATA SPACE WIDTH The data memory space is organized in byte addressable, 16-bit wide blocks. Data is aligned in data memory and registers as 16-bit words, but all data space EAs resolve to bytes. The Least Significant Bytes of each word have even addresses, while the Most Significant Bytes have odd addresses. DATA SPACE MEMORY MAP FOR PIC24FJ128GA PIC24FJ128GA FAMILY DEVICES MSB Address 0001h 07FFh 0801h MSB LSB SFR Space LSB Address 0000h 07FEh 0800h SFR Space Near Data Space Data RAM Implemented Data RAM 1FFFh 2001h 27FFh 2801h 1FFEh 2000h 07FEh 0800h Unimplemented Read as `0' 7FFFh 8001h 7FFFh 8000h Program Space Visibility Area FFFFh Note: FFFEh Data memory areas are not shown to scale. © 2006 Microchip Technology Inc. Preliminary DS39747C-page 27 PIC24FJ128GA PIC24FJ128GA FAMILY 3.2.2 DATA MEMORY ORGANIZATION AND ALIGNMENT A sign-extend instruction (SE) is provided to allow users to translate 8-bit signed data to 16-bit signed values. Alternatively, for 16-bit unsigned data, users can clear the MSB of any W register by executing a zero-extend (ZE) instruction on the appropriate address. To maintain backward compatibility with PICmicro® devices and improve data space memory usage efficiency, the PIC24 PIC24 instruction set supports both word and byte operations. As a consequence of byte accessibility, all effective address calculations are internally scaled to step through word-aligned memory. For example, the core recognizes that Post-Modified Register Indirect Addressing mode [Ws+] will result in a value of Ws + 1 for byte operations and Ws + 2 for word operations. Although most instructions are capable of operating on word or byte data sizes, it should be noted that some instructions operate only on words. 3.2.3 The 8-Kbyte area between 0000h and 1FFFh is referred to as the near data space. Locations in this space are directly addressable via a 13-bit absolute address field within all memory direct instructions. The remainder of the data space is addressable indirectly. Additionally, the whole data space is addressable using MOV instructions, which support Memory Direct Addressing with a 16-bit address field. Data byte reads will read the complete word which contains the byte, using the LSb of any EA to determine which byte to select. The selected byte is placed onto the LSB of the data path. That is, data memory and registers are organized as two parallel byte-wide entities with shared (word) address decode but separate write lines. Data byte writes only write to the corresponding side of the array or register which matches the byte address. 3.2.4 SFR SPACE The first 2 Kbytes of the near data space, from 0000h to 07FFh, are primarily occupied with Special Function Registers (SFRs). These are used by the PIC24 PIC24 core and peripheral modules for controlling the operation of the device. All word accesses must be aligned to an even address. Misaligned word data fetches are not supported, so care must be taken when mixing byte and word operations, or translating from 8-bit MCU code. If a misaligned read or write is attempted, an address error trap will be generated. If the error occurred on a read, the instruction underway is completed; if it occurred on a write, the instruction will be executed but the write will not occur. In either case, a trap is then executed, allowing the system and/or user to examine the machine state prior to execution of the address Fault. SFRs are distributed among the modules that they control, and are generally grouped together by module. Much of the SFR space contains unused addresses; these are read as `0'. A diagram of the SFR space, showing where SFRs are actually implemented, is shown in Table 3-2. Each implemented area indicates a 32-byte region where at least one address is implemented as an SFR. A complete listing of implemented SFRs, including their addresses, is shown in Tables 3-3 through 3-30. All byte loads into any W register are loaded into the Least Significant Byte. The Most Significant Byte is not modified. TABLE 3-2: NEAR DATA SPACE IMPLEMENTED REGIONS OF SFR DATA SPACE SFR Space Address xx00 xx20 000h xx60 Core 100h 200h xx40 Timers I2CTM 300h - ICN Capture UART - - SPI xxA0 xxC0 xxE0 - Interrupts Compare - - - - - - A/D 400h xx80 - - - - - - - - - - - 500h - - - - - - 600h PMP RTC/Comp CRC - - - - System NVM/PMD - - I/O - 700h I/O I/O - - Legend: - = No implemented SFRs in this block DS39747C-page 28 Preliminary © 2006 Microchip Technology Inc. © 2006 Microchip Technology Inc. TABLE 3-3: CPU CORE REGISTERS MAP Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0000 Working Register 0 0000 WREG1 0002 Working Register 1 0000 WREG2 0004 Working Register 2 0000 WREG3 0006 Working Register 3 0000 WREG4 0008 Working Register 4 0000 WREG5 000A Working Register 5 0000 WREG6 000C Working Register 6 0000 000E Working Register 7 0000 WREG8 0010 Working Register 8 0000 WREG9 0012 Working Register 9 0000 WREG10 WREG10 0014 Working Register 10 0000 WREG11 WREG11 0016 Working Register 11 0000 WREG12 WREG12 0018 Working Register 12 0000 WREG13 WREG13 001A Working Register 13 0000 WREG14 WREG14 001C Working Register 14 0000 WREG15 WREG15 001E Working Register 15 0800 SPLIM 0020 Stack Pointer Limit xxxx PCL 002E Program Counter, Low Word PCH 0030 - - - - - - - - Program Counter, High Byte 0000 TBLPAG 0032 - - - - - - - - Table Page Address Pointer 0000 PSVPAG 0034 - - - - - - - - Program Memory Visibility Page Address Pointer 0000 RCOUNT 0036 SR 0042 - - - - - - - DC IPL2 IPL1 IPL0 RA N OV Z C 0000 CORCON 0044 - - - - - - - - - - - - IPL3 PSV - - 0000 DISICNT 0052 - - 0000 Repeat Loop Counter xxxx Disable Interrupts Counter x = unknown value on Reset, - = unimplemented, read as `0'. Reset values are shown in hexadecimal. xxxx DS39747C-page 29 PIC24FJ128GA PIC24FJ128GA FAMILY WREG0 WREG7 Preliminary Addr Legend: Bit 15 All Resets File Name INTERRUPT CONTROLLER REGISTER MAP Bit 0 All Resets OSCFAIL - 0000 INT1EP INT0EP 0000 OC1IF IC1IF INT0IF 0000 CNIF CMIF MI2C1IF SI2C1IF 0000 - - - SPI2IF SPF2IF 0000 INT3IF - - MI2C2IF SI2C2IF - 0000 - - - CRCIF U2ERIF U1ERIF - 0000 T2IE OC2IE IC2IE - T1IE OC1IE IC1IE INT0IE 0000 - - - - INT1IE CNIE CMIE MI2C1IE SI2C1IE 0000 OC5IE - IC5IE IC4IE IC3IE - - - SPI2IE SPF2IE 0000 - - - - INT4IE INT3IE - - MI2C2IE SI2C2IE - 0000 - - - - - - - - CRCIE U2ERIE U1ERIE - 0000 T1IP0 - OC1IP2 OC1IP1 OC1IP0 - IC1IP2 IC1IP1 IC1IP0 - INT0IP2 INT0IP1 INT0IP0 4444 T2IP1 T2IP0 - OC2IP2 OC2IP1 OC2IP0 - IC2IP2 IC2IP1 IC2IP0 - - - - 4440 U1RXIP2 U1RXIP1 U1RXIP0 - SPI1IP2 SPI1IP1 SPI1IP0 - SPF1IP2 SPF1IP1 SPF1IP0 - T3IP2 T3IP1 T3IP0 4444 - - - - - - - - - AD1IP2 AD1IP1 AD1IP0 - U1TXIP2 U1TXIP1 U1TXIP0 0044 00AC - CNIP2 CNIP1 CNIP0 - CMIP2 CMIP1 CMIP0 - MI2C1P2 MI2C1P1 MI2C1P0 - SI2C1P2 SI2C1P1 SI2C1P0 4444 IPC5 00AE - - - - - - - - - - - - - INT1IP2 INT1IP1 INT1IP0 0004 IPC6 00B0 - T4IP2 T4IP1 T4IP0 - OC4IP2 OC4IP1 OC4IP0 - OC3IP2 OC3IP1 OC3IP0 - - - - 4440 IPC7 00B2 - U2TXIP2 U2TXIP1 U2TXIP0 - U2RXIP2 U2RXIP1 U2RXIP0 - INT2IP2 INT2IP1 INT2IP0 - T5IP2 T5IP1 T5IP0 4444 IPC8 00B4 - - - - - - - - - SPI2IP2 SPI2IP1 SPI2IP0 - SPF2IP2 SPF2IP1 SPF2IP0 0044 IPC9 00B6 - IC5IP2 IC5IP1 IC5IP0 - IC4IP2 IC4IP1 IC4IP0 - IC3IP2 IC3IP1 IC3IP0 - - - - 4440 IPC10 IPC10 00B8 - - - - - - - - - OC5IP2 OC5IP1 OC5IP0 - - - - 0040 IPC11 IPC11 00BA - - - - - - - - - PMPIP2 PMPIP1 PMPIP0 - - - - 0040 IPC12 IPC12 00BC - - - - - MI2C2P2 MI2C2P1 MI2C2P0 - SI2C2P2 SI2C2P1 SI2C2P0 - - - - 0440 IPC13 IPC13 00BE - - - - - INT4IP2 INT4IP1 INT4IP0 - INT3IP2 INT3IP1 INT3IP0 - - - - 0440 IPC15 IPC15 00C2 - - - - - RTCIP2 RTCIP1 RTCIP0 - - - - - - - - 0400 IPC16 IPC16 00C4 - CRCIP2 CRCIP1 CRCIP0 - U2ERIP2 U2ERIP1 U2ERIP0 - U1ERIP2 U1ERIP1 U1ERIP0 - - - - 4440 Legend: - = unimplemented, read as `0'. Reset values are shown in hexadecimal. File Name Addr Bit 15 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 NSTDIS - - - - - - - - - - ALTIVT DISI - - - - - - - - - INT4EP INT3EP INT2EP 0084 - - AD1IF U1TXIF U1RXIF SPI1IF SPF1IF T3IF T2IF OC2IF IC2IF - T1IF IFS1 0086 U2TXIF U2RXIF INT2IF T5IF T4IF OC4IF OC3IF - - - - INT1IF IFS2 0088 - - PMPIF - - - OC5IF - IC5IF IC4IF IC3IF IFS3 008A - RTCIF - - - - - - - INT4IF IFS4 008C - - - - - - - - - IEC0 0094 - - AD1IE U1TXIE U1RXIE SPI1IE SPF1IE T3IE IEC1 0096 U2TXIE U2RXIE INT2IE T5IE T4IE OC4IE OC3IE IEC2 0098 - - PMPIE - - - IEC3 009A - RTCIE - - - IEC4 009C - - - - IPC0 00A4 - T1IP2 T1IP1 IPC1 Preliminary Bit 14 INTCON1 0080 INTCON2 0082 IFS0 Bit 4 Bit 3 Bit 2 00A6 - T2IP2 IPC2 00A8 - IPC3 00AA IPC4 MATHERR ADDRERR STKERR Bit 1 PIC24FJ128GA PIC24FJ128GA FAMILY DS39747C-page 30 TABLE 3-4: © 2006 Microchip Technology Inc. © 2006 Microchip Technology Inc. TABLE 3-5: ICN REGISTER MAP Bit 0 All Resets CN1IE CN0IE 0000 CN17IE CN17IE CN16IE CN16IE 0000 CN0PUE 0000 CN21PUE CN21PUE CN20PUE CN20PUE CN19PUE CN19PUE CN18PUE CN18PUE CN17PUE CN17PUE CN16PUE CN16PUE 0000 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 CNEN1 0060 CN15IE CN15IE CN14IE CN14IE CN13IE CN13IE CN12IE CN12IE CN11IE CN11IE CN10IE CN10IE CN9IE CN8IE CN7IE CN6IE CN5IE CN4IE CN3IE CN2IE CNEN2 0062 - - - - - - - - - - CN21IE CN21IE CN20IE CN20IE CN19IE CN19IE CN18IE CN18IE CNPU1 0068 CN9PUE CN8PUE CN7PUE CN6PUE CN5PUE CN4PUE CN3PUE CN2PUE CN1PUE CNPU2 006A - - - - Legend: - = unimplemented, read as `0'. Reset values are shown in hexadecimal. Bit 9 Bit 8 Bit 7 Bit 6 TABLE 3-6: CN15PUE CN15PUE CN14PUE CN14PUE CN13PUE CN13PUE CN12PUE CN12PUE CN11PUE CN11PUE CN10PUE CN10PUE - - - - - - Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 TIMER REGISTER MAP Bit 15 TMR1 0100 Timer1 Register PR1 0102 Period Register 1 T1CON 0104 TMR2 0106 Timer2 Register xxxx TMR3HLD 0108 Timer3 Holding Register (For 32-bit timer operations only) xxxx TMR3 010A Timer3 Register xxxx PR2 010C Period Register 2 FFFF PR3 010E Period Register 3 T2CON 0110 TON - TSIDL - - - - - - TGATE TCKPS1 TCKPS0 T32 - TCS - 0000 T3CON 0112 TON - TSIDL - - - - - - TGATE TCKPS1 TCKPS0 - - TCS - 0000 TMR4 0114 Timer4 Register xxxx TMR5HLD 0116 Timer5 Holding Register (For 32-bit operations only) xxxx TMR5 0118 Timer5 Register xxxx PR4 011A Period Register 4 FFFF PR5 011C Period Register 5 T4CON 011E TON - TSIDL - - - - - - TGATE TCKPS1 TCKPS0 T32 - TCS - 0000 T5CON 0120 TON - TSIDL - - - - - - TGATE TCKPS1 TCKPS0 - - TCS - 0000 Legend: x = unknown value on Reset, - = unimplemented, read as `0'. Reset values are shown in hexadecimal. - Bit 13 TSIDL Bit 12 - Bit 11 - Bit 10 - - - - Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 xxxx FFFF TGATE TCKPS1 TCKPS0 - TSYNC TCS - 0000 FFFF FFFF DS39747C-page 31 PIC24FJ128GA PIC24FJ128GA FAMILY Preliminary Addr TON Bit 14 All Resets File Name INPUT CAPTURE REGISTER MAP File Name Addr IC1BUF 0140 IC1CON 0142 IC2BUF 0144 IC2CON 0146 IC3BUF 0148 IC3CON 014A IC4BUF 014C IC4CON 014E IC5BUF 0150 IC5CON 0152 Legend: Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 - - ICSIDL - - - - Bit 8 Bit 7 Preliminary Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ICI1 ICI0 ICOV ICBNE ICM2 ICM1 ICM0 ICI1 ICI0 ICOV ICBNE ICM2 ICM1 ICM0 ICI1 ICI0 ICOV ICBNE ICM2 ICM1 ICM0 ICI1 ICI0 ICOV ICBNE ICM2 ICM1 ICM0 ICI1 ICI0 ICOV ICBNE ICM2 ICM1 ICM0 0000 Bit 1 Bit 0 All Resets Input 1 Capture Register - ICTMR xxxx Input 2 Capture Register - - ICSIDL - - - - - ICTMR - ICSIDL - - - - - ICTMR - ICSIDL - - - - - ICTMR - ICSIDL - - - - - ICTMR 0000 xxxx OUTPUT COMPARE REGISTER MAP Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 0180 0182 0184 OC2RS 0186 018A OC3RS 018C Output Compare 3 Secondary Register OC3R 018E Output Compare 3 Register OC3CON 0190 OC4RS 0192 Output Compare 4 Secondary Register OC4R 0194 Output Compare 4 Register OC4CON 0196 OC5RS 0198 Output Compare 5 Secondary Register OC5R 019A Output Compare 5 Register OC5CON 019C Bit 2 Output Compare 2 Register OC2CON Bit 3 Output Compare 2 Secondary Register 0188 Bit 4 Output Compare 1 Register OC1CON Bit 5 Output Compare 1 Secondary Register OC1R OC2R © 2006 Microchip Technology Inc. OC1RS Legend: 0000 xxxx Input 5 Capture Register - 0000 xxxx Input 4 Capture Register - 0000 xxxx Input 3 Capture Register - All Resets Bit 6 x = unknown value on Reset, - = unimplemented, read as `0'. Reset values are shown in hexadecimal. TABLE 3-8: File Name Bit 15 - - - - - - - - - - OCSIDL OCSIDL OCSIDL OCSIDL OCSIDL - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - x = unknown value on Reset, - = unimplemented, read as `0'. Reset values are shown in hexadecimal. - - - - - xxxx xxxx - OCFLT OCTSEL OCM2 OCM1 OCM0 0000 xxxx xxxx - OCFLT OCTSEL OCM2 OCM1 OCM0 0000 xxxx xxxx - OCFLT OCTSEL OCM2 OCM1 OCM0 0000 xxxx xxxx - OCFLT OCTSEL OCM2 OCM1 OCM0 0000 xxxx xxxx - OCFLT OCTSEL OCM2 OCM1 OCM0 0000 PIC24FJ128GA PIC24FJ128GA FAMILY DS39747C-page 32 TABLE 3-7: I2C1 REGISTER MAP Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 I2C1RCV 0200 - - - - - - - - Receive Register 0000 I2C1TRN 0202 - - - - - - - - Transmit Register 00FF I2C1BRG 0204 - - - - - - - I2C1CON 0206 I2CEN - I2CSIDL SCLREL IPMIEN A10M DISSLW SMEN GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN 1000 I2C1STAT 0208 ACKSTAT TRSTAT - - - BCL GCSTAT ADD10 ADD10 IWCOL I2COV D/A P S R/W RBF TBF 0000 I2C1ADD 020A - - - - - - Address Register 0000 I2C1MSK 020C - - - - - - Address Mask 0000 Legend: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets File Name Baud Rate Generator 0000 - = unimplemented, read as `0'. Reset values are shown in hexadecimal. TABLE 3-10: I2C2 REGISTER MAP Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 I2C2RCV Preliminary Addr 0210 - - - - - - - - Receive Register 0000 I2C2TRN 0212 - - - - - - - - Transmit Register 00FF I2C2BRG 0214 - - - - - - - I2C2CON 0216 I2CEN - I2CSIDL SCLREL IPMIEN A10M DISSLW SMEN GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN 1000 I2C2STAT 0218 ACKSTAT TRSTAT - - - BCL GCSTAT ADD10 ADD10 IWCOL I2CPOV D/A P S R/W RBF TBF 0000 I2C2ADD 021A - - - - - - Address Register 0000 I2C2MSK 021C - - - - - - Address Mask 0000 Legend: - = unimplemented, read as `0'. Reset values are shown in hexadecimal. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets File Name Baud Rate Generator 0000 PIC24FJ128GA PIC24FJ128GA FAMILY DS39747C-page 33 TABLE 3-9: © 2006 Microchip Technology Inc. File Name Addr UART1 REGISTER MAP Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets U1MODE 0220 UARTEN - USIDL IREN RTSMD - UEN1 UEN0 WAKE LPBACK ABAUD RXINV BRGH PDSEL1 PDSEL0 STSEL 0000 U1STA 0222 UTXISEL1 UTXINV UTXISEL0 - UTXBRK UTXEN UTXBF TRMT URXISEL1 URXISEL0 ADDEN RIDLE PERR FERR OERR URXDA 0110 U1TXREG 0224 - - - - - - - Transmit Register xxxx U1RXREG 0226 - - - - - - - Receive Register 0000 U1BRG 0228 Legend: Baud Rate Generator Prescaler TABLE 3-12: UART2 REGISTER MAP Addr U2MODE 0230 UARTEN U2STA 0232 UTXISEL1 U2TXREG 0234 - U2RXREG Preliminary File Name 0236 - U2BRG 0238 Legend: Bit 15 Bit 14 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 WAKE LPBACK STSEL 0000 OERR URXDA 0110 USIDL IREN RTSMD - UEN1 UEN0 UTXISEL0 - UTXBRK UTXEN UTXBF TRMT - - - - - - Transmit Register xxxx - - - - - - Receive Register 0000 URXISEL1 URXISEL0 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 ABAUD RXINV BRGH PDSEL1 ADDEN RIDLE PERR FERR Baud Rate Generator Prescaler 0000 SPI1 REGISTER MAP Bit 14 Bit 13 SPI1STAT 0240 SPIEN - SPISIDL - - SPI1CON1 0242 - - - DISSCK DISSDO MODE16 MODE16 SMP CKE SPI1CON2 0244 FRMEN SPIFSD SPIFPOL - - - - - - SPI1BUF 0248 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 SPIBEC2 SPIBEC1 SPIBEC0 Bit 5 Bit 4 Bit 2 Bit 1 Bit 0 All Resets - - SPITBF SPIRBF 0000 SPRE1 SPRE0 PPRE1 PPRE0 0000 - SPIFE SPIBEN 0000 Bit 7 Bit 6 Bit 3 - SPIROV - - SSEN CKP MSTEN SPRE2 - - - - SPI1 Transmit and Receive Buffer 0000 - = unimplemented, read as `0'. Reset values are shown in hexadecimal. © 2006 Microchip Technology Inc. TABLE 3-14: SPI2 REGISTER MAP Addr Bit 15 Bit 14 Bit 13 SPI2STAT 0260 SPIEN - SPISIDL - - SPI2CON1 0262 - - - DISSCK DISSDO MODE16 MODE16 SMP CKE SPI2CON2 0264 FRMEN SPIFSD SPIFPOL - - - - - - SPI2BUF 0268 Legend: PDSEL0 - UTXINV Bit 15 File Name All Resets Bit 12 Addr Legend: Bit 0 Bit 13 x = unknown value on Reset, - = unimplemented, read as `0'. Reset values are shown in hexadecimal. TABLE 3-13: File Name 0000 x = unknown value on Reset, - = unimplemented, read as `0'. Reset values are shown in hexadecimal. Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 SPIBEC2 SPIBEC1 SPIBEC0 - = unimplemented, read as `0'. Reset values are shown in hexadecimal. Bit 4 Bit 1 Bit 0 All Resets - - SPITBF SPIRBF 0000 SPRE1 SPRE0 PPRE1 PPRE0 0000 - SPIFE SPIBEN 0000 Bit 6 - SPIROV - - SSEN CKP MSTEN SPRE2 - - - - SPI2 Transmit and Receive Buffer Bit 5 Bit 2 Bit 7 Bit 3 0000 PIC24FJ128GA PIC24FJ128GA FAMILY DS39747C-page 34 TABLE 3-11: © 2006 Microchip Technology Inc. TABLE 3-15: ADC REGISTER MAP 0300 ADC Data Buffer 0 xxxx ADC1BUF1 0302 ADC Data Buffer 1 xxxx ADC1BUF2 0304 ADC Data Buffer 2 xxxx ADC1BUF3 0306 ADC Data Buffer 3 xxxx ADC1BUF4 0308 ADC Data Buffer 4 xxxx ADC1BUF5 030A ADC Data Buffer 5 xxxx ADC1BUF6 030C ADC Data Buffer 6 xxxx 030E ADC Data Buffer 7 xxxx ADC1BUF8 0310 ADC Data Buffer 8 xxxx ADC1BUF9 0312 ADC Data Buffer 9 xxxx ADC1BUFA 0314 ADC Data Buffer 10 xxxx ADC1BUFB 0316 ADC Data Buffer 11 xxxx ADC1BUFC 0318 ADC Data Buffer 12 xxxx ADC1BUFD 031A ADC Data Buffer 13 xxxx ADC1BUFE 031C ADC Data Buffer 14 xxxx ADC1BUFF 031E ADC Data Buffer 15 AD1CON1 0320 ADON - ADSIDL - - - FORM1 FORM0 SSRC2 SSRC1 SSRC0 - - ASAM SAMP DONE 0000 AD1CON2 0322 VCFG2 VCFG1 VCFG0 OFFCAL - CSCNA - - BUFS - SMPI3 SMPI2 SMPI1 SMPI0 BUFM ALTS 0000 AD1CON3 0324 ADRC - - SAMC4 SAMC3 SAMC2 SAMC1 SAMC0 ADCS7 ADCS6 ADCS5 ADCS4 ADCS3 ADCS2 ADCS1 ADCS0 0000 AD1CHS 0328 CH0NB - - - CH0SB3 CH0SB2 CH0SB1 CH0SB0 CH0NA - - - CH0SA3 CH0SA2 CH0SA1 CH0SA0 0000 AD1PCFG 032C PCFG15 PCFG15 PCFG14 PCFG14 PCFG13 PCFG13 PCFG12 PCFG12 PCFG11 PCFG11 PCFG10 PCFG10 PCFG9 PCFG8 PCFG7 PCFG6 PCFG5 PCFG4 PCFG3 PCFG2 PCFG1 PCFG0 0000 AD1CSSL 0330 CSSL15 CSSL15 CSSL14 CSSL14 CSSL13 CSSL13 CSSL12 CSSL12 CSSL11 CSSL11 CSSL10 CSSL10 CSSL9 CSSL8 CSSL7 CSSL6 CSSL5 CSSL4 CSSL3 CSSL2 CSSL1 CSSL0 0000 Legend: x = unknown value on Reset, - = unimplemented, read as `0'. Reset values are shown in hexadecimal. File Name Addr TRISA 02C0 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 xxxx PORTA REGISTER MAP Bit 15 Bit 14 TRISA15 TRISA15(1) TRISA14 TRISA14(1) Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 - - - TRISA10 TRISA10(1) TRISA9(1) - RA9(1) RA14(1) - - - RA10(1) Bit 7 Bit 6 TRISA7(2) TRISA6(2) Bit 5 Bit 4 Bit 3 Bit 2 TRISA3(2) TRISA2(2) Bit 1 Bit 0 All Resets TRISA5(2) TRISA4(2) TRISA1(2) TRISA0(2) C6FF - RA7(2) RA6(2) RA5(2) RA4(2) RA3(2) RA2(2) RA1(2) RA0(2) xxxx DS39747C-page 35 PORTA 02C2 RA15(1) LATA 02C4 LATA15 LATA15(1) LATA14 LATA14(1) - - - LATA10 LATA10(1) LATA9(1) - LATA7(2) LATA6(2) LATA5(2) LATA4(2) LATA3(2) LATA2(2) LATA1(2) LATA0(2) xxxx ODCA 06C0 ODA15 ODA15(1) ODA14 ODA14(1) - - - ODA10 ODA10(1) ODA9(1) - ODA7(2) ODA6(2) ODA5(2) ODA4(2) ODA3(2) ODA2(2) ODA1(2) ODA0(2) 0000 Legend: Note 1: 2: x = unknown value on Reset, - = unimplemented, read as `0'. Reset values are shown in hexadecimal for 100-pin devices. Implemented in 80-pin and 100-pin devices only. Implemented in 100-pin devices only PIC24FJ128GA PIC24FJ128GA FAMILY ADC1BUF0 ADC1BUF7 Preliminary Addr TABLE 3-16: Bit 15 All Resets File Name © 2006 Microchip Technology Inc. TABLE 3-17: PORTB REGISTER MAP Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets TRISB 02C6 TRISB15 TRISB15 TRISB14 TRISB14 TRISB13 TRISB13 TRISB12 TRISB12 TRISB11 TRISB11 TRISB10 TRISB10 TRISB9 TRISB8 TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 FFFF PORTB 02C8 RB15 RB14 RB13 RB12 RB11 RB10 RB9 RB8 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx LATB 02CA LATB15 LATB15 LATB14 LATB14 LATB13 LATB13 LATB12 LATB12 LATB11 LATB11 LATB10 LATB10 LATB9 LATB8 LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 xxxx ODCB 06C6 ODB15 ODB15 ODB14 ODB14 ODB13 ODB13 ODB12 ODB12 ODB11 ODB11 ODB10 ODB10 ODB9 ODB8 ODB7 ODB6 ODB5 ODB4 ODB3 ODB2 ODB1 ODB0 0000 Legend: x = unknown value on Reset, - = unimplemented, read as `0'. Reset values are shown in hexadecimal for 100-pin devices. Bit 1 Bit 0 All Resets File Name TABLE 3-18: PORTC REGISTER MAP 02CC PORTC 02CE RC15 RC14 RC13 LATTC 02D0 LATC15 LATC15 LATC14 LATC14 ODCC 06CC ODC15 ODC15 ODC14 ODC14 Legend: Note 1: 2: x = unknown value on Reset, - = unimplemented, read as `0'. Reset values are shown in hexadecimal for 100-pin devices. Implemented in 80-pin and 100-pin devices only. Implemented in 100-pin devices only TABLE 3-19: File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 - - - - - - - - F01E RC12 - - - - - - - RC4(2) RC3(1) RC2(2) RC1(1) - xxxx LATC13 LATC13 LATC12 LATC12 - - - - - - - LATC4(2) LATC3(1) LATC2(2) LATC1(1) - xxxx ODC13 ODC13 ODC12 ODC12 - - - - - - - ODC4(2) ODC3(1) ODC2(2) ODC1(1) - 0000 TRISC15 TRISC15 TRISC14 TRISC14 TRISC13 TRISC13 TRISC12 TRISC12 Bit 4 Bit 3 Bit 2 TRISC4(2) TRISC3(1) TRISC2(2) TRISC1(1) PORTD REGISTER MAP Bit 15 Bit 14 Bit 13 Bit 12 TRISD15 TRISD15(1) TRISD14 TRISD14(1) TRISD13 TRISD13(1) TRISD12 TRISD12(1) Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets TRISD 02D2 TRISD11 TRISD11 TRISD10 TRISD10 TRISD9 TRISD8 TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 FFFF PORTD 02D4 RD15(1) RD14(1) RD13(1) RD12(1) RD11 RD10 RD9 RD8 RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxx LATD 02D6 LATD15 LATD15(1) LATD14 LATD14(1) LATD13 LATD13(1) LATD12 LATD12(1) LATD11 LATD11 LATD10 LATD10 LATD9 LATD8 LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATD0 xxxx ODCD 06D2 ODD15 ODD15(1) ODD14 ODD14(1) ODD13 ODD13(1) ODD12 ODD12(1) ODD11 ODD11 ODD10 ODD10 ODD9 ODD8 ODD7 ODD6 ODD5 ODD4 ODD3 ODD2 ODD1 ODD0 0000 Legend: Note 1: x = unknown value on Reset, - = unimplemented, read as `0'. Reset values are shown in hexadecimal for 100-pin devices. Implemented in 80-pin and 100-pin devices only. DS39747C-page 36 PIC24FJ128GA PIC24FJ128GA FAMILY Addr TRISC Preliminary File Name © 2006 Microchip Technology Inc. TABLE 3-20: PORTE REGISTER MAP Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets TRISE7 TRISE6 TRISE5 TRISE4 TRISE3 TRISE2 TRISE1 TRISE0 03FF RE7 RE6 RE5 RE4 RE3 RE2 RE1 RE0 xxxx LATE8(1) LATE7 LATE6 LATE5 LATE4 LATE3 LATE2 LATE1 LATE0 xxxx ODE8(1) ODE7 ODE6 ODE5 ODE4 ODE3 ODE2 ODE1 ODE0 0000 Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 TRISE 02D8 - - - - - - PORTE 02DA - - - - - - RE9(1) RE8(1) LATE 02DC - - - - - - LATE9(1) ODCE 06D8 - - - - - - ODE9(1) Legend: Note 1: x = unknown value on Reset, - = unimplemented, read as `0'. Reset values are shown in hexadecimal for 100-pin devices. Implemented in 80-pin and 100-pin devices only. TABLE 3-21: Bit 9 Bit 7 File Name Bit 8 TRISE9(1) TRISE8(1) PORTF REGISTER MAP File Name Addr Bit 15 Bit 14 TRISF 02DE - - Bit 13 Bit 12 TRISF13 TRISF13(1) TRISF12 TRISF12(1) (1) (1) RG12 Bit 10 Bit 9 Bit 8 Bit 7 - - - - - - RF8(2) RF7(2) TRISF8(2) TRISF7(2) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 TRISF0 31FF RF6 RF5 RF4 RF3 RF2 RF1 RF0 xxxx - - 02E2 - - LATF13 LATF13(1) LATF12 LATF12(1) - - - LATF8(2) LATF7(2) LATF6 LATF5 LATF4 LATF3 LATF2 LATF1 LATF0 xxxx ODCF 06DE - - ODF13 ODF13(1) ODF12 ODF12(1) - - - ODF8(2) ODF7(2) ODF6 ODF5 ODF4 ODF3 ODF2 ODF1 ODF0 0000 Legend: Note 1: 2: x = unknown value on Reset, - = unimplemented, read as `0'. Reset values are shown in hexadecimal for 100-pin devices. Implemented in 100-pin devices only. Implemented in 80-pin and 100-pin devices only. Bit 1 Bit 0 All Resets PORTG REGISTER MAP File Name Addr TRISG 02E4 PORTG 02E6 RG15(1) RG14(1) RG13(1) RG12(1) LATG 02E8 LATG15 LATG15(1) LATG14 LATG14(1) LATG13 LATG13(1) ODCG 06E4 ODG15 ODG15(1) ODG14 ODG14(1) ODG13 ODG13(1) Legend: Note 1: 2: x = unknown value on Reset, - = unimplemented, read as `0'. Reset values are shown in hexadecimal for 100-pin devices. Implemented in 100-pin devices only Implemented in 80-pin and 100-pin devices only. DS39747C-page 37 TABLE 3-23: Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 - - TRISG9 TRISG8 TRISG7 TRISG6 - - TRISG3 TRISG2 - - RG9 RG8 RG7 RG6 - - RG3 RG2 RG1(2) RG0(2) xxxx LATG12 LATG12(1) - - LATG9 LATG8 LATG7 LATG6 - - LATG3 LATG2 LATG1(2) LATG0(2) xxxx ODG12 ODG12(1) - - ODG9 ODG8 ODG7 ODG6 - - ODG3 ODG2 ODG1(2) ODG0(2) 0000 TRISG15 TRISG15(1) TRISG14 TRISG14(1) TRISG13 TRISG13(1) TRISG12 TRISG12(1 TRISG1(2) TRISG0(2) F3CF PAD CONFIGURATION MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets PADCFG1 02FC - - - - - - - - - - - - - - RTSECSEL PMPTTL 0000 Legend: x = unknown value on Reset, - = unimplemented, read as `0'. Reset values are shown in hexadecimal for 100-pin devices. PIC24FJ128GA PIC24FJ128GA FAMILY 02E0 LATF Preliminary PORTF TABLE 3-22: RG13 Bit 11 File Name PARALLEL MASTER/SLAVE PORT REGISTER MAP Addr Bit 15 PMCON 0600 PMPEN - PSIDL PMMODE 0602 BUSY IRQM1 IRQM0 CS2 CS1 PMADDR(1) PMDOUT1(1) 0604 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 ADRMUX1 ADRMUX0 PTBEEN PTWREN PTRDEN INCM1 INCM0 MODE16 MODE16 MODE1 MODE0 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets CSF1 CSF0 ALP CS2P CS1P BEP WRSP RDSP 0000 WAITB1 WAITB0 WAITM3 WAITM2 WAITM1 WAITM0 WAITE1 WAITE0 0000 Parallel Port Destination Address (Master modes) 0000 Parallel Port Data Out Register 1 (Buffers 0 and 1) 0000 PMDOUT2 0606 Parallel Port Data Out Register 2 (Buffers 2 and 3) 0000 PMDIN1 0608 Parallel Port Data In Register 1 (Buffers 0 and 1) 0000 PMPDIN2 060A Parallel Port Data In Register 2 (Buffers 2 and 3) PMPEN 060C PTEN15 PTEN15 PTEN14 PTEN14 PT