PIC18F87J90 DS39933C PIC32 ISO/TS-16949 LIN/J2602 PIC18F66J90 PIC18F67J90 - Datasheet Archive

 

Data Sheet 64/80-Pin, High-Performance Microcontrollers with LCD Driver and nanoWatt Technology © 2009 Microchip Technology

 

PIC18F87J90 PIC18F87J90 Family Data Sheet 64/80-Pin, High-Performance Microcontrollers with LCD Driver and nanoWatt Technology © 2009 Microchip Technology Inc. Preliminary DS39933C DS39933C Note the following details of the code protection feature on Microchip devices: · Microchip products meet the specification contained in their particular Microchip Data Sheet. · Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. · There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. · Microchip is willing to work with the customer who is concerned about the integrity of their code. · Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, rfPIC, SmartShunt and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, PICkit, PICDEM, PICDEM.net, PICtail, PIC32 PIC32 logo, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2009, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949 ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company's quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified. DS39933C-page ii Preliminary © 2009 Microchip Technology Inc. PIC18F87J90 PIC18F87J90 FAMILY 64/80-Pin, High-Performance Microcontrollers with LCD Driver and nanoWatt Technology LCD Driver and Keypad Interface Features: Peripheral Highlights: · High-Current Sink/Source 25 mA/25 mA (PORTB and PORTC) · Up to Four External Interrupts · Four 8-Bit/16-Bit Timer/Counter modules · Two Capture/Compare/PWM (CCP) modules · Master Synchronous Serial Port (MSSP) module with Two Modes of Operation: - 3-Wire/4-Wire SPI (supports all four SPI modes) - I2CTM Master and Slave mode · One Addressable USART module · One Enhanced Addressable USART module: - LIN/J2602 LIN/J2602 support - Auto-wake-up on Start bit and Break character - Auto-Baud Detect (ABD) · 10-Bit, up to 12-Channel A/D Converter: - Auto-acquisition - Conversion available during Sleep · Two Analog Comparators · Programmable Reference Voltage for Comparators · Hardware Real-Time Clock and Calendar (RTCC) with Clock, Calendar and Alarm Functions · Charge Time Measurement Unit (CTMU): - Capacitance measurement - Time measurement with 1 ns typical resolution · Direct LCD Panel Drive Capability: - Can drive LCD panel while in Sleep mode · Up to 48 Segments and 192 Pixels, Software Selectable · Programmable LCD Timing module: - Multiple LCD timing sources available - Up to four commons: static, 1/2, 1/3 or 1/4 multiplex - Static, 1/2 or 1/3 bias configuration · On-Chip LCD Boost Voltage Regulator for Contrast Control · Charge Time Measurement Unit (CTMU) for Capacitive Touch Sensing · ADC for Resistive Touch Sensing Low-Power Features: · Power-Managed modes: - Run: CPU On, Peripherals On - Idle: CPU Off, Peripherals On - Sleep: CPU Off, Peripherals Off · Two-Speed Oscillator Start-up Flexible Oscillator Structure: · · · · Two Crystal modes, 4-25 MHz Two External Clock modes, up to 48 MHz 4x Phase Lock Loop (PLL) Internal Oscillator Block with PLL: - Eight user-selectable frequencies from 31.25 kHz to 8 MHz · Secondary Oscillator using Timer1 at 32 kHz · Fail-Safe Clock Monitor: - Allows for safe shutdown if peripheral clock fails Special Microcontroller Features: SPI Master I2CTM EUSART AUSART 10-Bit A/D (Channels) Comparators BOR/LVD RTCC CTMU · 10,000 Erase/Write Cycle Flash Program Memory, Typical · Flash Retention 20 Years, Minimum · Self-Programmable under Software Control · Word Write Capability for Flash Program Memory for Data EEPROM Emulators Yes Yes 1/1 12 2 Yes Yes Yes MSSP SRAM Data Memory (Bytes) I/O PIC18F66J90 PIC18F66J90 64K 3,923 51 PIC18F67J90 PIC18F67J90 128K 3,923 51 132 1/3 2 Yes Yes 1/1 12 2 Yes Yes Yes PIC18F86J90 PIC18F86J90 64K 3,923 67 192 1/3 2 Yes Yes 1/1 12 2 Yes Yes Yes PIC18F87J90 PIC18F87J90 128K 3,923 67 192 1/3 2 Yes Yes 1/1 12 2 Yes Yes Yes Device © 2009 Microchip Technology Inc. LCD (Pixels) Timers 8/16-Bit Flash Program Memory (Bytes) CCP 132 1/3 2 Preliminary DS39933C-page 1 PIC18F87J90 PIC18F87J90 FAMILY Special Microcontroller Features (Continued): · Priority Levels for Interrupts · 8 x 8 Single-Cycle Hardware Multiplier · Extended Watchdog Timer (WDT): - Programmable period from 4 ms to 131s DS39933C-page 2 · In-Circuit Serial ProgrammingTM (ICSPTM) via Two Pins · In-Circuit Debug via Two Pins · Operating Voltage Range: 2.0V to 3.6V · 5.5V Tolerant Input (digital pins only) · Selectable Open-Drain Configuration for Serial Communication and CCP Pins for Driving Outputs up to 5V · On-Chip 2.5V Regulator Preliminary © 2009 Microchip Technology Inc. PIC18F87J90 PIC18F87J90 FAMILY Pin Diagrams ­ PIC18F6XJ90 PIC18F6XJ90 RD7/SEG7 RD6/SEG6 RD5/SEG5 RD4/SEG4 RD3/SEG3 RD2/SEG2 RD1/SEG1 VDD VSS RD0/SEG0/CTPLS RE7/CCP2(1)/SEG31 /SEG31 RE6/COM3 RE5/COM2 RE4/COM1 RE3/COM0 LCDBIAS3 64-Pin TQFP 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 RE1/LCDBIAS2 RE0/LCDBIAS1 RG0/LCDBIAS0 RG1/TX2/CK2 RG2/RX2/DT2/VLCAP1 RG3/VLCAP2 MCLR RG4/SEG26/RTCC RG4/SEG26/RTCC VSS VDDCORE/VCAP RF7/AN5/SS/SEG25 RF7/AN5/SS/SEG25 RF6/AN11/SEG24/C1INA RF6/AN11/SEG24/C1INA RF5/AN10/CVREF/SEG23/C1INB RF5/AN10/CVREF/SEG23/C1INB RF4/AN9/SEG22/C2INA RF4/AN9/SEG22/C2INA RF3/AN8/SEG21/C2INB RF3/AN8/SEG21/C2INB RF2/AN7/C1OUT/SEG20 RF2/AN7/C1OUT/SEG20 48 47 2 3 4 5 6 7 8 9 10 11 12 13 14 RB0/INT0/SEG30 RB0/INT0/SEG30 RB1/INT1/SEG8 46 45 1 RB2/INT2/SEG9/CTED1 44 43 42 PIC18F66J90 PIC18F66J90 41 40 PIC18F67J90 PIC18F67J90 39 38 37 36 35 15 34 33 16 RB3/INT3/SEG10/CTED2 RB3/INT3/SEG10/CTED2 RB4/KBI0/SEG11 RB4/KBI0/SEG11 RB5/KBI1/SEG29 RB5/KBI1/SEG29 RB6/KBI2/PGC VSS OSC2/CLKO/RA6 OSC1/CLKI/RA7 VDD RB7/KBI3/PGD RC5/SDO/SEG12 RC5/SDO/SEG12 RC4/SDI/SDA/SEG16 RC4/SDI/SDA/SEG16 RC3/SCK/SCL/SEG17 RC3/SCK/SCL/SEG17 RC2/CCP1/SEG13 RC2/CCP1/SEG13 Note 1: RC7/RX1/DT1/SEG28 RC7/RX1/DT1/SEG28 RC6/TX1/CK1/SEG27 RC6/TX1/CK1/SEG27 RC0/T1OSO/T13CKI RC0/T1OSO/T13CKI RA4/T0CKI/SEG14 RA4/T0CKI/SEG14 RC1/T1OSI/CCP2(1)/SEG32 /SEG32 VDD RA5/AN4/SEG15 RA5/AN4/SEG15 VSS RA0/AN0 RA1/AN1/SEG18 RA1/AN1/SEG18 RA2/AN2/VREF- AVSS RA3/AN3/VREF+ AVDD ENVREG RF1/AN6/C2OUT/SEG19 RF1/AN6/C2OUT/SEG19 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 The CCP2 pin placement depends on the CCP2MX bit setting. © 2009 Microchip Technology Inc. Preliminary DS39933C-page 3 PIC18F87J90 PIC18F87J90 FAMILY Pin Diagrams ­ PIC18F8XJ90 PIC18F8XJ90 RJ1/SEG33 RJ1/SEG33 RJ0 RD7/SEG7 RD6/SEG6 RD5/SEG5 RD4/SEG4 RD3/SEG3 RD2/SEG2 RD1/SEG1 VDD VSS RE7/CCP2(1)/SEG31 /SEG31 RD0/SEG0/CTPLS RE6/COM3 RE5/COM2 RE4/COM1 RE3/COM0 LCDBIAS3 RH0/SEG47 RH0/SEG47 RH1/SEG46 RH1/SEG46 80-Pin TQFP 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 RH2/SEG45 RH2/SEG45 RH3/SEG44 RH3/SEG44 RE1/LCDBIAS2 RE0/LCDBIAS1 RG0/LCDBIAS0 RG1/TX2/CK2 RG2/RX2/DT2/VLCAP1 RG3/VLCAP2 MCLR RG4/SEG26/RTCC RG4/SEG26/RTCC VSS VDDCORE/VCAP 1 60 2 3 59 58 57 4 5 6 7 8 9 56 55 54 53 52 51 50 49 PIC18F86J90 PIC18F86J90 10 PIC18F87J90 PIC18F87J90 11 12 RF7/AN5/SS/SEG25 RF7/AN5/SS/SEG25 RF6/AN11/SEG24/C1INA RF6/AN11/SEG24/C1INA RF5/AN10/CVREF/SEG23/C1INB RF5/AN10/CVREF/SEG23/C1INB RF4/AN9/SEG22/C2INA RF4/AN9/SEG22/C2INA 13 14 15 48 47 46 16 RF3/AN8/SEG21/C2INB RF3/AN8/SEG21/C2INB RF2/AN7/C1OUT/SEG20 RF2/AN7/C1OUT/SEG20 RH7/SEG43 RH7/SEG43 17 18 45 44 Note 1: RB0/INT0/SEG30 RB0/INT0/SEG30 RB1/INT1/SEG8 RB2/INT2/SEG9/CTED1 RB3/INT3/SEG10/CTED2 RB3/INT3/SEG10/CTED2 RB4/KBI0/SEG11 RB4/KBI0/SEG11 RB5/KBI1/SEG29 RB5/KBI1/SEG29 RB6/KBI2/PGC VSS OSC2/CLKO/RA6 OSC1/CLKI/RA7 VDD RB7/KBI3/PGD RC5/SDO/SEG12 RC5/SDO/SEG12 RC4/SDI/SDA/SEG16 RC4/SDI/SDA/SEG16 RC3/SCK/SCL/SEG17 RC3/SCK/SCL/SEG17 RC2/CCP1/SEG13 RC2/CCP1/SEG13 RJ7/SEG36 RJ7/SEG36 RJ6/SEG37 RJ6/SEG37 RJ5/SEG38 RJ5/SEG38 RJ4/SEG39 RJ4/SEG39 RC7/RX1/DT1/SEG28 RC7/RX1/DT1/SEG28 RC6/TX1/CK1/SEG27 RC6/TX1/CK1/SEG27 RC0/T1OSO/T13CKI RC0/T1OSO/T13CKI RA4/T0CKI/SEG14 RA4/T0CKI/SEG14 RC1/T1OSI/CCP2(1)I/SEG32 I/SEG32 VDD RA5/AN4/SEG15 RA5/AN4/SEG15 VSS RA0/AN0 RA1/AN1/SEG18 RA1/AN1/SEG18 RA2/AN2/VREF- AVSS RA3/AN3/VREF+ AVDD ENVREG RF1/AN6/C2OUT/SEG19 RF1/AN6/C2OUT/SEG19 RH4/SEG40 RH4/SEG40 RH5/SEG41 RH5/SEG41 RH6/SEG42 RH6/SEG42 43 42 19 41 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 RJ2/SEG34 RJ2/SEG34 RJ3/SEG35 RJ3/SEG35 The CCP2 pin placement depends on the CCP2MX bit setting. DS39933C-page 4 Preliminary © 2009 Microchip Technology Inc. PIC18F87J90 PIC18F87J90 FAMILY Table of Contents 1.0 Device Overview . 7 2.0 Oscillator Configurations . 29 3.0 Power-Managed Modes . 39 4.0 Reset . 47 5.0 Memory Organization . 59 6.0 Flash Program Memory. 83 7.0 8 x 8 Hardware Multiplier. 93 8.0 Interrupts . 95 9.0 I/O Ports . 111 10.0 Timer0 Module . 133 11.0 Timer1 Module . 137 12.0 Timer2 Module . 143 13.0 Timer3 Module . 145 14.0 Real-Time Clock and Calendar (RTCC). 149 15.0 Capture/Compare/PWM (CCP) Modules . 167 16.0 Liquid Crystal Display (LCD) Driver Module. 177 17.0 Master Synchronous Serial Port (MSSP) Module . 205 18.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) . 249 19.0 Addressable Universal Synchronous Asynchronous Receiver Transmitter (AUSART) . 269 20.0 10-bit Analog-to-Digital Converter (A/D) Module. 283 21.0 Comparator Module. 293 22.0 Comparator Voltage Reference Module. 299 23.0 Charge Time Measurement Unit (CTMU) . 303 24.0 Special Features of the CPU. 319 25.0 Instruction Set Summary . 333 26.0 Development Support. 383 27.0 Electrical Characteristics . 387 28.0 Packaging Information. 421 Appendix A: Revision History. 427 Appendix B: Migration From PIC18F85J90 PIC18F85J90 to PIC18F87J90 PIC18F87J90 . 427 The Microchip Web Site . 439 Customer Change Notification Service . 439 Customer Support . 439 Reader Response . 440 Product Identification System . 441 © 2009 Microchip Technology Inc. Preliminary DS39933C-page 5 PIC18F87J90 PIC18F87J90 FAMILY TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A DS30000A is version A of document DS30000 DS30000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: · Microchip's Worldwide Web site; http://www.microchip.com · Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. DS39933C-page 6 Preliminary © 2009 Microchip Technology Inc. PIC18F87J90 PIC18F87J90 FAMILY 1.0 DEVICE OVERVIEW This document contains device-specific information for the following devices: · PIC18F66J90 PIC18F66J90 · PIC18F67J90 PIC18F67J90 · PIC18F86J90 PIC18F86J90 · PIC18F87J90 PIC18F87J90 This family combines the traditional advantages of all PIC18 PIC18 microcontrollers ­ namely, high computational performance and a rich feature set ­ with a versatile on-chip LCD driver, while maintaining an extremely competitive price point. These features make the PIC18F87J90 PIC18F87J90 family a logical choice for many high-performance applications where price is a primary consideration. 1.1 1.1.1 Core Features nanoWatt TECHNOLOGY All of the devices in the PIC18F87J90 PIC18F87J90 family incorporate a range of features that can significantly reduce power consumption during operation. Key items include: · Alternate Run Modes: By clocking the controller from the Timer1 source or the internal RC oscillator, power consumption during code execution can be reduced by as much as 90%. · Multiple Idle Modes: The controller can also run with its CPU core disabled but the peripherals still active. In these states, power consumption can be reduced even further, to as little as 4% of normal operation requirements. · On-the-Fly Mode Switching: The power-managed modes are invoked by user code during operation, allowing the user to incorporate power-saving ideas into their application's software design. 1.1.2 · Fail-Safe Clock Monitor: This option constantly monitors the main clock source against a reference signal provided by the internal oscillator. If a clock failure occurs, the controller is switched to the internal oscillator, allowing for continued low-speed operation or a safe application shutdown. · Two-Speed Start-up: This option allows the internal oscillator to serve as the clock source from Power-on Reset, or wake-up from Sleep mode, until the primary clock source is available. 1.1.3 All of the devices in the PIC18F87J90 PIC18F87J90 family offer six different oscillator options, allowing users a range of choices in developing application hardware. These include: · Two Crystal modes, using crystals or ceramic resonators. · Two External Clock modes, offering the option of a divide-by-4 clock output. · A Phase Lock Loop (PLL) frequency multiplier, available to the External Oscillator modes which allows clock speeds of up to 40 MHz. PLL can also be used with the internal oscillator. · An internal oscillator block which provides an 8 MHz clock (±2% accuracy) and an INTRC source (approximately 31 kHz, stable over temperature and VDD), as well as a range of six user-selectable clock frequencies, between 125 kHz to 4 MHz, for a total of eight clock frequencies. This option frees the two oscillator pins for use as additional general purpose I/O. MEMORY OPTIONS The PIC18F87J90 PIC18F87J90 family provides ample room for application code, from 64 Kbytes to 128 Kbytes of code space. The Flash cells for program memory are rated to last up to 10,000 erase/write cycles. Data retention without refresh is conservatively estimated to be greater than 20 years. The Flash program memory is readable and writable. During normal operation, the PIC18F87J90 PIC18F87J90 family also provides plenty of room for dynamic application data with up to 3,923 bytes of data RAM. 1.1.4 EXTENDED INSTRUCTION SET The PIC18F87J90 PIC18F87J90 family implements the optional extension to the PIC18 PIC18 instruction set, adding 8 new instructions and an Indexed Addressing mode. Enabled as a device configuration option, the extension has been specifically designed to optimize re-entrant application code originally developed in high-level languages, such as `C'. 1.1.5 OSCILLATOR OPTIONS AND FEATURES © 2009 Microchip Technology Inc. The internal oscillator block provides a stable reference source that gives the family additional features for robust operation: EASY MIGRATION Regardless of the memory size, all devices share the same rich set of peripherals, allowing for a smooth migration path as applications grow and evolve. The consistent pinout scheme used throughout the entire family also aids in migrating to the next larger device. This is true when moving between the 64-pin members, between the 80-pin members, or even jumping from 64-pin to 80-pin devices. The PIC18F87J90 PIC18F87J90 family is also largely pin compatible with other PIC18 PIC18 families, such as the PIC18F8720 PIC18F8720 and PIC18F8722 PIC18F8722, the PIC18F85J11 PIC18F85J11, and the PIC18F8490 PIC18F8490 and PIC18F85J90 PIC18F85J90 families of microcontrollers with LCD drivers. This allows a new dimension to the evolution of applications, allowing developers to select different price points within Microchip's PIC18 PIC18 portfolio, while maintaining a similar feature set. Preliminary DS39933C-page 7 PIC18F87J90 PIC18F87J90 FAMILY 1.2 LCD Driver 1.4 Details on Individual Family Members The on-chip LCD driver includes many features that make the integration of displays in low-power applications easier. These include an integrated voltage regulator with charge pump that allows contrast control in software and display operation above device VDD. Devices in the PIC18F87J90 PIC18F87J90 family are available in 64-pin and 80-pin packages. Block diagrams for the two groups are shown in Figure 1-1 and Figure 1-2. 1.3 1. Other Special Features · Communications: The PIC18F87J90 PIC18F87J90 family incorporates a range of serial communication peripherals, including an Addressable USART, a separate Enhanced USART that supports LIN specification 1.2, and one Master SSP module capable of both SPI and I2CTM (Master and Slave) modes of operation. · CCP Modules: All devices in the family incorporate two Capture/Compare/PWM (CCP) modules. Up to four different time bases may be used to perform several different operations at once. · 10-Bit A/D Converter: This module incorporates programmable acquisition time, allowing for a channel to be selected and a conversion to be initiated without waiting for a sampling period and thus, reducing code overhead. · Charge Time Measurement Unit (CTMU): The CTMU is a flexible analog module that provides accurate differential time measurement between pulse sources, as well as asynchronous pulse generation. The devices are differentiated from each other in four ways: 2. 3. 4. Flash program memory (two sizes, 64 Kbytes for PIC18FX6J90 PIC18FX6J90 devices and 128 Kbytes for PIC18FX7J90 PIC18FX7J90 devices). Data RAM (3,923 bytes RAM for both PIC18FX6J90 PIC18FX6J90 and PIC18FX7J90 PIC18FX7J90 devices). I/O ports (7 bidirectional ports on PIC18F6XJ90 PIC18F6XJ90 devices, 9 bidirectional ports on PIC18F8XJ90 PIC18F8XJ90 devices). LCD Pixels: 132 pixels (33 SEGs x 4 COMs) can be driven by 64-pin devices; 192 pixels (48 SEGs x 4 COMs) can be driven by 80-pin devices. All other features for devices in this family are identical. These are summarized in Table 1-1 and Table 1-2. The pinouts for all devices are listed in Table 1-3 and Table 1-4. Together with other on-chip analog modules, the CTMU can precisely measure time, measure capacitance or relative changes in capacitance, or generate output pulses that are independent of the system clock. · Extended Watchdog Timer (WDT): This enhanced version incorporates a 16-bit prescaler, allowing an extended time-out range that is stable across operating voltage and temperature. See Section 27.0 "Electrical Characteristics" for time-out periods. · Real Time Clock and Calendar Module (RTCC): The RTCC module is intended for applications requiring that accurate time be maintained for extended periods of time with minimum to no intervention from the CPU. The module is a 100-year clock and calendar with automatic leap-year detection. The range of the clock is from 00:00:00 (midnight) on January 1, 2000 to 23:59:59 on December 31, 2099. DS39933C-page 8 Preliminary © 2009 Microchip Technology Inc. PIC18F87J90 PIC18F87J90 FAMILY TABLE 1-1: DEVICE FEATURES FOR THE PIC18F6XJ90 PIC18F6XJ90 (64-PIN 64-PIN DEVICES) Features PIC18F66J90 PIC18F66J90 Operating Frequency Program Memory (Bytes) Program Memory (Instructions) Data Memory (Bytes) PIC18F67J90 PIC18F67J90 DC ­ 48 MHz 64K 128K 32,768 65,536 3,923 3,923 Interrupt Sources 29 I/O Ports Ports A, B, C, D, E, F, G LCD Driver (available pixels to drive) 132 (33 SEGs x 4 COMs) Timers 4 Comparators 2 CTMU Yes RTCC Yes Capture/Compare/PWM Modules Serial Communications 2 MSSP, Addressable USART, Enhanced USART 10-Bit Analog-to-Digital Module Resets (and Delays) Instruction Set 12 Input Channels POR, BOR, RESET Instruction, Stack Full, Stack Underflow, MCLR, WDT (PWRT, OST) 75 Instructions, 83 with Extended Instruction Set enabled Packages 64-Pin TQFP TABLE 1-2: DEVICE FEATURES FOR THE PIC18F8XJ90 PIC18F8XJ90 (80-PIN 80-PIN DEVICES) Features PIC18F86J90 PIC18F86J90 Operating Frequency Program Memory (Bytes) Program Memory (Instructions) Data Memory (Bytes) DC ­ 48 MHz 64K 128K 32,768 65,536 3,923 3,923 Interrupt Sources I/O Ports LCD Driver (available pixels to drive) PIC18F87J90 PIC18F87J90 29 Ports A, B, C, D, E, F, G, H, J 192 (48 SEGs x 4 COMs) Timers 4 Comparators 2 CTMU Yes RTCC Yes Capture/Compare/PWM Modules Serial Communications 2 MSSP, Addressable USART, Enhanced USART 10-Bit Analog-to-Digital Module Resets (and Delays) Instruction Set 12 Input Channels POR, BOR, RESET Instruction, Stack Full, Stack Underflow, MCLR, WDT (PWRT, OST) 75 Instructions, 83 with Extended Instruction Set enabled Packages © 2009 Microchip Technology Inc. 80-Pin TQFP Preliminary DS39933C-page 9 PIC18F87J90 PIC18F87J90 FAMILY FIGURE 1-1: PIC18F6XJ90 PIC18F6XJ90 (64-PIN 64-PIN) BLOCK DIAGRAM Data Bus Table Pointer RA0:RA7(1,2) Data Memory (2.0, 3.9 Kbytes) PCLATU PCLATH 21 PORTA Data Latch 8 8 inc/dec logic Address Latch 20 PCU PCH PCL Program Counter 12 Data Address PORTB RB0:RB7(1) 31-Level Stack 4 BSR Address Latch Program Memory (96 Kbytes) STKPTR 4 Access Bank 12 FSR0 FSR1 FSR2 Data Latch 12 PORTC RC0:RC7(1) inc/dec logic 8 Table Latch Address Decode ROM Latch Instruction Bus PORTD RD0:RD7(1) IR 8 Instruction Decode and Control Power-up Timer Oscillator Start-up Timer Precision Band Gap Reference ENVREG Voltage Regulator PORTE RE0:RE1, RE3:RE7(1) PRODH PRODL 3 Timing Generation INTRC Oscillator 8 MHz Oscillator OSC2/CLKO OSC1/CLKI State Machine Control Signals 8 x 8 Multiply 8 BITOP W 8 8 8 8 Power-on Reset PORTF 8 RF1:RF7(1) ALU Watchdog Timer 8 BOR and LVD(3) PORTG RG0:RG4(1) VDDCORE/VCAP VDD, VSS MCLR Timer0 Timer1 Timer2 Timer3 CTMU ADC 10-bit Comparators CCP1 CCP2 AUSART EUSART RTCC MSSP LCD Driver Note 1: See Table 1-3 for I/O port pin descriptions. 2: RA6 and RA7 are only available as digital I/O in select oscillator modes. See Section 2.0 "Oscillator Configurations" for more information 3: Brown-out Reset and Low-Voltage Detect functions are provided when the on-board voltage regulator is enabled. DS39933C-page 10 Preliminary © 2009 Microchip Technology Inc. PIC18F87J90 PIC18F87J90 FAMILY FIGURE 1-2: PIC18F8XJ90 PIC18F8XJ90 (80-PIN 80-PIN) BLOCK DIAGRAM Data Bus Table Pointer RA0:RA7(1,2) Data Memory (2.0, 3.9 Kbytes) PCLATU PCLATH 21 PORTA Data Latch 8 8 inc/dec logic Address Latch 20 PCU PCH PCL Program Counter PORTB RB0:RB7(1) 12 Data Address 31-Level Stack 4 BSR Address Latch Program Memory (96 Kbytes) STKPTR 4 Access Bank 12 FSR0 FSR1 FSR2 Data Latch PORTC RC0:RC7(1) 12 inc/dec logic 8 Table Latch PORTD RD0:RD7(1) Address Decode ROM Latch Instruction Bus PORTE RE0:RE1, RE3:RE7(1) IR 8 Instruction Decode and Control PORTF PRODH PRODL 3 Timing Generation Power-up Timer INTRC Oscillator 8 MHz Oscillator OSC2/CLKO OSC1/CLKI State Machine Control Signals Oscillator Start-up Timer 8 x 8 Multiply 8 BITOP W 8 8 8 Precision Band Gap Reference Watchdog Timer Voltage Regulator PORTG RG0:RG4(1) 8 Power-on Reset RF1:RF7(1) 8 BOR and LVD(3) ENVREG ALU PORTH RH0:RH7(1) 8 PORTJ VDDCORE/VCAP VDD,VSS RJ0:RJ7(1) MCLR Timer0 Timer1 Timer2 Timer3 CTMU ADC 10-bit Comparators CCP1 CCP2 AUSART EUSART RTCC MSSP LCD Driver Note 1: See Table 1-3 for I/O port pin descriptions. 2: RA6 and RA7 are only available as digital I/O in select oscillator modes. See Section 2.0 "Oscillator Configurations" for more information. 3: Brown-out Reset and Low-Voltage Detect functions are provided when the on-board voltage regulator is enabled. © 2009 Microchip Technology Inc. Preliminary DS39933C-page 11 PIC18F87J90 PIC18F87J90 FAMILY TABLE 1-3: PIC18F6XJ90 PIC18F6XJ90 PINOUT I/O DESCRIPTIONS Pin Number Pin Name TQFP MCLR 7 OSC1/CLKI/RA7 OSC1 CLKI Pin Buffer Type Type I ST 39 I I CMOS CMOS I/O TTL O - CLKO O - RA6 I/O TTL RA7 OSC2/CLKO/RA6 OSC2 40 Description Master Clear (input) or programming voltage (input). This pin is an active-low Reset to the device. Oscillator crystal or external clock input. Oscillator crystal input. External clock source input. Always associated with pin function OSC1. (See related OSC1/CLKI, OSC2/CLKO pins.) General purpose I/O pin. Oscillator crystal or clock output. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. In EC modes, OSC2 pin outputs CLKO, which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. General purpose I/O pin. PORTA is a bidirectional I/O port. RA0/AN0 RA0 AN0 24 RA1/AN1/SEG18 RA1/AN1/SEG18 RA1 AN1 SEG18 SEG18 23 RA2/AN2/VREFRA2 AN2 VREF- 22 RA3/AN3/VREF+ RA3 AN3 VREF+ 21 RA4/T0CKI/SEG14 RA4/T0CKI/SEG14 RA4 T0CKI SEG14 SEG14 28 RA5/AN4/SEG15 RA5/AN4/SEG15 RA5 AN4 SEG15 SEG15 27 I/O I TTL Analog Digital I/O. Analog input 0. I/O I O TTL Analog Analog Digital I/O. Analog input 1. SEG18 SEG18 output for LCD. I/O I I TTL Analog Analog Digital I/O. Analog input 2. A/D reference voltage (low) input. I/O I I TTL Analog Analog Digital I/O. Analog input 3. A/D reference voltage (high) input. I/O I O ST ST Analog Digital I/O. Timer0 external clock input. SEG14 SEG14 output for LCD. I/O I O TTL Analog Analog Digital I/O. Analog input 4. SEG15 SEG15 output for LCD. RA6 See the OSC2/CLKO/RA6 pin. RA7 See the OSC1/CLKI/RA7 pin. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set. 2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared. DS39933C-page 12 Preliminary © 2009 Microchip Technology Inc. PIC18F87J90 PIC18F87J90 FAMILY TABLE 1-3: PIC18F6XJ90 PIC18F6XJ90 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP Pin Buffer Type Type Description PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs. RB0/INT0/SEG30 RB0/INT0/SEG30 RB0 INT0 SEG30 SEG30 48 RB1/INT1/SEG8 RB1 INT1 SEG8 47 RB2/INT2/SEG9/CTED1 RB2 INT2 CTED1 SEG9 46 RB3/INT3/SEG10/CTED2 RB3/INT3/SEG10/CTED2 RB3 INT3 SEG10 SEG10 CTED2 45 RB4/KBI0/SEG11 RB4/KBI0/SEG11 RB4 KBI0 SEG11 SEG11 44 RB5/KBI1/SEG29 RB5/KBI1/SEG29 RB5 KBI1 SEG29 SEG29 43 RB6/KBI2/PGC RB6 KBI2 PGC 42 RB7/KBI3/PGD RB7 KBI3 PGD 37 I/O I O TTL ST Analog Digital I/O. External interrupt 0. SEG30 SEG30 output for LCD. I/O I O TTL ST Analog Digital I/O. External interrupt 1. SEG8 output for LCD. I/O I I O TTL ST ST Analog Digital I/O. External interrupt 2. CTMU Edge 1 input. SEG9 output for LCD. I/O I O I TTL ST Analog ST Digital I/O. External interrupt 3. SEG10 SEG10 output for LCD. CTMU Edge 2 input. I/O I O TTL TTL Analog Digital I/O. Interrupt-on-change pin. SEG11 SEG11 output for LCD. I/O I O TTL TTL Analog Digital I/O. Interrupt-on-change pin. SEG29 SEG29 output for LCD. I/O I I/O TTL TTL ST Digital I/O. Interrupt-on-change pin. In-Circuit Debugger and ICSPTM programming clock pin. I/O I I/O TTL TTL ST Digital I/O. Interrupt-on-change pin. In-Circuit Debugger and ICSP programming data pin. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set. 2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared. © 2009 Microchip Technology Inc. Preliminary DS39933C-page 13 PIC18F87J90 PIC18F87J90 FAMILY TABLE 1-3: PIC18F6XJ90 PIC18F6XJ90 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP Pin Buffer Type Type Description PORTC is a bidirectional I/O port. RC0/T1OSO/T13CKI RC0/T1OSO/T13CKI RC0 T1OSO T13CKI T13CKI 30 RC1/T1OSI/CCP2/SEG32 RC1/T1OSI/CCP2/SEG32 RC1 T1OSI CCP2(1) SEG32 SEG32 29 RC2/CCP1/SEG13 RC2/CCP1/SEG13 RC2 CCP1 SEG13 SEG13 33 RC3/SCK/SCL/SEG17 RC3/SCK/SCL/SEG17 RC3 SCK SCL SEG17 SEG17 34 RC4/SDI/SDA/SEG16 RC4/SDI/SDA/SEG16 RC4 SDI SDA SEG16 SEG16 35 RC5/SDO/SEG12 RC5/SDO/SEG12 RC5 SDO SEG12 SEG12 36 RC6/TX1/CK1/SEG27 RC6/TX1/CK1/SEG27 RC6 TX1 CK1 SEG27 SEG27 31 RC7/RX1/DT1/SEG28 RC7/RX1/DT1/SEG28 RC7 RX1 DT1 SEG28 SEG28 32 I/O O I ST - ST I/O I I/O O ST CMOS ST Analog Digital I/O. Timer1 oscillator input. Capture2 input/Compare2 output/PWM2 output. SEG32 SEG32 output for LCD. I/O I/O O ST ST Analog Digital I/O. Capture 1 input/Compare 1 output/PWM1 output. SEG13 SEG13 output for LCD. I/O I/O I/O O ST ST ST Analog Digital I/O. Synchronous serial clock input/output for SPI mode. Synchronous serial clock input/output for I2CTM mode. SEG17 SEG17 output for LCD. I/O I I/O O ST ST ST Analog Digital I/O. SPI data in. I2C data I/O. SEG16 SEG16 output for LCD. I/O O O ST - Analog Digital I/O. SPI data out. SEG12 SEG12 output for LCD. I/O O I/O O ST - ST Analog Digital I/O. EUSART asynchronous transmit. EUSART synchronous clock (see related RX1/DT1). SEG27 SEG27 output for LCD. I/O I I/O O ST ST ST Analog Digital I/O. EUSART asynchronous receive. EUSART synchronous data (see related TX1/CK1). SEG28 SEG28 output for LCD. Digital I/O. Timer1 oscillator output. Timer1/Timer3 external clock input. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set. 2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared. DS39933C-page 14 Preliminary © 2009 Microchip Technology Inc. PIC18F87J90 PIC18F87J90 FAMILY TABLE 1-3: PIC18F6XJ90 PIC18F6XJ90 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP Pin Buffer Type Type Description PORTD is a bidirectional I/O port. RD0/SEG0/CTPLS RD0 SEG0 CTPLS 58 RD1/SEG1 RD1 SEG1 55 RD2/SEG2 RD2 SEG2 54 RD3/SEG3 RD3 SEG3 53 RD4/SEG4 RD4 SEG4 52 RD5/SEG5 RD5 SEG5 51 RD6/SEG6 RD6 SEG6 50 RD7/SEG7 RD7 SEG7 49 I/O O O ST Analog - Digital I/O. SEG0 output for LCD. CTMU pulse generator output. I/O O ST Analog Digital I/O. SEG1 output for LCD. I/O O ST Analog Digital I/O. SEG2 output for LCD. I/O O ST Analog Digital I/O. SEG3 output for LCD. I/O O ST Analog Digital I/O. SEG4 output for LCD. I/O O ST Analog Digital I/O. SEG5 output for LCD. I/O O ST Analog Digital I/O. SEG6 output for LCD. I/O O ST Analog Digital I/O. SEG7 output for LCD. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set. 2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared. © 2009 Microchip Technology Inc. Preliminary DS39933C-page 15 PIC18F87J90 PIC18F87J90 FAMILY TABLE 1-3: PIC18F6XJ90 PIC18F6XJ90 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP Pin Buffer Type Type Description PORTE is a bidirectional I/O port. RE0/LCDBIAS1 RE0 LCDBIAS1 2 RE1/LCDBIAS2 RE1 LCDBIAS2 1 LCDBIAS3 64 RE3/COM0 RE3 COM0 63 RE4/COM1 RE4 COM1 62 RE5/COM2 RE5 COM2 61 RE6/COM3 RE6 COM3 60 RE7/CCP2/SEG31 RE7/CCP2/SEG31 RE7 CCP2(2) SEG31 SEG31 59 I/O I ST Analog Digital I/O. BIAS1 input for LCD. I/O I ST Analog Digital I/O. BIAS2 input for LCD. I Analog BIAS3 input for LCD. I/O O ST Analog Digital I/O. COM0 output for LCD. I/O O ST Analog Digital I/O. COM1 output for LCD. I/O O ST Analog Digital I/O. COM2 output for LCD. I/O O ST Analog Digital I/O. COM3 output for LCD. I/O I/O O ST ST Analog Digital I/O. Capture 2 input/Compare 2 output/PWM2 output. SEG31 SEG31 output for LCD. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set. 2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared. DS39933C-page 16 Preliminary © 2009 Microchip Technology Inc. PIC18F87J90 PIC18F87J90 FAMILY TABLE 1-3: PIC18F6XJ90 PIC18F6XJ90 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP Pin Buffer Type Type Description PORTF is a bidirectional I/O port. RF1/AN6/C2OUT/SEG19 RF1/AN6/C2OUT/SEG19 RF1 AN6 C2OUT SEG19 SEG19 17 RF2/AN7/C1OUT/SEG20 RF2/AN7/C1OUT/SEG20 RF2 AN7 C1OUT SEG20 SEG20 16 RF3/AN8/SEG21/C2INB RF3/AN8/SEG21/C2INB RF3 AN8 SEG21 SEG21 C2INB 15 RF4/AN9/SEG22/C2INA RF4/AN9/SEG22/C2INA RF4 AN9 SEG22 SEG22 C2INA 14 RF5/AN10/CVREF/ RF5/AN10/CVREF/ SEG23/C1INB SEG23/C1INB RF5 AN10 CVREF SEG23 SEG23 C1INB 13 RF6/AN11/SEG24/C1INA RF6/AN11/SEG24/C1INA RF6 AN11 SEG24 SEG24 C1INA 12 RF7/AN5/SS/SEG25 RF7/AN5/SS/SEG25 RF7 AN5 SS SEG25 SEG25 11 I/O I O O ST Analog - Analog Digital I/O. Analog input 6. Comparator 2 output. SEG19 SEG19 output for LCD. I/O I O O ST Analog - Analog Digital I/O. Analog input 7. Comparator 1 output. SEG20 SEG20 output for LCD. I/O I O I ST Analog Analog Analog Digital I/O. Analog input 8. SEG21 SEG21 output for LCD. Comparator 2 input B. I/O I O I ST Analog Analog Analog Digital I/O. Analog input 9. SEG22 SEG22 output for LCD Comparator 2 input A. I/O I O O I ST Analog Analog Analog Analog Digital I/O. Analog input 10. Comparator reference voltage output. SEG23 SEG23 output for LCD. Comparator 1 input B. I/O I O I ST Analog Analog Analog Digital I/O. Analog input 11. SEG24 SEG24 output for LCD Comparator 1 input A. I/O O I O ST Analog TTL Analog Digital I/O. Analog input 5. SPI slave select input. SEG25 SEG25 output for LCD. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set. 2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared. © 2009 Microchip Technology Inc. Preliminary DS39933C-page 17 PIC18F87J90 PIC18F87J90 FAMILY TABLE 1-3: PIC18F6XJ90 PIC18F6XJ90 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP Pin Buffer Type Type Description PORTG is a bidirectional I/O port. RG0/LCDBIAS0 RG0 LCDBIAS0 3 RG1/TX2/CK2 RG1 TX2 CK2 4 RG2/RX2/DT2/VLCAP1 RG2 RX2 DT2 VLCAP1 5 RG3/VLCAP2 RG3 VLCAP2 6 RG4/SEG26/RTCC RG4/SEG26/RTCC RG4 SEG26 SEG26 RTCC 8 I/O I ST Analog Digital I/O. BIAS0 input for LCD. I/O O I/O ST - ST Digital I/O. AUSART asynchronous transmit. AUSART synchronous clock (see related RX2/DT2). I/O I I/O I ST ST ST Analog Digital I/O. AUSART asynchronous receive. AUSART synchronous data (see related TX2/CK2). LCD charge pump capacitor input. I/O I ST Analog Digital I/O. LCD charge pump capacitor input. I/O O O ST Analog - Digital I/O. SEG26 SEG26 output for LCD. RTCC output VSS 9, 25, 41, 56 P - Ground reference for logic and I/O pins. Positive supply for logic and I/O pins. VDD 26, 38, 57 P - AVSS 20 P - Ground reference for analog modules. AVDD 19 P - Positive supply for analog modules. ENVREG 18 I ST Enable for on-chip voltage regulator. VDDCORE/VCAP VDDCORE 10 P - P - VCAP Core logic power or external filter capacitor connection. Positive supply for microcontroller core logic (regulator disabled). External filter capacitor connection (regulator enabled). Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set. 2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared. DS39933C-page 18 Preliminary © 2009 Microchip Technology Inc. PIC18F87J90 PIC18F87J90 FAMILY TABLE 1-4: PIC18F8XJ90 PIC18F8XJ90 PINOUT I/O DESCRIPTIONS Pin Number Pin Name TQFP MCLR 9 OSC1/CLKI/RA7 OSC1 CLKI Pin Buffer Type Type I ST 49 I I CMOS CMOS I/O TTL O - CLKO O - RA6 I/O TTL RA7 OSC2/CLKO/RA6 OSC2 50 Description Master Clear (input) or programming voltage (input). This pin is an active-low Reset to the device. Oscillator crystal or external clock input. Oscillator crystal input. External clock source input. Always associated with pin function OSC1. (See related OSC1/CLKI, OSC2/CLKO pins.) General purpose I/O pin. Oscillator crystal or clock output. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. In EC modes, OSC2 pin outputs CLKO, which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. General purpose I/O pin. PORTA is a bidirectional I/O port. RA0/AN0 RA0 AN0 30 RA1/AN1/SEG18 RA1/AN1/SEG18 RA1 AN1 SEG18 SEG18 29 RA2/AN2/VREFRA2 AN2 VREF- 28 RA3/AN3/VREF+ RA3 AN3 VREF+ 27 RA4/T0CKI/SEG14 RA4/T0CKI/SEG14 RA4 T0CKI SEG14 SEG14 34 RA5/AN4/SEG15 RA5/AN4/SEG15 RA5 AN4 SEG15 SEG15 33 I/O I TTL Analog Digital I/O. Analog input 0. I/O I O TTL Analog Analog Digital I/O. Analog input 1. SEG18 SEG18 output for LCD. I/O I I TTL Analog Analog Digital I/O. Analog input 2. A/D reference voltage (low) input. I/O I I TTL Analog Analog Digital I/O. Analog input 3. A/D reference voltage (high) input. I/O I O ST ST Analog Digital I/O. Timer0 external clock input. SEG14 SEG14 output for LCD. I/O I O TTL Analog Analog Digital I/O. Analog input 4. SEG15 SEG15 output for LCD. RA6 See the OSC2/CLKO/RA6 pin. RA7 See the OSC1/CLKI/RA7 pin. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set. 2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared. © 2009 Microchip Technology Inc. Preliminary DS39933C-page 19 PIC18F87J90 PIC18F87J90 FAMILY TABLE 1-4: PIC18F8XJ90 PIC18F8XJ90 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP Pin Buffer Type Type Description PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs. RB0/INT0/SEG30 RB0/INT0/SEG30 RB0 INT0 SEG30 SEG30 58 RB1/INT1/SEG8 RB1 INT1 SEG8 57 RB2/INT2/SEG9/CTED1 RB2 INT2 SEG9 CTED1 56 RB3/INT3/SEG10/ RB3/INT3/SEG10/ CTED2 RB3 INT3 SEG10 SEG10 CTED2 55 RB4/KBI0/SEG11 RB4/KBI0/SEG11 RB4 KBI0 SEG11 SEG11 54 RB5/KBI1/SEG29 RB5/KBI1/SEG29 RB5 KBI1 SEG29 SEG29 53 RB6/KBI2/PGC RB6 KBI2 PGC 52 RB7/KBI3/PGD RB7 KBI3 PGD 47 I/O I O TTL ST Analog Digital I/O. External interrupt 0. SEG30 SEG30 output for LCD. I/O I O TTL ST Analog Digital I/O. External interrupt 1. SEG8 output for LCD. I/O I O I TTL ST Analog ST Digital I/O. External interrupt 2. SEG9 output for LCD. CTMU Edge 1 input. I/O I O I TTL ST Analog ST Digital I/O. External interrupt 3. SEG10 SEG10 output for LCD. CTMU Edge 2 input. I/O I O TTL TTL Analog Digital I/O. Interrupt-on-change pin. SEG11 SEG11 output for LCD. I/O I O TTL TTL Analog Digital I/O. Interrupt-on-change pin. SEG29 SEG29 output for LCD. I/O I I/O TTL TTL ST Digital I/O. Interrupt-on-change pin. In-Circuit Debugger and ICSPTM programming clock pin. I/O I I/O TTL TTL ST Digital I/O. Interrupt-on-change pin. In-Circuit Debugger and ICSP programming data pin. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set. 2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared. DS39933C-page 20 Preliminary © 2009 Microchip Technology Inc. PIC18F87J90 PIC18F87J90 FAMILY TABLE 1-4: PIC18F8XJ90 PIC18F8XJ90 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP Pin Buffer Type Type Description PORTC is a bidirectional I/O port. RC0/T1OSO/T13CKI RC0/T1OSO/T13CKI RC0 T1OSO T13CKI T13CKI 36 RC1/T1OSI/CCP2/SEG32 RC1/T1OSI/CCP2/SEG32 RC1 T1OSI CCP2(1) SEG32 SEG32 35 RC2/CCP1/SEG13 RC2/CCP1/SEG13 RC2 CCP1 SEG13 SEG13 43 RC3/SCK/SCL/SEG17 RC3/SCK/SCL/SEG17 RC3 SCK SCL SEG17 SEG17 44 RC4/SDI/SDA/SEG16 RC4/SDI/SDA/SEG16 RC4 SDI SDA SEG16 SEG16 45 RC5/SDO/SEG12 RC5/SDO/SEG12 RC5 SDO SEG12 SEG12 46 RC6/TX1/CK1/SEG27 RC6/TX1/CK1/SEG27 RC6 TX1 CK1 SEG27 SEG27 37 RC7/RX1/DT1/SEG28 RC7/RX1/DT1/SEG28 RC7 RX1 DT1 SEG28 SEG28 38 I/O O I ST - ST I/O I I/O O ST CMOS ST Analog Digital I/O. Timer1 oscillator input. Capture 2 input/Compare 2 output/PWM2 output. SEG32 SEG32 output for LCD. I/O I/O O ST ST Analog Digital I/O. Capture 1 input/Compare 1 output/PWM1 output. SEG13 SEG13 output for LCD. I/O I/O I/O O ST ST ST Analog Digital I/O. Synchronous serial clock input/output for SPI mode. Synchronous serial clock input/output for I2CTM mode. SEG17 SEG17 output for LCD. I/O I I/O O ST ST ST Analog Digital I/O. SPI data in. I2C data I/O. SEG16 SEG16 output for LCD. I/O O O ST - Analog Digital I/O. SPI data out. SEG12 SEG12 output for LCD. I/O O I/O O ST - ST Analog Digital I/O. EUSART asynchronous transmit. EUSART synchronous clock (see related RX1/DT1). SEG27 SEG27 output for LCD. I/O I I/O O ST ST ST Analog Digital I/O. EUSART asynchronous receive. EUSART synchronous data (see related TX1/CK1). SEG28 SEG28 output for LCD. Digital I/O. Timer1 oscillator output. Timer1/Timer3 external clock input. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set. 2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared. © 2009 Microchip Technology Inc. Preliminary DS39933C-page 21 PIC18F87J90 PIC18F87J90 FAMILY TABLE 1-4: PIC18F8XJ90 PIC18F8XJ90 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP Pin Buffer Type Type Description PORTD is a bidirectional I/O port. RD0/SEG0/CTPLS RD0 SEG0 CTPLS 72 RD1/SEG1 RD1 SEG1 69 RD2/SEG2 RD2 SEG2 68 RD3/SEG3 RD3 SEG3 67 RD4/SEG4 RD4 SEG4 66 RD5/SEG5 RD5 SEG5 65 RD6/SEG6 RD6 SEG6 64 RD7/SEG7 RD7 SEG7 63 I/O O O ST Analog ST Digital I/O. SEG0 output for LCD. CTMU pulse generator output. I/O O ST Analog Digital I/O. SEG1 output for LCD. I/O O ST Analog Digital I/O. SEG2 output for LCD. I/O O ST Analog Digital I/O. SEG3 output for LCD. I/O O ST Analog Digital I/O. SEG4 output for LCD. I/O O ST Analog Digital I/O. SEG5 output for LCD. I/O O ST Analog Digital I/O. SEG6 output for LCD. I/O O ST Analog Digital I/O. SEG7 output for LCD. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set. 2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared. DS39933C-page 22 Preliminary © 2009 Microchip Technology Inc. PIC18F87J90 PIC18F87J90 FAMILY TABLE 1-4: PIC18F8XJ90 PIC18F8XJ90 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP Pin Buffer Type Type Description PORTE is a bidirectional I/O port. RE0/LCDBIAS1 RE0 LCDBIAS1 4 RE1/LCDBIAS2 RE1 LCDBIAS2 3 LCDBIAS3 78 RE3/COM0 RE3 COM0 77 RE4/COM1 RE4 COM1 76 RE5/COM2 RE5 COM2 75 RE6/COM3 RE6 COM3 74 RE7/CCP2/SEG31 RE7/CCP2/SEG31 RE7 CCP2(2) SEG31 SEG31 73 I/O I ST Analog Digital I/O. BIAS1 input for LCD. I/O I ST Analog Digital I/O. BIAS2 input for LCD. I Analog BIAS3 input for LCD. I/O O ST Analog Digital I/O. COM0 output for LCD. I/O O ST Analog Digital I/O. COM1 output for LCD. I/O O ST Analog Digital I/O. COM2 output for LCD. I/O O ST Analog Digital I/O. COM3 output for LCD. I/O I/O O ST ST Analog Digital I/O. Capture 2 input/Compare 2 output/PWM2 output. SEG31 SEG31 output for LCD. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set. 2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared. © 2009 Microchip Technology Inc. Preliminary DS39933C-page 23 PIC18F87J90 PIC18F87J90 FAMILY TABLE 1-4: PIC18F8XJ90 PIC18F8XJ90 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP Pin Buffer Type Type Description PORTF is a bidirectional I/O port. RF1/AN6/C2OUT/SEG19 RF1/AN6/C2OUT/SEG19 RF1 AN6 C2OUT SEG19 SEG19 23 RF2/AN7/C1OUT/SEG20 RF2/AN7/C1OUT/SEG20 RF2 AN7 C1OUT SEG20 SEG20 18 RF3/AN8/SEG21/C2INB RF3/AN8/SEG21/C2INB RF3 AN8 SEG21 SEG21 C2INB 17 RF4/AN9/SEG22/C2INA RF4/AN9/SEG22/C2INA RF4 AN9 SEG22 SEG22 C2INA 16 RF5/AN10/CVREF/ RF5/AN10/CVREF/ SEG23/C1INB SEG23/C1INB RF5 AN10 CVREF SEG23 SEG23 C1INB 15 RF6/AN11/SEG24/C1INA RF6/AN11/SEG24/C1INA RF6 AN11 SEG24 SEG24 C1INA 14 RF7/AN5/SS/SEG25 RF7/AN5/SS/SEG25 RF7 AN5 SS SEG25 SEG25 13 I/O I O O ST Analog - Analog Digital I/O. Analog input 6. Comparator 2 output. SEG19 SEG19 output for LCD. I/O I O O ST Analog - Analog Digital I/O. Analog input 7. Comparator 1 output. SEG20 SEG20 output for LCD. I/O I O I ST Analog Analog Analog Digital I/O. Analog input 8. SEG21 SEG21 output for LCD. Comparator 2 input B. I/O I O I ST Analog Analog Analog Digital I/O. Analog input 9. SEG22 SEG22 output for LCD. Comparator 2 input A. I/O I O O I ST Analog Analog Analog Analog Digital I/O. Analog input 10. Comparator reference voltage output. SEG23 SEG23 output for LCD. Comparator 1 input B. I/O I O I ST Analog Analog Analog Digital I/O. Analog input 11. SEG24 SEG24 output for LCD. Comparator 1 input A. I/O O I O ST Analog TTL Analog Digital I/O. Analog input 5. SPI slave select input. SEG25 SEG25 output for LCD. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set. 2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared. DS39933C-page 24 Preliminary © 2009 Microchip Technology Inc. PIC18F87J90 PIC18F87J90 FAMILY TABLE 1-4: PIC18F8XJ90 PIC18F8XJ90 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP Pin Buffer Type Type Description PORTG is a bidirectional I/O port. RG0/LCDBIAS0 RG0 LCDBIAS0 5 RG1/TX2/CK2 RG1 TX2 CK2 6 RG2/RX2/DT2/VLCAP1 RG2 RX2 DT2 VLCAP1 7 RG3/VLCAP2 RG3 VLCAP2 8 RG4/SEG26/RTCC RG4/SEG26/RTCC RG4 SEG26 SEG26 RTCC 10 I/O I ST Analog Digital I/O. BIAS0 input for LCD. I/O O I/O ST - ST Digital I/O. AUSART asynchronous transmit. AUSART synchronous clock (see related RX2/DT2). I/O I I/O I ST ST ST Analog Digital I/O. AUSART asynchronous receive. AUSART synchronous data (see related TX2/CK2). LCD charge pump capacitor input. I/O I ST Analog Digital I/O. LCD charge pump capacitor input. I/O O O ST Analog - Digital I/O. SEG26 SEG26 output for LCD. RTCC output. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set. 2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared. © 2009 Microchip Technology Inc. Preliminary DS39933C-page 25 PIC18F87J90 PIC18F87J90 FAMILY TABLE 1-4: PIC18F8XJ90 PIC18F8XJ90 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP Pin Buffer Type Type Description PORTH is a bidirectional I/O port. RH0/SEG47 RH0/SEG47 RH0 SEG47 SEG47 79 RH1/SEG46 RH1/SEG46 RH1 SEG46 SEG46 80 RH2/SEG45 RH2/SEG45 RH2 SEG45 SEG45 1 RH3/SEG44 RH3/SEG44 RH3 SEG44 SEG44 2 RH4/SEG40 RH4/SEG40 RH4 SEG40 SEG40 22 RH5/SEG41 RH5/SEG41 RH5 SEG41 SEG41 21 RH6/SEG42 RH6/SEG42 RH6 SEG42 SEG42 20 RH7/SEG43 RH7/SEG43 RH7 SEG43 SEG43 19 I/O O ST Analog Digital I/O. SEG47 SEG47 output for LCD. I/O O ST Analog Digital I/O. SEG46 SEG46 output for LCD. I/O O ST Analog Digital I/O. SEG45 SEG45 output for LCD. I/O O ST Analog Digital I/O. SEG44 SEG44 output for LCD. I/O O ST Analog Digital I/O. SEG40 SEG40 output for LCD. I/O O ST Analog Digital I/O. SEG41 SEG41 output for LCD. I/O O ST Analog Digital I/O. SEG42 SEG42 output for LCD. I/O O ST Analog Digital I/O. SEG43 SEG43 output for LCD. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set. 2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared. DS39933C-page 26 Preliminary © 2009 Microchip Technology Inc. PIC18F87J90 PIC18F87J90 FAMILY TABLE 1-4: PIC18F8XJ90 PIC18F8XJ90 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP Pin Buffer Type Type Description PORTJ is a bidirectional I/O port. RJ0 62 RJ1/SEG33 RJ1/SEG33 RJ1 SEG33 SEG33 61 RJ2/SEG34 RJ2/SEG34 RJ2 SEG34 SEG34 60 RJ3/SEG35 RJ3/SEG35 RJ3 SEG35 SEG35 59 RJ4/SEG39 RJ4/SEG39 RJ4 SEG39 SEG39 39 RJ5/SEG38 RJ5/SEG38 RJ5 SEG38 SEG38 40 RJ6/SEG37 RJ6/SEG37 RJ6 SEG37 SEG37 41 RJ7/SEG36 RJ7/SEG36 RJ7 SEG36 SEG36 I/O ST Digital I/O. I/O O ST Analog Digital I/O. SEG33 SEG33 output for LCD. I/O O ST Analog Digital I/O. SEG34 SEG34 output for LCD. I/O O ST Analog Digital I/O. SEG35 SEG35 output for LCD. I/O O ST Analog Digital I/O. SEG39 SEG39 output for LCD. I/O O ST Analog Digital I/O SEG38 SEG38 output for LCD. I/O O ST Analog Digital I/O. SEG37 SEG37 output for LCD. 42 I/O O ST Analog Digital I/O. SEG36 SEG36 output for LCD. VSS 11, 31, 51, 70 P - Ground reference for logic and I/O pins. VDD 32, 48, 71 P - Positive supply for logic and I/O pins. AVSS 26 P - Ground reference for analog modules. AVDD 25 P - Positive supply for analog modules. ENVREG 24 I ST VDDCORE/VCAP VDDCORE 12 VCAP P - P - Enable for on-chip voltage regulator. Core logic power or external filter capacitor connection. Positive supply for microcontroller core logic (regulator disabled). External filter capacitor connection (regulator enabled). Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set. 2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared. © 2009 Microchip Technology Inc. Preliminary DS39933C-page 27 PIC18F87J90 PIC18F87J90 FAMILY NOTES: DS39933C-page 28 Preliminary © 2009 Microchip Technology Inc. PIC18F87J90 PIC18F87J90 FAMILY 2.0 OSCILLATOR CONFIGURATIONS 2.1 Oscillator Types All of these modes are selected by the user by programming the FOSC Configuration bits. The PIC18F87J90 PIC18F87J90 family of devices can be operated in eight different oscillator modes: 2. 3. 4. 5. 6. 7. 8. ECPLL OSC1/OSC2 as primary; ECPLL oscillator with PLL enabled, CLKO on RA6 EC OSC1/OSC2 as primary; external clock with FOSC/4 output HSPLL OSC1/OSC2 as primary; high-speed crystal/resonator with software PLL control HS OSC1/OSC2 as primary; high-speed crystal/resonator INTPLL1 Internal oscillator block with software PLL control, FOSC/4 output on RA6 and I/O on RA7 INTIO1 Internal oscillator block with FOSC/4 output on RA6 and I/O on RA7 INTPLL2 Internal oscillator block with software PLL control and I/O on RA6 and RA7 INTIO2 Internal oscillator block with I/O on RA6 and RA7 FIGURE 2-1: The clock sources for the PIC18F87J90 PIC18F87J90 family of devices are shown in Figure 2-1. PIC18F87J90 PIC18F87J90 FAMILY CLOCK DIAGRAM Primary Oscillator HS, EC OSC2 OSCTUNE Sleep HSPLL, ECPLL, INTPLL 4 x PLL OSC1 Secondary Oscillator T1OSC T1OSO OSCCON OSCCON 8 MHz 4 MHz Internal Oscillator Block 8 MHz (INTOSC) Postscaler 8 MHz Source 2 MHz 1 MHz 500 kHz 250 kHz 125 kHz Internal Oscillator 110 IDLEN 101 100 011 010 001 1 31 kHz 000 0 INTRC Source © 2009 Microchip Technology Inc. 31 kHz (INTRC) CPU 111 MUX T1OSI T1OSCEN Enable Oscillator Peripherals MUX 1. In addition, PIC18F87J90 PIC18F87J90 family devices can switch between different clock sources, either under software control or automatically under certain conditions. This allows for additional power savings by managing device clock speed in real time without resetting the application. Clock Control FOSC OSCCON Clock Source Option for Other Modules OSCTUNE WDT, PWRT, FSCM and Two-Speed Start-up Preliminary DS39933C-page 29 PIC18F87J90 PIC18F87J90 FAMILY 2.2 Control Registers The OSCTUNE register (Register 2-2) controls the tuning and operation of the internal oscillator block. It also implements the PLLEN bits which control the operation of the Phase Locked Loop (PLL) (see Section 2.4.3 "PLL Frequency Multiplier"). The OSCCON register (Register 2-1) controls the main aspects of the device clock's operation. It selects the oscillator type to be used, which of the power-managed modes to invoke and the output frequency of the INTOSC source. It also provides status on the oscillators. OSCCON: OSCILLATOR CONTROL REGISTER(1) REGISTER 2-1: R/W-0 R/W-1 IDLEN IRCF2(3) R/W-1 (3) IRCF1 R(2) R/W-0 IRCF0 (3) OSTS R-0 IOFS R/W-0 SCS1 (5) R/W-0 SCS0(5) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7 IDLEN: Idle Enable bit 1 = Device enters an Idle mode when a SLEEP instruction is executed 0 = Device enters Sleep mode when a SLEEP instruction is executed bit 6-4 IRCF: INTOSC Source Frequency Select bits(3) 111 = 8 MHz (INTOSC drives clock directly) 110 = 4 MHz (default) 101 = 2 MHz 100 = 1 MHz 011 = 500 kHz 010 = 250 kHz 001 = 125 kHz 000 = 31 kHz (from either INTOSC/256 INTOSC/256 or INTRC)(4) bit 3 OSTS: Oscillator Start-up Timer Time-out Status bit(2) 1 = Oscillator Start-up Timer (OST) time-out has expired; primary oscillator is running 0 = Oscillator Start-up Timer (OST) time-out is running; primary oscillator is not ready bit 2 IOFS: INTOSC Frequency Stable bit 1 = Fast RC oscillator frequency is stable 0 = Fast RC oscillator frequency is not stable bit 1-0 SCS: System Clock Select bits(5) 11 = Internal oscillator block 10 = Primary oscillator 01 = Timer1 oscillator 00 = Default primary oscillator (as defined by FOSC Configuration bits) Note 1: 2: 3: 4: 5: Default (legacy) SFR at this address; available when WDTCON = 0. Reset state depends on state of the IESO Configuration bit. Modifying these bits will cause an immediate clock frequency switch if the internal oscillator is providing the device clocks. Source selected by the INTSRC bit (OSCTUNE), see text. Modifying these bits will cause an immediate clock source switch. DS39933C-page 30 Preliminary © 2009 Microchip Technology Inc. PIC18F87J90 PIC18F87J90 FAMILY REGISTER 2-2: OSCTUNE: OSCILLATOR TUNING REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 INTSRC PLLEN TUN5 TUN4 TUN3 TUN2 TUN1 TUN0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7 INTSRC: Internal Oscillator Low-Frequency Source Select bit 1 = 31.25 kHz device clock derived from 8 MHz INTOSC source (divide-by-256 enabled) 0 = 31 kHz device clock derived from INTRC 31 kHz oscillator bit 6 PLLEN: Frequency Multiplier PLL Enable bit 1 = PLL enabled 0 = PLL disabled bit 5-0 TUN: Fast RC Oscillator (INTOSC) Frequency Tuning bits 011111 = Maximum frequency · · · · 000001 000000 = Center frequency. Fast RC oscillator is running at the calibrated frequency. 111111 · · · · 100000 = Minimum frequency 2.3 Clock Sources and Oscillator Switching Essentially, PIC18F87J90 PIC18F87J90 family devices have three independent clock sources: · Primary oscillators · Secondary oscillators · Internal oscillator The primary oscillators can be thought of as the main device oscillators. These are any external oscillators connected to the OSC1 and OSC2 pins, and include the External Crystal and Resonator modes and the External Clock modes. If selected by the FOSC Configuration bits, the internal oscillator block (either the 31 kHz INTRC or the 8 MHz INTOSC source) may be considered a primary oscillator. The particular mode is defined by the FOSC Configuration bits. The details of these modes are covered in Section 2.4 "External Oscillator Modes". functions such as a Real-Time Clock (RTC). The Timer1 oscillator is discussed in greater detail in Section 11.0 "Timer1 Module". In addition to being a primary clock source in some circumstances, the internal oscillator is available as a power-managed mode clock source. The INTRC source is also used as the clock source for several special features, such as the WDT and Fail-Safe Clock Monitor. The internal oscillator block is discussed in more detail in Section 2.5 "Internal Oscillator Block". The PIC18F87J90 PIC18F87J90 family includes features that allow the device clock source to be switched from the main oscillator, chosen by device configuration, to one of the alternate clock sources. When an alternate clock source is enabled, various power-managed operating modes are available. The secondary oscillators are external clock sources that are not connected to the OSC1 or OSC2 pins. These sources may continue to operate even after the controller is placed in a power-managed mode. PIC18F87J90 PIC18F87J90 family devices offer the Timer1 oscillator as a secondary oscillator source. This oscillator, in all power-managed modes, is often the time base for © 2009 Microchip Technology Inc. Preliminary DS39933C-page 31 PIC18F87J90 PIC18F87J90 FAMILY 2.3.1 CLOCK SOURCE SELECTION 2.3.1.1 The System Clock Select bits, SCS0 (OSCCON), select the clock source. The available clock sources are the primary clock defined by the FOSC Configuration bits, the secondary clock (Timer1 oscillator) and the internal oscillator. The clock source changes after one or more of the bits is written to, following a brief clock transition interval. The OSTS (OSCCON) and T1RUN (T1CON) bits indicate which clock source is currently providing the device clock. The OSTS bit indicates that the Oscillator Start-up Timer (OST) has timed out and the primary clock is providing the device clock in primary clock modes. The T1RUN bit indicates when the Timer1 oscillator is providing the device clock in secondary clock modes. In power-managed modes, only one of these bits will be set at any time. If neither of these bits is set, the INTRC is providing the clock, or the internal oscillator has just started and is not yet stable. The IDLEN bit determines if the device goes into Sleep mode or one of the Idle modes when the SLEEP instruction is executed. The use of the flag and control bits in the OSCCON register is discussed in more detail in Section 3.0 "Power-Managed Modes". Note 1: The Timer1 oscillator must be enabled to select the secondary clock source. The Timer1 oscillator is enabled by setting the T1OSCEN bit in the Timer1 Control register (T1CON). If the Timer1 oscillator is not enabled, then any attempt to select a secondary clock source when executing a SLEEP instruction will be ignored. 2: It is recommended that the Timer1 oscillator be operating and stable before executing the SLEEP instruction or a very long delay may occur while the Timer1 oscillator starts. DS39933C-page 32 System Clock Selection and Device Resets Since the SCS bits are cleared on all forms of Reset, this means the primary oscillator defined by the FOSC Configuration bits is used as the primary clock source on device Resets. This could either be the internal oscillator block by itself, or one of the other primary clock source (HS, EC, HSPLL, ECPLL1/2 or INTPLL1/2). In those cases when the internal oscillator block, without PLL, is the default clock on Reset, the Fast RC oscillator (INTOSC) will be used as the device clock source. It will initially start at 1 MHz, the postscaler selection that corresponds to the Reset value of the IRCF bits (`100'). Regardless of which primary oscillator is selected, INTRC will always be enabled on device power-up. It serves as the clock source until the device has loaded its configuration values from memory. It is at this point that the FOSC Configuration bits are read and the oscillator selection of the operational mode is made. Note that either the primary clock source, or the internal oscillator, will have two bit setting options for the possible values of the SCS bits at any given time. 2.3.2 OSCILLATOR TRANSITIONS PIC18F87J90 PIC18F87J90 family devices contain circuitry to prevent clock "glitches" when switching between clock sources. A short pause in the device clock occurs during the clock switch. The length of this pause is the sum of two cycles of the old clock source and three to four cycles of the new clock source. This formula assumes that the new clock source is stable. Clock transitions are discussed in greater detail in Section 3.1.2 "Entering Power-Managed Modes". Preliminary © 2009 Microchip Technology Inc. PIC18F87J90 PIC18F87J90 FAMILY 2.4 TABLE 2-2: External Oscillator Modes 2.4.1 CRYSTAL OSCILLATOR/CERAMIC RESONATORS (HS MODES) In HS or HSPLL Oscillator modes, a crystal or ceramic resonator is connected to the OSC1 and OSC2 pins to establish oscillation. Figure 2-2 shows the pin connections. The oscillator design requires the use of a crystal rated for parallel resonant operation. Note: Use of a crystal rated for series resonant operation may give a frequency out of the crystal manufacturer's specifications. TABLE 2-1: CAPACITOR SELECTION FOR CERAMIC RESONATORS Typical Capacitor Values Used: Mode Freq. OSC1 8.0 MHz 16.0 MHz 27 pF 22 pF 27 pF 22 pF Typical Capacitor Values Tested: Crystal Freq. Osc Type C1 4 MHz 27 pF 27 pF 8 MHz 22 pF 22 pF 20 MHz HS C2 15 pF 15 pF Capacitor values are for design guidance only. Different capacitor values may be required to produce acceptable oscillator operation. The user should test the performance of the oscillator over the expected VDD and temperature range for the application. Refer to the Microchip application notes cited in Table 2-1 for oscillator specific information. Also see the notes following this table for additional information. OSC2 HS CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR Capacitor values are for design guidance only. Note 1: Higher capacitance increases the stability of oscillator but also increases the start-up time. 2: Since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropriate values of external components. Different capacitor values may be required to produce acceptable oscillator operation. The user should test the performance of the oscillator over the expected VDD and temperature range for the application. Refer to the following application notes for oscillator specific information: · AN588 AN588, "PIC® Microcontroller Oscillator Design Guide" · AN826 AN826, "Crystal Oscillator Basics and Crystal Selection for rfPIC® and PIC® Devices" · AN849 AN849, "Basic PIC® Oscillator Design" · AN943 AN943, "Practical PIC® Oscillator Analysis and Design" · AN949 AN949, "Making Your Oscillator Work" 3: Rs may be required to avoid overdriving crystals with low drive level specification. 4: Always verify oscillator performance over the VDD and temperature range that is expected for the application. FIGURE 2-2: See the notes following Table 2-2 for additional information. CRYSTAL/CERAMIC RESONATOR OPERATION (HS OR HSPLL CONFIGURATION) C1(1) OSC1 XTAL RF(3) OSC2 C2(1) RS(2) To Internal Logic Sleep PIC18F87J90 PIC18F87J90 Note 1: 2: A series resistor (RS) may be required for AT strip cut crystals. 3: © 2009 Microchip Technology Inc. See Table 2-1 and Table 2-2 for initial values of C1 and C2. RF varies with the oscillator mode chosen. Preliminary DS39933C-page 33 PIC18F87J90 PIC18F87J90 FAMILY 2.4.2 EXTERNAL CLOCK INPUT (EC MODES) 2.4.3.1 The EC and ECPLL Oscillator modes require an external clock source to be connected to the OSC1 pin. There is no oscillator start-up time required after a Power-on Reset or after an exit from Sleep mode. In the EC Oscillator mode, the oscillator frequency divided by 4 is available on the OSC2 pin. This signal may be used for test purposes or to synchronize other logic. Figure 2-3 shows the pin connections for the EC Oscillator mode. FIGURE 2-3: EXTERNAL CLOCK INPUT OPERATION (EC CONFIGURATION) HSPLL and ECPLL Modes The HSPLL and ECPLL modes provide the ability to selectively run the device at 4 times the external oscillating source to produce frequencies up to 40 MHz. The PLL is enabled by programming the FOSC Configuration bits to either `111' (for ECPLL) or `101' (for HSPLL). In addition, the PLLEN bit (OSCTUNE) must also be set. Clearing PLLEN disables the PLL, regardless of the chosen oscillator configuration. It also allows additional flexibility for controlling the application's clock speed in software. FIGURE 2-5: PLL BLOCK DIAGRAM HSPLL or ECPLL (CONFIG2L) PLL Enable (OSCTUNE) OSC1/CLKI Clock from Ext. System PIC18F87J90 PIC18F87J90 FOSC/4 OSC2 OSC2/CLKO HS or EC Mode OSC1 An external clock source may also be connected to the OSC1 pin in the HS mode, as shown in Figure 2-4. In this configuration, the divide-by-4 output on OSC2 is not available. Current consumption in this configuration will be somewhat higher than EC mode, as the internal oscillator's feedback circuitry will be enabled (in EC mode, the feedback circuit is disabled). FIGURE 2-4: FOUT Loop Filter VCO MUX ÷4 SYSCLK EXTERNAL CLOCK INPUT OPERATION (HS OSC CONFIGURATION) 2.4.3.2 PIC18F87J90 PIC18F87J90 (HS Mode) Open PLL and INTOSC The PLL is also available to the internal oscillator block when the internal oscillator block is configured as the primary clock source. In this configuration, the PLL is enabled in software and generates a clock output of up to 32 MHz. The operation of INTOSC with the PLL is described in Section 2.5.2 "INTPLL Modes". OSC1 Clock from Ext. System 2.4.3 Phase Comparator FIN OSC2 PLL FREQUENCY MULTIPLIER A Phase Locked Loop (PLL) circuit is provided as an option for users who want to use a lower frequency oscillator circuit, or to clock the device up to its highest rated frequency from a crystal oscillator. This may be useful for customers who are concerned with EMI due to high-frequency crystals, or users who require higher clock speeds from an internal oscillator. DS39933C-page 34 Preliminary © 2009 Microchip Technology Inc. PIC18F87J90 PIC18F87J90 FAMILY 2.5 FIGURE 2-6: Internal Oscillator Block The PIC18F87J90 PIC18F87J90 family of devices includes an internal oscillator block which generates two different clock signals; either can be used as the microcontroller's clock source. This may eliminate the need for an external oscillator circuit on the OSC1 and/or OSC2 pins. The main output is the Fast RC oscillator, or INTOSC, an 8 MHz clock source which can be used to directly drive the device clock. It also drives a postscaler, which can provide a range of clock frequencies from 31 kHz to 4 MHz. INTOSC is enabled when a clock frequency from 125 kHz to 8 MHz is selected. The INTOSC output can also be enabled when 31 kHz is selected, depending on the INTSRC bit (OSCTUNE). The other clock source is the internal RC oscillator (INTRC), which provides a nominal 31 kHz output. INTRC is enabled if it is selected as the device clock source; it is also enabled automatically when any of the following are enabled: · · · · Power-up Timer Fail-Safe Clock Monitor Watchdog Timer Two-Speed Start-up These features are discussed in greater detail in Section 24.0 "Special Features of the CPU". The clock source frequency (INTOSC direct, INTOSC with postscaler or INTRC direct) is selected by configuring the IRCF bits of the OSCCON register. The default frequency on device Resets is 4 MHz. 2.5.1 INTIO MODES Using the internal oscillator as the clock source eliminates the need for up to two external oscillator pins, which can then be used for digital I/O. Two distinct oscillator configurations, which are determined by the FOSC Configuration bits, are available: · In INTIO1 mode, the OSC2 pin outputs FOSC/4, while OSC1 functions as RA7 (see Figure 2-6) for digital input and output. · In INTIO2 mode, OSC1 functions as RA7 and OSC2 functions as RA6 (see Figure 2-7), both for digital input and output. © 2009 Microchip Technology Inc. INTIO1 OSCILLATOR MODE I/O (OSC1) RA7 PIC18F87J90 PIC18F87J90 OSC2 FOSC/4 FIGURE 2-7: RA7 INTIO2 OSCILLATOR MODE I/O (OSC1) PIC18F87J90 PIC18F87J90 RA6 2.5.2 I/O (OSC2) INTPLL MODES The 4x Phase Locked Loop (PLL) can be used with the internal oscillator block to produce faster device clock speeds than are normally possible with the internal oscillator sources. When enabled, the PLL produces a clock speed of 16 MHz or 32 MHz. PLL operation is controlled through software. The control bit, PLLEN (OSCTUNE), is used to enable or disable its operation. The PLL is available only to INTOSC when the device is configured to use one of the INTPLL modes as the primary clock source (FOSC = 011 or 001). Additionally, the PLL will only function when the selected output frequency is either 4 MHz or 8 MHz (OSCCON = 111 or 110). Like the INTIO modes, there are two distinct INTPLL modes available: · In INTPLL1 mode, the OSC2 pin outputs FOSC/4, while OSC1 functions as RA7 for digital input and output. Externally, this is identical in appearance to INTIO1 (Figure 2-6). · In INTPLL2 mode, OSC1 functions as RA7 and OSC2 functions as RA6, both for digital input and output. Externally, this is identical to INTIO2 (Figure 2-7). Preliminary DS39933C-page 35 PIC18F87J90 PIC18F87J90 FAMILY 2.5.3 INTERNAL OSCILLATOR OUTPUT FREQUENCY AND TUNING The internal oscillator block is calibrated at the factory to produce an INTOSC output frequency of 8 MHz. It can be adjusted in the user's application by writing to TUN (OSCTUNE) in the OSCTUNE register (Register 2-2). When the OSCTUNE register is modified, the INTOSC frequency will begin shifting to the new frequency. The oscillator will stabilize within 1 ms. Code execution continues during this shift and there is no indication that the shift has occurred. The INTRC oscillator operates independently of the INTOSC source. Any changes in INTOSC across voltage and temperature are not necessarily reflected by changes in INTRC or vice versa. The frequency of INTRC is not affected by OSCTUNE. 2.5.4 INTOSC FREQUENCY DRIFT The INTOSC frequency may drift as VDD or temperature changes, and can affect the controller operation in a variety of ways. It is possible to adjust the INTOSC frequency by modifying the value in the OSCTUNE register. Depending on the device, this may have no effect on the INTRC clock source frequency. Tuning INTOSC requires knowing when to make the adjustment, in which direction it should be made, and in some cases, how large a change is needed. Three compensation techniques are shown here. 2.5.4.1 Compensating with the EUSART An adjustment may be required when the EUSART begins to generate framing errors or receives data with errors while in Asynchronous mode. Framing errors indicate that the device clock frequency is too high. To adjust for this, decrement the value in OSCTUNE to reduce the clock frequency. On the other hand, errors in data may suggest that the clock speed is too low. To compensate, increment OSCTUNE to increase the clock frequency. DS39933C-page 36 2.5.4.2 Compensating with the Timers This technique compares device clock speed to some reference clock. Two timers may be used; one timer is clocked by the peripheral clock, while the other is clocked by a fixed reference source, such as the Timer1 oscillator. Both timers are cleared, but the timer clocked by the reference generates interrupts. When an interrupt occurs, the internally clocked timer is read and both timers are cleared. If the internally clocked timer value is much greater than expected, then the internal oscillator block is running too fast. To adjust for this, decrement the OSCTUNE register. 2.5.4.3 Compensating with the CCP Module in Capture Mode A CCP module can use free-running Timer1 (or Timer3), clocked by the internal oscillator block and an external event with a known period (i.e., AC power frequency). The time of the first event is captured in the CCPRxH:CCPRxL registers and is recorded for use later. When the second event causes a capture, the time of the first event is subtracted from the time of the second event. Since the period of the external event is known, the time difference between events can be calculated. If the measured time is much greater than the calculated time, the internal oscillator block is running too fast. To compensate, decrement the OSCTUNE register. If the measured time is much less than the calculated time, the internal oscillator block is running too slow. To compensate, increment the OSCTUNE register. Preliminary © 2009 Microchip Technology Inc. PIC18F87J90 PIC18F87J90 FAMILY 2.6 Effects of Power-Managed Modes on the Various Clock Sources When PRI_IDLE mode is selected, the designated primary oscillator continues to run without interruption. For all other power-managed modes, the oscillator using the OSC1 pin is disabled. The OSC1 pin (and OSC2 pin if used by the oscillator) will stop oscillating. In secondary clock modes (SEC_RUN and SEC_IDLE), the Timer1 oscillator is operating and providing the device clock. The Timer1 oscillator may also run in all power-managed modes if required to clock Timer1 or Timer3. In RC_RUN and RC_IDLE modes, the internal oscillator provides the device clock source. The 31 kHz INTRC output can be used directly to provide the clock and may be enabled to support various special features, regardless of the power-managed mode (see Section 24.2 "Watchdog Timer (WDT)" through Section 24.5 "Fail-Safe Clock Monitor" for more information on WDT, Fail-Safe Clock Monitor and Two-Speed Start-up). If the Sleep mode is selected, all clock sources are stopped. Since all the transistor switching currents have been stopped, Sleep mode achieves the lowest current consumption of the device (only leakage currents). Enabling any on-chip feature that will operate during Sleep will increase the current consumed during Sleep. The INTRC is required to support WDT operation. The TABLE 2-3: Timer1 oscillator may be operating to support a RealTime Clock (RTC). Other features may be operating that do not require a device clock source (i.e., MSSP slave, INTx pins and others). Peripherals that may add significant current consumption are listed in Section 27.2 "DC Characteristics: Power-Down and Supply Current PIC18F87J90 PIC18F87J90 Family (Industrial)". 2.7 Power-up Delays Power-up delays are controlled by two timers, so that no external Reset circuitry is required for most applications. The delays ensure that the device is kept in Reset until the device power supply is stable under normal circumstances and the primary clock is operating and stable. For additional information on power-up delays, see Section 4.6 "Power-up Timer (PWRT)". The first timer is the Power-up Timer (PWRT), which provides a fixed delay on power-up (parameter 33, Table 27-11); it is always enabled. The second timer is the Oscillator Start-up Timer (OST), intended to keep the chip in Reset until the crystal oscillator is stable (HS modes). The OST does this by counting 1024 oscillator cycles before allowing the oscillator to clock the device. There is a delay of interval TCSD (parameter 38, Table 27-11), following POR, while the controller becomes ready to execute instructions. OSC1 AND OSC2 PIN STATES IN SLEEP MODE Oscillator Mode OSC1 Pin OSC2 Pin EC, ECPLL Floating, pulled by external clock At logic low (clock/4 output) HS, HSPLL Feedback inverter disabled at quiescent voltage level Feedback inverter disabled at quiescent voltage level INTOSC, INTPLL1/2 I/O pin RA6, direction controlled by TRISA I/O pin RA6, direction controlled by TRISA Note: See Section 4.0 "Reset" for time-outs due to Sleep and MCLR Reset. © 2009 Microchip Technology Inc. Preliminary DS39933C-page 37 PIC18F87J90 PIC18F87J90 FAMILY NOTES: DS39933C-page 38 Preliminary © 2009 Microchip Technology Inc. PIC18F87J90 PIC18F87J90 FAMILY 3.0 POWER-MANAGED MODES 3.1.1 CLOCK SOURCES The PIC18F87J90 PIC18F87J90 family devices provide the ability to manage power consumption by simply managing clocking to the CPU and the peripherals. In general, a lower clock frequency and a reduction in the number of circuits being clocked constitutes lower consumed power. For the sake of managing power in an application, there are three primary modes of operation: The SCS bits allow the selection of one of three clock sources for power-managed modes. They are: · Run mode · Idle mode · Sleep mode 3.1.2 These modes define which portions of the device are clocked and at what speed. The Run and Idle modes may use any of the three available clock sources (primary, secondary or internal oscillator block); the Sleep mode does not use a clock source. The power-managed modes include several power-saving features offered on previous PIC® devices. One is the clock switching feature, offered in other PIC18 PIC18 devices, allowing the controller to use the Timer1 oscillator in place of the primary oscillator. Also included is the Sleep mode, offered by all PIC devices, where all device clocks are stopped. 3.1 Selecting Power-Managed Modes Selecting a power-managed mode requires two decisions: if the CPU is to be clocked or not and which clock source is to be used. The IDLEN bit (OSCCON) controls CPU clocking, while the SCS bits (OSCCON) select the clock source. The individual modes, bit settings, clock sources and affected modules are summarized in Table 3-1. TABLE 3-1: · the primary clock, as defined by the FOSC Configuration bits · the secondary clock (Timer1 oscillator) · the internal oscillator ENTERING POWER-MANAGED MODES Switching from one power-managed mode to another begins by loading the OSCCON register. The SCS bits select the clock source and determine which Run or Idle mode is to be used. Changing these bits causes an immediate switch to the new clock source, assuming that it is running. The switch may also be subject to clock transition delays. These are discussed in Section 3.1.3 "Clock Transitions and Status Indicators" and subsequent sections. Entry to the power-managed Idle or Sleep modes is triggered by the execution of a SLEEP instruction. The actual mode that results depends on the status of the IDLEN bit. Depending on the current mode and the mode being switched to, a change to a power-managed mode does not always require setting all of these bits. Many transitions may be done by changing the oscillator select bits, or changing the IDLEN bit, prior to issuing a SLEEP instruction. If the IDLEN bit is already configured correctly, it may only be necessary to perform a SLEEP instruction to switch to the desired mode. POWER-MANAGED MODES OSCCON bits Mode (1) IDLEN Module Clocking Available Clock and Oscillator Source SCS CPU Peripherals 0 N/A Off Off PRI_RUN N/A 10 Clocked Clocked Primary ­ HS, EC, HSPLL, ECPLL; this is the normal full power execution mode SEC_RUN N/A 01 Clocked Clocked Secondary ­ Timer1 Oscillator RC_RUN N/A 11 Clocked Clocked Internal Oscillator PRI_IDLE 1 10 Off Clocked Primary ­ HS, EC, HSPLL, ECPLL SEC_IDLE 1 01 Off Clocked Secondary ­ Timer1 Oscillator RC_IDLE 1 11 Off Clocked Internal Oscillator Sleep Note 1: None ­ All clocks are disabled IDLEN reflects its value when the SLEEP instruction is executed. © 2009 Microchip Technology Inc. Preliminary DS39933C-page 39 PIC18F87J90 PIC18F87J90 FAMILY 3.1.3 CLOCK TRANSITIONS AND STATUS INDICATORS The length of the transition between clock sources is the sum of two cycles of the old clock source and three to four cycles of the new clock source. This formula assumes that the new clock source is stable. Two bits indicate the current clock source and its status: OSTS (OSCCON) and T1RUN (T1CON). In general, only one of these bits will be set while in a given power-managed mode. When the OSTS bit is set, the primary clock is providing the device clock. When the T1RUN bit is set, the Timer1 oscillator is providing the clock. If neither of these bits is set, INTRC is clocking the device. Note: 3.1.4 Executing a SLEEP instruction does not necessarily place the device into Sleep mode. It acts as the trigger to place the controller into either the Sleep mode, or one of the Idle modes, depending on the setting of the IDLEN bit. MULTIPLE SLEEP COMMANDS The power-managed mode that is invoked with the SLEEP instruction is determined by the setting of the IDLEN bit at the time the instruction is executed. If another SLEEP instruction is executed, the device will enter the power-managed mode specified by IDLEN at that time. If IDLEN has changed, the device will enter the new power-managed mode specified by the new setting. DS39933C-page 40 3.2 Run Modes In the Run modes, clocks to both the core and peripherals are active. The difference between these modes is the clock source. 3.2.1 PRI_RUN MODE The PRI_RUN mode is the normal, full power execution mode of the microcontroller. This is also the default mode upon a device Reset unless Two-Speed Start-up is enabled (see Section 24.4 "Two-Speed Start-up" for details). In this mode, the OSTS bit is set (see Section 2.2 "Control Registers"). 3.2.2 SEC_RUN MODE The SEC_RUN mode is the compatible mode to the "clock switching" feature offered in other PIC18 PIC18 devices. In this mode, the CPU and peripherals are clocked from the Timer1 oscillator. This gives users the option of lower power consumption while still using a high-accuracy clock source. SEC_RUN mode is entered by setting the SCS bits to `01'. The device clock source is switched to the Timer1 oscillator (see Figure 3-1), the primary oscillator is shut down, the T1RUN bit (T1CON) is set and the OSTS bit is cleared. Note: Preliminary The Timer1 oscillator should already be running prior to entering SEC_RUN mode. If the T1OSCEN bit is not set when the SCS bits are set to `01', entry to SEC_RUN mode will not occur. If the Timer1 oscillator is enabled, but not yet running, device clocks will be delayed until the oscillator has started. In such situations, initial oscillator operation is far from stable and unpredictable operation may result. © 2009 Microchip Technology Inc. PIC18F87J90 PIC18F87J90 FAMILY On transitions from SEC_RUN mode to PRI_RUN mode, the peripherals and CPU continue to be clocked from the Timer1 oscillator while the primary clock is started. When the primary clock becomes ready, a clock switch back to the primary clock occurs (see FIGURE 3-1: Figure 3-2). When the clock switch is complete, the T1RUN bit is cleared, the OSTS bit is set and the primary clock is providing the clock. The IDLEN and SCS bits are not affected by the wake-up; the Timer1 oscillator continues to run. TRANSITION TIMING FOR ENTRY TO SEC_RUN MODE Q1 Q2 Q3 Q4 Q1 Q2 1 T1OSI 2 3 n-1 Q3 Q4 Q1 Q2 Q3 n Clock Transition OSC1 CPU Clock Peripheral Clock Program Counter PC FIGURE 3-2: PC + 2 PC + 4 TRANSITION TIMING FROM SEC_RUN MODE TO PRI_RUN MODE (HSPLL) Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 T1OSI OSC1 TOST(1) TPLL(1) 1 PLL Clock Output 2 n-1 n Clock Transition CPU Clock Peripheral Clock Program Counter SCS bits Changed PC + 2 PC PC + 4 OSTS bit Set Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale. © 2009 Microchip Technology Inc. Preliminary DS39933C-page 41 PIC18F87J90 PIC18F87J90 FAMILY 3.2.3 RC_RUN MODE On transitions from RC_RUN mode to PRI_RUN mode, the device continues to be clocked from the INTRC while the primary clock is started. When the primary clock becomes ready, a clock switch to the primary clock occurs (see Figure 3-4). When the clock switch is complete, the OSTS bit is set and the primary clock is providing the device clock. The IDLEN and SCS bits are not affected by the switch. The INTRC source will continue to run if either the WDT or the Fail-Safe Clock Monitor is enabled. In RC_RUN mode, the CPU and peripherals are clocked from the internal oscillator; the primary clock is shut down. This mode provides the best power conservation of all the Run modes while still executing code. It works well for user applications which are not highly timing sensitive or do not require high-speed clocks at all times. This mode is entered by setting SCS bits to `11'. When the clock source is switched to the INTRC (see Figure 3-3), the primary oscillator is shut down and the OSTS bit is cleared. FIGURE 3-3: TRANSITION TIMING TO RC_RUN MODE Q1 Q2 Q3 Q4 Q1 Q2 1 INTRC 2 3 n-1 Q3 Q4 Q1 Q2 Q3 n Clock Transition OSC1 CPU Clock Peripheral Clock Program Counter FIGURE 3-4: PC PC + 2 PC + 4 TRANSITION TIMING FROM RC_RUN MODE TO PRI_RUN MODE Q1 Q2 Q3 Q4 Q2 Q3 Q4 Q1 Q2 Q3 Q1 INTRC OSC1 TOST(1) TPLL(1) 1 PLL Clock Output 2 n-1 n Clock Transition CPU Clock Peripheral Clock Program Counter PC + 2 PC SCS bits Changed PC + 4 OSTS bit Set Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale. DS39933C-page 42 Preliminary © 2009 Microchip Technology Inc. PIC18F87J90 PIC18F87J90 FAMILY 3.3 Sleep Mode 3.4 The power-managed Sleep mode is identical to the legacy Sleep mode offered in all other PIC devices. It is entered by clearing the IDLEN bit (the default state on device Reset) and executing the SLEEP instruction. This shuts down the selected oscillator (Figure 3-5). All clock source status bits are cleared. Idle Modes The Idle modes allow the controller's CPU to be selectively shut down while the peripherals continue to operate. Selecting a particular Idle mode allows users to further manage power consumption. If the IDLEN bit is set to a `1' when a SLEEP instruction is executed, the peripherals will be clocked from the clock source selected using the SCS bits; however, the CPU will not be clocked. The clock source status bits are not affected. Setting IDLEN and executing a SLEEP instruction provides a quick method of switching from a given Run mode to its corresponding Idle mode. Entering the Sleep mode from any other mode does not require a clock switch. This is because no clocks are needed once the controller has entered Sleep. If the WDT is selected, the INTRC source will continue to operate. If the Timer1 oscillator is enabled, it will also continue to run. If the WDT is selected, the INTRC source will continue to operate. If the Timer1 oscillator is enabled, it will also continue to run. When a wake event occurs in Sleep mode (by interrupt, Reset or WDT time-out), the device will not be clocked until the clock source selected by the SCS bits becomes ready (see Figure 3