PIC18F87J10 DS39663F PIC18F65J10 PIC18F65J15 PIC18F66J10 PIC18F66J15 - Datasheet Archive
PIC18F87J10 Family Rev. A4 Silicon Errata The PIC18F87J10 family parts you have received conform functionally to the Device Data
PIC18F87J10 PIC18F87J10 FAMILY PIC18F87J10 PIC18F87J10 Family Rev. A4 Silicon Errata The PIC18F87J10 PIC18F87J10 family parts you have received conform functionally to the Device Data Sheet (DS39663F DS39663F), except for the anomalies described below. Any Data Sheet Clarification issues related to the PIC18F87J10 PIC18F87J10 family will be reported in a separate Data Sheet errata. Please check the Microchip web site for any existing issues. The following silicon errata apply only to PIC18F87J10 PIC18F87J10 family devices with these Device/ Revision IDs: Part Number Device ID Revision ID PIC18F65J10 PIC18F65J10 0001 0101 001 0 0101 PIC18F65J15 PIC18F65J15 0001 0101 010 0 0101 PIC18F66J10 PIC18F66J10 0001 0101 011 0 0101 PIC18F66J15 PIC18F66J15 0001 0101 100 0 0101 PIC18F67J10 PIC18F67J10 0001 0101 101 0 0101 PIC18F85J10 PIC18F85J10 0001 0101 111 0 0101 PIC18F85J15 PIC18F85J15 0001 0111 000 0 0101 PIC18F86J10 PIC18F86J10 0001 0111 001 0 0101 PIC18F86J15 PIC18F86J15 0001 0111 010 0 0101 PIC18F87J10 PIC18F87J10 0001 0111 011 0 0101 The Device IDs (DEVID1 and DEVID2) are located at addresses 3FFFFEh:3FFFFFh in the device's configuration space. They are shown in hexadecimal in the format "DEVID2 DEVID1". 2. Module: External Memory Bus For PIC18F8XJXX PIC18F8XJXX devices, the Stack Pointer may incorrectly increment during a table read operation if the external memory bus wait states are enabled. This is when: · The Configuration bit, WAIT, is clear (CONFIG3L = 0) · The WAITx bits (MEMCON) are not equal to `11' Work around If using the external memory bus and performing TBLRD operations with a non-zero wait state described by the preceding two bullet points first disable interrupts by clearing the GIE/GIEH (INTCON) and PEIE/GIEL (INTCON) bits. Date Codes that pertain to this issue: All engineering and production devices. 3. Module: External Memory Bus The A EMB address lines and read/write control pins (OE, WRH and WRL) are released to their respective inactive states at the same time which violates the timing condition mentioned in Figure 27-5 and Figure 27-6 in the data sheet. Writes to program memory address 300000h, that are not blocked, can cause the program memory at different locations to be corrupted. This may result in the peripheral device on the bus detecting an address change when write/read is initiated. The bus capacitance and signal delay on the address and control lines can affect the probability of invalid detection. Work around Work around Do not write to address 300000h. If you wish to modify the contents of the Configuration registers, then modify the Configuration Words located at the end of the user memory and issue a Reset command. This will reload the Configuration registers with the new configuration setting. Do one of the following: 1. Module: Flash Program Memory The end of the user memory is: · PIC18FX5J10 PIC18FX5J10 devices 7FF4h · PIC18FX5J10 PIC18FX5J10 devices 3FF4h For additional information, see the Device Data Sheet (DS39663 DS39663), Section 24.1 "Configuration Bits". · Use a latch based on the falling edge of ALE to hold the A signals. · Add a delay circuit to extend the valid time for A signals to ensure the address is valid until read/write signals go inactive. Date Codes that pertain to this issue: All engineering and production devices. Date Codes that pertain to this issue: All engineering and production devices. 2010 Microchip Technology Inc. DS80340B-page 1 PIC18F87J10 PIC18F87J10 FAMILY 4. Module: Timer1 Work around Before disabling the MSSP module, ensure that: In 16-Bit Asynchronous Counter mode (with or without use of the Timer1 oscillator), the TMR1H and TMR3H buffers do not update when TMRxL is read. · WCOL is clear · If the buffer is full, SSPxBUF is read (thus clearing the BF flag) · If the module was configured in SPI Slave mode, the SSPOV bit is clear This issue only affects reading the TMRxH registers. The timers increment and set the interrupt flags as expected and the Timer registers can be written as expected. Date Codes that pertain to this issue: All engineering and production devices. Work around 1. Use 8-bit mode by clearing the RD16 bit (T1CON). 2. Use the internal clock synchronization option by clearing the T1SYNC bit (T1CON). 6. Module: Master Synchronous Serial Port (MSSP) In its current implementation, the Baud Rate Generator for I2CTM in Master mode is slower than the rates specified in Table 19-3 of the Device Data Sheet. Date Codes that pertain to this issue: All engineering and production devices. For this revision of silicon: 5. Module: Master Synchronous Serial Port (MSSP) · For the I2CTM clock rates use the values shown in Table 1 in place of those shown in Table 19-3 of the Device Data Sheet. (The differences are shown in bold text.) · For bit description, SSPM = 1000, use the following formula in place of the one shown in Register 18-2 (SSPxCON1) of the Device Data Sheet. In SPI mode, the following bits are not reset upon disabling the SPI module (by clearing the SSPEN bit in SSPxCON1 register): · Buffer Full bit BF in SSPxSTAT register · Write Collision Detect bit WCOL in SSPxCON1 · Receive Overflow Indicator bit SSPOV in SSPxCON1 SSPADD = INT(FCY/FSCL) (FCY/1.111 MHz) 1 Note: For example, if SSPxBUF is full (BF bit is set) and the MSSP module is disabled and re-enabled, the BF bit will remain set. In SPI Slave mode, that can mean: The I2C bus is a synchronous protocol, so the accuracy of the bus frequency is not critical. Date Codes that pertain to this issue: · A subsequent write to SSPxBUF will result in a write collision · A new byte will cause a receive overflow All engineering and production devices. I2CTM CLOCK RATE with BRG TABLE 1: FOSC FCY FCY * 2 BRG Value FSCL (2 Rollovers of BRG) 40 MHz 10 MHz 20 MHz 0Eh 400 kHz(1) 40 MHz 10 MHz 20 MHz 15h 312.5 kHz 40 MHz 10 MHz 20 MHz 59h 100 kHz 16 MHz 4 MHz 8 MHz 05h 400 kHz(1) 16 MHz 4 MHz 8 MHz 08h 308 kHz 16 MHz 4 MHz 8 MHz 23h 100 kHz 4 MHz 1 MHz 2 MHz 01h 333 kHz(1) 4 MHz 1 MHz 2 MHz 08h 100 kHz 1 MHz 2 MHz 00h 1 MHz(1) 4 MHz Note 1: I2CTM I2C The interface does not conform to the 400 kHz specification (which applies to rates greater than 100 kHz) in all details, but may be used with care where higher rates are required by the application. DS80340B-page 2 2010 Microchip Technology Inc. PIC18F87J10 PIC18F87J10 FAMILY 7. Module: Master Synchronous Serial Port (MSSP) After an I2C transfer is initiated, the SSPxBUF register may be written for up to 10 TCY before additional writes are blocked. The data transfer may be corrupted if SSPxBUF is written during this time. The WCOL bit is set any time an SSPxBUF write occurs during a transfer. Work around Avoid writing SSPxBUF until the data transfer is complete, indicated by the setting of the SSP1IF bit (PIR1). Verify the WCOL bit (SSPxCON1) is clear after writing SSPxBUF to ensure any potential transfer in progress is not corrupted. Date Codes that pertain to this issue: All engineering and production devices. 8. Module: Master Synchronous Serial Port (MSSP) When the SPI is using Timer2/2 as the clock source, a shorter than expected SCKx pulse may occur on the first bit of the transmitted/received data (see Figure 1). FIGURE 1: SCKx PULSE VARIATION USING TIMER2/2 Write SSPxBUF bit 7 = 1 bit 6 = 0 bit 5 = 1 . . . . SDOx EXAMPLE 1: AVOIDING THE INITIAL SHORT SCK1 PULSE (FOR MSSP1) LOOP BTFSS SSP1STAT, BF BRA MOVF MOVWF MOVF BCF CLRF MOVWF BSF LOOP SSP1BUF, W RXDATA TXDATA, W T2CON, TMR2ON TMR2 SSP1BUF T2CON, TMR2ON ;Data received? ;(Xmit complete?) ;No ;W = SSPBUF ;Save in user RAM ;W = TXDATA ;Timer2 off ;Clear Timer2 ;Xmit New data ;Timer2 on Date Codes that pertain to this issue: All engineering and production devices. 9. Module: Master Synchronous Serial Port (MSSP) In SPI mode, the SDOx output may change after the inactive clock edge of the bit `0' output. This may affect some SPI components that read data more than 300 ns after the inactive edge of SCKx. Work around None. Date Codes that pertain to this issue: All engineering and production devices. 10. Module: Master Synchronous Serial Port (MSSP) When the MSSP peripherals are configured for SPI mode, the Buffer Full bit, BF (SSPxSTAT) should not be polled in software to determine when the transfer is complete. Work around SCKx Work around To avoid producing the short pulse: 1. Turn off Timer2. 2. Clear the TMR2 register. 3. Load the SSPxBUF with the data to be transmitted. 4. Turn Timer2 back on. For sample code, see Example 1. Do one of the following: · Copy the SSPxSTAT register into a variable and perform the bit test on the variable. (Example 2 copies SSP1STAT into the working register where the bit test is performed.) EXAMPLE 2: Master Synchronous Serial Port (MSSP1) loop_MSB: MOVF SSP1STAT, W BTFSS WREG, BF BRA loop_MSB · Poll the Master Synchronous Serial Port Interrupt Flag bit, SSP1IF (PIR1). This bit can be polled and will set when the transfer is complete. Date Codes that pertain to this issue: All engineering and production devices. 2010 Microchip Technology Inc. DS80340B-page 3 PIC18F87J10 PIC18F87J10 FAMILY 11. Module: Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) In rare situations, one or more extra zero bytes have been observed in a packet transmitted by the module operating in Asynchronous mode. The actual data is not lost or corrupted; only unwanted (extra) zero bytes are observed in the packet. This situation has only been observed when the contents of the transmit buffer, TXREGx, are transferred to the TSR during the transmission of a Stop bit. For this to occur, three things must happen in the same instruction cycle: · The TXREGx is written to · The baud rate counter overflows (at the end of the bit period) · A Stop bit is transmitted (shifted out of TSR) Work around If possible, do not use the module's double-buffer capability. Instead, load the TXREGx register when the TRMT bit (TXSTAx) is set, indicating the TSR is empty. 12. Module: Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) In 9-Bit Asynchronous Full-Duplex Receive mode, the received data may be corrupted if the TX9D bit (TXSTAx) is not modified immediately after the RCIDL bit (BAUDCONx) is set. Work around Write to TX9D only when a reception is not in progress (RCIDL = 1). Since there is no interrupt associated with RCIDL, it must be polled in software to determine when TX9D can be updated. Date Codes that pertain to this issue: All engineering and production devices. 13. Module: Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) After the last received byte has been read from the EUSART Receive Buffer (RCREGx), the value is no longer valid for subsequent read operations. If double-buffering is used and back-to-back transmission is performed, load TXREGx immediately after TXxIF is set or wait 1-bit time after TXxIF is set. Both solutions prevent writing TXREGx while a Stop bit is transmitted. Note that TXxIF is set at the beginning of the Stop bit transmission. Work around If transmission is intermittent, do one of the following: · Poll the RCIDL bit (BAUDCONx) for a low-to-high transition · Use the EUSART Receive Interrupt Flag, RC1IF (PIR1) · Wait for the TRMT bit to be set before loading TXREGx. · Execute the following: - Use a free timer resource to time the baud period. - Set up the timer to overflow at the end of Stop bit. - Start the timer when you load the TXREGx. - Do not load the TXREGx when the timer is about to overflow. The RCREGx register should be read only once for each byte received. After each byte is received from the EUSART, store the byte into a user variable. To determine when a byte is available to read from RCREGx, do one of the following: Date Codes that pertain to this issue: All engineering and production devices. Date Codes that pertain to this issue: All engineering and production devices. DS80340B-page 4 2010 Microchip Technology Inc. PIC18F87J10 PIC18F87J10 FAMILY 14. Module: Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) With the auto-wake-up option enabled by setting the WUE bit (BAUDCONx), the RC1IF bit (PIR1) will become set on a high-to-low transition on the RXx pin. While the WUE bit is set, reading the receive buffer (RCREGx) will not clear the RCxIF interrupt flag. Because of this, RCxIF cannot be automatically cleared by reading RCREGx until the WUE bit is cleared. Note: RCxIF can only be cleared by reading RCREGx Work around Do the following: 1. Poll either the WUE bit or the RXx pin. 2. When WUE is clear or RXx is high, read RCREGx. 15. Module: 10-Bit Analog-to-Digital (A/D) Converter When the A/D conversion clock is selected to be either FOSC/64 FOSC/64, FOSC/32 FOSC/32 or FOSC/16 FOSC/16, the GO/DONE bit cannot be set for a second conversion without first selecting (temporarily) the RC oscillator as the A/D conversion clock. The A/D functions normally with the A/D conversion clock settings of FOSC/2, FOSC/4 and FRC. Work around For A/D conversion clock settings of FOSC/64 FOSC/64, FOSC/32 FOSC/32 or FOSC/16 FOSC/16, perform the work around shown in Example 3 prior to setting the GO/DONE bit for subsequent conversions. It is recommended that this code be inserted immediately after the A/D result has been read from the previous conversion. Date Codes that pertain to this issue: All engineering and production devices. Step 2 clears RCxIF. Date Codes that pertain to this issue: All engineering and production devices. EXAMPLE 3: MOVF BSF BSF MOVWF ADCON2, W ADCON2, ADCS0 ADCON2, ADCS1 ADCON2 2010 Microchip Technology Inc. ;copy the value of ADCON2 to WREG ;temporarily select RC oscillator as clock ;restore ADCON2 to original value DS80340B-page 5 PIC18F87J10 PIC18F87J10 FAMILY 16. Module: 10-Bit Analog-to-Digital (A/D) Converter When FOSC/8 is selected as the A/D conversion clock, A/D conversion will not be performed. Work around None. Date Codes that pertain to this issue: All engineering and production devices. 17. Module: Master Synchronous Serial Port (MSSP) In extremely rare cases, when configured for I2C slave reception, the MSSP module may not receive the correct data. This occurs only if the Serial Receive/Transmit Buffer Register (SSPxBUF) is not read within a window after the SSPxIF interrupt has occurred. Work around The issue can be resolved in either of these ways: · Prior to the I2C slave reception, enable the clock stretching feature. This is done by setting the SEN bit (SSPxCON2). · Each time the SSPxIF is set, read the SSPxBUF before the first rising clock edge of the next byte being received. 18. Module: I/O Ports During a Power-on Reset, the PORTJ pins will not behave as high-impedance pins. For the Power-up Timer period (approximately 65.6 ms), PORTJ pins may be driven high or low. Work around None. DS80340B-page 6 2010 Microchip Technology Inc. PIC18F87J10 PIC18F87J10 FAMILY REVISION HISTORY Rev A Document (8/2007) First release of this document. Includes silicon issues 1 (Flash Program Memory), 2-3 (External Memory Bus), 4 (Timer1), 5-10 (MSSP), 11-14 EUSART and 15-16 (10-Bit A/D Converter). Rev B Document (7/2010) Added silicon issues 17 (Master Synchronous Serial Port MSSP) and 18 (I/O Ports). 2010 Microchip Technology Inc. DS80340B-page 7 PIC18F87J10 PIC18F87J10 FAMILY NOTES: DS80340B-page 8 2010 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: · Microchip products meet the specification contained in their particular Microchip Data Sheet. · Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. · There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. · Microchip is willing to work with the customer who is concerned about the integrity of their code. · Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, PIC32 PIC32 logo, rfPIC and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code Generation, PICC, PICC-18 PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2010, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: Microchip received ISO/TS-16949 ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company's quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified. 2010 Microchip Technology Inc. DS80340B-page 9 WORLDWIDE SALES AND SERVICE AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://support.microchip.com Web Address: www.microchip.com Asia Pacific Office Suites 3707-14, 37th Floor Tower 6, The Gateway Harbour City, Kowloon Hong Kong Tel: 852-2401-1200 Fax: 852-2401-3431 India - Bangalore Tel: 91-80-3090-4444 Fax: 91-80-3090-4123 India - New Delhi Tel: 91-11-4160-8631 Fax: 91-11-4160-8632 Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 India - Pune Tel: 91-20-2566-1512 Fax: 91-20-2566-1513 France - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Japan - Yokohama Tel: 81-45-471- 6166 Fax: 81-45-471-6122 Germany - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Atlanta Duluth, GA Tel: 678-957-9614 Fax: 678-957-1455 Boston Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Cleveland Independence, OH Tel: 216-447-0464 Fax: 216-447-0643 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Farmington Hills, MI Tel: 248-538-2250 Fax: 248-538-2260 Kokomo Kokomo, IN Tel: 765-864-8360 Fax: 765-864-8387 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 Santa Clara Santa Clara, CA Tel: 408-961-6444 Fax: 408-961-6445 Toronto Mississauga, Ontario, Canada Tel: 905-673-0699 Fax: 905-673-6509 Australia - Sydney Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 China - Beijing Tel: 86-10-8528-2100 Fax: 86-10-8528-2104 China - Chengdu Tel: 86-28-8665-5511 Fax: 86-28-8665-7889 Korea - Daegu Tel: 82-53-744-4301 Fax: 82-53-744-4302 China - Chongqing Tel: 86-23-8980-9588 Fax: 86-23-8980-9500 Korea - Seoul Tel: 82-2-554-7200 Fax: 82-2-558-5932 or 82-2-558-5934 China - Hong Kong SAR Tel: 852-2401-1200 Fax: 852-2401-3431 Malaysia - Kuala Lumpur Tel: 60-3-6201-9857 Fax: 60-3-6201-9859 China - Nanjing Tel: 86-25-8473-2460 Fax: 86-25-8473-2470 Malaysia - Penang Tel: 60-4-227-8870 Fax: 60-4-227-4068 China - Qingdao Tel: 86-532-8502-7355 Fax: 86-532-8502-7205 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 China - Shenyang Tel: 86-24-2334-2829 Fax: 86-24-2334-2393 Taiwan - Hsin Chu Tel: 886-3-6578-300 Fax: 886-3-6578-370 China - Shenzhen Tel: 86-755-8203-2660 Fax: 86-755-8203-1760 Taiwan - Kaohsiung Tel: 886-7-213-7830 Fax: 886-7-330-9305 China - Wuhan Tel: 86-27-5980-5300 Fax: 86-27-5980-5118 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 China - Xian Tel: 86-29-8833-7252 Fax: 86-29-8833-7256 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 Philippines - Manila Tel: 63-2-634-9065 Fax: 63-2-634-9069 China - Shanghai Tel: 86-21-5407-5533 Fax: 86-21-5407-5066 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 Spain - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 UK - Wokingham Tel: 44-118-921-5869 Fax: 44-118-921-5820 China - Xiamen Tel: 86-592-2388138 Fax: 86-592-2388130 China - Zhuhai Tel: 86-756-3210040 Fax: 86-756-3210049 07/15/10 DS80340B-page 10 2010 Microchip Technology Inc.