PIC18F47J13 DS39974A PIC18F46J13 PIC18F27J13 PIC18F26J13 PIC18LF47J13 - Datasheet Archive
PIC18F47J13 Family Silicon Errata and Data Sheet Clarification The PIC18F47J13 Family devices that you have received conform
PIC18F47J13 PIC18F47J13 FAMILY PIC18F47J13 PIC18F47J13 Family Silicon Errata and Data Sheet Clarification The PIC18F47J13 PIC18F47J13 Family devices that you have received conform functionally to the current Device Data Sheet (DS39974A DS39974A), except for the anomalies described in this document. The silicon issues discussed in the following pages are for silicon revisions with the Device and Revision IDs listed in Table 1. The silicon issues are summarized in Table 2. The errata described in this document will be addressed in future revisions of the PIC18F47J13 PIC18F47J13 Family silicon. This document summarizes all silicon errata issues from all revisions of silicon, previous as well as current. Only the issues indicated in the last column of Table 2 apply to the current silicon revision (A1). Note: Data Sheet clarifications and corrections start on page 5, following the discussion of silicon issues. The silicon revision level can be identified using the current version of MPLAB® IDE and Microchip's programmers, debuggers, and emulation tools, which are available at the Microchip corporate web site (www.microchip.com). TABLE 1: For example, to identify the silicon revision level using MPLAB IDE in conjunction with MPLAB ICD 2 or PICkitTM 3: 1. Using the appropriate interface, connect the device to the MPLAB ICD 2 programmer/ debugger or PICkitTM 3. From the main menu in MPLAB IDE, select Configure>Select Device, and then select the target part number in the dialog box. Select the MPLAB hardware tool (Debugger>Select Tool). Perform a "Connect" operation to the device (Debugger>Connect). Depending on the development tool used, the part number and Device Revision ID value appear in the Output window. 2. 3. 4. Note: If you are unable to extract the silicon revision level, please contact your local Microchip sales office for assistance. The DEVREV values for the various PIC18F47J13 PIC18F47J13 Family silicon revisions are shown in Table 1. SILICON DEVREV VALUES Part Number Revision ID for Silicon Revision(2) Device ID(1) A1 PIC18F47J13 PIC18F47J13 2CFh PIC18F46J13 PIC18F46J13 2CDh PIC18F27J13 PIC18F27J13 2CBh PIC18F26J13 PIC18F26J13 2C9h PIC18LF47J13 PIC18LF47J13 2DFh PIC18LF46J13 PIC18LF46J13 2DDh PIC18LF27J13 PIC18LF27J13 2DBh PIC18LF26J13 PIC18LF26J13 2D9h Note 1: 2: 01h The Device IDs (DEVID and DEVREV) are located at the last two implemented addresses of configuration memory space. They are shown in hexadecimal in the format "DEVID DEVREV". Refer to the "PIC18F2XJXX/4XJXX PIC18F2XJXX/4XJXX Family Flash Microcontroller Programming Specification" (DS39687 DS39687) for detailed information on Device and Revision IDs for your specific device. 2010 Microchip Technology Inc. DS80503B-page 1 PIC18F47J13 PIC18F47J13 FAMILY TABLE 2: SILICON ISSUE SUMMARY Module CTMU Feature Constant Current Source Item Number 1. Affected Revisions(1) Issue Summary A1 Band gap must be manually enabled before using the CTMU. X Oscillator PLL Configurations 2. PLL can not be enabled unless the 8 or 4 MHz INTOSC option is set. X ADC A/D 3. ANx pin may output a pull-up pulse during acquisition. X MSSP I2CTM Mode 4. If a Stop condition occurs in the middle of an address or data reception, there will be issues with the SCL clock stream and RCEN bit. X MSSP I2C Slave Reception 5. In I2C slave reception, the module may have problems receiving correct data. X EUSART Enable/ Disable 6. If interrupts are enabled, disabling and re-enabling the module requires a 2 TCY delay. X Note 1: Only those issues indicated in the last column apply to the current silicon revision. DS80503B-page 2 2010 Microchip Technology Inc. PIC18F47J13 PIC18F47J13 FAMILY Silicon Errata Issues Note: This document summarizes all silicon errata issues from all revisions of silicon, previous as well as current. Only the issues indicated by the shaded column in the following tables apply to the current silicon revision (A1). 1. Module: Charge Time Measurement Unit (CTMU) When using the CTMU, the constant current source may not output if the internal band gap reference is not enabled. Work around Before using the CTMU, the internal band gap reference module should be manually enabled by setting the VBGEN bit to `1' (ANCON1 = 1). Affected Silicon Revisions A1 X 2. Module: Phase Locked Loop (PLL) When OSCCON are configured to settings other than a 4 MHz or 8 MHz INTOSC postscaler, the PLLEN bit (OSCTUNE) is forced to `0', even if firmware tries to set the PLLEN bit. This may prevent firmware from enabling the PLL. Work around Before attempting to set the PLLEN bit, configure OSCCON to 0b110 or 0b111 to select the 4 MHz or 8 MHz INTOSC postscaler. Affected Silicon Revisions 3. Module: Analog-to-Digital Converter (ADC) At the beginning of sample acquisition, one or more small pull-up pulses (approximately 25 ns long) may output to the currently selected ANx analog channel. These pulses can lead to a positive offset error when the analog signal voltage is near VSS and the external analog signal driver is unable to dissipate the added pull-up voltage before the A/D conversion occurs. Work around Do one or more of the following: · Use the "0 TAD" A/D acquisition time setting to start the next sample acquisition period immediately following an A/D conversion completion. This allows the external analog signal driver more time to dissipate the pull-up pulses that occur when the sample acquisition is started. · Use a longer A/D acquisition time setting to provide time for the external analog signal driver to dissipate the pull-up pulse voltage. · Use low-impedance, active analog signal drivers to reduce the time needed to dissipate the pull-up pulse voltage. · Experiment with external filter capacitor values to avoid allowing the pull-up voltage offset to affect the final voltage that gets converted. Small filter capacitor values (or none at all) will allow time for the external analog signal driver to dissipate the pull-up voltage quickly. Alternately, large filter capacitor values will prevent the short pull-up pulses from increasing the final voltage enough to cause A/D conversion error. Affected Silicon Revisions A1 X A1 X 2010 Microchip Technology Inc. DS80503B-page 3 PIC18F47J13 PIC18F47J13 FAMILY 4. Module: Master Synchronous Serial Port (MSSP) 2 In Master I C Receive mode, if a Stop condition occurs in the middle of an address or data reception, the SCL clock stream will continue endlessly and the RCEN bit of the SSPCON2 register will remain set improperly. When a Start condition occurs after the improper Stop condition, nine additional clocks will be generated followed by the RCEN bit going low. Work around The issue can be resolved in either of these ways: · Prior to the I2C slave reception, enable the clock stretching feature. This is done by setting the SEN bit (SSPxCON2). · Each time the SSPxIF is set, read the SSPxBUF before the first rising clock edge of the next byte being received. Affected Silicon Revisions A1 Work around Use low-impedance pull-ups on the SDA line to reduce the possibility of noise glitches that may trigger an improper Stop event. Use a time-out event timer to detect the unexpected Stop condition, and subsequently, the stuck RCEN bit. Clear the stuck RCEN bit by clearing the SSPEN bit of SSPCON1. Affected Silicon Revisions A1 X 5. Module: Master Synchronous Serial Port When configured for I2CTM slave reception, the MSSP module may not receive the correct data, in extremely rare cases. This occurs only if the Serial Receive/ Transmit Buffer Register (SSPBUF) is not read after the SSPIF interrupt (PIR1) has occurred, but before the first rising clock edge of the next byte being received. X 6. Module: Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) In rare situations when interrupts are enabled, unexpected results may occur if: · The EUSART is disabled (SPEN bit (RCSTAx) = 0) · The EUSART is re-enabled (RCSTAx = 1) · A two-cycle instruction is executed immediately after setting SPEN, CREN or TXEN = 1 Work around Add a 2 TCY delay after any instruction that reenables the EUSART module (sets SPEN, CREN or TXEN = 1). See Example 1. Affected Silicon Revisions A1 X EXAMPLE 1: RE-ENABLING A EUSART MODULE ;Initial conditions: SPEN = 0 (module disabled) ;To re-enable the module: ;Re-Initialize TXSTAx, BAUDCONx, SPBRGx, SPBRGHx registers (if needed) ;Re-Initialize RCSTAx register (if needed), but do not set SPEN = 1 yet ;Now enable the module, but add a 2-Tcy delay before executing any two-cycle ;instructions bsf RCSTA1, SPEN ;or RCSTA2 if EUSART2 nop ;1 Tcy delay nop ;1 Tcy delay (two total) DS80503B-page 4 2010 Microchip Technology Inc. PIC18F47J13 PIC18F47J13 FAMILY Data Sheet Clarifications The following typographic corrections and clarifications are to be noted for the latest version of the device data sheet (DS39974A DS39974A): Corrections are shown in bold. Where possible, the original bold text formatting has been removed for clarity. Note: On "LF" devices, the VCAP/VDDCORE pin must be tied to a voltage supply at the VDDCORE level. Refer to Section 30.0 "Electrical Characteristics" for information on VDD and VDDCORE. Note that the "LF" versions of these devices are provided with the voltage regulator permanently disabled; they must always be provided with a supply voltage on the VDDCORE pin. FIGURE 2-3 1. Module: Guidelines for Getting Started with PIC18FJ PIC18FJ Microcontrollers Section "2.4 Voltage Regulator Pins (VCAP/ VDDCORE)" has been replaced with a new and more detailed section. The entire text follows: FREQUENCY vs. ESR PERFORMANCE FOR SUGGESTED VCAP 10 1 Voltage Regulator Pins (VCAP/ VDDCORE) ESR () 2.4 On "F" devices, a low-ESR (< 5) capacitor is required on the VCAP/VDDCORE pin to stabilize the voltage regulator output voltage. The VCAP/VDDCORE pin must not be connected to VDD and must use a capacitor of 10 µF connected to ground. The type can be ceramic or tantalum. Suitable examples of capacitors are shown in Table 2-1. Capacitors with equivalent specifications can be used. 0.1 0.01 0.001 0.01 Note: 0.1 1 10 100 Frequency (MHz) 1000 10,000 Typical data measurement at 25°C, 0V DC bias. Designers may use Figure 2-3 to evaluate ESR equivalence of candidate devices. It is recommended that the trace length not exceed 0.25 inch (6 mm). Refer to Section 30.0 "Electrical Characteristics" for additional information. TABLE 2-1 . SUITABLE CAPACITOR EQUIVALENTS Make Part # Nominal Capacitance Base Tolerance Rated Voltage Temp. Range TDK C3216X7R1C106K C3216X7R1C106K 10 µF ±10% 16V -55 to 125ºC TDK C3216X5R1C106K C3216X5R1C106K 10 µF ±10% 16V -55 to 85ºC Panasonic ECJ-3YX1C106K ECJ-3YX1C106K 10 µF ±10% 16V -55 to 125ºC Panasonic ECJ-4YB1C106K ECJ-4YB1C106K 10 µF ±10% 16V -55 to 85ºC Murata GRM32DR71C106KA01L GRM32DR71C106KA01L 10 µF ±10% 16V -55 to 125ºC Murata GRM31CR61C106KC31L GRM31CR61C106KC31L 10 µF ±10% 16V -55 to 85ºC 2010 Microchip Technology Inc. DS80503B-page 5 PIC18F47J13 PIC18F47J13 FAMILY CONSIDERATIONS FOR CERAMIC CAPACITORS In recent years, large value, low-voltage, surface mount ceramic capacitors have become very cost effective in sizes up to a few tens of microfarad. The low-ESR, small physical size and other properties make ceramic capacitors very attractive in many types of applications. Ceramic capacitors are suitable for use with the internal voltage regulator of this microcontroller. However, some care is needed in selecting the capacitor to ensure that it maintains sufficient capacitance over the intended operating range of the application. Typical low-cost, 10 µF ceramic capacitors are available in X5R, X7R and Y5V dielectric ratings (other types are also available, but are less common). The initial tolerance specifications for these types of capacitors are often specified as ±10% to ±20% (X5R and X7R), or -20%/+80% (Y5V). However, the effective capacitance that these capacitors provide in an application circuit will also vary based on additional factors, such as the applied DC bias voltage and the temperature. The total in-circuit tolerance is, therefore, much wider than the initial tolerance specification. The X5R and X7R capacitors typically exhibit satisfactory temperature stability (ex: ±15% over a wide temperature range, but consult the manufacturer's data sheets for exact specifications). However, Y5V capacitors typically have extreme temperature tolerance specifications of +22%/-82%. Due to the extreme temperature tolerance, a 10 µF nominal rated Y5V type capacitor may not deliver enough total capacitance to meet minimum internal voltage regulator stability and transient response requirements. Therefore, Y5V capacitors are not recommended for use with the internal voltage regulator if the application must operate over a wide temperature range. DS80503B-page 6 In addition to temperature tolerance, the effective capacitance of large value ceramic capacitors can vary substantially, based on the amount of DC voltage applied to the capacitor. This effect can be very significant, but is often overlooked or is not always documented. A typical DC bias voltage vs. capacitance graph for 16V, 10V and 6.3V rated capacitors is shown in Figure 2-4. FIGURE 2-4 Capacitance Change(%) 2.4.1 DC BIAS VOLTAGE vs. CAPACITANCE CHARACTERISTICS 10 0 -10 16V Capacitor -20 -30 -40 10V Capacitor -50 -60 -70 6.3V Capacitor -80 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 DC Bias Voltage(VDC) When selecting a ceramic capacitor to be used with the internal voltage regulator, it is suggested to select a high-voltage rating, so that the operating voltage is a small percentage of the maximum rated capacitor voltage. For example, choose a ceramic capacitor rated at 16V for the 2.5V core voltage. Suggested capacitors are shown in Table 2-1. 2010 Microchip Technology Inc. PIC18F47J13 PIC18F47J13 FAMILY 2. Module: Reset Register 20-1 and Register 20-5 incorrectly define the SSP2STAT Reset state as `1111 1111'. The correct Reset state of the SSPxSTAT is `0000 0000'. 2010 Microchip Technology Inc. DS80503B-page 7 PIC18F47J13 PIC18F47J13 FAMILY APPENDIX A: DOCUMENT REVISION HISTORY Rev A Document (6/2010) Initial release of this document. Added silicon issues 1 (Charge Time Measurement Unit CTMU), 2 (Phase Locked Loop PLL). 3 (Analog-to-Digital Converter ADC), 4 (Master Synchronous Serial Port MSSP), 5 (Master Synchronous Serial Port MSSP) and 6 (Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART). Rev B Document 10/2010) Added data sheet clarification issues 1 (Guidelines For Getting Started with PIC18FJ PIC18FJ Microcontrollers) and 2 (Reset). DS80503B-page 8 2010 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: · Microchip products meet the specification contained in their particular Microchip Data Sheet. · Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. · There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. · Microchip is willing to work with the customer who is concerned about the integrity of their code. · Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. 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Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18 PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2010, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 978-1-60932-569-5 Microchip received ISO/TS-16949 ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company's quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified. 2010 Microchip Technology Inc. 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