PIC18F2331/2431/4331/4431 DS39616B PIC18F2331 PIC18F2431 PIC18F4331 PIC18F4431 - Datasheet Archive

 

PIC18F2331/2431/4331/4431 Rev. A3 Silicon/Data Sheet Errata The PIC18F2331/2431/4331/4431 Rev. A3 parts you have received conform

 

PIC18F2331/2431/4331/4431 PIC18F2331/2431/4331/4431 PIC18F2331/2431/4331/4431 PIC18F2331/2431/4331/4431 Rev. A3 Silicon/Data Sheet Errata The PIC18F2331/2431/4331/4431 PIC18F2331/2431/4331/4431 Rev. A3 parts you have received conform functionally to the Device Data Sheet (DS39616B DS39616B), except for the anomalies described below. All the issues listed here will be addressed in future revisions of the PIC18F2331/2431/4331/4431 PIC18F2331/2431/4331/4431 silicon. The following silicon errata apply only to PIC18F2331/2431/4331/4431 PIC18F2331/2431/4331/4431 devices with these Device/Revision IDs: Part Number Device ID Revision ID PIC18F2331 PIC18F2331 00 1000 111 00010 PIC18F2431 PIC18F2431 00 1000 110 00010 PIC18F4331 PIC18F4331 00 1000 101 00010 PIC18F4431 PIC18F4431 00 1000 100 00010 The Device IDs (DEVID1 and DEVID2) are located at addresses 3FFFFEh:3FFFFFh in the device's configuration space. They are shown in hexadecimal in the format "DEVID2 DEVID1". 2. Module: PCPWM When the PCPWM is operated in Center-Aligned mode with double updates and the duty cycle alternates on each update between a zero and non-zero value, an incorrect waveform is generated (the PWM output will alternate between one PWM period high and one PWM period low). If in Complementary mode, dead time will not be inserted properly. Work around Do not use zero duty cycle when in Center-Aligned mode with double updates. Instead of zero, set the duty cycle to a small, non-zero value. Date Codes that pertain to this issue: All engineering and production devices. 1. Module: PCPWM When the PCPWM is operated in Complementary mode with a non-zero dead-time value and the duty cycle results in an active-low time of less than 1 TCY, the PWM generator will miss the rising edge for a new PWM period and the PWM output will alternate between one PWM period high and one PWM period low. Work around When in Complementary mode with a non-zero dead-time value, ensure that the active-low time will always be greater than 1 TCY. In other words, when dead time is not equal to zero, ensure that: PDCH:PDCL < (4 * PTPERH:PTPERL) or PDCH:PDCL > (4 * (PTPERH:PTPERL + 1) Date Codes that pertain to this issue: All engineering and production devices. 2004 Microchip Technology Inc. DS80192B-page 1 PIC18F2331/2431/4331/4431 PIC18F2331/2431/4331/4431 3. Module: PCPWM When the PCPWM is operated in Center-Aligned mode with double updates and the duty cycle alternates on each update between a greater than 100% duty cycle and a non-zero value, an incorrect waveform is generated. 6. Module: PCPWM In Complementary mode with dead-time insertion, when using OVDCOND and OVDCONS to override the PWM outputs, dead time is not inserted correctly when the dead-time prescaler is FOSC/4, FOSC/8 or FOSC/16 FOSC/16. Work around Work around Do not use equal to or greater than 100% duty cycle when in Center-Aligned mode with double updates. Ensure that the maximum duty cycle value is always smaller than or equal to the PWM period (i.e., PDCH:PDCL (4 * (PTPERH:PTPERL). None. Use dead-time prescaler of FOSC/2 in these circumstances. Date Codes that pertain to this issue: All engineering and production devices. 4. Module: PCPWM If dead-time insertion is enabled and it is a nonzero value, glitches in the PWM output will occur under the following conditions: 1. When the PWM timer is stopped by clearing the PTEN bit. 2. When the duty cycle is changed to zero. Work around 1. Before disabling the PWM timer, ensure that PORTB is set up to maintain a safe state of external hardware and that TRISB is set up to define the pins as outputs. 2. Do not use zero duty cycle when dead-time insertion is enabled. Instead of zero, set the duty cycle to a small, non-zero value (such as `1'). Date Codes that pertain to this issue: All engineering and production devices. 5. Module: PCPWM The PTMRH register will read as `00' or the last value written to it, even though the upper four bits of the PWM timer may be different. Writing to PTMRH will effect the upper four bits of the PWM timer when PTMRL is subsequently written. Although the PWM timer operates correctly, the double-buffer circuit does not transfer data to the PTMRH register from the upper four bits of the PWM timer. Work around PWM operation is not affected. Do not attempt to read PTMRH. Date Codes that pertain to this issue: All engineering and production devices. 7. Module: Core (DAW Instruction) The DAW instruction may improperly clear the CARRY bit (STATUS) when executed. Work around Test the CARRY bit state before executing the DAW instruction. If the CARRY bit is set, increment the next higher byte to be added, using an instruction such as INCFSZ (this instruction does not affect any Status flags and will not overflow a BCD nibble). After the DAW instruction has been executed, process the CARRY bit normally (see Example 1). EXAMPLE 1: PROCESSING THE CARRY BIT DURING BCD ADDITIONS MOVLW ADDLW 0x80 0x80 ; .80 (BCD) ; .80 (BCD) BTFSC INCFSZ DAW BTFSC INCFSZ STATUS, C byte2 ; test C ; inc next higher LSB STATUS, C byte2 ; test C ; inc next higher LSB This is repeated for each DAW instruction. Date Codes that pertain to this issue: All engineering and production devices. 8. Module: EUSART Bit SENDB in the TXSTA register is not automatically cleared by hardware upon completion of transmission of a Sync Break. Work around Check the TRMT bit in TXSTA. If TRMT bit is set, Break transmission is said to be complete. Date Codes that pertain to this issue: All engineering and production devices. DS80192B-page 2 2004 Microchip Technology Inc. PIC18F2331/2431/4331/4431 PIC18F2331/2431/4331/4431 9. Module: EUSART 12. Module: EUSART If the transmitter is left enabled while the module is performing an auto-baud operation, an arbitrary data byte may get transmitted. The CREN (RCSTA) bit is cleared after every auto-baud operation. Work around Upon completion of auto-baud, manually set the CREN bit. Clear TXEN bit (TXSTA) before any auto-baud operation and set it after auto-baud is complete. Enable TXEN only when a data byte is to be transmitted. Care must be taken to ensure that the TX pin is pulled high, either through an external resistor, or by making the TX pin an output and writing `1' to it, to not disturb the transmit line. 10. Module: EUSART This module may perform incorrect auto-baud calculation if the ABDEN (BAUDCTL) bit was set while the receive pin was at a low level. Work around Wait for the RX pin to go high and then set the ABDEN bit. 11. Module: EUSART In Asynchronous Receiver mode, the EUSART does not load the SPBRGH value after completion of auto-baud. Work around 13. Module: EUSART Writing to the USART/EUSART TXREG faster than the baud rate in Synchronous mode will overwrite the previous value instead of double-buffering, as in Asynchronous mode. Work around Load the first character into TXREG and then wait for a TX interrupt, or check the TXIF bit before writing each additional character to TXREG. 14. Module: EUSART The EUSART cannot receive asynchronous data at the four fastest baud rates (BRGH = 1, BRG16 BRG16 = 1 and SPBRG < 4). Work around Use a slower baud rate or a faster system clock speed. Work around Do not enable the BRG16 BRG16 (BAUDCTL) bit. If the BRG16 BRG16 is in use, ensure that the auto-baud SPBRG value does not exceed the 8-bit value. 2004 Microchip Technology Inc. DS80192B-page 3 PIC18F2331/2431/4331/4431 PIC18F2331/2431/4331/4431 3. Module: PWM Equations Clarifications/Corrections to the Data Sheet: In the Device Data Sheet (DS39616B DS39616B), the following clarifications and corrections should be noted. In Section 17.5 "PWM Period", Equations 17-1, 17-2 and 17-3 should be corrected as shown. EQUATION 17-1: 1. Module: Power-on Reset The following note has been added to Section 4.1 "Power-on Reset (POR)": Note: The following decoupling method recommended: TPWM = (PTPER + 1) x PTMRPS FOSC/4 is 1. A 1 µF capacitor should be connected across AVDD and AVSS. 2. A similar capacitor should be connected across VDD and VSS. EQUATION 17-2: TPWM = 2. Module: Watchdog Timer In Table 22-2: Summary of Watchdog Timer Registers, the WINEN bit (CONFIG2H) should not be shaded. DS80192B-page 4 PWM PERIOD FOR FREE RUNNING MODE EQUATION 17-3: PWM PERIOD FOR UP/DOWN COUNTING MODE (2 x PTPER) x PTMRPS FOSC 4 PWM RESOLUTION FOSC log Fpwm Resolution = log(2) 2004 Microchip Technology Inc. PIC18F2331/2431/4331/4431 PIC18F2331/2431/4331/4431 4. Module: DC Characteristics Specifications and parameter numbers have been revised for specific temperature ranges for date codes from 0421xxx and higher. The specifications and parameter numbers for the Brown-out Reset Voltage limits (VBOR, originally parameter D005) in Section 25.1 "DC Characteristics: Supply Voltage" of the Device Data Sheet have been changed. The new information is shown in bold text. The specifications and parameter numbers have been revised for devices with date codes from 0401xxx to 0420xxx, inclusive. 25.1 DC Characteristics: Supply Voltage PIC18F2331/2431/4331/4431 PIC18F2331/2431/4331/4431 (Industrial) PIC18LF2331/2431/4331/4431 PIC18LF2331/2431/4331/4431 (Industrial, Extended) PIC18LF2331/2431/4331/4431 PIC18LF2331/2431/4331/4431 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial PIC18F2331/2431/4331/4431 PIC18F2331/2431/4331/4431 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Param No. Symbol Characteristic Min Typ Max Units Conditions Date Codes from 0401xxx to 0420xxx, inclusive VBOR Brown-out Reset Voltage D005A D005A PIC18LF2X31/4X31 PIC18LF2X31/4X31 Industrial Low Voltage (-40°C to +85°C) BORV1:BORV0 = 11 N/A N/A N/A V BORV1:BORV0 = 10 2.45 2.72 2.99 V BORV1:BORV0 = 01 3.80 4.22 4.64 V 4.09 4.54 4.99 V BORV1:BORV0 = 00 D005B D005B PIC18F2X31/4X31 PIC18F2X31/4X31 Reserved Industrial (-40°C to +85°C) BORV1:BORV0 = 1x N/A N/A N/A V Reserved BORV1:BORV0 = 01 3.80 4.22 4.64 V (Note 2) 4.09 4.54 4.99 V (Note 2) BORV1:BORV0 = 00 D005C D005C PIC18F2X31/4X31 PIC18F2X31/4X31 Extended (-40°C to +125°C) BORV1:BORV0 = 1x N/A N/A V Reserved 3.80 4.22 4.64 V (Note 2) BORV1:BORV0 = 00 Legend: Note 1: 2: N/A BORV1:BORV0 = 01 4.09 4.54 4.99 V (Note 2) Shading of rows is to assist in readability of the table. This is the limit to which VDD can be lowered in Sleep mode, or during a device Reset, without losing RAM data. When BOR is on and BORV = 0x, the device will operate correctly at 40 MHz for any VDD at which the BOR allows execution. 2004 Microchip Technology Inc. DS80192B-page 5 PIC18F2331/2431/4331/4431 PIC18F2331/2431/4331/4431 25.1 DC Characteristics: Supply Voltage PIC18F2331/2431/4331/4431 PIC18F2331/2431/4331/4431 (Industrial) PIC18LF2331/2431/4331/4431 PIC18LF2331/2431/4331/4431 (Industrial, Extended) PIC18LF2331/2431/4331/4431 PIC18LF2331/2431/4331/4431 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial PIC18F2331/2431/4331/4431 PIC18F2331/2431/4331/4431 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Param No. Symbol Characteristic Min Typ Max Units Conditions Date Codes from 0421xxx and higher VBOR D005D D005D Brown-out Reset Voltage PIC18LF2X31/4X31 PIC18LF2X31/4X31 Industrial Low Voltage (-10°C to +85°C) BORV1:BORV0 = 11 N/A N/A V 2.50 2.72 2.94 V BORV1:BORV0 = 01 3.88 4.22 4.56 V BORV1:BORV0 = 00 D005F D005F N/A BORV1:BORV0 = 10 4.18 4.54 4.90 V PIC18LF2X31/4X31 PIC18LF2X31/4X31 Industrial Low Voltage (-40°C to -10°C) BORV1:BORV0 = 11 N/A N/A N/A V BORV1:BORV0 = 10 2.34 2.72 3.10 V BORV1:BORV0 = 01 3.63 4.22 4.81 V BORV1:BORV0 = 00 D005G D005G Reserved 3.90 4.54 5.18 V PIC18F2X31/4X31 PIC18F2X31/4X31 Reserved Industrial (-10°C to +85°C) BORV1:BORV0 = 1x N/A N/A V Reserved 3.88 4.22 4.56 V (Note 2) BORV1:BORV0 = 00 D005H D005H N/A BORV1:BORV0 = 01 4.18 4.54 4.90 V (Note 2) PIC18F2X31/4X31 PIC18F2X31/4X31 Industrial (-40°C to -10°C) BORV1:BORV0 = 1x N/A N/A V Reserved N/A N/A N/A V Reserved BORV1:BORV0 = 00 D005J D005J N/A BORV1:BORV0 = 01 3.90 4.54 5.18 V (Note 2) PIC18F2X31/4X31 PIC18F2X31/4X31 Extended (-10°C to +85°C) BORV1:BORV0 = 1x N/A N/A V Reserved 3.88 4.22 4.56 V (Note 2) BORV1:BORV0 = 00 D005K D005K N/A BORV1:BORV0 = 01 4.18 4.54 4.90 V (Note 2) PIC18F2X31/4X31 PIC18F2X31/4X31 Extended (-40°C to -10°C, +85°C to +125°C) BORV1:BORV0 = 1x N/A N/A V Reserved N/A N/A N/A V Reserved BORV1:BORV0 = 00 Legend: Note 1: 2: N/A BORV1:BORV0 = 01 3.90 4.54 5.18 V (Note 2) Shading of rows is to assist in readability of the table. This is the limit to which VDD can be lowered in Sleep mode, or during a device Reset, without losing RAM data. When BOR is on and BORV = 0x, the device will operate correctly at 40 MHz for any VDD at which the BOR allows execution. DS80192B-page 6 2004 Microchip Technology Inc. PIC18F2331/2431/4331/4431 PIC18F2331/2431/4331/4431 5. Module: LVD Characteristics Specifications and parameter numbers have been revised for specific temperature ranges for date codes from 0421xxx and higher. The specifications and parameter numbers for the Low-Voltage Detect thresholds (VLVD, originally parameter D420) in Table 25-2 of the Device Data Sheet have been changed. The new information is shown in bold text. The specifications and parameter numbers have been revised for devices with date codes from 0401xxx to 0420xxx, inclusive. TABLE 25-2: LOW-VOLTAGE DETECT CHARACTERISTICS PIC18LF2331/2431/4331/4431 PIC18LF2331/2431/4331/4431 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial PIC18F2331/2431/4331/4431 PIC18F2331/2431/4331/4431 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Param No. Symbol Characteristic Min Typ Max Units Conditions Date Codes from 0401xxx to 0420xxx, inclusive D420A D420A VLVD LVD Voltage on VDD Transition High-to-Low PIC18LF2X31/4X31 PIC18LF2X31/4X31 LVDL = 0000 Industrial Low Voltage (-40°C to +85°C) N/A N/A N/A V Reserved Reserved LVDL = 0001 N/A N/A V 2.08 2.26 2.44 V LVDL = 0011 2.26 2.45 2.65 V LVDL = 0100 2.35 2.55 2.76 V LVDL = 0101 2.55 2.77 2.99 V LVDL = 0110 2.64 2.87 3.10 V LVDL = 0111 2.82 3.07 3.31 V LVDL = 1000 3.09 3.36 3.63 V LVDL = 1001 3.29 3.57 3.86 V LVDL = 1010 3.38 3.67 3.96 V LVDL = 1011 3.56 3.87 4.18 V LVDL = 1100 3.75 4.07 4.40 V LVDL = 1101 3.93 4.28 4.62 V LVDL = 1110 D420B D420B N/A LVDL = 0010 4.23 4.60 4.96 V LVD Voltage on VDD Transition High-to-Low Industrial (-40°C to +85°C) PIC18F2X31/4X31 PIC18F2X31/4X31 LVDL = 1011 3.87 4.18 V LVDL = 1100 3.75 4.07 4.40 V LVDL = 1101 3.93 4.28 4.62 V LVDL = 1110 D420C D420C 3.56 4.23 4.60 4.96 V LVD Voltage on VDD Transition High-to-Low Extended (-40°C to +125°C) PIC18F2X31/4X31 PIC18F2X31/4X31 LVDL = 1011 3.87 4.33 V 3.58 4.07 4.56 V LVDL = 1101 3.77 4.28 4.79 V LVDL = 1110 Legend: 3.41 LVDL = 1100 4.04 4.60 5.15 V Shading of rows is to assist in readability of the table. Production tested at TAMB = 25°C. Specifications over temperature limits ensured by characterization. 2004 Microchip Technology Inc. DS80192B-page 7 PIC18F2331/2431/4331/4431 PIC18F2331/2431/4331/4431 TABLE 25-2: LOW-VOLTAGE DETECT CHARACTERISTICS (CONTINUED) PIC18LF2331/2431/4331/4431 PIC18LF2331/2431/4331/4431 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial PIC18F2331/2431/4331/4431 PIC18F2331/2431/4331/4431 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Param No. Symbol Characteristic Min Typ Max Units Conditions Date Codes from 0421xxx and higher D420D D420D VLVD LVD Voltage on VDD Transition High-to-Low Industrial Low Voltage (-10°C to +85°C) PIC18LF2X31/4X31 PIC18LF2X31/4X31 LVDL = 0000 N/A N/A N/A V Reserved LVDL = 0001 N/A N/A N/A V Reserved LVDL = 0010 2.08 2.26 2.44 V LVDL = 0011 2.26 2.45 2.65 V LVDL = 0100 2.35 2.55 2.76 V LVDL = 0101 2.55 2.77 2.99 V LVDL = 0110 2.64 2.87 3.10 V LVDL = 0111 2.82 3.07 3.31 V LVDL = 1000 3.09 3.36 3.63 V LVDL = 1001 3.29 3.57 3.86 V LVDL = 1010 3.38 3.67 3.96 V LVDL = 1011 3.56 3.87 4.18 V LVDL = 1100 3.75 4.07 4.40 V LVDL = 1101 3.93 4.28 4.62 V LVDL = 1110 4.23 4.60 4.96 V LVD Voltage on VDD Transition High-to-Low D420F D420F Industrial Low Voltage (-40°C to -10°C) PIC18LF2X31/4X31 PIC18LF2X31/4X31 LVDL = 0000 N/A N/A V Reserved N/A N/A N/A V Reserved LVDL = 0010 1.99 2.26 2.53 V LVDL = 0011 2.16 2.45 2.75 V LVDL = 0100 2.25 2.55 2.86 V LVDL = 0101 2.43 2.77 3.10 V LVDL = 0110 2.53 2.87 3.21 V LVDL = 0111 2.70 3.07 3.43 V LVDL = 1000 2.96 3.36 3.77 V LVDL = 1001 3.14 3.57 4.00 V LVDL = 1010 3.23 3.67 4.11 V LVDL = 1011 3.41 3.87 4.34 V LVDL = 1100 3.58 4.07 4.56 V LVDL = 1101 3.76 4.28 4.79 V LVDL = 1110 Legend: N/A LVDL = 0001 4.04 4.60 5.15 V Shading of rows is to assist in readability of the table. Production tested at TAMB = 25°C. Specifications over temperature limits ensured by characterization. DS80192B-page 8 2004 Microchip Technology Inc. PIC18F2331/2431/4331/4431 PIC18F2331/2431/4331/4431 TABLE 25-2: LOW-VOLTAGE DETECT CHARACTERISTICS (CONTINUED) PIC18LF2331/2431/4331/4431 PIC18LF2331/2431/4331/4431 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial PIC18F2331/2431/4331/4431 PIC18F2331/2431/4331/4431 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Param No. Symbol Characteristic Min Typ Max Units Conditions Date Codes from 0421xxx and higher D420G D420G VLVD LVD Voltage on VDD Transition High-to-Low Industrial (-10°C to +85°C) PIC18F2X31/4X31 PIC18F2X31/4X31 LVDL = 1101 D420H D420H 3.93 4.28 4.62 V LVDL = 1110 4.23 4.60 4.96 V LVD Voltage on VDD Transition High-to-Low PIC18F2X31/4X31 PIC18F2X31/4X31 LVDL = 1101 LVDL = 1110 D420J D420J LVD Voltage on VDD Transition High-to-Low PIC18F2X31/4X31 PIC18F2X31/4X31 LVDL = 1101 LVDL = 1110 D420K D420K LVD Voltage on VDD Transition High-to-Low Industrial (-40°C to -10°C) 3.76 4.28 4.79 V 4.04 4.60 5.15 V Extended (-10°C to +85°C) 3.94 4.28 4.62 V 4.23 4.60 4.96 V Extended (-40°C to -10°C, +85°C to +125°C) PIC18F2X31/4X31 PIC18F2X31/4X31 LVDL = 1101 3.77 4.28 4.79 V LVDL = 1110 Legend: Reserved 4.05 4.60 5.15 V Reserved Shading of rows is to assist in readability of the table. Production tested at TAMB = 25°C. Specifications over temperature limits ensured by characterization. 2004 Microchip Technology Inc. DS80192B-page 9 PIC18F2331/2431/4331/4431 PIC18F2331/2431/4331/4431 6. Module: 28-Pin QFN Diagram A 28-pin QFN package has been introduced for the PIC18F2331 PIC18F2331 and PIC18F2431 PIC18F2431 devices. The Device Data Sheet has been updated as follows: · The Pin Diagram section (page 3) has been updated to include the new 28-pin QFN package. FIGURE 1: 28-PIN 28-PIN QFN DIAGRAM 28 27 26 25 24 23 22 RA1/AN1 RA0/AN0 MCLR/VPP/RE3 RB7/KBI3/PGD RB6/KBI2/PGC RB5/KBI1/PWM4/PGM(1) RB4/KBI0/PWM5 28-Pin QFN PIC18F2231 PIC18F2231 PIC18F2431 PIC18F2431 8 9 10 11 12 13 14 1 2 3 4 5 6 7 21 20 19 18 17 16 15 RB3/PWM3 RB2/PWM2 RB1/PWM1 RB0/PWM0 VDD VSS RC7/RX/DT/SDO RC0/T1OSO/T1CKI RC1/T1OSI/CCP2/FLTA RC2/CCP1/FLTB RC3/T0CKI/T5CKI/INT0 RC4/INT1/SDI/SDA RC5/INT2/SCK/SCL RC6/TX/CK/SS RA2/AN2/VREF-/CAP1/INDX RA3/AN3/VREF+/CAP2/QEA RA4/AN4/CAP3/QEB VDD VSS OSC1/CLKI/RA7 OSC2/CLKO/RA6 Note 1: Low-Voltage Programming must be enabled. · The Packages information in Table 1-1 (page 9) and Table B-1 (page 379) has been updated to include a reference to the 28-pin QFN. The new text is shown in bold. TABLE 1: Features Packages DS80192B-page 10 PIC18F2331 PIC18F2331 PIC18F2431 PIC18F2431 PIC18F4331 PIC18F4331 PIC18F4431 PIC18F4431 28-pin SDIP 28-pin SOIC 28-pin QFN 28-pin SDIP 28-pin SOIC 28-pin QFN 40-pin DIP 44-pin TQFP 44-pin QFN 40-pin DIP 44-pin TQFP 44-pin QFN 2004 Microchip Technology Inc. PIC18F2331/2431/4331/4431 PIC18F2331/2431/4331/4431 · A new column with pin number information for the 28-pin QFN package has been added to Table 1-2 (pages 12-14). New information is shown in bold. TABLE 1-2: PIC18F2331/2431 PIC18F2331/2431 PINOUT I/O DESCRIPTIONS Pin Number Pin Name DIP, QFN SOIC MCLR/VPP/RE3 MCLR 1 Pin Buffer Type Type 26 I P I VPP RE3 OSC1/CLKI/RA7 OSC1 9 6 ST ST Description Master Clear (input) or programming voltage (input). Master Clear (Reset) input. This pin is an active-low Reset to the device. High-voltage ICSP programming enable pin. Digital input. Available only when MCLR is disabled. Oscillator crystal or external clock input. Oscillator crystal input or external clock source input. ST buffer when configured in RC mode, CMOS otherwise. I CMOS External clock source input. Always associated with pin function OSC1. (See related OSC1/CLKI, OSC2/CLKO pins.) I/O TTL General purpose I/O pin. I ST O - CLKO O - RA6 I/O TTL CLKI RA7 OSC2/CLKO/RA6 OSC2 10 7 Oscillator crystal or clock output. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. In RC mode, OSC2 pin outputs CLKO, which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. General purpose I/O pin. PORTA is a bidirectional I/O port. RA0/AN0 RA0 AN0 2 RA1/AN1 RA1 AN1 3 RA2/AN2/VREF-/CAP1/INDX RA2 AN2 VREFCAP1 INDX 4 RA3/AN3/VREF+/CAP2/QEA RA3 AN3 VREF+ CAP2 QEA 5 RA4/AN4/CAP3/QEB RA4 AN4 CAP3 QEB 6 Legend: TTL ST O OD 27 I/O TTL I Analog Digital I/O. Analog input 0. I/O TTL I Analog Digital I/O. Analog input 1. TTL I/O I Analog I Analog I ST I ST Digital I/O. Analog input 2. A/D reference voltage (Low) input. Input capture pin 1. Quadrature Encoder Interface index input pin. I/O TTL I Analog I Analog I ST I ST Digital I/O. Analog input 3. A/D reference voltage (High) input. Input capture pin 2. Quadrature Encoder Interface channel A input pin. I/O TTL I Analog I ST I ST Digital I/O. Analog input 4. Input capture pin 3. Quadrature Encoder Interface channel B input pin. 28 1 2 3 = TTL compatible input = Schmitt Trigger input with CMOS levels = Output = Open-Drain (no diode to VDD) 2004 Microchip Technology Inc. CMOS = CMOS compatible input or output I = Input P = Power DS80192B-page 11 PIC18F2331/2431/4331/4431 PIC18F2331/2431/4331/4431 TABLE 1-2: PIC18F2331/2431 PIC18F2331/2431 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name Pin Buffer Type Type DIP, QFN SOIC Description PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs. RB0/PWM0 RB0 PWM0 21 RB1/PWM1 RB1 PWM1 22 RB2/PWM2 RB2 PWM2 23 RB3/PWM3 RB3 PWM3 24 RB4/KBI0/PWM5 RB4 KBI0 PWM5 25 RB5/KBI1/PWM4/PGM RB5 KBI1 PWM4 PGM 26 RB6/KBI2/PGC RB6 KBI2 PGC 27 RB7/KBI3/PGD RB7 KBI3 PGD 28 Legend: TTL ST O OD 18 I/O O TTL TTL Digital I/O. PWM output 0. I/O O TTL TTL Digital I/O. PWM output 1. I/O O TTL TTL Digital I/O. PWM output 2. I/O O TTL TTL Digital I/O. PWM output 3. I/O I O TTL TTL TTL Digital I/O. Interrupt-on-change pin. PWM output 5. I/O I O I/O TTL TTL TTL ST Digital I/O. Interrupt-on-change pin. PWM output 4. Low-Voltage ICSPTM Programming entry pin. I/O I I/O TTL TTL ST Digital I/O. Interrupt-on-change pin. In-Circuit Debugger and ICSP programming clock pin. I/O I I/O TTL TTL ST Digital I/O. Interrupt-on-change pin. In-Circuit Debugger and ICSP programming data pin. 19 20 21 22 23 24 25 = TTL compatible input = Schmitt Trigger input with CMOS levels = Output = Open-Drain (no diode to VDD) DS80192B-page 12 CMOS = CMOS compatible input or output I = Input P = Power 2004 Microchip Technology Inc. PIC18F2331/2431/4331/4431 PIC18F2331/2431/4331/4431 TABLE 1-2: PIC18F2331/2431 PIC18F2331/2431 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name Pin Buffer Type Type DIP, QFN SOIC Description PORTC is a bidirectional I/O port. RC0/T1OSO/T1CKI RC0 T1OSO T1CKI 11 RC1/T1OSI/CCP2/FLTA RC1 T1OSI CCP2 FLTA 12 RC2/CCP1/FLTB RC2 CCP1 FLTB 13 RC3/T0CKI/T5CKI/INT0 RC3 T0CKI T5CKI INT0 14 RC4/INT1/SDI/SDA RC4 INT1 SDI SDA 15 RC5/INT2/SCK/SCL RC5 INT2 SCK SCL 16 RC6/TX/CK/SS RC6 TX CK SS 17 RC7/RX/DT/SDO RC7 RX DT SDO 18 VSS VDD Legend: TTL ST O OD 8 I/O O I ST - ST Digital I/O. Timer1 oscillator output. Timer1 external clock input. I/O I I/O I ST CMOS ST ST Digital I/O. Timer1 oscillator input. Capture 2 input, Compare 2 output, PWM 2 output. Fault interrupt input pin. I/O I/O I ST ST ST Digital I/O. Capture 1 input/Compare 1 output/PWM 1 output. Fault interrupt input pin. I/O I I I ST ST ST ST Digital I/O. Timer0 alternate clock input. Timer5 alternate clock input. External interrupt 0. I/O I I I/O ST ST ST ST Digital I/O. External interrupt 1. SPITM data in. I2CTM data I/O. I/O I I/O I/O ST ST ST ST Digital I/O. External interrupt 2. Synchronous serial clock input/output for SPI mode. Synchronous serial clock input/output for I2C mode. I/O O I/O I ST - ST TTL Digital I/O. USART asynchronous transmit. USART synchronous clock (see related RX/DT). SPI slave select input. I/O I I/O O ST ST ST - Digital I/O. USART asynchronous receive. USART synchronous data (see related TX/CK). SPI data out. 8, 19 5, 16 P - Ground reference for logic and I/O pins. 7, 20 4, 17 P - Positive supply for logic and I/O pins. 9 10 11 12 13 14 15 = TTL compatible input = Schmitt Trigger input with CMOS levels = Output = Open-Drain (no diode to VDD) 2004 Microchip Technology Inc. CMOS = CMOS compatible input or output I = Input P = Power DS80192B-page 13 PIC18F2331/2431/4331/4431 PIC18F2331/2431/4331/4431 · 28-pin QFN details have been added to Section 27.1 "Package Marking Information" (page 373). 27.1 Package Marking Information 28-Lead QFN Example XXXXXXXX XXXXXXXX YYWWNNN Legend: XX.X Y YY WW NNN Note: * 18F2431 18F2431 -I/MM 0410017 Customer specific information* Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information. Standard PICmicro device marking consists of Microchip part number, year code, week code, and traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price. DS80192B-page 14 2004 Microchip Technology Inc. PIC18F2331/2431/4331/4431 PIC18F2331/2431/4331/4431 · 28-pin QFN packaging details have been added to Section 27.2 "Package Details" (page 374). 28-Lead Plastic Quad Flat No Lead Package (MM) 6x6x0.9 mm Body (QFN-S) ­ With 0.40 mm Contact Length (Saw Singulated) E2 E EXPOSED METAL PAD e D D2 b 2 1 n OPTIONAL INDEX AREA TOP VIEW ALTERNATE INDEX INDICATORS L BOTTOM VIEW A1 A Number of Pins Pitch Overall Height Standoff Overall Width Exposed Pad Width Overall Length Exposed Pad Length Lead Width Lead Length Units Dimension Limits n e A A1 E E2 D D2 b L MIN .031 .000 .232 .169 .232 .169 .013 .012 INCHES NOM 28 .026 BSC .035 .001 .236 .175 .236 .175 .015 .016 MAX .039 .002 .240 .177 .240 .177 .017 .020 MILLIMETERS* NOM 28 0.65 BSC 0.90 0.80 0.02 0.00 6.00 5.90 4.30 4.45 5.90 6.00 4.30 4.45 0.33 0.38 0.30 0.40 MIN MAX 1.00 0.05 6.10 4.50 6.10 4.50 0.43 0.50 *Controlling Parameter Notes: JEDEC equivalent: MO-220 MO-220 Drawing No. C04-124 C04-124 2004 Microchip Technology Inc. Revised 05/24/04 DS80192B-page 15 PIC18F2331/2431/4331/4431 PIC18F2331/2431/4331/4431 REVISION HISTORY Rev A Document (6/2004) First revision of this document. Silicon issues 1-6 (PCPWM), 7 (Core ­ DAW Instruction) and 8-14 (EUSART) and Data Sheet Clarification issues 1 (Poweron Reset), 2 (Watchdog Timer), 3 (PWM Equations), 4 (DC Characteristics) and 5 (LVD Characteristics). Rev B Document (12/2004) Added Data Sheet Clarification issue 6 (28-Pin QFN Diagram). DS80192B-page 16 2004 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: · Microchip products meet the specification contained in their particular Microchip Data Sheet. · Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. · There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. · Microchip is willing to work with the customer who is concerned about the integrity of their code. · Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip's products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC, and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB, PICMASTER, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2004, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949 ISO/TS-16949:2002 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona and Mountain View, California in October 2003. The Company's quality system processes and procedures are for its PICmicro® 8-bit MCUs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified. 2004 Microchip Technology Inc. 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