PIC18F1XK22/LF1XK22 DS41365D PIC18F1XK22/ LF1XK22 PIC18F14K22 PIC18F13K22

PIC18F1XK22/LF1XK22 Family Silicon Errata and Data Sheet Clarification The PIC18F1XK22/LF1XK22 family devices that you have

PIC18F1XK22/LF1XK22 PIC18F1XK22/LF1XK22 PIC18F1XK22/LF1XK22 PIC18F1XK22/LF1XK22 Family Silicon Errata and Data Sheet Clarification The PIC18F1XK22/LF1XK22 PIC18F1XK22/LF1XK22 family devices that you have received conform functionally to the current Device Data Sheet (DS41365D DS41365D), except for the anomalies described in this document. The silicon issues discussed in the following pages are for silicon revisions with the Device and Revision IDs listed in Table 1. The silicon issues are summarized in Table 2. The errata described in this document will be addressed in future revisions of the PIC18F1XK22/LF1XK22 PIC18F1XK22/LF1XK22 silicon. Note: This document summarizes all silicon errata issues from all revisions of silicon, previous as well as current. Data Sheet clarifications and corrections start on page 9, following the discussion of silicon issues. The silicon revision level can be identified using the current version of MPLAB® IDE and Microchip's programmers, debuggers, and emulation tools, which are available at the Microchip corporate web site (www.microchip.com). TABLE 1: For example, to identify the silicon revision level using MPLAB IDE in conjunction with MPLAB ICD 2 or PICkitTM 3: 1. 2. 3. 4. Using the appropriate interface, connect the device to the MPLAB ICD 2 programmer/ debugger or PICkitTM 3. From the main menu in MPLAB IDE, select Configure>Select Device, and then select the target part number in the dialog box. Select the MPLAB hardware tool (Debugger>Select Tool). Perform a "Connect" operation to the device (Debugger>Connect). Depending on the development tool used, the part number and Device Revision ID value appear in the Output window. Note: If you are unable to extract the silicon revision level, please contact your local Microchip sales office for assistance. The DEVREV values for the various PIC18F1XK22/ PIC18F1XK22/ LF1XK22 LF1XK22 silicon revisions are shown in Table 1. SILICON DEVREV VALUES Revision ID for Silicon Revision(1) Part Number Device ID A3 PIC18F14K22 PIC18F14K22 4F20h A7 A8 03h 07h 08h PIC18F13K22 PIC18F13K22 4F40h 03h 07h 08h PIC18LF14K22 PIC18LF14K22 4F60h 03h 07h 08h PIC18LF13K22 PIC18LF13K22 4F80h 03h 07h 08h Note 1: 2: The Device IDs (DEVID and DEVREV) are located at the last two implemented addresses in program memory. They are shown in hexadecimal in the format "DEVID:DEVREF". Refer to the "PIC18F1XK22/LF1XK22 PIC18F1XK22/LF1XK22 Flash Memory Programming Specification" (DS41357 DS41357) for detailed information on Device and Revision IDs for your specific device. 2010 Microchip Technology Inc. DS80437D-page 1 PIC18F1XK22/LF1XK22 PIC18F1XK22/LF1XK22 TABLE 2: SILICON ISSUE SUMMARY Module Feature Item Number Issue Summary Affected Revisions(1) A3 A7 A8 X ADC (Analog-to-Digital Converter) ADC Conversion 1.1 Large INL error on AN3. X X ADC (Analog-to-Digital Converter) ADC Conversion 1.2 ADC conversion does not complete. X X ECCP Full Bridge mode 2. Delay time with direction change. X X X X EUSART - 3.1 Unreliable RCIDL bit. X X EUSART - 3.2 Clear the OERR flag. X X EUSART - 3.3 RX and TX are unavailable for output. X X EUSART - 3.4 Unexpected results. X X X MSSP (Master Synchronous Serial Port) - 4. I2CTM mode and SPI mode. X X X In-Circuit Serial ProgrammingTM (ICSPTM) - 5. ICSPTM works only at VDD>2V. X X X Clock Switching 6. FCMEN Configuration bit. X X X IOCB 7. Interrupt-on-change. X X X Power-on Reset (POR) 8. Low-power conditions. X Oscillator PORTB Interrupt-on-Change Resets Note 1: X Only those issues indicated in the last column apply to the current silicon revision. DS80437D-page 2 2010 Microchip Technology Inc. PIC18F1XK22/LF1XK22 PIC18F1XK22/LF1XK22 Silicon Errata Issues Note: This document summarizes all silicon errata issues from all revisions of silicon, previous as well as current. Only the issues indicated by the shaded column in the following tables apply to the current silicon revision (A8). 1. Module: ADC (Analog-to-Digital Converter) 1.1 ADC conversion on AN3/OSC2 will have large INL error up to approximately 8 LSb. Work around None for the AN3 pin. For better accuracy, use another analog pin. 1.2 An ADC conversion may not complete under these conditions: 1. When FOSC is greater than 8 MHz and is the clock source used for the ADC converter. 2. The ADC is operating from its dedicated internal FRC oscillator and the device is not in Sleep mode (an FOSC frequency). When this occurs, the ADC Interrupt Fag (ADIF) does not get set, the GO/ DONE bit does not get cleared, and the conversion result does not get loaded into the ADRESH and ADRESL result registers. Work around Method 1: Select the system clock, FOSC, as the ADC clock source and reduce the FOSC frequency to 8 MHz or less when performing ADC conversions. Method Select the dedicated FRC oscillator as the ADC conversion clock source and perform all conversions with the device in Sleep. Affected Silicon Revisions A3 A7 A8 X X X 2: Method 3: Method 3 is provided if the application cannot use Sleep mode and requires continuous operation at frequencies above 8 MHz. This method requires early termination of an ADC conversion. Provide a fixed time delay in software to stop the Ato-D conversion manually, after all 10 bits are converted, but before the conversion would complete automatically. The conversion is stopped by clearing the GO/DONE bit in software. The GO/DONE bit must be cleared during the last ½ TAD cycle, before the conversion would have completed automatically. Refer to Figure 1 for details. 2010 Microchip Technology Inc. DS80437D-page 3 PIC18F1XK22/LF1XK22 PIC18F1XK22/LF1XK22 FIGURE 1: INSTRUCTION CYCLE DELAY CALCULATION EXAMPLE FOSC = 32 MHz TCY = 4/32 MHz = 125 nsec TAD = 1 µsec, ADCS = FOSC/32 FOSC/32 88 TCY 8 TCY 84 TCY } 4 TCY 11 TAD Stop the A/D conversion between 10.5 and 11 TAD cycles. See the Analog-to-Digital Conversion Timing diagram in the Analog-to-Digital Converter chapter of the device data sheet. 1 TAD See ADC Clock Period (TAD) vs. Device Operating Frequencies Table, in the Analog-to-Digital Converter chapter of the device data sheet. DS80437D-page 4 2010 Microchip Technology Inc. PIC18F1XK22/LF1XK22 PIC18F1XK22/LF1XK22 In Figure 1, 88 instruction cycles (TCY) will be required to complete the full conversion. Each TAD cycle consists of 8 TCY periods. A fixed delay is provided to stop the A/D conversion after 86 instruction cycles and terminate the conversion at the correct time as shown in the figure above. 2. Module: ECCP 2.1 Changing direction in Full-Bridge mode inserts a dead band time of 4/FOSC * TMR2 Prescale instead of 1/FOSC * TMR2 Prescale as specified in the data sheet. Work around Note: The exact delay time will depend on the TAD divisor (ADCS) selection. The TCY counts shown in the timing diagram above apply to this example only. Refer to Table 3 for the required delay counts for other configurations. EXAMPLE 1: CODE EXAMPLE OF INSTRUCTION CYCLE DELAY BSF ADCON0, GO BCF ADCON0, GO MOVF ADRESH, W None. Affected Silicon Revisions A3 A7 A8 X X X 2.2 ; Start ADC conversion ; Provide 86 instruction cycle delay here ; Terminate the conversion manually ; Read conversion result Work around Avoid changing direction when the duty cycle is within three least significant steps of 100% duty cycle. Instead, clear the DC1B bits before the direction change and then set them to the desired value after the direction change is complete. For other combinations of FOSC, TAD values and Instruction cycle delay counts, refer to Table 3. TABLE 3: INSTRUCTION CYCLE DELAY COUNT VS. TAD In Full-Bridge mode, when PR2 = CCPR1L, DC1B = 00, and the direction is changed, then the dead time before the modulated output starts is compromised. The modulated signal improperly starts immediately with the direction change and stays on for TOSC * TMR2 Prescale * DC1B. Affected Silicon Revisions TAD Instruction Cycle Delay Counts A3 A7 A8 X X X FOSC/64 FOSC/64 172 FOSC/32 FOSC/32 86 FOSC/16 FOSC/16 43 Affected Silicon Revisions A3 A7 X 3. Module: EUSART 3.1 A8 X In Asynchronous Receive mode, the RCIDL bit of the BAUDCON register will properly go low when a low pulse greater than 1/16th of a bit time is received on the RX input. The RCIDL bit will then improperly go high if a low pulse less than 1/16 bit time occurs on the RX input within one bit period, after the falling edge of the first pulse. This erratum affects only users monitoring the RCIDL bit as a part of their serial protocol. Work around None. Affected Silicon Revisions A3 A8 X 2010 Microchip Technology Inc. A7 X X DS80437D-page 5 PIC18F1XK22/LF1XK22 PIC18F1XK22/LF1XK22 3.2 The OERR flag of the RCSTA register is reset only by either clearing the CREN bit of the RCSTA register or by a device Reset. Clearing the SPEN bit of the RCSTA register does not clear the OERR flag. 4. Module: MSSP (Master Synchronous Serial Port) 4.1 Work around Work around Clear the OERR flag by clearing the CREN bit in lieu of clearing the SPEN bit. Affected Silicon Revisions A3 A7 X X 3.3 A8 When the SPEN bit of the RCSTA register is set and the CREN bit of the RCSTA register is clear, the RX pin is not available for general purpose output. Likewise, when the SPEN bit of the RCSTA register is set and the TXEN bit of the TXSTA register is clear, the TX pin is not available for general purpose output. However, both the RX and TX pins can be read regardless of the state of the RCSTA and TXSTA control registers. Ensure SSPADD is set to a value greater than or equal to 0x03. Affected Silicon Revisions A3 A7 A8 X X X 4.2 In SPI Master mode, when the CKE bit is cleared and the SMP bit is set, the last bit of the incoming data stream (bit 0) at the SDI pin will not be sampled properly. Work around None. Affected Silicon Revisions None. Affected Silicon Revisions A3 A7 X A7 A8 X X 4.3 A8 X A3 X Work around X 3.4 In I2CTM Master mode, baud rates obtained by setting SSPADD to a value less than 0x03 will cause unexpected operation. Unexpected results occur if the EUSART is disabled and then re-enabled with the EUSART receive interrupt and global interrupts enabled, then a single cycle instruction is followed by a 2 cycle instruction. Work around Always execute at least 2 single-cycle instructions, immediately following setting the SPEN bit to `1'. Work around Configure the SCK pin as an input until after the MSSP is setup. Affected Silicon Revisions A3 A7 A8 X X X 4.4 Affected Silicon Revisions A3 A7 X In I2C Master mode, SSPADD values of 0x00, 0x01, 0x02 are invalid. The current I2C Baud Rate Generator (BRG) is not set up to generate a clock signal for these values. Work around A8 X When SPI is enabled in Master mode with CKE = 1 and CKP = 0, a 1/FOSC wide pulse will occur on the SCK pin. X None. Affected Silicon Revisions A3 A8 X DS80437D-page 6 A7 X X 2010 Microchip Technology Inc. PIC18F1XK22/LF1XK22 PIC18F1XK22/LF1XK22 4.5 In I2C Master mode, the RCEN bit is not cleared by hardware if improper Stop is received on the bus. 5. Module: In-Circuit Serial ProgrammingTM (ICSPTM) Work around The device cannot be programmed using ICSP when the device VDD is less than 2.0V. Reset the module via clearing and setting the SSPEN bit of SSPCON1. Work around Affected Silicon Revisions A3 A7 A8 X X X 4.6 In SPI Master mode, when the SPI clock is configured for Timer2/2 (SSPCON1 = 0011), the first SPI high time may be short. Work around Option 1: Ensure TMR2 value rolls over to zero immediately before writing to SSPBUF. Option 2: Turn Timer2 off and clear TMR2 before writing SSPBUF. Enable TMR2 after SSPBUF is written. Affected Silicon Revisions A3 A7 A8 X X X 4.7 In any SPI Master mode, SCK = TMR2/2, if SSPBUF is written to while shifting out data, a ninth SCK pulse is incorrectly generated. At that point, the module locks the user from writing to the SSPBUF register, but a write attempt will still cause 8 or 9 more SCK pulses to be generated. Work around The WCOL bit of the SSPCON register is correctly set to indicate that there was a write collision. Any time this bit is set, the module must be disabled and enabled (toggle SSPEN) to return to the correct operation. The bus will remain out of synchronization. Affected Silicon Revisions. A3 A7 X Affected Silicon Revisions A3 A7 A8 X X X 6. Module: Oscillator 6.1 Clock Switching 6.2 When the FCMEN Configuration bit is set and the IESO Configuration bit is not set, then a clock failure during Sleep will not be detected. Work around The IESO Configuration bit must also be set when the FCMEN Configuration bit is set. Affected Silicon Revisions A3 A7 A8 X X X 7. Module: PORTB Interrupt-on-Change Setting a PORTB interrupt-on-change enable bit of the IOCB register while the corresponding PORTB input is high will cause an RBIF interrupt. Work around Set the IOCB bits to the desired configuration, then read PORTB to clear the mismatch latches. Finally, clear the RBIF bit before setting the RBIE bit. Affected Silicon Revisions A3 A7 A8 X X X A8 X Ensure that the device voltage is 2.0V or higher when programming the device. X 2010 Microchip Technology Inc. DS80437D-page 7 PIC18F1XK22/LF1XK22 PIC18F1XK22/LF1XK22 8. Module: Resets 8.1 Note: Reset under Low Power Conditions This issue pertains only to the F product versions, PIC18F14K22/13K22 PIC18F14K22/13K22. The LF product versions, PIC18LF14K22/13K22 PIC18LF14K22/13K22, are not affected by this issue in any way. When employing any one of the low-power oscillators (ECL mode, LP mode, LFINTOSC or Timer1 Oscillator) at temperatures of -20°C or colder, while at the same time the source voltage supplied to the VDD pin drops below 2.4 volts, the device may experience a Power-on Reset (POR). Also, when the source voltage supplied to the VDD pin is below 2.4 volts, at temperatures of -20°C or colder, and a SLEEP instruction is executed, the device may experience a Power-on Reset (POR) upon entering Sleep mode, regardless of the type of clock source being used or which powermanaged mode is being employed. Work around There are four work arounds available to avoid this Reset condition: 1. 2. 3. 4. Enabling the Brown-out Reset (BOR) circuitry. Enabling the Fixed Voltage Reference (FVR) module. Maintaining a source voltage (VDD) to the device above 2.4 volts when operating at temperatures of -20°C or colder. Use the LF product version (PIC18LF14K22/ PIC18LF14K22/ 13K22 13K22) where the operational VDD requirement is between 1.8V and 3.6V. Affected Silicon Revisions A3 A7 A8 X DS80437D-page 8 2010 Microchip Technology Inc. PIC18F1XK22/LF1XK22 PIC18F1XK22/LF1XK22 Data Sheet Clarifications The following typographic corrections and clarifications are to be noted for the latest version of the device data sheet (DS41365D DS41365D). None. 2010 Microchip Technology Inc. DS80437D-page 9 PIC18F1XK22/LF1XK22 PIC18F1XK22/LF1XK22 APPENDIX A: DOCUMENT REVISION HISTORY Rev. A Document (3/2009) Initial release of this document. Rev. B Document (5/2009) Revised Table 1; Added Table 2; Added Module 8: Internal Oscillator. Added Data Sheet Clarifications Module 1: Electrical Specifications and Module 2: Device Overview. Rev. C Document (4/2010) Updated Table 1 and Table 2 adding revisions A7 and A8; Added Module 1.2; Added Module 3.4; Added Module 9: PORTB Interrupt-on-Change. Data Sheet Clarifications: Removed Modules 1 and 2. Rev. D Document (7/2010) Deleted Module 5, Module 6 and renumbered modules; Added Module 8 (Resets). DS80437D-page 10 2010 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: · Microchip products meet the specification contained in their particular Microchip Data Sheet. · Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. · There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. · Microchip is willing to work with the customer who is concerned about the integrity of their code. · Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, PIC32 PIC32 logo, rfPIC and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code Generation, PICC, PICC-18 PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2010, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 978-1-60932-371-4 Microchip received ISO/TS-16949 ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company's quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified. 2010 Microchip Technology Inc. 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