PIC18FX220/X320 PIC18F1220 PIC18F1320 PIC18F2220 PIC18F2320 PIC18F4220 - Datasheet Archive

 

PIC18FX220/X320 Programming for PIC18FX220/X320 FLASH MCUs 1.0 DEVICE OVERVIEW 2.1 · PIC18F1220 · PIC18F1320

 

M PIC18FX220/X320 PIC18FX220/X320 Programming for PIC18FX220/X320 PIC18FX220/X320 FLASH MCUs 1.0 DEVICE OVERVIEW 2.1 · PIC18F1220 PIC18F1220 · PIC18F1320 PIC18F1320 · PIC18F2220 PIC18F2220 · PIC18F2320 PIC18F2320 · PIC18F4220 PIC18F4220 · PIC18F4320 PIC18F4320 2.0 Hardware Requirements In high voltage ICSP mode, these devices require two programmable power supplies: one for VDD and one for MCLR/VPP. Both supplies should have a minimum resolution of 0.25V. Refer to Section 6.0 for additional hardware parameters. This document includes the programming specifications for the following devices: 2.1.1 LOW VOLTAGE ICSP PROGRAMMING PROGRAMMING OVERVIEW In low voltage ICSP mode, these devices can be programmed using a VDD source in the operating range. This only means that MCLR/VPP does not have to be brought to a different voltage, but can instead be left at the normal operating voltage. Refer to Section 6.0 for additional hardware parameters. These devices can be programmed using the high voltage In-Circuit Serial ProgrammingTM (ICSPTM) method, or the low voltage ICSP method; both while in the user's system. The low voltage ICSP method is slightly different than the high voltage method and these differences are noted where applicable. This programming specification applies to these devices in all package types. TABLE 2-1: 2.2 Pin Diagrams The programming pin descriptions for these devices are shown in Table 2-1, and pin diagrams are shown in Figure 2-1 through Figure 2-3. The pin descriptions of these diagrams do not represent the complete functionality of the device types. One should refer to the appropriate device data sheet for complete pin descriptions. PIN DESCRIPTIONS (DURING PROGRAMMING) During Programming Pin Name Function Pin Type MCLR/VPP/RA5(2) VPP P High Voltage Programming Enable Pin Description VDD VDD P Power Supply VSS VSS P Ground Low Voltage ICSP Input when LVP Configuration bit equals `1' (1) RB5 PGM I RB6 PGC I Serial Clock RB7 PGD I/O Serial Data Legend: I = Input, O = Output, P = Power Note 1: See Section 5.3 for more detail. 2: RA5 is only available on the PIC18F1X20 PIC18F1X20. 2002 Microchip Technology Inc. Preliminary DS39592B-page 1 PIC18FX220/X320 PIC18FX220/X320 PIC18F4X20 PIC18F4X20 44-PIN 44-PIN TQFP 44 43 42 41 40 39 38 37 36 35 34 RC6/TX/CK RC5/SDO RC4/SDI/SDA RD3/PSP3 RD2/PSP2 RD1/PSP1 RD0/PSP0 RC3/SCK/SCL RC2/CCP1/P1A RC1/T1OSI/CCP2 NC FIGURE 2-1: 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 PIC18F4X20 PIC18F4X20 NC RC0/T1OSO/T1CKI OSC2/CLKO/RA6 OSC1/CLKI/RA7 VSS VDD RE2/AN7/CS RE1/AN6/WR RE0/AN5/RD RA5/AN4/SS/LVDIN/C2OUT RA4/T0CKI/C1OUT NC NC RB4/AN11/KBI0 RB4/AN11/KBI0 RB5/KBI1/PGM RB6/KBI2/PGC RB7/KBI3/PGD MCLR/VPP/RE3 RA0/AN0 RA1/AN1 RA2/AN2/VREF -/CVREFRA3/AN3/VREF+ 22 21 20 19 18 17 16 15 14 13 12 RC7/RX/DT RD4/PSP4 RD5/PSP5/P1B RD6/PSP6/P1C RD7/PSP7/P1D VSS VDD RB0/AN12/INT0 RB0/AN12/INT0 RB1/AN10/INT1 RB1/AN10/INT1 RB2/AN8/INT2 RB3/AN9/CCP2* * Alternate pinout for CCP2 is enabled by a fuse. PIC18F4X20 PIC18F4X20 40-PIN 40-PIN PDIP (600 MIL) MCLR/VPP/RE3 RA0/AN0 RA1/AN1 RA2/AN2/VREF-/CVREF RA3/AN3/VREF+ RA4/T0CKI RA5/AN4/SS/LVDIN RE0/AN5/RD RE1/AN6/WR RE2/AN7/CS VDD VSS OSC1/CLKI/RA7 OSC2/CLKO/RA6 RC0/T1OSO/T13CKI RC0/T1OSO/T13CKI RC1/T1OSI/CCP2 RC2/CCP1/P1A RC3/SCK/SCL RD0/PSP0 RD1/PSP1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 PIC18F4X20 PIC18F4X20 FIGURE 2-2: 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 RB7/KBI3/PGD RB6/KBI2/PGC RB5/KBI1/PGM RB4/AN11/KBI0 RB4/AN11/KBI0 RB3/AN9/CCP2* RB2/AN8/INT2 RB1/AN10/INT1 RB1/AN10/INT1 RB0/AN12/INT0 RB0/AN12/INT0 VDD VSS RD7/PSP7/P1D RD6/PSP6/P1C RD5/PSP5/P1B RD4/PSP4 RC7/RX/DT RC6/TX/CK RC5/SDO RC4/SDI/SDA RD3/PSP3 RD2/PSP2 * Alternate pinout for CCP2 is enabled by a fuse. DS39592B-page 2 Preliminary 2002 Microchip Technology Inc. PIC18FX220/X320 PIC18FX220/X320 PIC18F2X20 PIC18F2X20 28-PIN 28-PIN SDIP (300 MIL), SOIC MCLR/VPP/RE3 RA0/AN0 RA1/AN1 RA2/AN2/VREF-/CVREF RA3/AN3/VREF+ RA4/T0CKI/C1OUT RA5/AN4/SS/LVDIN/C2OUT VSS OSC1/CLKI/RA7 OSC2/CLKO/RA6 RC0/T1OSO/T13CKI RC0/T1OSO/T13CKI RC1/T1OSI/CCP2 RC2/CCP1 RC3/SCK/SCL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 PIC18F2X20 PIC18F2X20 FIGURE 2-3: RB7/KBI3/PGD RB6/KBI2/PGC RB5/KBI1/PGM RB4/AN11/KBI0 RB4/AN11/KBI0 RB3/AN9/CCP2* RB2/AN8/INT2 RB1/AN10/INT1 RB1/AN10/INT1 RB0/AN12/INT0 RB0/AN12/INT0 VDD VSS RC7/RX/DT RC6/TX/CK RC5/SDO RC4/SDI/SDA * Alternate pinout for CCP2 is enabled by a fuse. FIGURE 2-4: PIC18F1X20 PIC18F1X20 18-PIN 18-PIN PDIP, SOIC 18 RB3/CCP1A/P1A 2 17 RB2/P1B/INT2 RA4/T0CKI 3 16 OSC1/CLKI/RA7 MCLR/VPP/RA5 4 15 OSC2/CLKO/RA6 Vss/AVss 5 14 VDD/AVDD RA2/AN2/VREF- 6 13 RB7/PGD/T1OSI/P1D RA3/AN3/VREF+ 7 12 RB6/PGC/T1OSO/T1CKI/P1C RB0/AN4/INT0 8 11 RB5/PGM RB1/AN5/TX/CK/INT1 FIGURE 2-5: 1 9 10 RB4/AN6/RX/DT PIC18F1X20 PIC18F1X20 RA0/AN0 RA1/AN1/LVDIN PIC18F1X20 PIC18F1X20 20-PIN 20-PIN SSOP 1 20 RB3/CCP1A/P1A 2 19 RB2/P1B/INT2 RA4/T0CKI 3 18 OSC1/CLKI/RA7 MCLR/VPP/RA5 4 17 OSC2/CLKO/RA6 VSS 5 16 VDD AVSS 6 15 AVDD RA2/AN2/VREF - 7 14 RB7/PGD/T1OSI/P1D RA3/AN3/VREF+ 8 13 RB6/PGC/T1OSO/T1CKI/P1C RB0/AN4/INT0 9 12 RB5/PGM 10 11 RB4/AN6/RX/DT RB1/AN5/TX/CK/INT1 2002 Microchip Technology Inc. PIC18F1X20 PIC18F1X20 RA0/AN0 RA1/AN1/LVDIN Preliminary DS39592B-page 3 PIC18FX220/X320 PIC18FX220/X320 RA0/AN0 NC RB3/CCP1A RB2/P1B/INT2 NC 25 24 23 22 RA4/T0CKI RA1/AN1/LVDIN 26 27 PIC18F1X20 PIC18F1X20 28-PIN 28-PIN QFN 28 FIGURE 2-6: MCLR/VPP/RA5 1 21 RA7/OSC1/CLKI NC VSS 2 20 RA6/OSC2/CLKO 3 19 VDD NC 4 18 NC AVSS 5 17 AVDD NC 6 16 RB7/PGD/T1OSI/P1D/KBI3 RA2/AN2/VREF- 7 15 RB6/PGC/T1OSO/T1CKI/P1C/KBI2 11 12 13 14 NC RB4/AN6/RX/DT/KBI0 RB5/PGM/KBI1 NC 9 RB0/AN4/INT0 10 8 RA3/AN3/VREF + DS39592B-page 4 RB1/AN5/TX/CK/INT1 PIC18F1X20 PIC18F1X20 Preliminary 2002 Microchip Technology Inc. PIC18FX220/X320 PIC18FX220/X320 2.3 Locations 300001h through 30000Dh are reserved for the configuration words. These words may be set to select various device options, and are described in Section 5.0. These configuration words read out normally, even after code protected. Memory Map The code memory space extends from 0000h to 1FFFh (8 Kbytes) in a single 8-Kbyte panel. Addresses 0000h through 01FFh, however, define a "Boot Block" region that is treated separately from Panel 1. All code memory is on-chip. Locations 3FFFFEh and 3FFFFFh are reserved for the device ID words. These words may be used by the programmer to identify what device type is being programmed, and are described in Section 5.0. These configuration words read out normally, even after code protection. A user may store identification information (ID) in eight ID registers. These ID registers are mapped in addresses 200000h through 200007h. The ID locations read out normally, even after code protection is applied. TABLE 2-2: IMPLEMENTATION OF CODE MEMORY Device Code Memory Size (Bytes) Data EEPROM Size (Bytes) PIC18F1220 PIC18F1220 0000h - 0FFFh (4K) 000 - 0FFh (256) PIC18F2220 PIC18F2220 0000h - 0FFFh (4K) 000 - 0FFh (256) PIC18F4220 PIC18F4220 0000h - 0FFFh (4K) 000 - 0FFh (256) PIC18F1320 PIC18F1320 0000h - 1FFFh (8K) 000 - 0FFh (256) PIC18F2320 PIC18F2320 0000h - 1FFFh (8K) 000 - 0FFh (256) PIC18F4320 PIC18F4320 0000h - 1FFFh (8K) 000 - 0FFh (256) FIGURE 2-7: MEMORY MAP FOR PIC18F2X20/PIC18F4X20 PIC18F2X20/PIC18F4X20 8 Kbytes ID Location 1 ID Location 2 ID Location 3 ID Location 4 ID Location 5 ID Location 6 ID Location 7 ID Location 8 300000h 300001h 300002h 300003h 3FFFFEh 3FFFFFh Device ID1 Device ID2 Boot Block Block 0 Block 1 CONFIG1L CONFIG1H CONFIG2L CONFIG2H 4 Kbytes Boot Block Block 0 0000h 200h 200000h 200001h 200002h 200003h 200004h 200005h 200006h 200007h Block 1 07FFh 0FFFh Block 2 17FFh Block 3 1FFFh Unimplemented Unimplemented Read as 0's Read as 0's 200000h 3FFFFFh 2002 Microchip Technology Inc. Preliminary DS39592B-page 5 PIC18FX220/X320 PIC18FX220/X320 FIGURE 2-8: MEMORY MAP FOR PIC18F1X20 PIC18F1X20 8 Kbytes 0000h 200h 200000h 200001h 200002h 200003h 200004h 200005h 200006h 200007h ID Location 1 ID Location 2 ID Location 3 ID Location 4 ID Location 5 ID Location 6 ID Location 7 ID Location 8 300000h 300001h 300002h 300003h CONFIG1L CONFIG1H CONFIG2L CONFIG2H 3FFFFEh 3FFFFFh Device ID1 Device ID2 07FFh 4 Kbytes Boot Block Boot Block Block 0 Block 0 Block 1 0FFFh 17FFh Block 1 1FFFh Unimplemented Unimplemented Read as 0's Read as 0's 200000h 3FFFFFh 2.3.1 MEMORY ADDRESS POINTER 2.4 Memory in the address space 000000h to 3FFFFFh is addressed via the Table Pointer, which is comprised of three pointer registers: · TBLPTRU, at address 0FF8h · TBLPTRH, at address 0FF7h · TBLPTRL, at address 0FF6h TBLPTRU TBLPTRH TBLPTRL Addr[21:16] Addr[15:8] High Level Overview of the Programming Process Figure 2-9 shows the high level overview of the Programming Process. The device is first checked to see if it is blank; if it is not, a bulk erase is performed. Next, the Program Memory, ID locations and Data EEPROM are written. These memories are then verified to ensure that programming was successful. If no errors are detected, the configuration bits are then written and verified. Addr[7:0] DS39592B-page 6 Preliminary 2002 Microchip Technology Inc. PIC18FX220/X320 PIC18FX220/X320 FIGURE 2-9: HIGH LEVEL PROGRAMMING FLOW Start Blank Check Is part blank ? No Perform Bulk Erase Yes Write Program Memory Write ID Loc's Write EEPROM Verify Program Verify IDs Verify EEPROM Write Configuration Bits Verify Configuration Bits Done 2002 Microchip Technology Inc. Preliminary DS39592B-page 7 PIC18FX220/X320 PIC18FX220/X320 2.5 Entering High Voltage ICSP Program/Verify Mode 2.6 The high voltage ICSP Program/Verify mode is entered by holding PGC and PGD low, and then raising MCLR/ VPP to VIHH (high voltage). Once in this mode, the Code Memory, Data EEPROM, ID locations and configuration bits can be accessed and written in serial fashion. The sequence that enters the device into the Programming/Verify mode places all unused I/Os in the high impedance state. FIGURE 2-10: ENTERING HIGH VOLTAGE PROGRAM/ VERIFY MODE P13 P12 D110 Serial Program/Verify Operation The PGC pin is used as a clock input pin and the PGD pin is used for entering command bits and data input/ output during serial operation. Commands and data are transmitted on the rising edge of PGC, latched on the falling edge of PGC, and are sent Least Significant bit (LSb) first. 2.6.1 4-BIT COMMANDS All instructions are 20-bits, consisting of a leading 4-bit command followed by a 16-bit operand, which depends on the type of command being executed. To input a command, PGC is cycled four times. The commands needed for programming and verification are shown in Table 2-3. TABLE 2-3: MCLR/VPP COMMANDS FOR PROGRAMMING 4-Bit Command Description VDD PGD Core Instruction (Shift in 16-bit instruction) 0000 PGC Shift out TABLAT register 0010 Table Read 1000 Table Read, post-increment 1001 Table Read, post-decrement 1010 Table Read, pre-increment 1011 Table Write 1100 Table Write, post-increment by 2 1101 Table Write, post-decrement by 2 1110 Table Write, start programming 1111 PGD = Input 2.5.1 ENTERING LOW VOLTAGE ICSP PROGRAM/VERIFY MODE When the LVP configuration bit is 1 (see Section 5.3), the low voltage ICSP mode is enabled. Low voltage ICSP Program/Verify mode is entered by holding PGC and PGD low, placing a logic high on PGM, and then raising MCLR/V PP to VIH. In this mode, the RB5/PGM pin is dedicated to the programming function and ceases to be a general purpose I/O pin. The sequence that enters the device into the Programming/Verify mode places all unused I/Os in the high impedance state. FIGURE 2-11: ENTERING LOW VOLTAGE PROGRAM/ VERIFY MODE P15 P12 Depending on the 4-bit command, the 16-bit operand represents 16-bits or 8-bits of data. Throughout this specification, commands and data are presented as illustrated in Table 2-4. The 4-bit command is shown MSb first. The command operand, or "Data Payload" is shown . Figure 2-12 demonstrates how to serially present a 20-bit command/operand to the device. TABLE 2-4: VIH MCLR/VPP SAMPLE COMMAND SEQUENCE 4-Bit Command Data Payload 1101 3C 40 VDD VIH Core Instruction Table Write, post-increment by 2 PGM PGD PGC PGD = Input DS39592B-page 8 Preliminary 2002 Microchip Technology Inc. PIC18FX220/X320 PIC18FX220/X320 FIGURE 2-12: TABLE WRITE, POST INCREMENT TIMING (1101) P2 1 P2a P2b 2 3 4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 2 1 3 4 PGC P5a P5 P4 P3 PGD 1 0 1 1 0 0 0 0 0 0 0 4-bit Command (LSb first) 1 0 0 4 0 1 C 16-bit Data Payload (LSb first) 1 1 1 0 0 n n n n 3 Fetch Next 4-bit Command PGD = Input 2.6.2 CORE INSTRUCTION The core instruction passes a 16-bit instruction to the CPU core for execution. This is needed to setup registers, as appropriate for use with other commands. If the instruction is a 2-word, 2-cycle instruction, another core instruction command is required with the second word of the instruction. The instruction will complete when a third 4-bit command has been loaded. If the instruction is a 1-word, 1-cycle instruction, it will be executed while the next command is clocked in. 2002 Microchip Technology Inc. Preliminary DS39592B-page 9 PIC18FX220/X320 PIC18FX220/X320 3.0 DEVICE PROGRAMMING 3.2 3.1 Blank Check Erasing Code or Data EEPROM is accomplished by writing an "erase option" to address 3C0004h. Code memory may be erased portions at a time, or the user may erase the entire device in one action. "Bulk Erase" operations will also clear any code protect settings associated with the memory block erased. Erase options are detailed in Table 3-1. The term "Blank Check" means to verify that the device has no programmed memory cells. All memories must be verified: Code memory, Data EEPROM, ID locations and configuration bits. The Device ID registers (3FFFFEh:3FFFFFh) should be ignored. A "blank" or "erased" memory cell will read as a `1'. So, "Blank Checking" a device merely means to verify that all bytes read as FFh, except the configuration bits. Unused (reserved) configuration bits will read `0' (programmed). Refer to Table 5-2 for blank configuration expected data for the various devices. High Voltage ICSP Bulk Erase TABLE 3-1: BULK ERASE OPTIONS Description Data Chip Erase 80h Erase Data EEPROM 81h If it is determined that the device is not blank, then the device should be Bulk Erased (see Section 3.2) before any attempt to program is made. Erase Boot Block 83h Erase Block 0 88h Erase Block 1 89h Given that "Blank Checking" is merely code and data EEPROM verification with FFh as the expected data, refer to Section 4.1 and Section 4.3 for implementation details. Erase Block 2 8Ah Erase Block 3 8Bh FIGURE 3-1: BLANK CHECK FLOW Start The actual Bulk Erase function is a self-timed operation. Once the erase has started (falling edge of the 4th PGC after the WRITE command), serial execution will cease until the erase completes (parameter P11). During this time, PGC may continue to toggle, but PGD must be held low. The code sequence to erase the entire device is shown in Table 3-2 and the flow chart is shown in Figure 3-2. Blank Check Device Note: Is device blank? Yes Continue A bulk erase is the only way to reprogram code protect bits from an on-state to an off-state. TABLE 3-2: BULK ERASE COMMAND SEQUENCE No 4-bit Data Command Payload Bulk Erase Device Blank Check Device Is device blank? No Abort DS39592B-page 10 Yes Continue 0000 0000 0000 0000 0000 0000 1100 0E 6E 0E 6E 0E 6E 00 0000 0000 00 00 00 00 Preliminary 3C F8 00 F7 04 F6 80 Core Instruction MOVLW 3Ch MOVWF TBLPTRU MOVLW 00h MOVWF TBLPTRH MOVLW 04h MOVWF TBLPTRL Write 80h TO 3C0004h to erase entire device. NOP Hold PGD low until erase completes. 2002 Microchip Technology Inc. PIC18FX220/X320 PIC18FX220/X320 FIGURE 3-2: BULK ERASE FLOW Start Load Address Pointer to 3C0004h Write 80h to Erase Entire Device Delay P11+P10 Time Done FIGURE 3-3: BULK ERASE TIMING P10 1 2 3 4 2 1 15 16 1 2 3 4 1 2 15 16 1 2 3 1 2 n 4 n PGC PGD 0 0 1 1 4-bit Command P5 P5a P5 0 0 0 0 16-bit Data Payload 0 0 0 0 P5a 0 4-bit Command 0 0 0 NOP P11 0 0 0 0 4-bit Command Erase Time 16-bit Data Payload PGD = Input 3.2.1 LOW VOLTAGE ICSP BULK ERASE When using low voltage ICSP, the part must be supplied by the voltage specified in parameter D111, if a bulk erase is to be executed. All other bulk erase details as described above apply. If it is determined that a program memory erase must be performed at a supply voltage below the bulk erase limit, refer to the erase methodology described in Section 3.3.1. If it is determined that a data EEPROM erase must be performed at a supply voltage below the bulk erase limit, follow the methodology described in Section 3.4 and write zeroes to the array. 3.3 Code Memory Programming Programming code memory is accomplished by first loading data into the appropriate write buffers and then initiating a programming sequence. Each panel in the code memory space (see Figure 2-8) has an 8-byte deep write buffer that must be loaded prior to initiating 2002 Microchip Technology Inc. a write sequence. The actual memory write sequence takes the contents of these buffers and programs the associated EEPROM code memory. The programming duration is externally timed and is controlled by PGC. After a "Start Programming" command is issued (4-bit command 1111), a NOP is issued where the 4th PGC is held high for the duration of the programming time, P9 (see Figure 3-6). After PGC is brought low, the programming sequence is terminated. PGC must be held low for the time specified by parameter P10 to allow high voltage discharge of the memory array. The code sequence to program a device is shown in Table 3-3. The flow chart shown in Figure 3-5 depicts the logic necessary to completely write a device. Note: Preliminary The TBLPTR register must contain the same offset value when initiating the programming sequence as it did when the write buffers were loaded. DS39592B-page 11 PIC18FX220/X320 PIC18FX220/X320 FIGURE 3-4: ERASE AND WRITE BOUNDARIES Unimplemented Read as `0' Panel 1 8-byte Write Buffer TBLPTR = 0 TBLPTR = 7 TBLPTR = 6 TBLPTR = 5 TBLPTR = 4 TBLPTR = 3 TBLPTR = 2 TBLPTR = 1 TBLPTR = 0 Erase Region (64 bytes) Offset = TBLPTR Offset = TBLPTR Note: TBLPTR = TBLPTRU:TBLPTRH:TBLPTRL. DS39592B-page 12 Preliminary 2002 Microchip Technology Inc. PIC18FX220/X320 PIC18FX220/X320 TABLE 3-3: 4-bit Command WRITE CODE MEMORY CODE SEQUENCE Data Payload Core Instruction Step 1: Direct access to code memory. 0000 0000 8E A6 9C A6 BSF EECON1, EEPGD BCF EECON1, CFGS Step 2: Load write buffer for Panel 1. 0000 0000 0000 0000 0000 0000 1101 1101 1101 1100 0000 0E 6E F8 0E 6E F7 0E 6E F6 00 00 MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF Write Write Write Write NOP - TBLPTRU TBLPTRH TBLPTRL 2 bytes and post-increment address by 2 2 bytes and post-increment address by 2 2 bytes and post-increment address by 2 2 bytes and start programming hold PGC high for time P9 To continue writing data, repeat step 2, where the address pointer is incremented by 8 at each iteration of the loop. FIGURE 3-5: PROGRAM CODE MEMORY FLOW Start LoopCount = 0 Load 8 bytes to Panel Write Buffer at Start Write Sequence and Hold PGC High Until Done LoopCount = LoopCount + 1 Delay P9+P10 Time for Write to Occur No All locations done? Yes Done 2002 Microchip Technology Inc. Preliminary DS39592B-page 13 PIC18FX220/X320 PIC18FX220/X320 FIGURE 3-6: TABLE WRITE AND START PROGRAMMING INSTRUCTION TIMING (1111) P10 1 2 3 4 1 2 3 4 5 6 15 16 1 2 3 4 PGC 3 2 P5a P5 PGD 1 P9 1 1 1 1 4-bit Command n n n n n n n n 16-bit Data Payload 0 0 0 4-bit Command 0 0 Programming Time 0 0 16-bit Data Payload PGD = Input 3.3.1 MODIFYING CODE MEMORY All of the programming examples up to this point have assumed that the device is blank prior to programming. In fact, if the device is not blank, the direction has been to completely erase the device via a Bulk Erase operation (see Section 3.2) operation. It may be the case, however, that the user wishes to modify only a section of an already programmed device. In such a situation, erasing the entire device is not a realistic option. The minimum amount of data that can be written to the device is 8-bytes. This is accomplished by loading the 8-byte write buffer for the panel, and then initiating a write sequence. In this case, however, it is assumed that the address space to be written already has data in it (i.e., it is not blank). The minimum amount of code memory that may be erased at a given time is one row of 64 bytes and it is selected using the TBLPTR registers. The sixth LSb of the TBLPTR address is ignored. The EECON1 register must then be used to erase the 64-byte target space prior to writing the data. DS39592B-page 14 When using the EECON1 register to act on code memory, the EEPGD bit must be set (EECON1 = 1) and the CFGS bit must be cleared (EECON1 = 0). The WREN bit must be set (EECON1 = 1) to enable writes of any sort (e.g., erases), and this must be done prior to initiating a write sequence. The FREE bit must be set (EECON1 = 1) in order to erase the program space being pointed to by the Table Pointer. The erase sequence is initiated by the setting the WR bit (EECON1 = 1). It is strongly recommended that the WREN bit be set only when absolutely necessary. To help prevent inadvertent writes when using the EECON1 register, EECON2 is used to "enable" the WR bit. This register must be sequentially loaded with 55h and then, AAh, immediately prior to asserting the WR bit in order for the write to occur. The erase will begin on the falling edge of the 4th PGC after the WR bit is set. After the erase sequence terminates, PGC must still be held low for the time specified by parameter P10 to allow high voltage discharge of the memory array. Preliminary 2002 Microchip Technology Inc. PIC18FX220/X320 PIC18FX220/X320 TABLE 3-4: MODIFYING CODE MEMORY 4-bit Command Data Payload Core Instruction Step 1: Direct access to code memory. 0000 0000 8E A6 9C A6 BSF EECON1, EEPGD BCF EECON1, CFGS Step 2: Set the Table Pointer for the block to be erased. 0000 0000 0000 0000 0000 0000 0E 6E 0E 6E 0E 6E F8 F7 F6 MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF TBLPTRU TBLPTRH TBLPTRL Step 3: Enable memory writes and setup an erase. 0000 0000 84 A6 88 A6 BSF EECON1, WREN BSF EECON1, FREE Step 4: Perform FLASH unlock sequence. 0000 0000 0000 0000 0E 6E 0E 6E 55 A7 AA A7 MOVLW MOVWF MOVLW MOVWF 0X55 EECON2 0XAA EECON2 Step 5: Initiate Erase. 0000 0000 82 A6 00 00 BSF EECON1, WR NOP Step 6: Wait for P11+P10 and then disable writes. 0000 94 A6 BCF EECON1, WREN Step 7: Load write buffer for Panel. 1101 1101 1101 1111 0000 00 00 Write Write Write Write NOP - 2 bytes and post-increment address by 2 2 bytes and post-increment address by 2 2 bytes and post-increment address by 2 2 bytes and start programming hold PGC high for time P9 at the end of 4-bit command To continue writing data, repeat step 7, where the address pointer is incremented by 8 at each iteration of the loop. 2002 Microchip Technology Inc. Preliminary DS39592B-page 15 PIC18FX220/X320 PIC18FX220/X320 3.4 FIGURE 3-7: Data EEPROM Programming PROGRAM DATA FLOW Data EEPROM is accessed one byte at a time via an address pointer, EEADR, and a data latch, EEDATA. Data EEPROM is written by loading EEADR with the desired memory location, EEDATA with the data to be written, and initiating a memory write by appropriately configuring the EECON1 and EECON2 registers. A byte write automatically erases the location and writes the new data (erase-before-write). Start Set Address Set Data When using the EECON1 register to perform a data EEPROM write, the EEPGD bit must be cleared (EECON1 = 0) and the CFGS bit must be cleared (EECON1 = 0). The WREN bit must be set (EECON1 = 1) to enable writes of any sort, and this must be done prior to initiating a write sequence. Enable Write Unlock Sequence 55h - EECON2 AAh - EECON2 To help prevent inadvertent writes when using the EECON1 register, EECON2 is used to "enable" the WR bit. This register must be sequentially loaded with 55h and then, AAh, immediately prior to asserting the WR bit in order for the write to occur. The write sequence is initiated by the setting the WR bit (EECON1 = 1). It is strongly recommended that the WREN bit be set only when absolutely necessary. Start Write Sequence Delay P11+P10 for Write to Occur No The write will begin on the falling edge of the 4th PGC after the WR bit is set. Done? Yes After the programming sequence terminates, PGC must still be held low for the time specified by parameter P10 to allow high voltage discharge of the memory array. FIGURE 3-8: Done DATA EEPROM WRITE TIMING P10 1 2 3 4 1 2 15 16 1 2 4 3 1 2 15 16 1 2 3 1 4 2 PGC P5 PGD 0 0 0 0 4-bit Command P5 P5a 0 BSF EECON1, WR 0 0 0 4-bit Command P5a 0 0 0 16-bit Data Payload 0 P11 0 0 0 0 n 4-bit Command Data EEPROM Write Time n 16-bit Data Payload PGD = Input DS39592B-page 16 Preliminary 2002 Microchip Technology Inc. PIC18FX220/X320 PIC18FX220/X320 TABLE 3-5: PROGRAMMING DATA MEMORY 4-bit Command Data Payload Core Instruction Step 1: Direct access to data EEPROM. 0000 0000 9E A6 9C A6 BCF EECON1, EEPGD BCF EECON1, CFGS Step 2: Set the data EEPROM address pointer. 0000 0000 0E 6E A9 MOVLW MOVWF EEADR Step 3: Load the data to be written. 0000 0000 0E 6E A8 MOVLW MOVWF EEDATA Step 4: Enable memory writes. 0000 84 A6 BSF EECON1, WREN Step 5: Perform Data EEPROM unlock sequence. 0000 0000 0000 0000 0E 6E 0E 6E 55 A7 AA A7 MOVLW MOVWF MOVLW MOVWF 0X55 EECON2 0XAA EECON2 Step 6: Initiate write. 0000 0000 0000 82 A6 00 00 00 00 BSF EECON1, WR NOP NOP Step 7: Wait for P11 and then disable writes. 0000 94 A6 BCF EECON1, WREN Repeat steps 2 through7 to write more data. 2002 Microchip Technology Inc. Preliminary DS39592B-page 17 PIC18FX220/X320 PIC18FX220/X320 3.5 ID Location Programming The ID locations are programmed much like the code memory. The single panel that will be written will automatically be enabled, based on the value of the Table Pointer. The ID registers are mapped in addresses 200000h through 200007h. These locations read out normally, even after code protection. Note: Table 3-6 demonstrates the code sequence required to write the ID locations. The Table Pointer must be manually set to 200000h (base address of the ID locations). The post-increment feature of the Table Read 4-bit command may not be used to increment the Table Pointer to 200000h. The post-increment feature may then be used to increment to 200001h, 200002h . . The user must fill the 8-byte data buffer for the panel. TABLE 3-6: WRITE ID SEQUENCE 4-bit Command Data Payload Core Instruction Step 1: Direct access to code memory. 0000 0000 8E A6 9C A6 BSF EECON1, EEPGD BCF EECON1, CFGS Step 2: Load write buffer. 0000 0000 0000 0000 0000 0000 1101 1101 1101 1111 0000 0E 20 6E F8 0E 00 6E F7 0E 00 6E F6 00 00 DS39592B-page 18 MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF Write Write Write Write NOP - 20h TBLPTRU 00h TBLPTRH 00h TBLPTRL 2 bytes and post-increment address by 2 2 bytes and post-increment address by 2 2 bytes and post-increment address by 2 2 bytes and start programming hold PGC high for time P9 Preliminary 2002 Microchip Technology Inc. PIC18FX220/X320 PIC18FX220/X320 3.6 Boot Block Programming 3.7 The Boot Block segment is programmed in exactly the same manner as the ID locations (see Section 3.5). The code sequence detailed in Table 3-6 should be used, except that the address data used in "Step 2" will be in the range 000000h to 0001FFh. TABLE 3-7: 4-bit Command Configuration Bits Programming Unlike code memory, the configuration bits are programmed a byte at a time. The "Table Write, Begin Programming" 4-bit command (1111) is used, but only 8 bits of the following 16-bit payload will be written. The LSB of the payload will be written to even addresses, and the MSB will be written to odd addresses. The code sequence to program two consecutive configuration locations is shown in Table 3-7. SET ADDRESS POINTER TO CONFIGURATION LOCATION Data Payload Core Instruction Step 1: Direct access to configuration memory. 0000 0000 8E A6 8C A6 BSF EECON1, EEPGD BSF EECON1, CFGS Step 2: Position the program counter.(1) 0000 0000 EF 00 F8 00 GOTO 0x100000 Step 3: Set Table Pointer for configuration word to be written. Write even/odd addresses. 0000 0000 0000 0000 0000 0000 1111 0000 0000 1111 0000 0E 30 6E F8 0E 00 6E F7 0E 00 6E F6 00 00 2A F6 00 00 MOVLW 30h MOVWF TBLPTRU MOVLW 00h MOVWF TBLPRTH MOVLW 00h MOVWF TBLPTRL Load 2 bytes and start programming NOP - hold PGC high for time P9 INCF TBLPTRL Load 2 bytes and start programming NOP - hold PGC high for time P9 Note 1: If the code protection bits are programmed while the program counter resides in the same block, then the interaction of code protection logic may prevent further table write. To avoid this situation, move the program counter outside the code protection area (e.g., GOTO 0x100000). 2: Enabling the write protection of configuration bits (WRTC = 0 in CONFIG6H) will prevent further writing of configuration bits. Always write all the configuration bits before enabling the write protection for configuration bits. FIGURE 3-9: CONFIGURATION PROGRAMMING FLOW Start Start Load Even Configuration Address Load Odd Configuration Address Program LSB Program MSB Delay P9 Time for Write Delay P9 Time for Write Done Done 2002 Microchip Technology Inc. Preliminary DS39592B-page 19 PIC18FX220/X320 PIC18FX220/X320 4.0 READING THE DEVICE 4.1 Read Data EEPROM Memory FIGURE 4-1: READ DATA EEPROM FLOW Start Data EEPROM is accessed one byte at a time via an address pointer, EEADR, and a data latch, EEDATA. Data EEPROM is read by loading EEADR with the desired memory location and initiating a memory read by appropriately configuring the EECON1 register. The data will be loaded into EEDATA, where it may be serially output on PGD via the 4-bit command 0010 (shift out data holding register). A delay of P6 must be introduced after the falling edge of the 8th PGC of the operand to allow PGD to transition from an input to an output. During this time, PGC must be held low (see Figure 4-2). Set Address Read Byte Move to TABLAT The command sequence to read a single byte of data is shown in Table 4-1. Shift Out Data No Done? Yes Done TABLE 4-1: READ DATA EEPROM MEMORY 4-bit Command Data Payload Core Instruction Step 1: Direct access to data EEPROM. 0000 0000 9E A6 9C A6 BCF EECON1, EEPGD BCF EECON1, CFGS Step 2: Set the data EEPROM address pointer. 0000 0000 0E 6E A9 MOVLW MOVWF EEADR Step 3: Initiate a memory read. 0000 80 A6 BSF EECON1, RD Step 4: Load data into the serial data holding register. MOVF EEDATA, W, 0 MOVWF TABLAT Shift Out Data(1) 50 A8 6E F5 0000 0000 0010 Note 1: The is undefined. The is the data. FIGURE 4-2: 1 SHIFT OUT DATA HOLDING REGISTER TIMING (0010) 2 3 4 1 2 3 4 5 6 7 9 8 10 11 12 13 14 15 16 1 2 3 4 PGC P5 P5a P6 P14 PGD 0 1 0 LSb 1 0 2 3 4 5 Shift Data Out PGD = Input DS39592B-page 20 PGD = Output Preliminary 6 MSb n n n n Fetch Next 4-bit Command PGD = Input 2002 Microchip Technology Inc. PIC18FX220/X320 PIC18FX220/X320 4.2 P6 must be introduced after the falling edge of the 8th PGC of the operand to allow PGD to transition from an input to an output. During this time, PGC must be held low (see Table 4-2). This operation also increments the Table Pointer by one, pointing to the next byte in code memory for the next read. Read Code Memory, ID Locations, and Configuration Bits Code memory is accessed one byte at a time, via the 4-bit command 1001 (Table Read, post increment). The contents of memory pointed to by the Table Pointer (TBLPTRU:TBLPTRH:TBLPTRL) are loaded into the Table Latch and then serially output on PGD. This technique will work to read any memory in the 000000h to 3FFFFFh address space, so it also applies to the reading of the ID and configuration registers. The 4-bit command is shifted in LSb first. The Read is executed during the next 8 clocks, then shifted out on PGD during the last 8 clocks, LSb to MSb. A delay of TABLE 4-2: READ CODE MEMORY SEQUENCE 4-bit Command Data Payload Core Instruction Step 1: Set Table Pointer. 0E 6E 0E 6E 0E 6E 0000 0000 0000 0000 0000 0000 MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF F8 F7 F6 Addr[21:16] TBLPTRU TBLPTRH TBLPTRL Step 2: Read memory into Table Latch and then shift out on PGD, LSb to MSb. 1001 00 00 FIGURE 4-3: 1 TBLRD *+ TABLE READ POST INCREMENT INSTRUCTION TIMING (1001) 2 3 4 1 2 3 4 5 6 7 9 8 10 11 12 13 1 14 15 16 2 3 4 PGC P5 P5a P6 P14 PGD 1 0 0 LSb 1 1 2 3 4 5 Shift Data Out PGD = Input 2002 Microchip Technology Inc. PGD = Output Preliminary 6 MSb n n n n Fetch Next 4-bit Command PGD = Input DS39592B-page 21 PIC18FX220/X320 PIC18FX220/X320 4.3 Verify Code Memory and ID locations The verify step involves reading back the code memory space and comparing against the copy held in the programmer's buffer. Memory reads occur a single byte at a time, so two bytes must be read to compare against the word in the programmer's buffer. Refer to Section 4.2 for implementation details of reading code memory. FIGURE 4-4: The Table Pointer must be manually set to 200000h (base address of the ID locations). The post-increment feature of the Table Read 4-bit command may not be used to increment the Table Pointer to 200000h. The post-increment feature may then be used to increment to 200001h, 200002h . . VERIFY CODE MEMORY FLOW Start Set Pointer = 0 Set Pointer = 200000h Read Low Byte Read Low Byte Read High byte Read High byte Does word = expect data? Does No word = expect data? Failure, Report Error Yes No No Failure, Report Error Yes All code memory verified? No All ID locations verified? Yes Yes Done 4.4 Verify Configuration Bits 4.5 A configuration address may be read and output on PGD via the 4-bit command 1001. Configuration data is read and written in a byte-wise fashion, so it is not necessary to merge two bytes into a word prior to a compare. The result may then be immediately compared to the appropriate configuration data in the programmer's memory for verification. Refer to Section 4.2 for implementation details of reading configuration data. DS39592B-page 22 Verify Data EEPROM A data EEPROM address may be read via a sequence of core instructions (4-bit command 0000) and then output on PGD via the 4-bit command 0010 (shift out data holding register). The result may then be immediately compared to the appropriate data in the programmer's memory for verification. Refer to Section 4.1 for implementation details of reading data EEPROM. Preliminary 2002 Microchip Technology Inc. PIC18FX220/X320 PIC18FX220/X320 5.0 CONFIGURATION WORD 5.3 5.1 If Low Voltage Programming mode is not used, the LVP bit can be programmed to a `0' and RB5/PGM becomes a digital I/O pin. However, the LVP bit may only be programmed by entering the high voltage ICSP mode, where MCLR/VPP is raised to VIHH. Once the LVP bit is programmed to a `0', only the high voltage ICSP mode is available and only the high voltage ICSP mode can be used to program the device. ID Locations A user may store identification information (ID) in eight ID locations mapped in 200000h:200007h. It is recommended that the most significant nibble of each ID be 0Fh. In doing so, if the user code inadvertently tries to execute from the ID space, the ID data will execute as NOP. 5.2 Note 1: The normal high voltage ICSP mode is always available, regardless of the state of the LVP bit, by applying VIHH to the MCLR/VPP pin. 2: While in Low Voltage ICSP mode, the RB5 pin can no longer be used as a general purpose I/O. Device ID Word The device ID word for the devices is located at 3FFFFEh:3FFFFFh. These bits may be used by the programmer to identify what device type is being programmed and read out normally, even after code or read protected. TABLE 5-1: Low Voltage Programming (LVP) Bit The LVP bit in configuration register CONFIG4L enables low voltage ICSP programming. The LVP bit defaults to a `1' following an erase. The devices have several configuration words. Bits in these registers can be set or cleared to select various device configurations. All other memory areas should be programmed and verified prior to setting configuration words. These bits may be read out normally even after read or code protected. Tables 5-2, 5-3 and 5-4 provide information on various configuration bits. DEVICE ID VALUE Device Device ID Value DEVID2 DEVID1 PIC18F1220 PIC18F1220 07 111x xxxx PIC18F2220 PIC18F2220 05 100x xxxx PIC18F4220 PIC18F4220 05 101x xxxx PIC18F1320 PIC18F1320 07 110x xxxx PIC18F2320 PIC18F2320 05 000x xxxx PIC18F4320 PIC18F4320 05 001x xxxx 2002 Microchip Technology Inc. Preliminary DS39592B-page 23 PIC18FX220/X320 PIC18FX220/X320 TABLE 5-2: PIC18F2X20/PIC18F4X20 PIC18F2X20/PIC18F4X20 CONFIGURATION BITS AND DEVICE IDs File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Erased or "Blank" Value 300000h CONFIG1L - - - - - - - - 0000 0000 300001h CONFIG1H IESO FCMEM - - FOSC3 FOSC2 FOSC1 FOSC0 1100 1111 300002h CONFIG2L - - - - BORV1 BORV0 BOREN PWRTEN 0000 1111 300003h CONFIG2H - - - WDPS3 WDPS2 WDPS1 WDPS0 WDTEN 0001 1111 300004h CONFIG3L - - - - - - - - 0000 0000 300005h CONFIG3H MCLRE - - - - - PBADEN CCP2MX 1000 0011 300006h CONFIG4L DEBUG - - - - LVP - STVREN 1000 0101 300007h CONFIG4H - - - - - - - - 0000 0000 300008h CONFIG5L - - - - CP3 CP2 CP1 CP0 0000 1111 300009h CONFIG5H CPD CPB - - - - - - 1100 0000 30000Ah CONFIG6L - - - - WRT3 WRT2 WRT1 WRT0 0000 1111 30000Bh CONFIG6H WRTD WRTB WRTC - - - - - 1110 0000 30000Ch CONFIG7L - - - - EBTR3 EBTR2 EBTR1 EBTR0 0000 1111 - EBTRB - - - - - - 0100 0000 3FFFFEh DEVID1 30000Dh CONFIG7H DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0 Table 5-1 3FFFFFh DEVID2 DEV10 DEV10 DEV9 DEV8 DEV7 DEV6 DEV5 DEV4 DEV3 Table 5-1 TABLE 5-3: PIC18F1X20 PIC18F1X20 CONFIGURATION BITS AND DEVICE IDs File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Erased or "Blank" Value 300000h CONFIG1L - - - - - - - - 0000 0000 300001h CONFIG1H IESO FCMEM - - FOSC3 FOSC2 FOSC1 FOSC0 1100 1111 300002h CONFIG2L - - - - BORV1 BORV0 BOREN PWRTEN 0000 1111 300003h CONFIG2H - - - WDPS3 WDPS2 WDPS1 WDPS0 WDTEN 0001 1111 300004h CONFIG3L - - - - - - - - 0000 0000 300005h CONFIG3H MCLRE - - - - - - - 1000 0000 300006h CONFIG4L DEBUG - - - - LVP - STVREN 1000 0101 300007h CONFIG4H - - - - - - - - 0000 0000 300008h CONFIG5L - - - - - - CP1 CP0 0000 0011 300009h CONFIG5H CPD CPB - - - - - - 1100 0000 30000Ah CONFIG6L - - - - - - WRT1 WRT0 0000 0011 30000Bh CONFIG6H WRTD WRTB WRTC - - - - - 1110 0000 30000Ch CONFIG7L - - - - - - EBTR1 EBTR0 0000 0011 - EBTRB - - - - - - 0100 0000 3FFFFEh DEVID1 30000Dh CONFIG7H DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0 Table 5-1 3FFFFFh DEVID2 DEV10 DEV10 DEV9 DEV8 DEV7 DEV6 DEV5 DEV4 DEV3 Table 5-1 DS39592B-page 24 Preliminary 2002 Microchip Technology Inc. PIC18FX220/X320 PIC18FX220/X320 TABLE 5-4: Bit Name PIC18FX220/X320 PIC18FX220/X320 BIT DESCRIPTION Configuration Words Description IESO CONFIG1H Internal External Switch Over bit 1 = Internal External Switch Over mode enabled 0 = Internal External Switch Over mode disabled FCMEN CONFIG1H Fail-Safe Clock Monitor Enable bit 1 = Fail-Safe Clock Monitor enabled 0 = Fail-Safe Clock Monitor disabled FOSC3:FOSC0 CONFIG1H Oscillator Selection bits 11xx = External RC oscillator, CLKO function on RA6 101x = External RC oscillator, CLKO function on RA6 1001 = Internal RC oscillator, CLKO function on RA6, port function on RA7 1000 = Internal RC oscillator, port function on RA6, port function on RA7 0111 = External RC oscillator, port function on RA6 0110 = HS oscillator, PLL enabled (clock frequency = 4 x FOSC1) 0101 = EC oscillator, port function on RA6 0100 = EC oscillator, CLKO function on RA6 0011 = External RC oscillator, CLKO function on RA6 0010 = HS oscillator 0001 = XT oscillator 0000 = LP oscillator BORV1:BORV0 CONFIG2L Brown-out Reset Voltage bits 11 = VBOR set to 2.0V 10 = VBOR set to 2.7V 01 = VBOR set to 4.2V 00 = VBOR set to 4.5V BOREN CONFIG2L Brown-out Reset Enable bit 1 = Brown-out Reset enabled 0 = Brown-out Reset disabled PWRTEN CONFIG2L Power-up Timer Enable bit 1 = PWRT disabled 0 = PWRT enabled WDPS3:WDPS0 CONFIG2H Watchdog Timer Postscaler Select bits 1111 = 1:32,768 1110 = 1:16,384 1101 = 1:8,192 1100 = 1:4,096 1011 = 1:2,048 1010 = 1:1,024 1001 = 1:512 1000 = 1:256 0111 = 1:128 0110 = 1:64 0101 = 1:32 0100 = 1:16 0011 = 1:8 0010 = 1:4 0001 = 1:2 0000 = 1:1 WDTEN CONFIG2H Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled (control is placed on SWDTEN bit) 2002 Microchip Technology Inc. Preliminary DS39592B-page 25 PIC18FX220/X320 PIC18FX220/X320 TABLE 5-4: Bit Name PIC18FX220/X320 PIC18FX220/X320 BIT DESCRIPTION (CONTINUED) Configuration Words Description MCLRE CONFIG3H MCLR Pin Enable bit for PIC18F2X20 PIC18F2X20, PIC18F4X20 PIC18F4X20 1 = MCLR pin enabled, RE3 input pin disabled 0 = RE3 input pin enabled, MCLR pin disabled MCLRE CONFIG3H MCLR Pin Enable bit for PIC18F1X20 PIC18F1X20 1 = MCLR pin enabled, RA5 input pin disabled 0 = RA5 input pin enabled, MCLR pin disabled PBADEN CONFIG3H PORTB A/D Enable bit 1 = PORTB A/D pins are configured as analog input channels on RESET 0 = PORTB A/D pins are configured as digital I/O on RESET CCP2MX CONFIG3H CCP2 MUX bit 1 = CCP2 input/output is multiplexed with RC1 0 = CCP2 input/output is multiplexed with RB3 DEBUG CONFIG4L In-Circuit Debugger Enable bit 1 = In-Circuit debugger disabled (RB6, RB7 have I/O port function) 0 = In-Circuit debugger enabled (RB6, RB7 have ICSP serial communication function) LVP CONFIG4L Low Voltage Programming Enable bit 1 = Low Voltage Programming enabled, RB5 is the PGM pin 0 = Low Voltage Programming disabled, RB5 is an I/O pin STVREN CONFIG4L Stack Overflow/Underflow Reset Enable bit 1 = RESET on Stack Overflow/Underflow enabled 0 = RESET on Stack Overflow/Underflow disabled CP3 CONFIG5L Code Protection bits (Block 3 code memory area: 001800h - 001FFFh) for PIC18F2X20/PIC18F4X20 PIC18F2X20/PIC18F4X20 1 = Block 3 is not code protected 0 = Block 3 is code protected CP2 CONFIG5L Code Protection bits (Block 2 code memory area: 001000h - 0017FFh) for PIC18F2X20/PIC18F4X20 PIC18F2X20/PIC18F4X20 1 = Block 2 is not code protected 0 = Block 2 is code protected CP1 CONFIG5L Code Protection bits (Block 1 code memory area: 000800h - 000FFFh) for PIC18F1220 PIC18F1220 1 = Block 1 is not code protected 0 = Block 1 is code protected CP1 CONFIG5L Code Protection bits (Block 1 code memory area: 001000h - 001FFFh) for PIC18F1320 PIC18F1320 1 = Block 1 is not code protected 0 = Block 1 is code protected CP1 CONFIG5L Code Protection bits (Block 1 code memory area: 000800h - 000FFFh) for PIC18F2X20/PIC18F4X20 PIC18F2X20/PIC18F4X20 1 = Block 1 is not code protected 0 = Block 1 is code protected CP0 CONFIG5L Code Protection bits (Block 0 code memory area: 000200h - 0007FFh) for PIC18F1220 PIC18F1220 1 = Block 0 is not code protected 0 = Block 0 is code protected DS39592B-page 26 Preliminary 2002 Microchip Technology Inc. PIC18FX220/X320 PIC18FX220/X320 TABLE 5-4: Bit Name PIC18FX220/X320 PIC18FX220/X320 BIT DESCRIPTION (CONTINUED) Configuration Words Description CP0 CONFIG5L Code Protection bits (Block 0 code memory area: 000200h - 000FFFh) for PIC18F1320 PIC18F1320 1 = Block 0 is not code protected 0 = Block 0 is code protected CP0 CONFIG5L Code Protection bits (Block 0 code memory area: 000200h - 0007FFh) for PIC18F2X20/PIC18F4X20 PIC18F2X20/PIC18F4X20 1 = Block 0 is not code protected 0 = Block 0 is code protected CPD CONFIG5H Code Protection bits (Data EEPROM) 1 = Data EEPROM is not code protected 0 = Data EEPROM is code protected CPB CONFIG5H Code Protection bits (Boot block memory area: 000000h - 0001FFh) 1 = Boot block is not code protected 0 = Boot block is code protected WRT3 CONFIG6L Write Protection bits (Block 3 code memory area: 001800h - 001FFFh) for PIC18F2X20/PIC18F4X20 PIC18F2X20/PIC18F4X20 1 = Block 3 is not write protected 0 = Block 3 is write protected WRT2 CONFIG6L Write Protection bits (Block 2 code memory area: 001000h - 0017FFh) for PIC18F2X20/PIC18F4X20 PIC18F2X20/PIC18F4X20 1 = Block 2 is not write protected 0 = Block 2 is write protected WRT1 CONFIG6L Write Protection bits (Block 1 code memory area: 000800h - 000FFFh) for PIC18F1220 PIC18F1220 1 = Block 1 is not write protected 0 = Block 1 is write protected WRT1 CONFIG6L Write Protection bits (Block 1 code memory area: 001000h - 001FFFh) for PIC18F1320 PIC18F1320 1 = Block 1 is not write protected 0 = Block 1 is write protected WRT1 CONFIG6L Write Protection bits (Block 1 code memory area: 000800h - 000FFFh) for PIC18F2X20/PIC18F4X20 PIC18F2X20/PIC18F4X20 1 = Block 1 is not write protected 0 = Block 1 is write protected WRT0 CONFIG6L Write Protection bits (Block 0 code memory area: 000200h - 0007FFh) for PIC18F1220 PIC18F1220 1 = Block 0 is not write protected 0 = Block 0 is write protected WRT0 CONFIG6L Write Protection bits (Block 0 code memory area: 000200h - 000FFFh) for PIC18F1320 PIC18F1320 1 = Block 0 is not write protected 0 = Block 0 is write protected WRT0 CONFIG6L Write Protection bits (Block 0 code memory area: 000200h - 0007FFh) for PIC18F2X20/PIC18F4X20 PIC18F2X20/PIC18F4X20 1 = Block 0 is not write protected 0 = Block 0 is write protected WRTD CONFIG6H Write Protection bit (Data EEPROM) 1 = Data EEPROM is not write protected 0 = Data EEPROM is write protected 2002 Microchip Technology Inc. Preliminary DS39592B-page 27 PIC18FX220/X320 PIC18FX220/X320 TABLE 5-4: Bit Name PIC18FX220/X320 PIC18FX220/X320 BIT DESCRIPTION (CONTINUED) Configuration Words Description WRTB CONFIG6H Write Protection bit (Boot block memory area: 000000h - 0001FFh) 1 = Boot block is not write protected 0 = Boot block is write protected WRTC CONFIG6H Write Protection bit (Configuration Registers: 300000h - 3000FFh) 1 = Configuration Registers are not write protected 0 = Configuration Registers are write protected EBTR3 CONFIG7L Table Read Protection bit (Block 3 code memory area: 001800h - 001FFFh) for PIC18F2X20/PIC18F4X20 PIC18F2X20/PIC18F4X20 1 = Block 3 is not protected from table reads executed in other blocks 0 = Block 3 is protected from table reads executed in other blocks EBTR2 CONFIG7L Table Read Protection bit (Block 2 code memory area: 001000h - 0017FFh) for PIC18F2X20/PIC18F4X20 PIC18F2X20/PIC18F4X20 1 = Block 2 is not protected from table reads executed in other blocks 0 = Block 2 is protected from table reads executed in other blocks EBTR1 CONFIG7L Table Read Protection bit (Block 1 code memory area: 000800h - 000FFFh) for PIC18F1220 PIC18F1220 1 = Block 1 is not protected from table reads executed in other blocks 0 = Block 1 is protected from table reads executed in other blocks EBTR1 CONFIG7L Table Read Protection bit (Block 1 code memory area: 001000h - 001FFFh) for PIC18F1320 PIC18F1320 1 = Block 1 is not protected from table reads executed in other blocks 0 = Block 1 is protected from table reads executed in other blocks EBTR1 CONFIG7L Table Read Protection bit (Block 1 code memory area: 000800h - 000FFFh) for PIC18F2X20/PIC18F4X20 PIC18F2X20/PIC18F4X20 1 = Block 1 is not protected from table reads executed in other blocks 0 = Block 1 is protected from table reads executed in other blocks EBTR0 CONFIG7L Table Read Protection bit (Block 0 code memory area: 000200h - 0007FFh) for PIC18F1220 PIC18F1220 1 = Block 0 is not protected from table reads executed in other blocks 0 = Block 0 is protected from table reads executed in other blocks EBTR0 CONFIG7L Table Read Protection bit (Block 0 code memory area: 000200h - 000FFFh) for PIC18F1320 PIC18F1320 1 = Block 0 is not protected from table reads executed in other blocks 0 = Block 0 is protected from table reads executed in other blocks EBTR0 CONFIG7L Table Read Protection bit (Block 0 code memory area: 000200h - 0007FFh) for PIC18F2X20/PIC18F4X20 PIC18F2X20/PIC18F4X20 1 = Block 0 is not protected from table reads executed in other blocks 0 = Block 0 is protected from table reads executed in other blocks EBTRB CONFIG7H Table Read Protection bit (Boot block memory area: 000000h - 0001FFh) 1 = Boot block is not protected from table reads executed in other blocks 0 = Boot block is protected from table reads executed in other blocks DEV10 DEV10:DEV3 DEVID2 Device ID bits These bits are used with the DEV2:DEV0 bits in the DEVID1 register to identify part number. DEV2:DEV0 DEVID1 Device ID bits These bits are used with the DEV10 DEV10:DEV3 bits in the DEVID2 register to identify part number. REV4:REV0 DS39592B-page 28 DEVID1 Revision ID bits These bits are used to indicate the revision of the device. Preliminary 2002 Microchip Technology Inc. PIC18FX220/X320 PIC18FX220/X320 5.4 Embedding Configuration Word Information in the HEX File To allow portability of code, a device programmer is required to read the configuration word locations from the HEX file. If configuration word information is not present in the HEX file, then a simple warning message should be issued. Similarly, while saving a HEX file, all configuration word information must be included. An option to not include the configuration word information may be provided. When embedding configuration word information in the HEX file, it should start at address 300000h. Microchip Technology Inc. feels strongly that this feature is important for the benefit of the end customer. 5.5 Microchip Technology Inc. believes that this feature is important for the benefit of the end customer. 5.6 · The contents of all code memory locations · The configuration word, appropriately masked · ID locations The Least Significant 16-bits of this sum are the checksum. Table 5-7 describes how to calculate the checksum for each device. Note: Embedding Data EEPROM Information in the HEX File To allow portability of code, a device programmer is required to read the data EEPROM information from the HEX file. If data EEPROM information is not present, a simple warning message should be issued. Similarly, when saving a HEX file, all data EEPROM information must be included. An option to not include the data EEPROM information may be provided. When embedding data EEPROM information in the HEX file, it should start at address F00000h. TABLE 5-5: Checksum Computation The checksum is calculated by summing the following: The checksum calculation differs depending on the code protect setting. Since the code memory locations read out differently depending on the code protect setting, the table describes how to manipulate the actual code memory values to simulate the values that would be read from a protected device. When calculating a checksum by reading a device, the entire code memory can simply be read and summed. The configuration word and ID locations can always be read. CHECKSUM COMPUTATION - PIC18F1320 PIC18F1320 0xAA at 0 and Max Address SUM (0000:01FFh) + SUM (0200:07FFh) + SUM (0800:0FFFh) + (CONFIG1H & 0CFh) + (CONFIG2L & 0Fh) + (CONFIG2H & 1Fh) + (CONFIG3H & 080h) + (CONFIG4L & 085h) + (CONFIG5L & 03h) + (CONFIG5H & 0C0h) + (CONFIG6L & 03h) + (CONFIG6H & 0E0h) + (CONFIG7L & 03h) + (CONFIG7H & 040h) E3EB E341 Boot Block SUM (0200:07FFh) + SUM (0800:0FFFh) + (CONFIG1H & 0CFh) + (CONFIG2L & 0Fh) + (CONFIG2H & 1Fh) + (CONFIG3H & 080h) + (CONFIG4L & 085h) + (CONFIG5L & 03h) + (CONFIG5H & 0C0h) + (CONFIG6L & 03h) + (CONFIG6H & 0E0h) + (CONFIG7L & 03h) + (CONFIG7H & 040h) + SUM (IDs) E5D5 E56C Boot/ Panel1/ Panel2 (CONFIG1H & 0CFh) + (CONFIG2L & 0Fh) + (CONFIG2H & 1Fh) + (CONFIG3H & 080h) + (CONFIG4L & 085h) + (CONFIG5L & 03h) + (CONFIG5H & 0C0h) + (CONFIG6L & 03h) + (CONFIG6H & 0E0h) + (CONFIG7L & 03h) + (CONFIG7H & 040h) + SUM (IDs) 03D2 03BE All PIC18F1320 PIC18F1320 Legend: Blank Value (CONFIG1H & 0CFh) + (CONFIG2L & 0Fh) + (CONFIG2H & 1Fh) + (CONFIG3H & 083h) + (CONFIG4L & 085h) + (CONFIG5L & 0Fh) + (CONFIG5H & 0C0h) + (CONFIG6L & 0Fh) + (CONFIG6H & 0E0h) + (CONFIG7L & 0Fh) + (CONFIG7H & 040h) + SUM (IDs) 03D2 03BE Code Protect Device None Item CONFIG SUM[a:b] SUM (IDs) + & = = = = = Checksum Description Configuration Word Sum of locations, a to b inclusive Byte-wise sum of lower four bits of all ID locations Addition Bit-wise AND 2002 Microchip Technology Inc. Preliminary DS39592B-page 29 PIC18FX220/X320 PIC18FX220/X320 TABLE 5-6: CHECKSUM COMPUTATION - PIC18F1220 PIC18F1220 0xAA at 0 and Max Address SUM (0000:01FFh) + SUM (0200:0FFFh) + SUM (1000:1FFFh) + (CONFIG1H & 0CFh) + (CONFIG2L & 0Fh) + (CONFIG2H & 1Fh) + (CONFIG3H & 080h) + (CONFIG4L & 085h) + (CONFIG5L & 03h) + (CONFIG5H & 0C0h) + (CONFIG6L & 03h) + (CONFIG6H & 0E0h) + (CONFIG7L & 03h) + (CONFIG7H & 040h) F3EB F341 Boot Block SUM (0200:0FFFh) + SUM (1000:1FFFh) + (CONFIG1H & 0CFh) + (CONFIG2L & 0Fh) + (CONFIG2H & 1Fh) + (CONFIG3H & 080h) + (CONFIG4L & 085h) + (CONFIG5L & 03h) + (CONFIG5H & 0C0h) + (CONFIG6L & 03h) + (CONFIG6H & 0E0h) + (CONFIG7L & 03h) + (CONFIG7H & 040h) + SUM (IDs) F5D6 F56D Boot/ Panel1/ Panel2 (CONFIG1H & 0CFh) + (CONFIG2L & 0Fh) + (CONFIG2H & 1Fh) + (CONFIG3H & 080h) + (CONFIG4L & 085h) + (CONFIG5L & 03h) + (CONFIG5H & 0C0h) + (CONFIG6L & 03h) + (CONFIG6H & 0E0h) + (CONFIG7L & 03h) + (CONFIG7H & 040h) + SUM (IDs) 03D3 03BF All PIC18F1220 PIC18F1220 Legend: Blank Value (CONFIG1H & 0CFh) + (CONFIG2L & 0Fh) + (CONFIG2H & 1Fh) + (CONFIG3H & 080h) + (CONFIG4L & 085h) + (CONFIG5L & 03h) + (CONFIG5H & 0C0h) + (CONFIG6L & 03h) + (CONFIG6H & 0E0h) + (CONFIG7L & 03h) + (CONFIG7H & 040h) + SUM (IDs) 03D3 03BF Code Protect Device None Item CONFIG SUM[a:b] SUM (IDs) + & DS39592B-page 30 = = = = = Checksum Description Configuration Word Sum of locations, a to b inclusive Byte-wise sum of lower four bits of all ID locations Addition Bit-wise AND Preliminary 2002 Microchip Technology Inc. PIC18FX220/X320 PIC18FX220/X320 TABLE 5-7: CHECKSUM COMPUTATION - PIC18F2X20/PIC18F4X20 PIC18F2X20/PIC18F4X20 Blank Value 0xAA at 0 and Max Address 0E412h 0E368h Boot Block SUM (0200:07FFh) + SUM (0800:0FFFh) + SUM (1000:17FFh) + SUM (1800:1FFFh) + (CONFIG1H & 0CFh) + (CONFIG2L & 0Fh) + (CONFIG2H & 1Fh) + (CONFIG3H & 083h) + (CONFIG4L & 085h) + (CONFIG5L & 0Fh) + (CONFIG5H & 0C0h) + (CONFIG6L & 0Fh) + (CONFIG6H & 0E0h) + (CONFIG7L & 0Fh) + (CONFIG7H & 040h) + SUM (IDs) 0E5E7h 0E59Ch Boot Block/ SUM (0800:0FFFh) + SUM (1000:17FFh) + SUM (1800:1FFFh) + Block 0 (CONFIG1H & 0CFh) + (CONFIG2L & 0Fh) + (CONFIG2H & 1Fh) + (CONFIG3H & 083h) + (CONFIG4L & 085h) + (CONFIG5L & 0Fh) + (CONFIG5H & 0C0h) + (CONFIG6L & 0Fh) + (CONFIG6H & 0E0h) + (CONFIG7L & 0Fh) + (CONFIG7H & 040h) + SUM (IDs) 0EBE6h 0EB9Bh 0F3E4h Boot Block/ SUM (1000:17FFh) + SUM (1800:1FFFh) + (CONFIG1H & 0CFh) + (CONFIG2L & 0Fh) + (CONFIG2H & 1Fh) + (CONFIG3H & 083h) + (CONFIG4L Block 0/ & 085h) + (CONFIG5L & 0Fh) + (CONFIG5H & 0C0h) + (CONFIG6L & 0Fh) + Block 1 (CONFIG6H & 0E0h) + (CONFIG7L & 0Fh) + (CONFIG7H & 040h) + SUM (IDs) Device 0F399h Code Protect PIC18F2320/ PIC18F2320/ None PIC18F4320 PIC18F4320 Checksum SUM (0000:01FFh) + SUM (0200:07FFh) + SUM (0800:0FFFh) + SUM (1000:17FFh) + SUM (1800:1FFFh) + (CONFIG1H & 0CFh) + (CONFIG2L & 0Fh) + (CONFIG2H & 1Fh) + (CONFIG3H & 083h) + (CONFIG4L & 085h) + (CONFIG5L & 0Fh) + (CONFIG5H & 0C0h) + (CONFIG6L & 0Fh) + (CONFIG6H & 0E0h) + (CONFIG7L & 0Fh) + (CONFIG7H & 040h) Boot Block/ Block 0/ Block 1/ Block 2 0FBE0h 0FB95h Boot Block/ Block 0/ Block 1/ Block 2/ Block 3 (CONFIG1H & 0CFh) + (CONFIG2L & 0Fh) + (CONFIG2H & 1Fh) + (CONFIG3H & 083h) + (CONFIG4L & 085h) + (CONFIG5L & 0Fh) + (CONFIG5H & 0C0h) + (CONFIG6L & 0Fh) + (CONFIG6H & 0E0h) + (CONFIG7L & 0Fh) + (CONFIG7H & 040h) + SUM (IDs) 03D8h 03E2h All Legend: SUM (1800:1FFFh) + (CONFIG1H & 0CFh) + (CONFIG2L & 0Fh) + (CONFIG2H & 1Fh) + (CONFIG3H & 083h) + (CONFIG4L & 085h) + (CONFIG5L & 0Fh) + (CONFIG5H & 0C0h) + (CONFIG6L & 0Fh) + (CONFIG6H & 0E0h) + (CONFIG7L & 0Fh) + (CONFIG7H & 040h) + SUM (IDs) (CONFIG1H & 0CFh) + (CONFIG2L & 0Fh) + (CONFIG2H & 1Fh) + (CONFIG3H & 083h) + (CONFIG4L & 085h) + (CONFIG5L & 0Fh) + (CONFIG5H & 0C0h) + (CONFIG6L & 0Fh) + (CONFIG6H & 0E0h) + (CONFIG7L & 0Fh) + (CONFIG7H & 040h) + SUM (IDs) 03D8h 03E2h Item CONFIG SUM[a:b] SUM (IDs) + & = = = = = Description Configuration Word Sum of locations, a to b inclusive Byte-wise sum of lower four bits of all ID locations Addition Bit-wise AND 2002 Microchip Technology Inc. Preliminary DS39592B-page 31 PIC18FX220/X320 PIC18FX220/X320 TABLE 5-7: CHECKSUM COMPUTATION - PIC18F2X20/PIC18F4X20 PIC18F2X20/PIC18F4X20 (CONTINUED) Blank Value 0xAA at 0 and Max Address 0F412h 0F368h 0F5E8h Boot Block SUM (0200:07FFh) + SUM (0800:0FFFh) + (CONFIG1H & 0CFh) + (CONFIG2L & 0Fh) + (CONFIG2H & 1Fh) + (CONFIG3H & 083h) + (CONFIG4L & 085h) + (CONFIG5L & 0Fh) + (CONFIG5H & 0C0h) + (CONFIG6L & 0Fh) + (CONFIG6H & 0E0h) + (CONFIG7L & 0Fh) + (CONFIG7H & 040h) + SUM (IDs) 0F59Dh 0FBE7h Boot Block/ SUM (0800:0FFFh) + (CONFIG1H & 0CFh) + (CONFIG2L & 0Fh) + Block 0 (CONFIG2H & 1Fh) + (CONFIG3H & 083h) + (CONFIG4L & 085h) + (CONFIG5L & 0Fh) + (CONFIG5H & 0C0h) + (CONFIG6L & 0Fh) + (CONFIG6H & 0E0h) + (CONFIG7L & 0Fh) + (CONFIG7H & 040h) + SUM (IDs) Device 0FB9Ch Code Protect PIC18F2220/ PIC18F2220/ None PIC18F4220 PIC18F4220 Checksum SUM (0000:01FFh) + SUM (0200:07FFh) + SUM (0800:0FFFh) + (CONFIG1H & 0CFh) + (CONFIG2L & 0Fh) + (CONFIG2H & 1Fh) + (CONFIG3H & 083h) + (CONFIG4L & 085h) + (CONFIG5L & 0Fh) + (CONFIG5H & 0C0h) + (CONFIG6L & 0Fh) + (CONFIG6H & 0E0h) + (CONFIG7L & 0Fh) + (CONFIG7H & 040h) Boot Block/ (CONFIG1H & 0CFh) + (CONFIG2L & 0Fh) + (CONFIG2H & 1Fh) + (CONFIG3H & 083h) + (CONFIG4L & 085h) + (CONFIG5L & 0Fh) + Block 0/ (CONFIG5H & 0C0h) + (CONFIG6L & 0Fh) + (CONFIG6H & 0E0h) + Block 1 (CONFIG7L & 0Fh) + (CONFIG7H & 040h) + SUM (IDs) 03EFh All Legend: 03E5h 03E5h 03EFh Item CONFIG SUM[a:b] SUM (IDs) + & DS39592B-page 32 (CONFIG1H & 0CFh) + (CONFIG2L & 0Fh) + (CONFIG2H & 1Fh) + (CONFIG3H & 083h) + (CONFIG4L & 085h) + (CONFIG5L & 0Fh) + (CONFIG5H & 0C0h) + (CONFIG6L & 0Fh) + (CONFIG6H & 0E0h) + (CONFIG7L & 0Fh) + (CONFIG7H & 040h) + SUM (IDs) = = = = = Description Configuration Word Sum of locations, a to b inclusive Byte-wise sum of lower four bits of all ID locations Addition Bit-wise AND Preliminary 2002 Microchip Technology Inc. PIC18FX220/X320 PIC18FX220/X320 6.0 AC/DC CHARACTERISTICS TABLE 6-1: TIMING REQUIREMENTS FOR PROGRAM/VERIFY TEST MODE Standard Operating Conditions Operating Temperature: 25°C is recommended Param No. Min Max Units D110 VIHH Sym High Voltage Programming Voltage on MCLR/VPP Characteristic 9.00 13.25 V D110A D110A VIHL Low Voltage Programming Voltage on MCLR/VPP 2.00 5.50 V D111 VDD Supply Voltage during Programming Conditions D112 IPP 2.00 V Normal programming 5.50 V Bulk erase operations - Programming Current on MCLR/VPP 5.50 4.50 300 µA D113 IDDP Supply Current during Programming - 1 mA D031 VIL Input Low Voltage VSS 0.2 VSS V D041 VIH Input High Voltage 0.8 VDD VDD V D080 VOL Output Low Voltage - 0.6 V D090 VOH Output High Voltage VDD - 0.7 - V IOH = -3.0 mA D012 CIO Capacitive Loading on I/O pin (PGD) - 50 pF To meet AC specifications P2 Tsclk Serial Clock (Program Clock (PGC) Period 100 - ns VDD = 5.0V 1 - µs VDD = 2.0V P2A TsclkL Serial Clock (Program Clock (PGC) Low Time 40 - ns VDD = 5.0V 400 - ns VDD = 2.0V IOL = 8.5 mA P2B TsclkH Serial Clock (Program Clock (PGC) High Time 40 - ns VDD = 5.0V 400 - ns VDD = 2.0V P3 Tset1 Input Data Setup Time to Serial Clock 15 - ns P4 Thld1 Input Data Hold Time from SCLK 15 - ns P5 Tdly1 Delay between 4-bit Command and Command Operand 20 - ns P5A Tdly1a Delay between 4-bit Command Operand and next 4-bit Command 20 - ns P6 Tdly2 Delay between last SCLK of Command Byte to first SCLK of Read of Data Word 20 - ns P9 Tdly5 SCLK High Time (minimum programming time) 1 - ms P10 Tdly6 SCLK Low Time after Programming (high voltage discharge time) 5 - µs ms P11 Tdly7 Delay to allow Self-timed Data Write or Bulk Erase to occur 5 - P12 Thld2 Input Data Hold Time from MCLR/VPP 2 - µs P13 Tset2 VDD Setup Time to MCLR/VPP 100 - ns P14 Tvalid Data Out Valid from SCLK 10 - ns P15 Tset3 PGM Setup Time to MCLR/VPP 2 - µs 2002 Microchip Technology Inc. Preliminary DS39592B-page 33 PIC18FX220/X320 PIC18FX220/X320 NOTES: DS39592B-page 34 Preliminary 2002 Microchip Technology Inc. Note the following details of the code protection feature on PICmicro® MCUs. · · · · · · The PICmicro family meets the specifications contained in the Microchip Data Sheet. Microchip believes that its family of PICmicro microcontrollers is one of the most secure products of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the PICmicro microcontroller in a manner outside the operating specifications contained in the data sheet. The person doing so may be engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable". Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our product. If you have any further questions about this matter, please contact the local sales office nearest to you. Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip's products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, K EELOQ, MPLAB, PIC, PICmicro, PICSTART and PRO MATE are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, microID, MXDEV, MXLAB, PICMASTER, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. dsPIC, dsPICDEM.net, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, microPort, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, PICC, PICDEM, PICDEM.net, rfPIC, Select Mode and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. Serialized Quick Turn Programming (SQTP) is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2002, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received QS-9000 QS-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona in July 1999 and Mountain View, California in March 2002. The Company's quality system processes and procedures are QS-9000 QS-9000 compliant for its PICmicro ® 8-bit MCUs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, non-volatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001 certified. 2002 Microchip Technology Inc. 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