PIC18C658/858 DS30475A D022A PIC18LCXX8 PIC18CXX8 D020A D021B D022B D023A

PIC18C658/858 Rev. B2 Silicon Errata Sheet The PIC18C658/858 parts you have received conform functionally to the Device Data

PIC18C658/858 PIC18C658/858 PIC18C658/858 PIC18C658/858 Rev. B2 Silicon Errata Sheet The PIC18C658/858 PIC18C658/858 parts you have received conform functionally to the Device Data Sheet (DS30475A DS30475A), except for the anomalies described below. All the problems listed here will be addressed in future revisions of the PIC18C658/858 PIC18C658/858 silicon. Date Codes that pertain to this issue: ALL Note: 1. Module: CAN The CAN module may send a passive error flag earlier than expected. This will occur at the transition point of error active to error passive, TEC (Transmit Error Count), or REC (Receive Error Count) 128. When the manufacture date of a newer version of silicon is in production, the last date where this issue may occur will be specified. 3. Module: LVD The minimum and maximum LVD voltage levels (parameter D420) have changed. The new values are shown in Table 1. Work around Work around None for current silicon revision. Use the latest silicon revision when it becomes available. None Date Codes that pertain to this issue: ALL 2. Module: CAN The CAN module may not synchronize correctly if there is a phase error between nodes that is equal to the Synchronization Jump Width (SJW). As a result, the module may request retransmission of messages from the transmitting node. Note: When the manufacture date of a newer version of silicon is in production, the last date where this issue may occur will be specified. Work around 1. Use the longest SJW possible that will work with the application. 2. Use the latest silicon revision when it becomes available. TABLE 1: LVD MINIMUM VOLTAGES Param No. Symbol D420 VLVD Characteristic LVD Voltage Min. Max. Units 2.35 2.80 V 2.55 3.02 V LVDL = 0110 2.64 3.14 V LVDL = 0111 2.83 3.37 V LVDL = 1000 3.11 3.71 V LVDL = 1001 3.29 3.93 V LVDL = 1010 3.39 4.04 V LVDL = 1011 3.58 4.26 V LVDL = 1100 3.77 4.49 V LVDL = 1101 3.95 4.71 V LVDL = 1110 2001 Microchip Technology Inc. LVDL = 0100 LVDL = 0101 4.23 5.05 V DS80107B-page 1 PIC18C658/858 PIC18C658/858 4. Module: BOR 6. Module: CAN The minimum and maximum BOR Voltage levels (parameter D005) have changed. The new values are shown in Table 2 (bottom of this page). Work around None. Date Codes that pertain to this issue: ALL Note: When the manufacture date of a newer version of silicon is in production, the last date where this issue may occur will be specified. Two of the Receive Buffer modes defined by bits RXM1 and RXM0 of the RXB0CON register (RXB0CON), are currently reversed from their description in the original Device Data Sheet (DS30475A DS30475A). The actual values for these bits are shown in the excerpt from Register 17-12 (changes from the original data sheet in bold). This anomaly is particular to this silicon revision. Future revisions will restore the operation of these bits to their original description in the Device Data Sheet (DS30475A DS30475A). Work around 1. Always configure the mode for Receive Buffer 0 as `Receive All Valid Messages' (bits RXM1:RXM0 = `00'). In addition, use the EXIDEN bit of the RXF0SIDL register (RXF0SIDL) to set the filter for standard or extended ID messages. Set EXIDEN (= '1') for extended ID messages, and clear EXIDEN for standard ID messages. 2. Use the latest silicon revision when it becomes available. 5. Module: Watchdog Timer After the WDT is allowed to time-out, all subsequent WDT periods following the very first, may double in duration. This can occur if the CLRWDT instruction is not executed prior to the timer timing out. Work around Always execute the CLRWDT instruction prior to entering a potential WDT time-out condition. TABLE 2: BOR MAXIMUM VOLTAGES Param No. Symbol D005 VBOR Characteristic Max. Units BORV = 11 2.35 2.80 V BORV = 10 2.55 3.02 V BORV = 01 3.95 4.71 V BORV = 00 BOR Voltage Min. 4.23 5.05 V REGISTER 17-12: RXB0CON - RECEIVE BUFFER 0 CONTROL REGISTER bit 6-5 DS80107B-page 2 RXM1:RXM0: Receive Buffer Mode bits 11 = Receive all messages (including those with errors) 10 = Receive only valid messages with standard identifier 01 = Receive only valid messages with extended identifier 00 = Receive all valid messages 2001 Microchip Technology Inc. PIC18C658/858 PIC18C658/858 7. Module: WDT When the device is configured for either EC, or RC oscillator modes, with the Power-up Timer enabled, bit TO of the RCON register (RCON) may default to `0', even though no WDT time-out has occurred. The TO bit functions normally in all other configurations. 9. Module: Interrupts High priority interrupts may become improperly enabled, while low priority interrupts become improperly disabled at the same time. This may occur when low priority interrupts are in an enabled state and the following conditions occur simultaneously: · Work around 1. Use bit TO in conjunction with bit POR (RCON), to determine if a RESET condition has occurred. · High priority interrupts are being changed from an enabled to a disabled state; and One or more low priority interrupts occur. Work around 1. Always disable low priority interrupts before disabling high priority interrupts. Re-enable the low priority interrupts afterwards, if necessary. 2. 2. Use the latest silicon revision when it becomes available. Use the latest silicon revision when it becomes available. 8. Module: I/O (Parallel Slave Port) The Input Buffer Status bit of the PSPCON register (PSPCON) may be inadvertently cleared, even when the PORTD input buffer has not been read. This will occur only when the following two conditions occur simultaneously: · · The four Least Significant bits of the BSR register are equal to 0Fh (BSR = `1111'), and Any instruction that contains 83h in its 8 Least Significant bits (i.e., register file addresses, literal data, address offsets, etc.) is executed. Work around All work arounds will involve setting the contents of BSR to some value other than 0Fh. In addition to those proposed below, other solutions may exist. 1. When developing or modifying code, keep these guidelines in mind: · · · Assign 12-bit addresses to all variables. This allows the assembler to know when Access Banking can be used. Do not set the BSR to point to Bank 15 (BSR = 0Fh). Allow the assembler to manipulate the Access bit present in most instructions. Accessing the SFRs in Bank 15 will be done through the Access bank. Continue to use the BSR to select Banks 1 through 5 and the upper half of Bank 0. 2. If accessing a part of Bank 15 is required and the use of Access Banking is not possible, consider using indirect addressing. 3. If pointing the BSR to Bank 15 is unavoidable, review the absolute file listing. Verify that no instructions contains 83h in the 8 Least Significant bits while the BSR points to Bank 15 (BSR = 0Fh). 2001 Microchip Technology Inc. DS80107B-page 3 PIC18C658/858 PIC18C658/858 Clarifications/Corrections to the Data Sheet: 2. Table 25-1 of the Device Data Sheet is amended to include parameters D421, D422, D423 and D425, related to the performance of the Low Voltage Detect module. In the Device Data Sheet (DS30475A DS30475A), the following clarifications and corrections should be noted. 1. Module: LVD Module: Timer1 Section 11.1 (Timer1 Operation) is amended with the following clarification: In addition, the minimum and maximum LVD voltage levels (specification D420) are also amended (see Issue 3 of this Errata), and typical voltage levels are provided. When Timer1 is configured to operate as an asynchronous counter, care must be taken that there is no incoming pulse while the module is being turned off. If an incoming pulse arrives while Timer1 is being turned off, the value of register TMR1 may become unpredictable. Table 25-1 should read as follows (changes and additions in bold): If an application requires that Timer1 be turned off and if it is possible that Timer1 may receive an incoming pulse while being turned off, synchronize the external clock first, by clearing the T1SYNC bit of register T1CON. Please note that this may cause Timer1 to miss up to one count. TABLE 25-1: LOW VOLTAGE DETECT CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Param Symbol No. D420 D421 D425 VLVD ILVD VBG DS80107B-page 4 Characteristic LVD Voltage LVDL = 0100 LVDL = 0101 LVDL = 0110 LVDL = 0111 LVDL = 1000 LVDL = 1001 LVDL = 1010 LVDL = 1011 LVDL = 1100 LVDL = 1101 LVDL = 1110 Supply Current Internally Generated Reference Voltage Min. Typ Max. Units 2.35 2.55 2.64 2.83 3.11 3.29 3.39 3.58 3.77 3.95 4.23 - TBD 2.58 2.78 2.89 3.1 3.41 3.61 3.72 3.92 4.13 4.33 4.64 35 1.22 2.80 3.02 3.14 3.37 3.71 3.93 4.04 4.26 4.49 4.71 5.05 50 TBD Conditions V V V V V V V V V V V µA V 2001 Microchip Technology Inc. PIC18C658/858 PIC18C658/858 3. Module: BOR Also, the typical and maximum values for parameter D022A D022A are amended, as noted (see Issue 4 of this Errata). The minimum and maximum specified values for parameter D005, as listed in Section 25.1 of the Device Data Sheet, are amended as noted (see also Issue 4 of this Errata). Section 25.1 in part should read as follows (changes and additions in bold): 25.1 DC Characteristics PIC18LCXX8 PIC18LCXX8 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial PIC18CXX8 PIC18CXX8 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Param Symbol No. D005 D005 VBOR Characteristic/ Device Brown-out Reset Voltage PIC18LCXX8 PIC18LCXX8 BORV1:BORV0 = 11 BORV1:BORV0 = 10 BORV1:BORV0 = 01 BORV1:BORV0 = 00 PIC18CXX8 PIC18CXX8 BORV1:BORV0 = 1x Min Typ Max Units 2.35 2.55 3.95 4.23 N.A. - - - - N.A. 2.80 3.02 4.71 5.05 N.A. V V V V V Conditions Not in operating voltage range of device BORV1:BORV0 = 01 3.95 - 4.71 V BORV1:BORV0 = 00 4.23 - 5.05 V D022A D022A IBOR PIC18LCXX8 PIC18LCXX8 - 10 TBD µA VDD = 5.5V Brown-out Reset - 10 TBD µA VDD = 2.5V, 25°C D022A D022A PIC18CXX8 PIC18CXX8 - 10 TBD µA VDD = 5.5V, -40°C to +85°C Brown-out Reset - 10 TBD µA VDD = 5.5V, -40°C to +125° - 10 TBD µA VDD = 4.2V, 25°C Legend: Shading added to differentiate characteristics for "LC" devices. Characteristics are assumed to be common for "C" and "LC" devices unless otherwise noted. * These parameters are characterized but not tested. 2001 Microchip Technology Inc. DS80107B-page 5 PIC18C658/858 PIC18C658/858 4. Module: Comparator Section 25.1 of the Device Data Sheet is amended to add parameter D023 related to the Analog Comparator module. In addition, a new table is added to describe the Analog Comparator specifications. Section 25.1 in part should read as follows (changes and additions in bold): 25.1 DC Characteristics (cont'd) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial PIC18LCXX8 PIC18LCXX8 (Industrial) PIC18CXX8 PIC18CXX8 (Industrial, Extended) Param Symbol No. D020 IPD Characteristic/ Device Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Min Typ Max Units Conditions Power-down Current(3) PIC18LCXX8 PIC18LCXX8 -