PIC17C42A PIC17C4X DS30412C PIC17LC42A 10F-1C DK-2750 D-81739 QS-9000

PIC17C42A Rev. A Silicon Errata Sheet The PIC17C42A (Rev. A) parts you have received conform functionally to the PIC17C4X

PIC17C42A PIC17C42A PIC17C42A PIC17C42A Rev. A Silicon Errata Sheet The PIC17C42A PIC17C42A (Rev. A) parts you have received conform functionally to the PIC17C4X PIC17C4X preliminary data sheet (DS30412C DS30412C), except for the following clarifications and corrections. NONE Clarifications/Corrections to the Data Sheet: The PIC17C42A PIC17C42A Preliminary Data Sheet (document DS30412C DS30412C) that you have received, requires the following clarifications and corrections. 1. The clearing of any interrupt enable bit(s) in the INTSTA register should be preceded by the disabling of the global interrupt control bit (setting GLINTD). Global interrupts may then be reenabled. The individual interrupts may be reenabled without further control of the GLINTD bit. When global interrupts are enabled, if the interrupt flag is being set when the corresponding enable bit is being cleared the device will branch to the reset vector address (0h). The interrupt flag will not be (automatically) cleared. 2. 3. Note: The RETURN instruction causes an update of the PCLATH register. The PCLATH register is loaded with the high address of the RETURN instruction. The Table write to internal program memory (self programming) can occur even when the MCLR pin is either at the VIH or VIHH voltage level. When the MCLR pin is at VIH, the table write sequence occurs, but the programming voltage is marginal since the MCLR pin is not at the correct level. This table write may cause the specified program memory location to be corrupted (depending on the data in the TABLAT register). As with any windowed EPROM device, please cover the window at all times, except when erasing. © October, 1997 Microchip Technology Inc. DS30412C/42A/E1A2-page 1 PIC17C42A PIC17C42A 4. 5. Unexpected results may occur if a table write (TABLWT instruction) to external memory occurs after a table read (TABLRD instruction). To ensure that the proper 16-bit value is written, a table write (TLWT) intruction(s) needs to be followed by the TABLWT instruction. If not the value that is written will not be as expected. The value will contain the values that were last written to the TABLATH and TABLATL registers and will not contain the values that had been read from the external memory into the TABLATH:TABLATL registers by the TABLRD instruction. The Power-down current of the PIC17C42A PIC17C42A has been increased as shown in Table 1. The specification of 5 µA remains for the PIC17LC42A PIC17LC42A devices. Example: TABLAT Ext Bus TLWT TABLWT : LO, fn1 HI, 1, fn2 x:fn1 fn2:fn1 -:fn2:fn1 TABLRD TLRD : HI, 0, fn3 LO, fn4 X1:X0 X1:X0 X1:X0 -:- TABLWT HI, 1, fn5 fn5:X0 fn5:fn1 TABLE 1: DC SPECIFICATION LIMITS THAT VARY FROM DATA SHEET Tested Param No. Sym. D021 IPD Data Sheet Characteristic Units Condition Min DS30412C/42A/E1A2-page 2 Max Min Typ Max -