PIC16F87/88 PIC16F87 PIC16F88 18-PIN 20-PIN 28-PIN RA2/AN2/CVREF/VREF26 QS-9000 - Datasheet Archive
FLASH Memory Programming Specification 1.0 DEVICE OVERVIEW Both algorithms can be used with the two available programming entry
PIC16F87/88 PIC16F87/88 FLASH Memory Programming Specification 1.0 DEVICE OVERVIEW Both algorithms can be used with the two available programming entry methods. The first method follows the normal Microchip Programming mode entry of holding pins RB6 and RB7 low, while raising MCLR pin from VIL to VIHH (13V ± 0.5V). The second method, called Low Voltage ICSPTM or LVP for short, applies VDD to MCLR and uses the I/O pin RB3 to enter Programming mode. When RB3 is driven to VDD from ground, the PIC16F87/88 PIC16F87/88 device enters Programming mode. This document includes programming specifications for the following devices: · PIC16F87 PIC16F87 · PIC16F88 PIC16F88 2.0 PROGRAMMING THE PIC16F87/88 PIC16F87/88 2.2 The PIC16F87/88 PIC16F87/88 is programmed using a serial method. The Serial mode will allow the PIC16F87/88 PIC16F87/88 to be programmed while in the user's system. This allows for increased design flexibility. This programming specification applies to PIC16F87/88 PIC16F87/88 devices in all packages. 2.1 Programming Mode The Programming mode for the PIC16F87/88 PIC16F87/88 allows programming of user program memory, data memory, special locations used for ID, and the configuration words. Programming Algorithm Requirements The programming algorithm used depends on the operating voltage (VDD) of the PIC16F87/88 PIC16F87/88 device. Algorithm # VDD Range 1 2.0V £ VDD < 5.5V 2 4.5V £ VDD £ 5.5V FIGURE 2-1: PIC16F87 PIC16F87 18-PIN 18-PIN DIP, SOIC 1 18 RA1/AN1 RA3/AN3/C1OUT 2 17 RA0/AN0 RA4/T0CKI/C2OUT 3 16 RA7/OSC1/CLKI RA5/MCLR/VPP 4 15 RA6/OSC2/CLKO VSS 5 14 VDD RB0/INT/CCP1(1) 6 13 RB7/PGD/T1OSI RB1/SDI/SDA 7 12 RB6/PGC/T1OSO/T1CKI RB2/SDO/RX/DT 8 11 RB5/SS/TX/CK RB3/PGM/CCP1(1) 9 10 RB4/SCK/SCL PIC16F87 PIC16F87 RA2/AN2/CVREF Note 1: Location of CCP1 function is determined by CCPMX. ã 2002 Microchip Technology Inc. Advance Information DS39607A-page 1 PIC16F87/88 PIC16F87/88 FIGURE 2-2: PIC16F87 PIC16F87 20-PIN 20-PIN SSOP 1 20 RA1/AN1 RA3/AN3/C1OUT 2 19 RA0/AN0 RA4/T0CKI/C2OUT 3 18 RA7/OSC1/CLKI RA5/MCLR/VPP 4 17 RA6/OSC2/CLKO VSS 5 16 VDD AVSS 6 15 AVDD RB0/INT/CCP1(1) 7 14 RB7/PGD/T1OSI RB1/SDI/SDA 8 13 RB6/PGC/T1OSO/T1CKI RB2/SDO/RX/DT 9 12 RB5/SS/TX/CK 10 11 RB4/SCK/SCL RB3/PGM/CCP1(1) PIC16F87 PIC16F87 RA2/AN2/CVREF Note 1: Location of CCP1 function is determined by CCPMX. RA4/T0CKI/C2OUT RA3/AN3/C1OUT RA2/AN2/CVREF NC RA1/AN1 RA0/AN0 NC 27 26 25 24 23 22 PIC16F87 PIC16F87 28-PIN 28-PIN QFN 28 FIGURE 2-3: RA5/MCLR/VPP 1 21 RA7/OSC1/CLKI NC 2 20 RA6/OSC2/CLKO VSS 3 19 VDD NC 4 18 NC AVSS 5 17 AVDD NC 6 16 RB7/PGD/T1OSI RB0/INT/CCP1(1) 7 15 RB6/PGC/T1OSO/T1CKI 8 9 10 11 12 13 14 RB1/SDI/SDA RB2/SDO/RX/DT RB3/PGM/CCP1(1) NC RB4/SCK/SCL RB5/SS/TX/CK NC PIC16F87 PIC16F87 Note 1: Location of CCP1 function is determined by CCPMX. DS39607A-page 2 Advance Information ã 2002 Microchip Technology Inc. PIC16F87/88 PIC16F87/88 FIGURE 2-4: PIC16F88 PIC16F88 18-PIN 18-PIN DIP, SOIC 1 18 RA1/AN1 RA3/AN3/VREF+/C1OUT 2 17 RA0/AN0 RA4/AN4/T0CKI/C2OUT 3 16 RA7/OSC1/CLKI RA5/MCLR/VPP 4 15 RA6/OSC2/CLKO VSS 5 14 VDD RB0/INT/CCP1(1) 6 13 RB7/AN6/PGD/T1OSI RB1/SDI/SDA 7 12 RB6/AN5/PGC/T1OSO/T1CKI RB2/SDO/RX/DT 8 11 RB5/SS/TX/CK (1) 9 10 RB4/SCK/SCL RB3/PGM/CCP1 PIC16F88 PIC16F88 RA2/AN2/CVREF/VREF- Note 1: Location of CCP1 function is determined by CCPMX. FIGURE 2-5: PIC16F88 PIC16F88 20-PIN 20-PIN SSOP 1 20 RA1/AN1 RA3/AN3/VREF+/C1OUT 2 19 RA0/AN0 RA4/AN4/T0CKI/C2OUT 3 18 RA7/OSC1/CLKI RA5/MCLR/VPP 4 17 RA6/OSC2/CLKO VSS 5 16 VDD AVSS 6 15 AVDD RB0/INT/CCP1(1) 7 14 RB7/AN6/PGD/T1OSI RB1/SDI/SDA 8 13 RB6/AN5/PGC/T1OSO/T1CKI RB2/SDO/RX/DT 9 12 RB5/SS/TX/CK 10 11 RB4/SCK/SCL RB3/PGM/CCP1(1) PIC16F88 PIC16F88 RA2/AN2/CVREF/VREF- Note 1: Location of CCP1 function is determined by CCPMX. ã 2002 Microchip Technology Inc. Advance Information DS39607A-page 3 PIC16F87/88 PIC16F87/88 RA1/AN1 RA0/AN0 NC 22 NC 25 23 RA2/AN2/CVREF/VREF26 RA2/AN2/CVREF/VREF26 24 RA4/AN4/T0CKI/C2OUT RA3/AN3/VREF+/C1OUT 1 21 RA7/OSC1/CLKI NC 2 20 RA6/OSC2/CLKO VSS 3 19 VDD NC 4 18 NC AVSS 5 17 AVDD NC 6 16 RB7/AN6/PGD/T1OSI RB0/INT/CCP1(1) 7 15 RB6/AN5/PGC/T1OSO/T1CKI 13 14 NC 11 NC RB5/SS/TX/CK 10 RB3/PGM/CCP1(1) 12 9 RB4/SCK/SCL 8 RB1/SDI/SDA PIC16F88 PIC16F88 RB2/SDO/RX/DT RA5/MCLR/VPP 27 PIC16F88 PIC16F88 28-PIN 28-PIN QFN 28 FIGURE 2-6: Note 1: Location of CCP1 function is determined by CCPMX. TABLE 2-1: Pin Name PIN DESCRIPTIONS (DURING PROGRAMMING): PIC16F87/88 PIC16F87/88 During Programming Function Pin Type Pin Description RB3 PGM I Low Voltage ICSP Programming Input if LVP Configuration bit equals `1' RB6 CLOCK I Clock Input RB7 DATA I/O Data Input/Output MCLR VPP P* Program Mode Select VDD VDD P Power Supply VSS VSS P Ground Legend: I = Input, O = Output, P = Power * To activate the Programming mode, high voltage needs to be applied to the MCLR input. Since MCLR is used for a level source, this means that MCLR does not draw any significant current. DS39607A-page 4 Advance Information ã 2002 Microchip Technology Inc. PIC16F87/88 PIC16F87/88 3.0 PROGRAM MODE ENTRY 3.2 3.1 User Program Memory Map The EEPROM data memory space is a separate block of high endurance memory that the user accesses, using a special sequence of instructions. The amount of data EEPROM memory depends on the device and is shown below in number of bytes. The user memory space extends from 0x0000 to 0x1FFF (8K) of which 4K (0000h-0FFFh) is physically implemented. In Programming mode, the program memory space extends from 0x0000 to 0x3FFF, with the first half (0x0000-0x1FFF) being user program memory and the second half (0x2000-0x3FFF) being configuration memory. The PC will increment from 0x0000 to 0x0FFF, then increment to 0x1000 and access 0x0000. Once the PC reaches 0x1FFF, it will increment to 0x2000. From 0x2000, the PC will increment up to 0x3FFF and wrap around to 0x2000 (not to 0x0000). Once in configuration memory, the highest bit of the PC stays a `1', thus always pointing to the configuration memory. The only way to point to user program memory is to reset the part and re-enter Program mode, as described in Section 3.4. Device Program FLASH PIC16F87 PIC16F87 4K PIC16F88 PIC16F88 Data EEPROM Memory Device # of Bytes PIC16F87 PIC16F87 256 PIC16F88 PIC16F88 256 The contents of data EEPROM memory have the capability to be embedded into the HEX file. The programmer should be able to read data EEPROM information from a HEX file and conversely (as an option), write data EEPROM contents to a HEX file, along with program memory information and configuration bit information. The 256 data memory locations are logically mapped and use PC. The format for data memory storage is one data byte per address location, LSb aligned. 4K In the configuration memory space, 0x2000-0x201F are physically implemented. However, only locations 0x2000 through 0x2008 are available. Other locations are reserved. Locations beyond 0x201F will physically access user memory (see Figure 3-1). ã 2002 Microchip Technology Inc. Advance Information DS39607A-page 5 PIC16F87/88 PIC16F87/88 3.3 ID Locations For these devices, it is recommended that ID location is written as "11 1111 1000 bbbb", where `bbbb' is ID information. A user may store identification information (ID) in four ID locations. The ID locations are mapped in [0x2000 : 0x2003]. It is recommended that the user use only the four Least Significant bits of each ID location. In some devices, the ID locations read out in an unscrambled fashion after code protection is enabled. FIGURE 3-1: In other devices, the ID locations read out normally, even after code protection. To understand how the devices behave, refer to Table 6-1. PROGRAM MEMORY MAPPING 4K words 0h 2000h ID Location 2001h ID Location 2002h ID Location 2003h ID Location 2004h Reserved 2005h Reserved 2006h Device ID 2007h Config1 2008h Config2 Implemented FFFh Accesses 0x0000 to 0x0FFF 1FFFh 2009h Reserved 3FFFh DS39607A-page 6 Advance Information ã 2002 Microchip Technology Inc. PIC16F87/88 PIC16F87/88 3.4 Program Mode 3.4.1 Program mode is entered by holding pins RB6 and RB7 low, while raising MCLR pin from VIL to VIHH (high voltage). In this mode, the state of the RB3 pin does not effect programming. Low Voltage ICSP Programming mode is entered by raising RB3 from VIL to VDD, and then applying VDD to MCLR. Once in this mode, the user program memory and the configuration memory can be accessed and programmed in serial fashion. The mode of operation is serial, and the memory accessed is the user program memory. RB6 and RB7 are Schmitt Trigger inputs in this mode. Note: The Osc must not have 72 osc clocks while the device MCLR is between VIL and VIHH. The sequence that enters the device into the Programming mode places all other logic into the RESET state (the MCLR pin was initially at VIL). This means all I/O are in the RESET state (high impedance inputs). A device RESET will clear the PC and set the address to `0'. The `Increment Address' command will increment the PC. The `Load Configuration' command will set the PC to 0x2000. The available commands are shown in Table 3-1. The normal sequence for programming four program memory words at a time is as follows: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. Set pointer to row location. Issue a `Begin Erase' command. Wait tprog2. Issue an `End Programming' command. Load a word at the current program memory address using the `Load Data' command. Issue an `Increment Address' command. Load a word at the current program memory address using the `Load Data' command. Repeat Step 6 and Step 7 two times. Issue a `Begin Programming' command to begin programming. Wait tprog1. Issue an `End Programming' command. Increment to the next address. Repeat steps 5 through 12 seven times to program one row. The address and program counter are reset to 0x0000 by resetting the device (taking MCLR below VIL) and re-entering Programming mode. Program and configuration memory may then be read or verified using the `Read Data' and `Increment Address' commands. ã 2002 Microchip Technology Inc. LOW VOLTAGE ICSP PROGRAMMING MODE Low Voltage ICSP Programming mode allows a PIC16F87/88 PIC16F87/88 device to be programmed using VDD only. However, when this mode is enabled by a configuration bit (LVP), the PIC16F87/88 PIC16F87/88 device dedicates RB3 to control entry/exit into Programming mode. When LVP bit is set to `1', the low voltage ICSP programming entry is enabled. Since the LVP configuration bit allows low voltage ICSP programming entry in its erased state, an erased device will have the LVP bit enabled at the factory. While LVP is `1', RB3 is dedicated to low voltage ICSP programming. Bring RB3 and then, MCLR to VDD to enter Programming mode. All other specifications for high voltage ICSP apply. To disable Low Voltage ICSP mode, the LVP bit must be programmed to `0'. This must be done while entered with the High Voltage Entry mode (LVP bit = 1). RB3 is now a general purpose I/O pin. 3.4.2 SERIAL PROGRAM OPERATION The RB6 pin is used as a clock input pin, and the RB7 pin is used to enter command bits, and to input or output data during serial operation. To input a command, the clock pin (RB6) is cycled six times. Each command bit is latched on the falling edge of the clock, with the Least Significant bit (LSb) of the command being input first. The data on RB7 is required to have a minimum setup (tset1) and hold (thold1) time (see AC/DC specifications), with respect to the falling edge of the clock. Commands with associated data (read and load) are specified to have a minimum delay (tdly1) of 1 ms between the command and the data. After this delay, the clock pin is cycled 16 times, with the first cycle being a START bit (0) and the last cycle being a STOP bit (0). Data is transferred LSb first. During a read operation, the LSb will be transmitted onto RB7 on the rising edge of the second cycle, and during a load operation, the LSb will be latched on the falling edge of the second cycle. A minimum 1 ms delay (tdly2) is specified between consecutive commands. All commands and data words are transmitted LSb first. The data is transmitted on the rising edge and latched on the falling edge of the clock. To allow decoding of commands and reversal of data pin configuration, a time separation of at least 1 ms (tdly1) is required between a command and a data word, or another command. The available commands are described in the following paragraphs and listed in Table 3-1. Advance Information DS39607A-page 7 PIC16F87/88 PIC16F87/88 184.108.40.206 Load Configuration 220.127.116.11 After receiving this command, the program counter (PC) will be set to 0x2000. By then applying 16 cycles to the clock pin, the chip will load 14 bits in a "data word," as described above, to be programmed into the configuration memory. A description of the memory mapping schemes of the program memory for normal operation and Configuration mode operation is shown in Figure 3-1. After the configuration memory is entered, the only way to get back to the user program memory is to exit the Program mode by taking MCLR low (VIL). 18.104.22.168 Load Data for Program Memory After receiving this command, the chip will load one word (with 14 bits as a "data word") to be programmed into user program memory when 16 cycles are applied. A timing diagram for this command is shown in Figure 7-1. 22.214.171.124 Load Data for Data Memory After receiving this command, the chip will load in a 14-bit "data word" when 16 cycles are applied. However, the data memory is only 8-bits wide, and thus, only the first 8 bits of data after the START bit will be programmed into the data memory. It is still necessary to cycle the clock the full 16 cycles in order to allow the internal circuitry to reset properly. The data memory contains up to 256 bytes. If the device is code protected, the data is read as all zeros. A timing diagram for this command is shown in Figure 7-2. 126.96.36.199 Read Data from Program Memory Begin Erase (Program and Data Memory) The erase block size for program memory is 32 words (row) and 1 word for data memory. The row or word to be programmed must first be erased. This is done by setting the pointer to a location in the row or word and then performing a `Begin Erase' command. The row or word is then erased. The user must allow the combined time for row erase and programming, as specified in the electrical specifications, for programming to complete. This is an externally timed event. The internal timer is not used for this command, so the `End Programming' command must be used to stop erase. Note 1: The code protect bits cannot be erased with this command. 2: All `Begin Erase' operations can take place over the entire VDD range. A timing diagram for this command is shown in Figure 7-6. 188.8.131.52 Begin Programming Only Programming of program and data memory will begin after this command is received and decoded. The user must allow the time for programming, as specified in the electrical specifications, for programming to complete. An `End Programming' command is required. The internal timer is not used for this command, so the `End Programming' command must be used to stop programming. After receiving this command, the chip will transmit data bits out of the program memory (user or configuration) currently accessed, starting with the second rising edge of the clock input. The RB7 pin will go into Output mode on the second rising clock edge, and it will revert back to Input mode (hi-impedance) after the 16th rising edge. A timing diagram of this command is shown in Figure 7-3. 1. 184.108.40.206 A timing diagram for this command is shown in Figure 7-7. Read Data from Data Memory After receiving this command, the chip will transmit data bits out of the data memory, starting with the second rising edge of the clock input. The RB7 pin will go into Output mode on the second rising edge, and it will revert back to Input mode (hi-impedance) after the 16th rising edge. As previously stated, the data memory is 8-bits wide and therefore, only the first 8 bits that are output are actual data. A timing diagram for this command is shown in Figure 7-4. 220.127.116.11 2. If the address is pointing to user memory, the user memory alone will be affected. If the address is pointing to the physically implemented configuration memory (2000h - 2008h), the configuration memory will be written. The configuration words will not be written unless the address is specifically pointing to the corresponding address. 18.104.22.168 End Programming After receiving this command, the chip stops programming the memory (configuration memory or user program memory), that it was programming at the time. Note: Increment Address This command will also set the write data shift latches to all `1's to avoid issues with downloading only one word before the write. The PC is incremented when this command is received. A timing diagram of this command is shown in Figure 7-5. DS39607A-page 8 Advance Information ã 2002 Microchip Technology Inc. PIC16F87/88 PIC16F87/88 TABLE 3-1: COMMAND MAPPING FOR PIC16F87/88 PIC16F87/88 Command Load Configuration Mapping (MSB . LSB) 0 0 0 0 Data 0 0, data (14), 0 Voltage Range 2.0V - 5.5V Load Data for Program Memory 0 0 0 1 0 0, data (14), 0 2.0V - 5.5V Read Data from Program Memory 0 0 1 0 0 0, data (14), 0 2.0V - 5.5V Increment Address 0 0 1 1 0 Begin Erase 0 1 0 0 0 externally timed 2.0V - 5.5V 2.0V - 5.5V Begin Programming Only Cycle 1 1 0 0 0 externally timed 2.0V - 5.5V Bulk Erase Program Memory 0 1 0 0 1 externally timed 4.5V - 5.5V Bulk Erase Data Memory 0 1 0 1 1 externally timed 4.5V - 5.5V Chip Erase 1 1 1 1 1 internally timed 4.5V - 5.5V Load Data for Data Memory 0 0 0 1 1 0, zeroes (6), data (14), 0 2.0V - 5.5V Read Data from Data Memory 0 0 1 0 1 0, zeroes (6), data (14), 0 2.0V - 5.5V End Programming 1 0 1 1 1 3.5 Erasing Program and Data Memory Depending on the state of the code protection bits, program and data memory will be erased using different methods. The first two commands are used when both program and data memories are not code protected. The third command is used when either memory is code protected, or if you want to also erase the code protect bits. A device programmer should determine the state of the code protection bits and then apply the proper command to erase the desired memory. 3.5.1 ERASING PROGRAM AND DATA MEMORY Previously, a load data with 0FFh command was recommended before any `Bulk Erase'. On these devices, this will not be required. The `Bulk Erase' command is disabled when the CP bit is programmed to `0', enabling code protect. A timing diagram for this command is shown in Figure 7-8. 22.214.171.124 When both program and data memories are non-code protected, they can be individually erased by the following `Bulk Erase' commands. If it is desired to erase both program and data memory with a single command, then the `Chip Erase' command must be used whether code protection is disabled or enabled (`Chip Erase' detailed in Section 126.96.36.199). 188.8.131.52 If the address is pointing to the configuration memory (2000h - 2008h), then both the user memory and the configuration memory will be erased. The configuration words will not be erased, even if the address is pointing to location 2007h. Bulk Erase Program Memory Bulk Erase Data Memory When this command is performed, and is followed by a `Begin Erase' command, the entire data memory will be erased. The `Bulk Erase Data' command is disabled when the CPD bit is programmed to `0', enabling protected data memory. A timing diagram for this command is shown in Figure 7-9. Note: When this command is performed, and is followed by a `Begin Erase' command, the entire program memory will be erased. All `Bulk Erase' operations must take place at the 4.5V to 5.5V VDD range. If the address is pointing to user memory, only the user memory will be erased. ã 2002 Microchip Technology Inc. Advance Information DS39607A-page 9 PIC16F87/88 PIC16F87/88 184.108.40.206 Chip Erase 3.5.2 This command, when performed, will erase the program memory, EE data memory, and all of the code protection bits. All on-chip FLASH and EEPROM memory is erased, regardless of the address contained in the PC. The data in 2000h - 201Fh (excluding 2006h, 2007h, and 2008h) can only be erased if the PC is pointing to 2000h when a `Chip Erase' command is issued. The `Chip Erase' is internally self-timed to ensure that all program and data memory is erased before the code protect bits are erased. A timing diagram for this command is shown in Figure 7-10. Note: ERASING CODE PROTECTED MEMORY For the PIC16F87/88 PIC16F87/88 devices, once code protection is enabled, all protected program and data memory locations read all '0's and further programming is disabled. The ID locations and configuration words read out unscrambled and can be reprogrammed normally. The only command to erase a code protected PIC16F87/88 PIC16F87/88 device is the `Chip Erase'. This erases program memory, data memory, configuration bits and ID locations, as described in Section 220.127.116.11. Since all data within the program and data memory will be erased when this command is executed, the security of the data or code is not compromised. The `Chip Erase' operation must take place at the 4.5V to 5.5V VDD range. DS39607A-page 10 Advance Information ã 2002 Microchip Technology Inc. PIC16F87/88 PIC16F87/88 FIGURE 3-2: ALGORITHM 1 FLOW CHART PROGRAM MEMORY (2.0V £ VDD < 5.5V) Start Set VDD = VDDP Begin Erase Command Wait tprog2 End Programming Command Load Data Command Increment Address Command No Four Loads Done? Yes Begin Programming Only Command Wait tprog1 End Programming Command Increment Address Command No Yes Increment Address Command No All Locations Done? Yes ã 2002 Microchip Technology Inc. Verify all Locations All Row Locations Done? Advance Information Report Verify Error No Data Correct? Yes End DS39607A-page 11 PIC16F87/88 PIC16F87/88 FIGURE 3-3: ALGORITHM 2 FLOW CHART PROGRAM MEMORY (4.5V £ VDD £ 5.5V) Start Chip Erase Sequence Set VDD = VDDP Load Data Command Increment Address Command No Four Loads Done? Yes Begin Programming Only Command Wait tprog1 End Programming Command Increment Address Command No All Locations Done? Yes Verify all Locations Report Verify Error No Data Correct? Yes End DS39607A-page 12 Advance Information ã 2002 Microchip Technology Inc. PIC16F87/88 PIC16F87/88 FIGURE 3-4: FLOW CHART PIC16F87/88 PIC16F87/88 CONFIGURATION MEMORY (2.0V £ VDD < 5.5V) AND (4.5V £ VDD < 5.5V) PROGRAM FOUR LOCATIONS Start Start Load Configuration Data (Set PC = 2000h) Begin Erase Command Load Configuration Data Wait tprog2 Yes Program ID Location? Program Four Locations End Programming Command Read Data Command No Report Programming Failure No Load Data Command Data Correct? Yes Yes Increment Address Command Increment Address Command Address = 0x2003? Address = 0x2004? Four Loads Done? Yes Begin Program Only Command No No No Increment Address Command Wait tprog1 Yes End Programming Command Increment Address Command End Increment Address Command PROGRAM CONFIG1 and CONFIG2 Increment Address Command Report Program Configuration Word Error No Program Config1 Data Correct? Read Data Command Increment Address Command Program Config2 Start Load Data Command Begin Program Only Command Wait tprog1 End Programming Command Yes End End ã 2002 Microchip Technology Inc. Advance Information DS39607A-page 13 PIC16F87/88 PIC16F87/88 4.0 CONFIGURATION WORD The PIC16F87/88 PIC16F87/88 has several configuration bits. These bits can be written to `0' or `1' with the `Begin Program Only' command. A `Begin Erase' command is not required when programming configuration memory. 4.1 Device ID Word The device ID word for the PIC16F87/88 PIC16F87/88 is located at 2006h. TABLE 4-1: Device DEVICE ID VALUE Device ID Value Dev Rev PIC16F87 PIC16F87 00 0111 0010 XXXX PIC16F88 PIC16F88 00 0111 0110 XXXX DS39607A-page 14 Advance Information ã 2002 Microchip Technology Inc. PIC16F87/88 PIC16F87/88 REGISTER 4-1: CP CONFIGURATION WORD 1 (2007h) REGISTER CCPMX DEBUG WRT1 WRT0 CPD LVP BOREN MCLRE FOSC2 PWRTEN WDTEN FOSC1 FOSC0 bit 13 bit 13 bit 0 CP: FLASH Program Memory Code Protection bits 1 = Code protection off 0 = 0000h to 0FFFh code protected (all protected) bit 12 CCPMX: CCP Mux bit 1 = CCP1 function on RB0 0 = CCP1 function on RB3 bit 11 DEBUG: In-Circuit Debugger Mode bit 1 = In-Circuit Debugger disabled, RB6 and RB7 are general purpose I/O pins 0 = In-Circuit Debugger enabled, RB6 and RB7 are dedicated to the debugger bit 10-9 WRT1:WRT0: FLASH Program Memory Write Enable bits 11 = Write protection off 10 = 0000h to 00FFh write protected, 0100h to 0FFFh may be modified by EECON control 01 = 0000h to 07FFh write protected, 0800h to 0FFFh may be modified by EECON control 00 = 0000h to 0FFFh write protected bit 8 CPD: Data EE Memory Code Protection bit 1 = Code protection off 0 = Data EE memory code protected bit 7 LVP: Low Voltage Programming Enable bit 1 = RB3/PGM pin has PGM function, low voltage programming enabled 0 = RB3 is digital I/O, HV on MCLR must be used for programming bit 6 BOREN: Brown-out Reset Enable bit 1 = BOR enabled 0 = BOR disabled bit 5 MCLRE: RA5/MCLR Pin Function Select bit 1 = RA5/MCLR pin function is MCLR 0 = RA5/MCLR pin function is digital I/O, MCLR internally tied to VDD bit 3 PWRTEN: Power-up Timer Enable bit 1 = PWRT disabled 0 = PWRT enabled bit 2 WDTEN: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled bit 4, 1-0 FOSC2:FOSC0: Oscillator Selection bits 111 = EXTRC oscillator; CLKO function on RA6/OSC2/CLKO 110 = EXTRC oscillator; Port I/O function on RA6/OSC2/CLKO 101 = INTRC oscillator; CLKO function on RA6/OSC2/CLKO 100 = INTRC oscillator; Port I/O function on RA6/OSC2/CLKO 011 = EXTCLK; Port I/O function on RA6/OSC2/CLKO 010 = HS oscillator 001 = XT oscillator 000 = LP oscillator Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR 1 = bit is set 0 = bit is cleared ã 2002 Microchip Technology Inc. Advance Information x = bit is unknown DS39607A-page 15 PIC16F87/88 PIC16F87/88 REGISTER 4-2: CONFIGURATION WORD 2 (2008h) REGISTER U-1 U-1 U-1 U-1 U-1 U-1 U-1 U-1 U-1 U-1 U-1 U-1 - - - - - - - - - - - - IESO bit 13 FCMEN bit 0 bit 13-2 Unimplemented: Read as `1' bit 1 IESO: Internal External Switch Over bit 1 = Internal External Switch Over mode enabled 0 = Internal External Switch Over mode disabled bit 0 FCMEN: Fail-Safe Clock Monitor Enable bit 1 = Fail-Safe Clock Monitor enabled 0 = Fail-Safe Clock Monitor disabled Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR 1 = bit is set 0 = bit is cleared DS39607A-page 16 Advance Information x = bit is unknown ã 2002 Microchip Technology Inc. PIC16F87/88 PIC16F87/88 5.0 EMBEDDING CONFIGURATION WORD AND ID INFORMATION IN HEX FILE To allow portability of code, the programmer is required to read the configuration word and ID locations from the HEX file when loading the HEX file. If configuration word information was not present in the HEX file, then a simple warning message may be issued. Similarly, while saving a HEX file, configuration word and ID information must be included. An option to not include this information may be provided. Specifically for the PIC16F87/88 PIC16F87/88, the EEPROM data memory should also be embedded in the HEX file (see Section 3.2). Microchip Technology Inc. feels strongly that this feature is important for the benefit of the end customer. 6.0 CHECKSUM COMPUTATION Checksum is calculated by reading the contents of the PIC16F87/88 PIC16F87/88 memory locations and adding up the opcodes, up to the maximum user addressable location (e.g., 0xFFF for the PIC16F87/88 PIC16F87/88). Any carry bits exceeding 16 bits are neglected. Finally, the configuration word (appropriately masked) is added to the checksum. Checksum computation for each member of the PIC16F87/88 PIC16F87/88 devices is shown in Table 6-1. The checksum is calculated by summing the following: · The contents of all program memory locations · The configuration words, appropriately masked · Masked ID locations (when applicable) TABLE 6-1: The Least Significant 16 bits of this sum are the checksum. The following table describes how to calculate the checksum for each device. Note that the checksum calculation differs depending on the code protect setting. Since the program memory locations read out differently depending on the code protect setting, the table describes how to manipulate the actual program memory values to simulate the values that would be read from a protected device. When calculating a checksum by reading a device, the entire program memory can simply be read and summed. The configuration words and ID locations can always be read. Note that some older devices have an additional value added in the checksum. This is to maintain compatibility with older device programmer checksums. CHECKSUM COMPUTATION Blank Value 0x25E6 at 0 and Max Address SUM(0000:0FFF) + (CONFIG0 & 3FFF) + (CONFIG1 & 0003) 3002 FBD0 (CONFIG0 & 3FFF) + (CONFIG1 & 0003) + SUM_ID 5004 IBD2 SUM(0000:0FFF) + (CONFIG0 & 3FFF) + (CONFIG1 & 0003) 3002 FBD0 (CONFIG0 & 3FFF) + (CONFIG1 & 0003) + SUM_ID 5004 IBD2 Code Protect Checksum* OFF ON OFF ON Device PIC16F87 PIC16F87 PIC16F88 PIC16F88 Legend: CFGW SUM[a:b] SUM_ID = Configuration Word = [Sum of locations a to b inclusive] = ID locations masked by 0xF, then made into a 16-bit value with ID0 as the Most Significant nibble. For example, ID0 = 0x1, ID1 = 0x2, ID3 = 0x3, ID4 = 0x4, then SUM_ID = 0x1234. *Checksum = [Sum of all the individual expressions] MODULO [0xFFFF] + = Addition & = Bitwise AND ã 2002 Microchip Technology Inc. Advance Information DS39607A-page 17 PIC16F87/88 PIC16F87/88 7.0 PROGRAM MODE ELECTRICAL CHARACTERISTICS TABLE 7-1: TIMING REQUIREMENTS FOR PROGRAM MODE AC/DC CHARACTERISTICS POWER SUPPLY PINS Characteristics Standard Operating Procedure (unless otherwise stated) Operating Temperature 0 £ TA £ +70°C Operating Voltage 2.0V £ VDD £ 5.5V Sym Min Typ Max Units Conditions/Comments General VDD level for Begin Erase, Begin Program operations and EECON1 writes of program memory VDD 2.0 - 5.5 V VDD level for Begin Erase, Begin Program operations and EECON1 writes of data memory VDD 2.0 - 5.5 V VDD level for Bulk Erase, Chip Erase, and Begin Program operations of program and data memory VDD 4.5 - 5.5 V Begin Programming Only cycle time tprog1 1 - - ms Externally Timed, > 4.5V 2 - - ms Externally Timed, < 4.5V Begin Erase tprog2 1 - - ms Externally Timed, > 4.5V 2 - - ms Externally Timed, < 4.5V 2 - - ms Externally Timed Internally Timed Bulk Erase cycle time tprog3 Chip Erase cycle time tprog4 High voltage on MCLR and RA4/T0CKI for Program mode entry VIHH 8 - - ms VDD + 3.5 - 13.5 V MCLR rise time (VSS to VHH) for Program mode entry tVHHR - - 1.0 ms (RB6, RB7) input high level VIH1 0.8 VDD - - V Schmitt Trigger input (RB6, RB7) input low level VIL1 0.2 VDD - - V Schmitt Trigger input RB setup time before MCLR (Program mode selection pattern setup time) tset0 100 - - ns RB hold time after MCLR (Program mode selection pattern setup time) thld0 5 - - ms Data in setup time before clock¯ tset1 100 - - ns Data in hold time after clock¯ thld1 100 - - ns Data input not driven to next clock input (delay required between command/data or command/ command) tdly1 Delay between clock¯ to clock of next command or data tdly2 Clock to data out valid (during read data) tdly3 Serial Program DS39607A-page 18 1.0 - - ms 2.0V £ VDD < 4.5V 100 - - ns 4.5V £ VDD £ 5.5V 1.0 - - ms 2.0V £ VDD < 4.5V 100 - - ns 4.5V £ VDD £ 5.5V 80 - - ns Advance Information ã 2002 Microchip Technology Inc. PIC16F87/88 PIC16F87/88 FIGURE 7-1: LOAD DATA FOR USER PROGRAM MEMORY COMMAND (PROGRAM) VIHH MCLR 1 ms min tset0 1 2 3 4 5 6 1 tdly2 RB6 (Clock) 2 3 4 5 15 16 thld0 1 0 RB7 (Data) 0 0 0 strt_bit X tset1 stp_bit tset1 tdly1 1 ms min thld1 } } } } thld1 100 ns min 100 ns min Program Mode RESET FIGURE 7-2: LOAD DATA FOR USER DATA MEMORY COMMAND (PROGRAM) VIHH MCLR 1 ms min tset0 1 2 3 4 5 6 1 tdly2 RB6 (Clock) 2 3 4 5 15 16 thld0 1 1 RB7 (Data) 0 0 0 tset1 strt_bit X stp_bit tset1 tdly1 1 ms min thld1 } } } } thld1 100 ns min 100 ns min Program Mode RESET FIGURE 7-3: READ DATA FROM PROGRAM MEMORY COMMAND (PROGRAM) VIHH MCLR tset0 tdly2 thld0 1 2 3 4 1 0 5 6 1 ms min 1 2 3 RB6 (Clock) RB7 (Data) 4 5 15 16 tdly3 0 0 0 bit 13 bit 0 X tdly1 tset1 thld1 RESET ã 2002 Microchip Technology Inc. 1 ms min } } 100 ns min RB7 = Input RB7 = Output RB7 Input Program Mode Advance Information DS39607A-page 19 PIC16F87/88 PIC16F87/88 FIGURE 7-4: READ DATA FROM DATA MEMORY COMMAND (PROGRAM) VIHH MCLR tdly2 tset0 thld0 1 2 3 4 1 5 0 1 ms min 6 1 2 3 RB6 (Clock) 4 5 15 16 tdly3 RB7 (Data) 1 0 0 bit 13 bit 0 X tdly1 tset1 thld1 1 ms min } } 100 ns min RB7 = Input RB7 = Output RB7 Input Program Mode RESET FIGURE 7-5: INCREMENT ADDRESS COMMAND (SERIAL PROGRAM) VIHH MCLR tdly2 1 2 3 4 5 Next Command 1 ms min. 6 1 2 RB6 (Clock) RB7 (Data) 0 1 0 1 X X X tset1 0 tdly1 thld1 } } 1 ms min. 100 ns min. Program Mode RESET FIGURE 7-6: BEGIN ERASE (SERIAL PROGRAM) VIHH MCLR tprog2 1 2 3 4 5 End Programming Command 1 6 2 RB6 (Clock) RB7 (Data) 0 0 0 1 0 X tset1 X 0 ? thld1 } } 100 ns min. RESET DS39607A-page 20 Program Mode Advance Information ã 2002 Microchip Technology Inc. PIC16F87/88 PIC16F87/88 FIGURE 7-7: BEGIN PROGRAMING ONLY COMMAND (SERIAL PROGRAM) VIHH MCLR tprog1 1 2 0 3 0 4 5 End Programming Command 1 6 2 RB6 (Clock) RB7 (Data) 0 1 1 X X tset1 0 ? thld1 } } 100 ns min. Program Mode RESET FIGURE 7-8: BULK ERASE PROGRAM MEMORY COMMAND (SERIAL PROGRAM/VERIFY) VIHH MCLR Begin Erase 1 2 3 4 5 6 1 End Programming tprog3 2 1 2 RB6 (Clock) RB7 (Data) 1 0 1 0 X X X 0 tset1 X 0 ? thld1 } } 100 ns min. Program/Verify Test Mode RESET FIGURE 7-9: BULK ERASE DATA MEMORY COMMAND (SERIAL PROGRAM/VERIFY) VIHH MCLR Begin Erase 1 2 3 4 5 6 1 tprog3 2 End Programming 1 2 RB6 (Clock) RB7 (Data) 1 1 1 0 X X X tset1 0 X 0 ? thld1 } } 100 ns min. RESET ã 2002 Microchip Technology Inc. Program/Verify Test Mode Advance Information DS39607A-page 21 PIC16F87/88 PIC16F87/88 FIGURE 7-10: CHIP ERASE COMMAND (SERIAL PROGRAM) VIHH MCLR tprog4 1 2 3 1 1 4 1 5 X X Next Command 1 6 2 RB6 (Clock) RB7 (Data) 1 X tdly1 0 tset1 thld1 1 ms min. } } 100 ns min. RESET DS39607A-page 22 Program Mode Advance Information ã 2002 Microchip Technology Inc. Note the following details of the code protection feature on PICmicro® MCUs. · · · · · · The PICmicro family meets the specifications contained in the Microchip Data Sheet. Microchip believes that its family of PICmicro microcontrollers is one of the most secure products of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the PICmicro microcontroller in a manner outside the operating specifications contained in the data sheet. The person doing so may be engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable". Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our product. If you have any further questions about this matter, please contact the local sales office nearest to you. Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip's products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, KEELOQ, MPLAB, PIC, PICmicro, PICSTART and PRO MATE are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, microID, MXDEV, MXLAB, PICMASTER, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. dsPIC, dsPICDEM.net, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, microPort, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, PICC, PICDEM, PICDEM.net, rfPIC, Select Mode and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. Serialized Quick Turn Programming (SQTP) is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2002, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received QS-9000 QS-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona in July 1999 and Mountain View, California in March 2002. The Company's quality system processes and procedures are QS-9000 QS-9000 compliant for its PICmicro® 8-bit MCUs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, non-volatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001 certified. Ó 2002 Microchip Technology Inc. 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Le Colleoni 1 20041 Agrate Brianza Milan, Italy Tel: 39-039-65791-1 Fax: 39-039-6899883 United Kingdom Microchip Ltd. 505 Eskdale Road Winnersh Triangle Wokingham Berkshire, England RG41 5TU Tel: 44 118 921 5869 Fax: 44-118 921-5820 08/01/02 DS39607A-page 24 Advance Information ã 2002 Microchip Technology Inc.