PIC16F/LF1826/27 DS41391B PICC-18 PIC32 ISO/TS-16949 PIC16F1826/27 - Datasheet Archive

 

Data Sheet 18/20/28-Pin Flash Microcontrollers with nanoWatt XLP Technology © 2009 Microchip Technology Inc. Preliminary

 

PIC16F/LF1826/27 PIC16F/LF1826/27 Data Sheet 18/20/28-Pin Flash Microcontrollers with nanoWatt XLP Technology © 2009 Microchip Technology Inc. Preliminary DS41391B DS41391B Note the following details of the code protection feature on Microchip devices: · Microchip products meet the specification contained in their particular Microchip Data Sheet. · Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. · There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. · Microchip is willing to work with the customer who is concerned about the integrity of their code. · Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, rfPIC and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code Generation, PICC, PICC-18 PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, PIC32 PIC32 logo, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2009, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949 ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company's quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified. DS41391B-page 2 Preliminary © 2009 Microchip Technology Inc. PIC16F/LF1826/27 PIC16F/LF1826/27 18/20/28-Pin Flash Microcontrollers with nanoWatt XLP Technology High-Performance RISC CPU: · C Compiler Optimized Architecture · 256 bytes Data EEPROM · Up to 4 Kbytes Linear Program Memory Addressing · Up to 384 bytes Linear Data Memory Addressing · Interrupt Capability with Automatic Context Saving · 16-Level Deep Hardware Stack with Optional Overflow/Underflow Reset · Direct, Indirect and Relative Addressing modes: - Two full 16-bit File Select Registers (FSRs) - FSRs can read program and data memory Flexible Oscillator Structure: · Precision 32 MHz Internal Oscillator Block: - Factory calibrated to ± 1%, typical - Software selectable frequencies range of 31 kHz to 32 MHz · 31 kHz Low-Power Internal Oscillator · Four Crystal modes up to 32 MHz · Three External Clock modes up to 32 MHz · 4X Phase Lock Loop (PLL) · Fail-Safe Clock Monitor: - Allows for safe shutdown if peripheral clock stops · Two-Speed Oscillator Start-up · Reference Clock Module: - Programmable clock output frequency and duty-cycle · · · · · · · Full 5.5V Operation ­ PIC16F1826/27 PIC16F1826/27 1.8V-3.6V Operation ­ PIC16LF1826/27 PIC16LF1826/27 Self-reprogrammable under Software Control Power-on Reset (POR), Power-up Timer (PWRT) and Oscillator Start-up Timer (OST) Programmable Brown-out Reset (BOR) Extended Watchdog Timer (WDT): - Programmable period from 1ms to 268s Programmable Code Protection In-Circuit Serial ProgrammingTM (ICSPTM) via two pins In-Circuit Debug (ICD) via two pins Enhance Low-Voltage Programming Power-Saving Sleep mode © 2009 Microchip Technology Inc. · Sleep mode: 30 nA · Watchdog Timer: 500 nA · Timer1 Oscillator: 600 nA @ 32 kHz Analog Features: · Analog-to-Digital Converter (ADC) Module: - 10-bit resolution, 12 channels - Auto acquisition capability - Conversion available during Sleep · Analog Comparator Module: - Two rail-to-rail analog comparators - Power mode control - Software controllable hysteresis · Voltage Reference Module: - Fixed Voltage Reference (FVR) with 1.024V, 2.048V and 4.096V output levels - 5-bit rail-to-rail resistive DAC with positive and negative reference selection Peripheral Highlights: Special Microcontroller Features: · · · · Extreme Low-Power Management PIC16LF1826/27 PIC16LF1826/27 with nanoWatt XLP: · 15 I/O Pins and 1 Input Only Pin: - High current sink/source 25 mA/25 mA - Programmable weak pull-ups - Programmable interrupt-on- change pins · Timer0: 8-Bit Timer/Counter with 8-Bit Prescaler · Enhanced Timer1: - 16-bit timer/counter with prescaler - External Gate Input mode - Dedicated, low-power 32 kHz oscillator driver · Up to three Timer2-types: 8-Bit Timer/Counter with 8-Bit Period Register, Prescaler and Postscaler · Up to two Capture, Compare, PWM (CCP) Modules · Up to two Enhanced CCP (ECCP) Modules: - Software selectable time bases - Auto-shutdown and auto-restart - PWM steering · Up to two Master Synchronous Serial Port (MSSP) with SPI and I2CTM with: - 7-bit address masking - SMBus/PMBusTM compatibility · Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) Module · mTouchTM Sensing Oscillator Module: - Up to 12 input channels · Data Signal Modulator Module: - Selectable modulator and carrier sources · SR Latch: - Multiple Set/Reset input options - Emulates 555 Timer applications Preliminary DS41391B-page 3 PIC16F/LF1826/27 PIC16F/LF1826/27 I/O's(1) 10-bit ADC (ch) CapSense (ch) Comparators Timers (8/16-bit) EUSART MSSP ECCP (Full-Bridge) ECCP (Half-Bridge) CCP SR Latch PIC16LF1826 PIC16LF1826 2K 256 PIC16F1826 PIC16F1826 2K 256 PIC16LF1827 PIC16LF1827 4K 384 PIC16F1827 PIC16F1827 4K 384 Note 1: One pin is input only. DS41391B-page 4 256 256 256 256 16 16 16 16 12 12 12 12 12 12 12 12 2 2 2 2 2/1 2/1 4/1 4/1 1 1 1 1 1 1 2 2 1 1 1 1 - - 1 1 - - 2 2 Yes Yes Yes Yes Data Memory SRAM (bytes) Words Device Program Memory Data EEPROM (bytes) PIC16F/LF1826/27 PIC16F/LF1826/27 Family Types Preliminary © 2009 Microchip Technology Inc. © 2009 Microchip Technology Inc. 1: 2: 1 Preliminary (1) (2) (2) (1) 9 8 1 Pin feature is dependent on device configuration. ECCP2, CCP3, CCP4, MSSP2 functions are only available on the PIC16F/LF1827 PIC16F/LF1827. RB3/AN9/CPS9/MDOUT/CCP1(1)/P1A(1) RB2/AN10/CPS10/MDMIN/TX RB2/AN10/CPS10/MDMIN/TX /CK /RX /DT /SDA2 /SDI2 /SDO1 (1) 7 (1) RB1/AN11/CPS11/RX RB1/AN11/CPS11/RX(1)/DT(1)/SDA1/SDI1 (1) 7 6 VSS (1) Pin feature is dependent on device configuration. ECCP2, CCP3, CCP4, MSSP2 functions are only available on the PIC16F/LF1827 PIC16F/LF1827. RB3/AN9/CPS9/MDOUT/CCP1 /P1A (1) 10 9 8 (1,3)/DT(1,3)/SDA1/SDI1 RB1/AN11/CPS11/RX RB1/AN11/CPS11/RX RB0/SRI/T1G/CCP1 /P1A /INT/FLT0 (1) 5 VSS (1) 4 RA5/MCLR/VPP/SS1(1,2) 3 RA4/AN4/CPS4/C2OUT/T0CKI/CCP4(2)/SRNQ 2 RA2/AN2/CPS2/C12IN2-/C12IN RA2/AN2/CPS2/C12IN2-/C12IN+/VREF-/DACOUT ) 1: 2: 5 PIC16F/LF1826/27 PIC16F/LF1826/27 Note SSOP VSS 6 (1) 4 RB0/SRI/T1G/CCP1 /P1A /INT/SRI/FLT0 (1) RA5/MCLR/VPP/SS1 (1,2) 3 RA4/AN4/CPS4/C2OUT/T0CKI/CCP4(2)/SRNQ 2 RA2/AN2/CPS2/C12IN2-/C12IN RA2/AN2/CPS2/C12IN2-/C12IN+/VREF-/DACOUT Pin Diagram ­ 20-Pin SSOP (PIC16F/LF1826/27 PIC16F/LF1826/27) Note PDIP, SOIC Pin Diagram ­ 18-Pin PDIP, SOIC (PIC16F/LF1826/27 PIC16F/LF1826/27) RA1/AN1/CPS1/C12IN1-/SS2 RA1/AN1/CPS1/C12IN1-/SS2(2) RA6/OSC2/CLKOUT/CLKR/P1D(1)/P2B(1,2)/SDO1(1) VDD RB7/AN6/CPS6/T1OSO/P1D(1)/P2B(1,2)/MDCIN1/ICSPDAT ) RB4/AN8/CPS8/SCL1/SCK1/MDCIN2 RA1/AN1/CPS1/C12IN1-/SS2 RA1/AN1/CPS1/C12IN1-/SS2(2) RA0/AN0/CPS0/C12IN0-/SDO2 RA0/AN0/CPS0/C12IN0-/SDO2(2) RA7/OSC1/CLKIN/P1C(1)/CCP2(1,2)/P2A(1,2) 16 15 14 13 12 11 10 20 19 18 11 12 13 14 15 16 RB4/AN8/CPS8/SCL1/SCK1/MDCIN2 ) RB7/AN6/CPS6/T1OSO/P1D(1)/P2B(1,2)/MDCIN1/ICSPDAT VDD VDD RA6/OSC2/CLKOUT/CLKR/P1D(1)/P2B(1,2)/SDO1(1) RA7/OSC1/CLKIN/P1C(1)/CCP2(1,2)/P2A(1,2) 17 17 RA0/AN0/CPS0/C12IN0-/SDO2 RA0/AN0/CPS0/C12IN0-/SDO2(2) 18 PIC16F/LF1826/27 PIC16F/LF1826/27 PIC16F/LF1826/27 PIC16F/LF1826/27 DS41391B-page 5 PIC16F/LF1826/27 PIC16F/LF1826/27 NC RA1/AN1/CPS1/C12IN1-/SS2 RA1/AN1/CPS1/C12IN1-/SS2(2) RA0/AN0/CPS0/C12IN0-/SDO2 RA0/AN0/CPS0/C12IN0-/SDO2(2) 28 27 26 25 24 23 22 NC RA4/AN4/CPS4/C2OUT/T0CKI/CCP4(2)/SRNQ QFN/UQFN RA2/AN2/CPS2/C12IN2-/C12IN RA2/AN2/CPS2/C12IN2-/C12IN+/VREF-/DACOUT Pin Diagram ­ 28-Pin QFN/UQFN (PIC16F/LF1826/27 PIC16F/LF1826/27) VSS NC VSS NC 1: 2: RA7/OSC1/CLKIN/P1C(1)/CCP2(1,2)/P2A(1,2) RA6/OSC2/CLKOUT/CLKR/P1D(1)/P2B(1,2)/SDO1(1) VDD NC VDD RB7/AN6/CPS6/T1OSO/P1D(1)/P2B(1,2)/MDCIN1/ICSPDAT RB5/AN7/CPS7/P1B/TX /CK /SCL2 /SCK2 /SS1 (1) (2) (2) (1) (1) RB4/AN8/CPS8/SCL1/SCK1/MDCIN2 RB3/AN9/CPS9/MDOUT/CCP1(1)/P1A(1) RB1/AN11/CPS11/RX RB1/AN11/CPS11/RX(1)/DT(1)/SDA1/SDI1 Note ) NC RB0/SRI/T1G/CCP1(1)/P1A(1)/INT/SRI/FLT0 1 21 2 20 3 19 4 PIC16F/LF1826/27 PIC16F/LF1826/27 18 17 5 6 16 7 15 NC NC 8 9 10 11 12 13 14 RA5/ MCLR/VPP/SS1(1) Pin feature is dependent on device configuration. ECCP2, CCP3, CCP4, MSSP2 functions are only available on the PIC16F/LF1827 PIC16F/LF1827. DS41391B-page 6 Preliminary © 2009 Microchip Technology Inc. 18 1 2 3 4 15 16 6 7 8 9 10 11 12 13 I/O RA1 RA2 RA3 RA4 RA5 RA6 RA7 RB0 RB1 RB2 RB3 RB4 RB5 RB6 RB7 © 2009 Microchip Technology Inc. Preliminary Note 1: 2: 3: 4: 16 15 13 12 10 9 8 7 21 20 1 28 5,6 3,5 15,16 17,19 14 13 12 11 10 9 8 7 18 17 4 3 27 26 - - Y Y Y Y Y Y Y N N N N Y Y Y - - AN6 AN5 AN7 AN8 AN9 AN10 AN11 - - - - AN4 AN3 AN2 AN1 - - - - - - - - - - - - - - VREF+ VREFDACOUT - - - CPS6 CPS5 CPS7 CPS8 CPS9 CPS10 CPS10 CPS11 CPS11 - - - - CPS4 CPS3 CPS2 CPS1 - - - - - - - - - - - - - C2OUT C12IN3C1IN C12IN3C1IN+ C1OUT C12IN2C12IN C12IN2C12IN+ C12IN1- C12IN1- - - - - - - - - - SRI - - - SRNQ SRQ - - - - T1OSO T1CKI T1OSI - - - - - T1G - - - T0CKI - - - Pin functions can be moved using the APFCON register(s) Functions are only available on the PIC16F/LF1827 PIC16F/LF1827. Weak pull-up always enabled when MCLR is enabled, otherwise the pull-up is under user control. Default function location. 5 Vss 20-Pin SSOP - - SDA1 SDI1 SDA2(2) SDI2(2) SDO1(1,4) - RX(1,4) DT(1,4) RX(1),DT(1) TX(1,4) CK(1,4) - CCP1(1) P1A(1) FLT0 - CCP1(1,4) P1A(1,4) - P1D(1,4) P2B(1,2,4) - - - - P1C(1,4) CCP2(1,2,4) P2A(1,2,4) - SCL2(2) SCK2(2) SS1(1,4) TX(1) CK(1) P1B - - - - SCL1 SCK1 - - - - - - - P1C(1) CCP2(1,2) P2A(1,2) SDO1(1) - - - IOC IOC IOC IOC IOC IOC IOC INT IOC - - - - - SS1(1) P1D(1) P2B(1,2) - CCP4(2) - - - CCP3(2) - - SS2(2) - - SDO2(2) - - - - - - - MSSP 2 28-Pin QFN/UQFN - Interrupt 1 ANSEL Y A/D 24 Reference 20 Cap Sense C12IN0- C12IN0- Comparator CPS0 SR Latch - Timers AN0 CCP Y EUSART 23 - - MDCIN1 - - MDCIN2 MDOUT MDMIN - - - - - - - - - - Modulator 19 - - Y Y Y Y Y Y Y Y N N Y(3) N N N N N Pull-up 14 17 18/20/28-PIN 18/20/28-PIN SUMMARY (PIC16F/LF1826/27 PIC16F/LF1826/27) VSS VDD ICSPDAT/ ICDDAT ICSPCLK/ ICDCLK - - - - - - OSC1 CLKIN OSC2 CLKOUT CLKR MCLR, VPP - - - - - Basic VDD 18-Pin PDIP/SOIC RA0 TABLE 1: PIC16F/LF1826/27 PIC16F/LF1826/27 DS41391B-page 7 PIC16F/LF1826/27 PIC16F/LF1826/27 Table of Contents 1.0 Device Overview . 11 2.0 Enhanced Mid-range CPU . 17 3.0 Memory Organization . 19 4.0 Device Configuration . 49 5.0 Oscillator Module (With Fail-Safe Clock Monitor). 55 6.0 Reference Clock Module . 71 7.0 Resets . 75 8.0 Interrupts . 83 9.0 Power-Down Mode (Sleep) . 99 10.0 Watchdog Timer (WDT) . 101 11.0 Data EEPROM and Flash Program Memory Control . 105 12.0 I/O Ports . 117 13.0 Interrupt-on-Change . 131 14.0 Fixed Voltage Reference (FVR) . 135 15.0 Analog-to-Digital Converter (ADC) Module . 137 16.0 Digital-to-Analog Converter (DAC) Module . 151 17.0 Comparator Module. 157 18.0 SR Latch. 167 19.0 Timer0 Module . 173 21.0 Timer1 Module . 177 22.0 Timer2/4/6 Modules. 189 23.0 Data Signal Modulator (DSM) . 193 24.0 Capture/Compare/PWM (ECCP1, ECCP2, ECCP3, CCP4) Modules. 203 25.0 Master Synchronous Serial Port (MSSP) Module . 233 26.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) . 287 27.0 Capacitive Sensing Module . 315 28.0 In-Circuit Serial ProgrammingTM (ICSPTM) . 321 29.0 Instruction Set Summary . 323 30.0 Electrical Specifications. 337 31.0 DC and AC Characteristics Graphs and Tables . 371 32.0 Development Support. 373 33.0 Packaging Information. 377 Appendix A: Revision History. 387 Appendix B: Device Differences. 387 Index . 389 The Microchip Web Site . 397 Customer Change Notification Service . 397 Customer Support . 397 Reader Response . 398 Product Identification System. 399 DS41391B-page 8 Preliminary © 2009 Microchip Technology Inc. PIC16F/LF1826/27 PIC16F/LF1826/27 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@mail.microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A DS30000A is version A of document DS30000 DS30000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: · Microchip's Worldwide Web site; http://www.microchip.com · Your local Microchip sales office (see last page) · The Microchip Corporate Literature Center; U.S. FAX: (480) 792-7277 When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com/cn to receive the most current information on all of our products. © 2009 Microchip Technology Inc. Preliminary DS41391B-page 9 PIC16F/LF1826/27 PIC16F/LF1826/27 NOTES: DS41391B-page 10 Preliminary © 2009 Microchip Technology Inc. PIC16F/LF1826/27 PIC16F/LF1826/27 1.0 DEVICE OVERVIEW The PIC16F/LF1826/27 PIC16F/LF1826/27 are described within this data sheet. They are available in 18/20/28-pin packages. Figure 1-1 shows a block diagram of the PIC16F/LF1826/27 PIC16F/LF1826/27 devices. Table 1-2 shows the pinout descriptions. Reference Table 1-1 for peripherals available per device. Peripheral PIC16F/LF1827 PIC16F/LF1827 DEVICE PERIPHERAL SUMMARY PIC16F/LF1826 PIC16F/LF1826 TABLE 1-1: ADC Capacitive Sensing Module Digital-to-Analog Converter (DAC) Digital Signal Modulator (DSM) EUSART Fixed Voltage Reference (FVR) Reference Clock Module SR Latch Capture/Compare/PWM Modules ECCP1 ECCP2 CCP3 CCP4 Comparators C1 C2 Master Synchronous Serial Ports MSSP1 MSSP2 Timers Timer0 Timer1 Timer2 Timer4 Timer6 © 2009 Microchip Technology Inc. Preliminary DS41391B-page 11 PIC16F/LF1826/27 PIC16F/LF1826/27 FIGURE 1-1: PIC16F/LF1826/27 PIC16F/LF1826/27 BLOCK DIAGRAM Program Flash Memory CLKR OSC2/CLKO OSC1/CLKI EEPROM RAM Clock Reference Timing Generation PORTA CPU INTRC Oscillator (Figure 2-1) PORTB MCLR SR Latch ADC 10-Bit Timer0 Timer1 Timer2Types DAC Comparators ECCPx CCPx MSSPx Modulator EUSART FVR CapSense Note 1: 2: DS41391B-page 12 See applicable chapters for more information on peripherals. See Table 1-1 for peripherals available on specific devices. Preliminary © 2009 Microchip Technology Inc. PIC16F/LF1826/27 PIC16F/LF1826/27 TABLE 1-2: PIC16F/LF1826/27 PIC16F/LF1826/27 PINOUT DESCRIPTION Name RA0/AN0/CPS0/C12IN0-/ RA0/AN0/CPS0/C12IN0-/ SDO2(2) Function Input Type RA0 TTL AN0 AN Output Type Description CMOS General purpose I/O. - A/D Channel 0 input. CPS0 AN - Capacitive sensing input 0. C12IN0- C12IN0- AN - Comparator C1 or C2 negative input. SDO2 RA1/AN1/CPS1/C12IN1-/SS2 RA1/AN1/CPS1/C12IN1-/SS2(2) - RA1 TTL CMOS SPI data output. CMOS General purpose I/O. AN1 - AN - Capacitive sensing input 1. C12IN1- C12IN1- AN - Comparator C1 or C2 negative input. SS2 ST - Slave Select input 2. RA2 TTL AN2 AN - CPS2 AN - Capacitive sensing input 2. C12IN2- C12IN2- AN - Comparator C1 or C2 negative input. C12IN C12IN+ AN - Comparator C1 or C2 positive input. VREF- RA2/AN2/CPS2/C12IN2-/ RA2/AN2/CPS2/C12IN2-/ C12IN C12IN+/VREF-/DACOUT AN CPS1 AN - A/D Negative Voltage Reference input. AN Voltage Reference output. DACOUT RA3/AN3/CPS3/C12IN3-/C1IN RA3/AN3/CPS3/C12IN3-/C1IN+/ VREF+/C1OUT/CCP3(2)/SRQ - RA3 TTL A/D Channel 1 input. CMOS General purpose I/O. A/D Channel 2 input. CMOS General purpose I/O. AN3 AN - CPS3 AN - A/D Channel 3 input. Capacitive sensing input 3. C12IN3- C12IN3- AN - Comparator C1 or C2 negative input. C1IN+ AN - Comparator C1 positive input. - A/D Voltage Reference input. VREF+ - CMOS Comparator C1 output. CCP3 ST CMOS Capture/Compare/PWM3. SRQ - CMOS SR Latch non-inverting output. RA4 TTL AN4 AN - A/D Channel 4 input. CPS4 AN - Capacitive sensing input 4. C2OUT RA4/AN4/CPS4/C2OUT/T0CKI/ CCP4(2)/SRNQ AN C1OUT - CMOS General purpose I/O. CMOS Comparator C2 output. T0CKI ST CMOS Capture/Compare/PWM4. SRNQ RA5/MCLR/VPP/SS1(1,2) ST CCP4 - Timer0 clock input. - CMOS SR Latch inverting output. RA5 TTL CMOS General purpose I/O. MCLR ST - Master Clear with internal pull-up. VPP HV - Programming voltage. SS1 ST - Slave Select input 1. Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open Drain TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2CTM = Schmitt Trigger input with I2C HV = High Voltage XTAL = Crystal levels Note 1: Pin functions can be moved using the APFCON register(s). 2: Functions are only available on the PIC16F/LF1827 PIC16F/LF1827. 3: Default function location. © 2009 Microchip Technology Inc. Preliminary DS41391B-page 13 PIC16F/LF1826/27 PIC16F/LF1826/27 TABLE 1-2: PIC16F/LF1826/27 PIC16F/LF1826/27 PINOUT DESCRIPTION (CONTINUED) Function Name RA6/OSC2/CLKOUT/CLKR/ P1D(1)/P2B(1,2)/SDO1(1) Input Type RA6 TTL Output Type Description CMOS General purpose I/O. OSC2 - CLKOUT - CMOS FOSC/4 output. XTAL Crystal/Resonator (LP, XT, HS modes). CLKR - CMOS Clock Reference Output. P1D - CMOS PWM output. CMOS PWM output. P2B OSC1 XTAL CMOS - CMOS PWM output. ST CMOS Capture/Compare/PWM2. P2A - CMOS PWM output. RB0 TTL T1G ST CCP1 ST CMOS Capture/Compare/PWM1. P1A - CMOS PWM output. INT ST - External interrupt. SRI RB0/T1G/CCP1 /P1A /INT/ SRI/FLT0 TTL CCP2 (1) RA7 P1C (1) - CLKIN RA7/OSC1/CLKIN/P1C(1)/ CCP2(1,2)/P2A(1,2) - SDO1 ST - SR Latch input. - ECCP Auto-Shutdown Fault input. CMOS SPI data output 1. CMOS General purpose I/O. - Crystal/Resonator (LP, XT, HS modes). - External clock input (EC mode). CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. - Timer1 Gate input. FLT0 ST RB1 TTL AN11 AN - A/D Channel 11 input. CPS11 CPS11 RB1/AN11/CPS11/RX RB1/AN11/CPS11/RX(1,3)/ DT(1,3)/SDA1/SDI1 AN - Capacitive sensing input 11. - USART asynchronous input. RX ST SDA1 I2CTM SDI1 RB2/AN10/CPS10/MDMIN/ RB2/AN10/CPS10/MDMIN/ TX(1,3)/CK(1,3)/RX(1)/DT(1)/ SDA2(2)/SDI2(2)/SDO1(1,3) ST DT CMOS RB2 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. CMOS USART synchronous data. OD I2CTM data input/output 1. - SPI data input 1. CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. AN10 AN - A/D Channel 10 input. CPS10 CPS10 AN - Capacitive sensing input 10. MDMIN - CMOS Modulator source input. TX - CMOS USART asynchronous transmit. CK ST CMOS USART synchronous clock. RX ST DT ST SDA2 I2CTM SDI2 ST SDO1 - - USART asynchronous input. CMOS USART synchronous data. OD I2CTM data input/output 2. - SPI data input 2. CMOS SPI data output 1. Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open Drain TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2CTM = Schmitt Trigger input with I2C HV = High Voltage XTAL = Crystal levels Note 1: Pin functions can be moved using the APFCON register(s). 2: Functions are only available on the PIC16F/LF1827 PIC16F/LF1827. 3: Default function location. DS41391B-page 14 Preliminary © 2009 Microchip Technology Inc. PIC16F/LF1826/27 PIC16F/LF1826/27 TABLE 1-2: PIC16F/LF1826/27 PIC16F/LF1826/27 PINOUT DESCRIPTION (CONTINUED) Name RB3/AN9/CPS9/MDOUT/ CCP1(1,3)/P1A(1,3) Function Input Type RB3 TTL Output Type Description CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. AN9 AN - A/D Channel 9 input. CPS9 AN - Capacitive sensing input 9. MDOUT - CMOS Modulator output. CCP1 ST CMOS Capture/Compare/PWM1. P1A RB4/AN8/CPS8/SCL1/SCK1/ MDCIN2 - RB4 TTL CMOS PWM output. CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. AN8 AN - A/D Channel 8 input. CPS8 AN - Capacitive sensing input 8. OD I2CTM clock 1. SCL1 2 I CTM SCK1 RB5/AN7/CPS7/P1B/TX(1)/CK(1)/ SCL2(2)/SCK2(2)/SS1(1,3) ST MDCIN2 ST RB5 TTL CMOS SPI clock 1. - Modulator Carrier Input 2. CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. AN7 AN - A/D Channel 7 input. CPS7 AN - Capacitive sensing input 7. P1B - CMOS PWM output. TX - CMOS USART asynchronous transmit. CK ST CMOS USART synchronous clock. SCL2 I2CTM SCK2 RB6/AN5/CPS5/T1CKI/T1OSI/ P1C(1,3)/CCP2(1,2,3)/P2A(1,2,3)/ ICSPCLK ST SS1 ST RB6 TTL OD I2CTM clock 2. CMOS SPI clock 2. - Slave Select input 1. CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. AN5 AN - CPS5 AN - Capacitive sensing input 5. T1CKI ST - Timer1 clock input. T1OSO XTAL P1C - CMOS PWM output. CCP2 ST CMOS Capture/Compare/PWM2. P2A - CMOS PWM output. ICSPCLK RB7/AN6/CPS6/T1OSO/ P1D(1,3)/P2B(1,2,3)/MDCIN1/ ICSPDAT ST RB7 TTL XTAL - A/D Channel 5 input. Timer1 oscillator connection. Serial Programming Clock. CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. AN6 AN - CPS6 AN - T1OSO XTAL XTAL P1D - CMOS PWM output. CMOS PWM output. P2B - MDCIN1 ST ICSPDAT ST - A/D Channel 6 input. Capacitive sensing input 6. Timer1 oscillator connection. Modulator Carrier Input 1. CMOS ICSPTM Data I/O. Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open Drain TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2CTM = Schmitt Trigger input with I2C HV = High Voltage XTAL = Crystal levels Note 1: Pin functions can be moved using the APFCON register(s). 2: Functions are only available on the PIC16F/LF1827 PIC16F/LF1827. 3: Default function location. © 2009 Microchip Technology Inc. Preliminary DS41391B-page 15 PIC16F/LF1826/27 PIC16F/LF1826/27 TABLE 1-2: PIC16F/LF1826/27 PIC16F/LF1826/27 PINOUT DESCRIPTION (CONTINUED) Function Input Type Output Type VDD VDD Power - Positive supply. VSS VSS Power - Ground reference. Name Description Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open Drain TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2CTM = Schmitt Trigger input with I2C HV = High Voltage XTAL = Crystal levels Note 1: Pin functions can be moved using the APFCON register(s). 2: Functions are only available on the PIC16F/LF1827 PIC16F/LF1827. 3: Default function location. DS41391B-page 16 Preliminary © 2009 Microchip Technology Inc. PIC16F/LF1826/27 PIC16F/LF1826/27 2.0 ENHANCED MID-RANGE CPU This family of devices contains an enhanced mid-range 8-bit CPU core. The CPU has 49 instructions. Interrupt capability includes automatic context saving. The hardware stack is 16 levels deep and has Overflow and Underflow Reset capability. Direct, indirect, and relative addressing modes are available. Two File Select Registers (FSRs) provide the ability to read program and data memory. The Enhanced Mid-range CPU contains the following: · · · · Automatic Interrupt Context Saving 16-level Stack with Overflow and Underflow File Select Registers Instruction Set 2.1 Automatic Interrupt Context Saving During interrupts, certain registers are automatically saved in shadow registers and restored when returning from the interrupt. This saves stack space and user code. See Section 8.5 "Automatic Context Saving", for more information. 2.2 16-level Stack with Overflow and Underflow These devices have an external stack memory 15 bits wide and 16 words deep. A Stack Overflow or Underflow will set the appropriate bit (STKOVF or STKUNF) in the PCON register, and if enabled will cause a software Reset. See section Section 3.4 "Stack" for more details. 2.3 File Select Registers There are two 16-bit File Select Registers (FSR). FSRs can access all file registers and program memory, which allows one data pointer for all memory. When an FSR points to program memory, there is 1 additional instruction cycle in instructions using INDFx to allow the data to be fetched. General purpose memory can also be addressed linearly, providing the ability to access contiguous data larger than 80 bytes. There are also new instructions to support the FSRs. See Section 3.5 "Indirect Addressing"for more details. 2.4 Instruction Set There are 49 instructions for the enhanced mid-range CPU to support the features of the CPU. See Section 28.0 "Instruction Set Summary" for more details. © 2009 Microchip Technology Inc. Preliminary DS41391B-page 17 PIC16F/LF1826/27 PIC16F/LF1826/27 FIGURE 2-1: CORE BLOCK DIAGRAM 15 Configuration 15 MUX Flash Program Memory Program Bus 16-LevelStack 8 Level Stack (15-bit) (13-bit) 14 Instruction Reg. Instruction reg 8 Data Bus Program Counter RAM Program Memory Read (PMR) 9 RAM Addr Addr MUX Direct Addr 7 12 15 Indirect Addr 12 FSR0reg FSR Reg. FSR1 Reg. FSR reg 15 STATUS Reg. STATUS reg 8 3 Power-up Timer OSC1/CLKIN OSC2/CLKOUT Instruction Decode and Decode & Control Timing Generation Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Reset MUX ALU 8 W Reg. W reg Internal Oscillator Block VDD DS41391B-page 18 VSS Preliminary © 2009 Microchip Technology Inc. PIC16F/LF1826/27 PIC16F/LF1826/27 3.0 MEMORY ORGANIZATION There are three types of memory in PIC16F/LF1826/27 PIC16F/LF1826/27: Data Memory, Program Memory and Data EEPROM Memory(1). · Program Memory · Data Memory - Core Registers - Special Function Registers - General Purpose RAM - Common RAM - Device Memory Maps - Special Function Registers Summary · Data EEPROM memory(1) The following features are associated with access and control of program memory and data memory: · PCL and PCLATH · Stack · Indirect Addressing 3.1 Program Memory Organization The enhanced mid-range core has a 15-bit program counter capable of addressing a 32K x 14 program memory space. Table 3-1 shows the memory sizes implemented for the PIC16F/LF1826/27 PIC16F/LF1826/27 family. Accessing a location above these boundaries will cause a wrap-around within the implemented memory space. The Reset vector is at 0000h and the interrupt vector is at 0004h (see Figures 3-1 and 3-2). Note 1: The Data EEPROM Memory and the method to access Flash memory through the EECON registers is described in Section 11.0 "Data EEPROM and Flash Program Memory Control". TABLE 3-1: DEVICE SIZES AND ADDRESSES Device Program Memory Space (Words) Last Program Memory Address PIC16F/LF1826 PIC16F/LF1826 2,048 07FFh PIC16F/LF1827 PIC16F/LF1827 4,096 0FFFh © 2009 Microchip Technology Inc. Preliminary DS41391B-page 19 PIC16F/LF1826/27 PIC16F/LF1826/27 FIGURE 3-1: PROGRAM MEMORY MAP AND STACK FOR PIC16F/LF1826 PIC16F/LF1826 FIGURE 3-2: PC CALL, CALLW RETURN, RETLW Interrupt, RETFIE PROGRAM MEMORY MAP AND STACK FOR PIC16F/LF1827 PIC16F/LF1827 PC CALL, CALLW RETURN, RETLW Interrupt, RETFIE 15 15 Stack Level 0 Stack Level 1 Stack Level 0 Stack Level 1 Stack Level 15 Stack Level 15 Reset Vector Reset Vector 0000h Interrupt Vector On-chip Program Memory 0000h 0004h 0005h Interrupt Vector 0004h 0005h Page 0 Rollover to Page 0 Wraps to Page 0 07FFh 0800h On-chip Program Memory Page 0 07FFh 0800h Page 1 Rollover to Page 0 Wraps to Page 0 0FFFh 1000h Wraps to Page 0 Rollover to Page 0 DS41391B-page 20 7FFFh Preliminary Rollover to Page 1 7FFFh © 2009 Microchip Technology Inc. PIC16F/LF1826/27 PIC16F/LF1826/27 3.1.1 READING PROGRAM MEMORY AS DATA There are two methods of accessing constants in program memory. The first method is to use tables of RETLW instructions. The second method is to set an FSR to point to the program memory. 3.1.1.1 RETLW Instruction The RETLW instruction can be used to provide access to tables of constants. The recommended way to create such a table is shown in Example 3-1. EXAMPLE 3-1: constants brw retlw retlw retlw retlw DATA0 DATA1 DATA2 DATA3 RETLW INSTRUCTION ;Add Index in W to ;program counter to ;select data ;Index0 data ;Index1 data my_function ;. LOTS OF CODE. movlw DATA_INDEX call constants ;. THE CONSTANT IS IN W The BRW instruction makes this type of table very simple to implement. If your code must remain portable with previous generations of microcontrollers, then the BRW instruction is not available so the older table read method must be used. © 2009 Microchip Technology Inc. Preliminary DS41391B-page 21 PIC16F/LF1826/27 PIC16F/LF1826/27 3.1.1.2 Indirect Read with FSR 3.2.1 The program memory can be accessed as data by setting bit 7 of the FSRxH register and reading the matching INDFx register. The MOVIW instruction will place the lower 8 bits of the addressed word in the W register. Writes to the program memory cannot be performed via the INDF registers. Instructions that access the program memory via the FSR require one extra instruction cycle to complete. Example 3-2 demonstrates accessing the program memory via an FSR. The HIGH directive will set bit if a label points to a location in program memory. EXAMPLE 3-2: ACCESSING PROGRAM MEMORY VIA FSR constants RETLW DATA0 ;Index0 data RETLW DATA1 ;Index1 data RETLW DATA2 RETLW DATA3 my_function ;. LOTS OF CODE. MOVLW LOW constants MOVWF FSR1L MOVLW HIGH constants MOVWF FSR1H MOVIW 0[INDF1] ;THE PROGRAM MEMORY IS IN W 3.2 CORE REGISTERS The core registers contain the registers that directly affect the basic operation of the PIC16F/LF1826/27 PIC16F/LF1826/27. These registers are listed below: · · · · · · · · · · · · INDF0 INDF1 PCL STATUS FSR0 Low FSR0 High FSR1 Low FSR1 High BSR WREG PCLATH INTCON Note: The core registers are the first 12 addresses of every data memory bank. Data Memory Organization The data memory is partitioned in 32 memory banks with 128 bytes in a bank. Each bank consists of (Figure 3-3): · · · · 12 core registers 20 Special Function Registers (SFR) Up to 80 bytes of General Purpose RAM (GPR) 16 bytes of common RAM The active bank is selected by writing the bank number into the Bank Select Register (BSR). Unimplemented memory will read as `0'. All data memory can be accessed either directly (via instructions that use the file registers) or indirectly via the two File Select Registers (FSR). See Section 3.5 "Indirect Addressing" for more information. DS41391B-page 22 Preliminary © 2009 Microchip Technology Inc. PIC16F/LF1826/27 PIC16F/LF1826/27 3.2.1.1 STATUS Register The STATUS register, shown in Register 3-1, contains: · the arithmetic status of the ALU · the Reset status The STATUS register can be the destination for any instruction, like any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not writable. Therefore, the result of an instruction with the STATUS register as destination may be different than intended. REGISTER 3-1: For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the STATUS register as `000u u1uu' (where u = unchanged). It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the STATUS register, because these instructions do not affect any Status bits. For other instructions not affecting any Status bits (Refer to Section 28.0 "Instruction Set Summary"). Note 1: The C and DC bits operate as Borrow and Digit Borrow out bits, respectively, in subtraction. STATUS: STATUS REGISTER U-0 U-0 U-0 R-1/q R-1/q R/W-0/u R/W-0/u R/W-0/u - - - TO PD Z DC(1) C(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = Value depends on condition bit 7-5 Unimplemented: Read as `0' bit 4 TO: Time-out bit 1 = After power-up, CLRWDT instruction or SLEEP instruction 0 = A WDT time-out occurred bit 3 PD: Power-down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction bit 2 Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero bit 1 DC: Digit Carry/Digit Borrow bit(1) 1 = A carry-out from the 4th low-order bit of the result occurred 0 = No carry-out from the 4th low-order bit of the result bit 0 C: Carry/Borrow bit(1) 1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the two's complement of the second operand. © 2009 Microchip Technology Inc. Preliminary DS41391B-page 23 PIC16F/LF1826/27 PIC16F/LF1826/27 3.2.2 SPECIAL FUNCTION REGISTER 3.2.5 The Special Function Registers are registers used by the application to control the desired operation of peripheral functions in the device. The registers associated with the operation of the peripherals are described in the appropriate peripheral chapter of this data sheet. 3.2.3 The memory maps for the device family are as shown in Table 3-2. TABLE 3-2: PIC16F/LF1826/27 PIC16F/LF1826/27 Banks Table No. Linear Access to GPR 0-7 Table 3-3 8-15 Table 3-4 16-23 Table 3-5 24-31 GENERAL PURPOSE RAM The general purpose RAM can be accessed in a non-banked method via the FSRs. This can simplify access to large memory structures. See Section 3.5.2 "Linear Data Memory" for more information. 3.2.4 MEMORY MAP TABLES Device There are up to 80 bytes of GPR in each data memory bank. 3.2.3.1 DEVICE MEMORY MAPS Table 3-6 31 Table 3-7 COMMON RAM There are 16 bytes of common RAM accessible from all banks. FIGURE 3-3: 7-bit Bank Offset BANKED MEMORY PARTITIONING Memory Region 00h 0Bh 0Ch Core Registers (12 bytes) Special Function Registers (20 bytes maximum) 1Fh 20h General Purpose RAM (80 bytes maximum) 6Fh 70h Common RAM (16 bytes) 7Fh DS41391B-page 24 Preliminary © 2009 Microchip Technology Inc. © 2009 Microchip Technology Inc. Preliminary Note 1: Legend: 07Fh 06Fh 070h 000h 001h 002h 003h 004h 005h 006h 007h 008h 009h 00Ah 00Bh 00Ch 00Dh 00Eh 00Fh 010h 011h 012h 013h 014h 015h 016h 017h 018h 019h 01Ah 01Bh 01Ch 01Dh 01Eh 01Fh 020h 080h 081h 082h 083h 084h 085h 086h 087h 088h 089h 08Ah 08Bh 08Ch 08Dh 08Eh 08Fh 090h 091h 092h 093h 094h 095h 096h 097h 098h 099h 09Ah 09Bh 09Ch 0FFh 0EFh 0F0h Accesses 70h ­ 7Fh General Purpose Register 80 Bytes ADCON0 ADCON1 - 17Fh 16Fh 170h 11Dh 11Eh 11Fh 120h 100h 101h 102h 103h 104h 105h 106h 107h 108h 109h 10Ah 10Bh 10Ch 10Dh 10Eh 10Fh 110h 111h 112h 113h 114h 115h 116h 117h 118h 119h 11Ah 11Bh 11Ch Accesses 70h ­ 7Fh General Purpose Register 80 Bytes APFCON0 APFCON1 - INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON LATA LATB - - - CM1CON0 CM1CON1 CM2CON0 CM2CON1 CMOUT BORCON FVRCON DACCON0 DACCON1 SRCON0 SRCON1 - BANK2 Available only on PIC16F/LF1827 PIC16F/LF1827. = Unimplemented data memory locations, read as `0' General Purpose Register 96 Bytes 09Dh 09Eh 09Fh 0A0h - CPSCON0 CPSCON1 INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON TRISA TRISB - - - PIE1 PIE2 PIE3(1) PIE4(1) OPTION PCON WDTCON OSCTUNE OSCCON OSCSTAT ADRESL ADRESH BANK1 1FFh 1EFh 1F0h 19Dh 19Eh 19Fh 1A0h 180h 181h 182h 183h 184h 185h 186h 187h 188h 189h 18Ah 18Bh 18Ch 18Dh 18Eh 18Fh 190h 191h 192h 193h 194h 195h 196h 197h 198h 199h 19Ah 19Bh 19Ch Accesses 70h ­ 7Fh General Purpose Register 80 Bytes(1) RCSTA TXSTA BAUDCON INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON ANSELA ANSELB - - - EEADRL EEADRH EEDATL EEDATH EECON1 EECON2 - - RCREG TXREG SPBRGL SPBRGH BANK3 PIC16F/LF1826/27 PIC16F/LF1826/27 MEMORY MAP, BANKS 0-7 INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON PORTA PORTB - - - PIR1 PIR2 PIR3(1) PIR4(1) TMR0 TMR1L TMR1H T1CON T1GCON TMR2 PR2 T2CON BANK0 TABLE 3-3: 27Fh 26Fh 270h 21Dh 21Eh 21Fh 220h 200h 201h 202h 203h 204h 205h 206h 207h 208h 209h 20Ah 20Bh 20Ch 20Dh 20Eh 20Fh 210h 211h 212h 213h 214h 215h 216h 217h 218h 219h 21Ah 21Bh 21Ch Accesses 70h ­ 7Fh Unimplemented Read as `0' SSP2CON2(1) SSP2CON3(1) General Purpose Register 48 Bytes(1) SSP2BUF(1) SSP2ADD(1) SSP2MASK(1) SSP2STAT(1) SSP2CON(1) INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON WPUA WPUB - - - SSP1BUF SSP1ADD SSP1MASK SSP1STAT SSP1CON SSP1CON2 SSP1CON3 - BANK4 2FFh 2EFh 2F0h 29Dh 29Eh 29Fh 2A0h 280h 281h 282h 283h 284h 285h 286h 287h 288h 289h 28Ah 28Bh 28Ch 28Dh 28Eh 28Fh 290h 291h 292h 293h 294h 295h 296h 297h 298h 299h 29Ah 29Bh 29Ch 300h 301h 302h 303h 304h 305h 306h 307h 308h 309h 30Ah 30Bh 30Ch 30Dh 30Eh 30Fh 310h 311h 312h 313h 314h 315h 316h 317h 318h 319h 31Ah 31Bh 31Ch Accesses 70h ­ 7Fh 37Fh 36Fh 370h PSTR2CON(1) CCPTMRS(1) - Unimplemented Read as `0' 31Dh 31Eh 31Fh 320h INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON - - - - - CCPR1L CCPR1H CCP1CON PWM1CON CCP1AS PSTR1CON - CCPR2L(1) CCPR2H(1) CCP2CON(1) PWM2CON(1) CCP2AS(1) BANK5 Accesses 70h ­ 7Fh Unimplemented Read as `0' - INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON - - - - - CCPR3L(1) CCPR3H(1) CCP3CON(1) - - - - CCPR4L(1) CCPR4H(1) CCP4CON(1) - - - - BANK6 3FFh 3EFh 3F0h 39Dh 39Eh 39Fh 3A0h 380h 381h 382h 383h 384h 385h 386h 387h 388h 389h 38Ah 38Bh 38Ch 38Dh 38Eh 38Fh 390h 391h 392h 393h 394h 395h 396h 397h 398h 399h 39Ah 39Bh 39Ch Accesses 70h ­ 7Fh Unimplemented Read as `0' INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON - - - - - - - - IOCBP IOCBN IOCBF - - - CLKRCON - MDCON MDSRC MDCARL MDCARH BANK7 PIC16F/LF1826/27 PIC16F/LF1826/27 DS41391B-page 25 DS41391B-page 26 Preliminary 497h 498h 499h 49Ah 49Bh 49Ch 49Dh T4CON(1) - - - - TMR6(1) PR6(1) 417h 418h 419h 41Ah 41Bh 41Ch 41Dh Legend: 47Fh 46Fh 470h 4FFh 4EFh 4F0h Accesses 70h ­ 7Fh Unimplemented Read as `0' - - - - - - - - - - 57Fh 56Fh 570h 51Eh 51Fh 520h 51Dh 51Ch 517h 518h 519h 51Ah 51Bh 516h 515h 500h 501h 502h 503h 504h 505h 506h 507h 508h 509h 50Ah 50Bh 50Ch 50Dh 50Eh 50Fh 510h 511h 512h 513h 514h Accesses 70h ­ 7Fh Unimplemented Read as `0' - - - - - - - - - - - INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON - - - - - - - - - BANK 10 = Unimplemented data memory locations, read as `0' Accesses 70h ­ 7Fh Unimplemented Read as `0' 49Eh 49Fh 4A0h 496h PR4(1) 416h T6CON(1) - 495h TMR4(1) 415h 41Eh 41Fh 420h INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON - - - - - - - - - - BANK 9 480h 481h 482h 483h 484h 485h 486h 487h 488h 489h 48Ah 48Bh 48Ch 48Dh 48Eh 48Fh 490h 491h 492h 493h 494h INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON - - - - - - - - - 400h 401h 402h 403h 404h 405h 406h 407h 408h 409h 40Ah 40Bh 40Ch 40Dh 40Eh 40Fh 410h 411h 412h 413h 414h 5FFh 5EFh 5F0h 59Eh 59Fh 5A0h 59Dh 59Ch 597h 598h 599h 59Ah 59Bh 596h 595h 580h 581h 582h 583h 584h 585h 586h 587h 588h 589h 58Ah 58Bh 58Ch 58Dh 58Eh 58Fh 590h 591h 592h 593h 594h Accesses 70h ­ 7Fh Unimplemented Read as `0' - - - - - - - - - - - INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON - - - - - - - - - BANK 11 PIC16F/LF1826/27 PIC16F/LF1826/27 MEMORY MAP, BANKS 8-15 BANK 8 TABLE 3-4: 67Fh 66Fh 670h 61Eh 61Fh 620h 61Dh 61Ch 617h 618h 619h 61Ah 61Bh 616h 615h 600h 601h 602h 603h 604h 605h 606h 607h 608h 609h 60Ah 60Bh 60Ch 60Dh 60Eh 60Fh 610h 611h 612h 613h 614h Accesses 70h ­ 7Fh Unimplemented Read as `0' - - - - - - - - - - - INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON - - - - - - - - - BANK 12 6FFh 6EFh 6F0h 69Eh 69Fh 6A0h 69Dh 69Ch 697h 698h 699h 69Ah 69Bh 696h 695h 680h 681h 682h 683h 684h 685h 686h 687h 688h 689h 68Ah 68Bh 68Ch 68Dh 68Eh 68Fh 690h 691h 692h 693h 694h Accesses 70h ­ 7Fh Unimplemented Read as `0' - - - - - - - - - - - INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON - - - - - - - - - BANK 13 77Fh 76Fh 770h 71Eh 71Fh 720h 71Dh 71Ch 717h 718h 719h 71Ah 71Bh 716h 715h 700h 701h 702h 703h 704h 705h 706h 707h 708h 709h 70Ah 70Bh 70Ch 70Dh 70Eh 70Fh 710h 711h 712h 713h 714h Accesses 70h ­ 7Fh Unimplemented Read as `0' - - - - - - - - - - - INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON - - - - - - - - - BANK 14 7FFh 7EFh 7F0h 79Eh 79Fh 7A0h 79Dh 79Ch 797h 798h 799h 79Ah 79Bh 796h 795h 780h 781h 782h 783h 784h 785h 786h 787h 788h 789h 78Ah 78Bh 78Ch 78Dh 78Eh 78Fh 790h 791h 792h 793h 794h Accesses 70h ­ 7Fh Unimplemented Read as `0' - - - - - - - - - - - INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON - - - - - - - - - BANK 15 PIC16F/LF1826/27 PIC16F/LF1826/27 © 2009 Microchip Technology Inc. © 2009 Microchip Technology Inc. Preliminary Legend: 87Fh 86Fh 870h 800h 801h 802h 803h 804h 805h 806h 807h 808h 809h 80Ah 80Bh 80Ch 80Dh 80Eh 80Fh 810h 811h 812h 813h 814h 815h 816h 817h 818h 819h 81Ah 81Bh 81Ch 81Dh 81Eh 81Fh 820h 8FFh Accesses 70h ­ 7Fh Unimplemented Read as `0' INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON - - - - - - - - - - - - - - - - - - - - BANK17 BANK17 97Fh 96Fh 970h 900h 901h 902h 903h 904h 905h 906h 907h 908h 909h 90Ah 90Bh 90Ch 90Dh 90Eh 90Fh 910h 911h 912h 913h 914h 915h 916h 917h 918h 919h 91Ah 91Bh 91Ch 91Dh 91Eh 91Fh 920h Accesses 70h ­ 7Fh Unimplemented Read as `0' INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON - - - - - - - - - - - - - - - - - - - - BANK18 BANK18 = Unimplemented data memory locations, read as `0' Accesses 70h ­ 7Fh 8EFh 8F0h 880h 881h 882h 883h 884h 885h 886h 887h 888h 889h 88Ah 88Bh 88Ch 88Dh 88Eh 88Fh 890h 891h 892h 893h 894h 895h 896h 897h 898h 899h 89Ah 89Bh 89Ch 89Dh 89Eh 89Fh 8A0h 9FFh 9EFh 9F0h 980h 981h 982h 983h 984h 985h 986h 987h 988h 989h 98Ah 98Bh 98Ch 98Dh 98Eh 98Fh 990h 991h 992h 993h 994h 995h 996h 997h 998h 999h 99Ah 99Bh 99Ch 99Dh 99Eh 99Fh 9A0h Accesses 70h ­ 7Fh Unimplemented Read as `0' INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON - - - - - - - - - - - - - - - - - - - - BANK19 BANK19 PIC16F/LF1826/27 PIC16F/LF1826/27 MEMORY MAP, BANKS 16-23) Unimplemented Read as `0' INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON - - - - - - - - - - - - - - - - - - - - BANK16 BANK16 TABLE 3-5: A7Fh A6Fh A70h A00h A01h A02h A03h A04h A05h A06h A07h A08h A09h A0Ah A0Bh A0Ch A0Dh A0Eh A0Fh A10h A11h A12h A13h A14h A15h A16h A17h A18h A19h A1Ah A1Bh A1Ch A1Dh A1Eh A1Fh A20h Accesses 70h ­ 7Fh Unimplemented Read as `0' INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON - - - - - - - - - - - - - - - - - - - - BANK20 BANK20 AFFh AEFh AF0h A80h A81h A82h A83h A84h A85h A86h A87h A88h A89h A8Ah A8Bh A8Ch A8Dh A8Eh A8Fh A90h A91h A92h A93h A94h A95h A96h A97h A98h A99h A9Ah A9Bh A9Ch A9Dh A9Eh A9Fh AA0h Accesses 70h ­ 7Fh Unimplemented Read as `0' INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON - - - - - - - - - - - - - - - - - - - - BANK21 BANK21 B7Fh B6Fh B70h B00h B01h B02h B03h B04h B05h B06h B07h B08h B09h B0Ah B0Bh B0Ch B0Dh B0Eh B0Fh B10h B11h B12h B13h B14h B15h B16h B17h B18h B19h B1Ah B1Bh B1Ch B1Dh B1Eh B1Fh B20h Accesses 70h ­ 7Fh Unimplemented Read as `0' INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON - - - - - - - - - - - - - - - - - - - - BANK22 BANK22 BFFh BEFh BF0h B80h B81h B82h B83h B84h B85h B86h B87h B88h B89h B8Ah B8Bh B8Ch B8Dh B8Eh B8Fh B90h B91h B92h B93h B94h B95h B96h B97h B98h B99h B9Ah B9Bh B9Ch B9Dh B9Eh B9Fh BA0h Accesses 70h ­ 7Fh Unimplemented Read as `0' INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON - - - - - - - - - - - - - - - - - - - - BANK23 BANK23 PIC16F/LF1826/27 PIC16F/LF1826/27 DS41391B-page 27 DS41391B-page 28 Preliminary Legend: CFFh C6Fh C70h C00h C01h C02h C03h C04h C05h C06h C07h C08h C09h C0Ah C0Bh C0Ch C0Dh C0Eh C0Fh C10h C11h C12h C13h C14h C15h C16h C17h C18h C19h C1Ah C1Bh C1Ch C1Dh C1Eh C1Fh C20h CFFh CEFh CF0h Accesses 70h ­ 7Fh Unimplemented Read as `0' INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON - - - - - - - - - - - - - - - - - - - - BANK 25 D7Fh D6Fh D70h D00h D01h D02h D03h D04h D05h D06h D07h D08h D09h D0Ah D0Bh D0Ch D0Dh D0Eh D0Fh D10h D11h D12h D13h D14h D15h D16h D17h D18h D19h D1Ah D1Bh D1Ch D1Dh D1Eh D1Fh D20h Accesses 70h ­ 7Fh Unimplemented Read as `0' INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON - - - - - - - - - - - - - - - - - - - - BANK 26 = Unimplemented data memory locations, read as `0' Accesses 70h ­ 7Fh Unimplemented Read as `0' INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON - - - - - - - - - - - - - - - - - - - - C80h C81h C82h C83h C84h C85h C86h C87h C88h C89h C8Ah C8Bh C8Ch C8Dh C8Eh C8Fh C90h C91h C92h C93h C94h C95h C96h C97h C98h C99h C9Ah C9Bh C9Ch C9Dh C9Eh C9Fh CA0h DFFh DEFh DF0h D80h D81h D82h D83h D84h D85h D86h D87h D88h D89h D8Ah D8Bh D8Ch D8Dh D8Eh D8Fh D90h D91h D92h D93h D94h D95h D96h D97h D98h D99h D9Ah D9Bh D9Ch D9Dh D9Eh D9Fh DA0h Accesses 70h ­ 7Fh Unimplemented Read as `0' INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON - - - - - - - - - - - - - - - - - - - - BANK 27 PIC16F/LF1826/27 PIC16F/LF1826/27 MEMORY MAP, BANKS 24-31 BANK 24 TABLE 3-6: E7Fh E6Fh E70h E00h E01h E02h E03h E04h E05h E06h E07h E08h E09h E0Ah E0Bh E0Ch E0Dh E0Eh E0Fh E10h E11h E12h E13h E14h E15h E16h E17h E18h E19h E1Ah E1Bh E1Ch E1Dh E1Eh E1Fh E20h Accesses 70h ­ 7Fh Unimplemented Read as `0' INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON - - - - - - - - - - - - - - - - - - - - BANK 28 EFFh EEFh EF0h E80h E81h E82h E83h E84h E85h E86h E87h E88h E89h E8Ah E8Bh E8Ch E8Dh E8Eh E8Fh E90h E91h E92h E93h E94h E95h E96h E97h E98h E99h E9Ah E9Bh E9Ch E9Dh E9Eh E9Fh EA0h Accesses 70h ­ 7Fh Unimplemented Read as `0' INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON - - - - - - - - - - - - - - - - - - - - BANK 29 F7Fh F6Fh F70h F00h F01h F02h F03h F04h F05h F06h F07h F08h F09h F0Ah F0Bh F0Ch F0Dh F0Eh F0Fh F10h F11h F12h F13h F14h F15h F16h F17h F18h F19h F1Ah F1Bh F1Ch F1Dh F1Eh F1Fh F20h Accesses 70h ­ 7Fh Unimplemented Read as `0' INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON - - - - - - - - - - - - - - - - - - - - BANK 30 FFFh FEFh FF0h F80h F81h F82h F83h F84h F85h F86h F87h F88h F89h F8Ah F8Bh F8Ch F8Dh F8Eh F8Fh F90h F91h F92h F93h F94h F95h F96h F97h F98h F99h F9Ah F9Bh F9Ch F9Dh F9Eh F9Fh FA0h Accesses 70h ­ 7Fh See Table 3-7 for more information INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON - - - - - - - - - - - - - - - - - - - - BANK 31 PIC16F/LF1826/27 PIC16F/LF1826/27 © 2009 Microchip Technology Inc. PIC16F/LF1826/27 PIC16F/LF1826/27 TABLE 3-7: PIC16F/LF1826/27 PIC16F/LF1826/27 MEMORY MAP, BANK 31 Bank 31 FA0h 3.2.6 The Special Function Register Summary for the device family are as follows: Unimplemented Read as `0' FE3h FE4h FE5h FE6h FE7h FE8h FE9h FEAh FEBh FECh FEDh FEEh FEFh Legend: STATUS_SHAD WREG_SHAD BSR_SHAD PCLATH_SHAD FSR0L_SHAD FSR0H_SHAD FSR1L_SHAD FSR1H_SHAD - Device Page No. 30 1 31 2 32 3 33 4 34 5 35 6 36 7 37 8 PIC16F/LF1826/27 PIC16F/LF1826/27 Bank(s) 0 STKPTR TOSL TOSH 38 9-30 Preliminary 39 31 = Unimplemented data memory locations, read as `0'. © 2009 Microchip Technology Inc. SPECIAL FUNCTION REGISTERS SUMMARY 40 DS41391B-page 29 PIC16F/LF1826/27 PIC16F/LF1826/27 TABLE 3-8: Address Name SPECIAL FUNCTION REGISTER SUMMARY Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other resets Bank 0 000h(2) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 001h(2) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 002h(2) PCL Program Counter (PC) Least Significant Byte 003h(2) STATUS 004h(2) FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu 005h(2) FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000 006h(2) FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu 007h(2) FSR1H Indirect Data Memory Address 1 High Pointer 008h(2) BSR 009h(2) WREG 00Ah(2) PCLATH - 00Bh(2) INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 000x 0000 000u 00Ch PORTA RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 xxxx xxxx xxxx xxxx 00Dh PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx xxxx xxxx 00Eh - Unimplemented - - 00Fh - Unimplemented - - 010h - Unimplemented - - 011h PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF 012h PIR2 OSFIF C2IF C1IF EEIF BCL1IF - - 013h PIR3(1) - - CCP4IF CCP3IF TMR6IF - TMR4IF - -00 0-0- -00 0-0- 014h PIR4(1) - - - - - - BCL2IF SSP2IF - -00 - -00 015h TMR0 Timer0 Module Register xxxx xxxx uuuu uuuu 016h TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu 017h TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register 018h T1CON TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0 T1OSCEN T1SYNC - TMR1ON 0000 00-0 uuuu uu-u 019h T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/ DONE T1GVAL T1GSS1 T1GSS0 0000 0x00 uuuu uxuu 01Ah TMR2 Timer2 Module Register 01Bh PR2 Timer2 Period Register 01Ch T2CON - - - - - 0000 0000 0000 0000 TO - PD Z DC C 0000 0000 0000 0000 BSR4 BSR3 BSR2 BSR1 BSR0 Working Register - -1 1000 -q quuu -0 0000 -0 0000 0000 0000 uuuu uuuu Write Buffer for the upper 7 bits of the Program Counter T2OUTPS3 -000 0000 -000 0000 TMR1IF 0000 0000 0000 0000 CCP2IF(1) 0000 0-0 0000 0-0 xxxx xxxx uuuu uuuu 0000 0000 0000 0000 1111 1111 1111 1111 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON 01Dh - 01Eh CPSCON0 CPSON - - - 01Fh CPSCON1 - - - - Legend: T2CKPS1 T2CKPS0 -000 0000 -000 0000 x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as `0'. PIC16F/LF1827 PIC16F/LF1827 only. These registers can be addressed from any bank. Note 1: 2: DS41391B-page 30 Unimplemented - CPSRNG1 CPSRNG0 CPSOUT CPSCH3 Preliminary CPSCH2 CPSCH1 - T0XCS 0- 0000 0- 0000 CPSCH0 - 0000 - 0000 © 2009 Microchip Technology Inc. PIC16F/LF1826/27 PIC16F/LF1826/27 TABLE 3-8: Address SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other resets Bank 1 080h(2) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 081h(2) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 082h(2) PCL Program Counter (PC) Least Significant Byte 083h(2) STATUS 084h(2) FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu 085h(2) FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000 086h(2) FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu 087h(2) FSR1H Indirect Data Memory Address 1 High Pointer 088h(2) BSR 089h(2) WREG 08Ah(2) PCLATH - 08Bh(2) INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 000x 0000 000u 08Ch TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 1111 1111 1111 1111 08Dh TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 1111 1111 08Eh - Unimplemented - - 08Fh - Unimplemented - - 090h - Unimplemented - - 091h PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE 092h PIE2 - - - - 0000 0000 0000 0000 - TO - PD Z DC C -1 1000 -q quuu 0000 0000 0000 0000 BSR4 BSR3 BSR2 BSR1 BSR0 Working Register -0 0000 -0 0000 0000 0000 uuuu uuuu Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000 TMR1IE 0000 0000 0000 0000 CCP2IE(1) 0000 0-0 0000 0-0 OSFIE C2IE C1IE EEIE BCL1IE - - 093h (1) PIE3 - - CCP4IE CCP3IE TMR6IE - TMR4IE - 094h PIE4(1) - - - - - - BCL2IE SSP2IE - -00 - -00 095h OPTION_REG WPUEN INTEDG TMR0CS TMR0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 096h PCON STKOVF STKUNF - - RMCLR RI POR BOR 00- 11qq qq- qquu 097h WDTCON - - WDTPS4 WDTPS3 WDTPS2 WDTPS1 WDTPS0 098h OSCTUNE - - TUN5 TUN4 TUN3 TUN2 TUN1 TUN0 -00 0000 -00 0000 099h OSCCON SPLLEN IRCF3 IRCF2 IRCF1 IRCF0 - SCS1 SCS0 0011 1-00 0011 1-00 T1OSCR PLLR OSTS HFIOFR HFIOFL MFIOFR LFIOFR HFIOFS 10q0 0q00 qqqq qq0q 09Ah OSCSTAT 09Bh ADRESL ADRESH A/D Result Register High 09Dh ADCON0 09Eh ADCON1 09Fh - Legend: SWDTEN -01 0110 -01 0110 A/D Result Register Low 09Ch -00 0-0- -00 0-0- x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as `0'. PIC16F/LF1827 PIC16F/LF1827 only. These registers can be addressed from any bank. Note 1: 2: xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu - CHS4 CHS3 CHS2 CHS1 CHS0 GO/DONE ADFM ADCS2 ADCS1 ADCS0 - ADNREF ADPREF1 Unimplemented © 2009 Microchip Technology Inc. ADON -000 0000 -000 0000 ADPREF0 0000 -000 0000 -000 - Preliminary DS41391B-page 31 - PIC16F/LF1826/27 PIC16F/LF1826/27 TABLE 3-8: Address Name SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other resets Bank 2 100h(2) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 101h(2) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 102h(2) PCL Program Counter (PC) Least Significant Byte 103h(2) STATUS 104h(2) FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu 105h(2) FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000 106h(2) FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu 107h(2) FSR1H Indirect Data Memory Address 1 High Pointer 108h(2) BSR 109h(2) WREG 10Ah(2) PCLATH - 10Bh(2) INTCON GIE - - - - 0000 0000 0000 0000 - TO - PD Z DC C -1 1000 -q quuu 0000 0000 0000 0000 BSR4 BSR3 BSR2 BSR1 BSR0 Working Register -0 0000 -0 0000 0000 0000 uuuu uuuu Write Buffer for the upper 7 bits of the Program Counter PEIE TMR0IE INTE IOCIE -000 0000 -000 0000 TMR0IF INTF IOCIF 0000 000x 0000 000u 10Ch LATA LATA7 LATA6 - LATA4 LATA3 LATA2 LATA1 LATA0 xx-x xxxx uu-u uuuu 10Dh LATB LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 xxxx xxxx uuuu uuuu 10Eh - Unimplemented - - 10Fh - Unimplemented - - 110h - Unimplemented - - 111h CM1CON0 C1ON C1OUT C1OE C1POL - C1SP C1HYS C1SYNC 0000 -100 0000 -100 0000 -00 0000 -00 112h CM1CON1 C1INTP C1INTN C1PCH1 C1PCH0 - - C1NCH1 C1NCH0 113h CM2CON0 C2ON C2OUT C2OE C2POL - C2SP C2HYS C2SYNC 0000 -100 0000 -100 114h CM2CON1 C2INTP C2INTN C2PCH1 C2PCH0 - - C2NCH1 C2NCH0 0000 -00 0000 -00 MC1OUT - -00 - -00 115h CMOUT 116h BORCON 117h 118h - - - - - - MC2OUT SBOREN - - - - - - FVRCON FVREN FVRRDY Reserved Reserved CDAFVR1 CDAFVR0 ADFVR1 ADFVR0 0qrr 0000 0qrr 0000 DACCON0 DACEN DACLPS DACOE - DACPSS1 DACPSS0 - DACNSS 000- 00-0 000- 00-0 BORRDY 1- -q u- -u 119h DACCON1 - - - DACR4 DACR3 DACR2 DACR1 DACR0 -0 0000 -0 0000 11Ah SRCON0 SRLEN SRCLK2 SRCLK1 SRCLK0 SRQEN SRNQEN SRPS SRPR 0000 0000 0000 0000 11Bh SRCON1 SRSPE SRSCKE SRSC2E SRSC1E SRRPE SRRCKE SRRC2E SRRC1E 0000 0000 0000 0000 11Ch - 11Dh APFCON0 P1DSEL P1CSEL CCP1SEL 0000 0000 0000 0000 11Eh APFCON1 - - TXCKSEL - -0 - -0 11Fh - Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as `0'. PIC16F/LF1827 PIC16F/LF1827 only. These registers can be addressed from any bank. Note 1: 2: DS41391B-page 32 Unimplemented - RXDTSEL SDO1SEL SS1SEL - - - P2BSEL(1) CCP2SEL(1) - - Unimplemented - Preliminary © 2009 Microchip Technology Inc. - - PIC16F/LF1826/27 PIC16F/LF1826/27 TABLE 3-8: Address Name SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other resets Bank 3 180h(2) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 181h(2) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 182h(2) PCL Program Counter (PC) Least Significant Byte 183h(2) STATUS 184h(2) FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu 185h(2) FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000 186h(2) FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu 187h(2) FSR1H Indirect Data Memory Address 1 High Pointer 188h(2) BSR 189h(2) WREG 18Ah(2) PCLATH - 18Bh(2) INTCON GIE 18Ch ANSELA - 18Dh ANSELB ANSB7 - - - 0000 0000 0000 0000 - - TO - PD Z DC C -1 1000 -q quuu 0000 0000 0000 0000 BSR4 BSR3 BSR2 BSR1 BSR0 Working Register -0 0000 -0 0000 0000 0000 uuuu uuuu Write Buffer for the upper 7 bits of the Program Counter PEIE -000 0000 -000 0000 TMR0IE INTE IOCIE TMR0IF INTF IOCIF - - ANSA4 ANSA3 ANSB6 ANSB5 ANSB4 ANSB3 ANSA2 ANSA1 ANSA0 -1 1111 -1 1111 ANSB2 ANSB1 - 1111 111- 1111 111- 0000 000x 0000 000u 18Eh - Unimplemented - - 18Fh - Unimplemented - - 190h - Unimplemented - - 191h EEADRL EEPROM / Program Memory Address Register Low Byte 192h EEADRH 193h EEDATL 194h EEDATH 195h EECON1 196h EECON2 EEPROM control register 2 197h - Unimplemented - - 198h - Unimplemented - - 199h RCREG USART Receive Data Register 0000 0000 0000 0000 19Ah TXREG USART Transmit Data Register 0000 0000 0000 0000 19Bh SPBRGL Baud Rate Generator Data Register Low 0000 0000 0000 0000 19Ch SPBRGH Baud Rate Generator Data Register High 19Dh RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x 19Eh TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010 19Fh BAUDCON ABDOVF RCIDL - SCKP BRG16 BRG16 - WUE ABDEN 01-0 0-00 01-0 0-00 Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as `0'. PIC16F/LF1827 PIC16F/LF1827 only. These registers can be addressed from any bank. Note 1: 2: - 0000 0000 0000 0000 EEPROM / Program Memory Address Register High Byte -000 0000 -000 0000 EEPROM / Program Memory Read Data Register Low Byte - - EEPGD CFGS © 2009 Microchip Technology Inc. xxxx xxxx uuuu uuuu EEPROM / Program Memory Read Data Register High Byte LWLO FREE WRERR WREN WR -xx xxxx -uu uuuu RD 0000 x000 0000 q000 0000 0000 0000 0000 0000 0000 0000 0000 Preliminary DS41391B-page 33 PIC16F/LF1826/27 PIC16F/LF1826/27 TABLE 3-8: Address SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other resets Bank 4 200h(2) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 201h(2) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 202h(2) PCL Program Counter (PC) Least Significant Byte 203h(2) STATUS 204h(2) FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu 205h(2) FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000 206h(2) FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu 207h(2) FSR1H Indirect Data Memory Address 1 High Pointer 208h(2) BSR 209h(2) WREG 20Ah(2) PCLATH - 20Bh(2) INTCON GIE - - - - 0000 0000 0000 0000 - TO - PD Z DC C -1 1000 -q quuu 0000 0000 0000 0000 BSR4 BSR3 BSR2 BSR1 BSR0 Working Register -0 0000 -0 0000 0000 0000 uuuu uuuu Write Buffer for the upper 7 bits of the Program Counter PEIE TMR0IE INTE IOCIE -000 0000 -000 0000 TMR0IF INTF IOCIF 0000 000x 0000 000u 20Ch WPUA - - WPUA5 - - - - - -1- - -1- - 20Dh WPUB WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0 1111 1111 1111 1111 20Eh - Unimplemented - - 20Fh - Unimplemented - - 210h - Unimplemented - - 211h SSP1BUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu 212h SSP1ADD ADD7 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0 0000 0000 0000 0000 213h SSP1MSK MSK7 MSK6 MSK5 MSK4 MSK3 MSK2 MSK1 MSK0 1111 1111 1111 1111 214h SSP1STAT SMP CKE D/A P S R/W UA BF 0000 0000 0000 0000 215h SSP1CON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000 216h SSP1CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 0000 0000 217h SSP1CON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 0000 0000 0000 0000 218h - Unimplemented 219h SSP2BUF(1) Synchronous Serial Port Receive Buffer/Transmit Register 21Ah SSP2ADD(1) ADD7 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0 0000 0000 0000 0000 21Bh SSP2MSK(1) MSK7 MSK6 MSK5 MSK4 MSK3 MSK2 MSK1 MSK0 1111 1111 1111 1111 21Ch SSP2STAT(1) SMP CKE D/A P S R/W UA BF 0000 0000 0000 0000 21Dh SSP2CON1(1) WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000 21Eh SSP2CON2(1) GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 0000 0000 21Fh SSP2CON3(1) ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 0000 0000 0000 0000 Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as `0'. PIC16F/LF1827 PIC16F/LF1827 only. These registers can be addressed from any bank. Note 1: 2: DS41391B-page 34 - - xxxx xxxx uuuu uuuu Preliminary © 2009 Microchip Technology Inc. PIC16F/LF1826/27 PIC16F/LF1826/27 TABLE 3-8: Address SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other resets Bank 5 280h(2) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 281h(2) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 282h(2) PCL Program Counter (PC) Least Significant Byte 283h(2) STATUS 284h(2) FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu 285h(2) FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000 286h(2) FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu 287h(2) FSR1H Indirect Data Memory Address 1 High Pointer 288h(2) BSR 289h(2) WREG 28Ah(2) PCLATH - 28Bh(2) INTCON GIE - - - - - 0000 0000 0000 0000 TO - PD Z DC C -1 1000 -q quuu 0000 0000 0000 0000 BSR4 BSR3 BSR2 BSR1 BSR0 Working Register -0 0000 -0 0000 0000 0000 uuuu uuuu Write Buffer for the upper 7 bits of the Program Counter PEIE TMR0IE INTE IOCIE -000 0000 -000 0000 TMR0IF INTF IOCIF 0000 000x 0000 000u 28Ch - Unimplemented - - 28Dh - Unimplemented - - 28Eh - Unimplemented - - 28Fh - Unimplemented - - 290h - Unimplemented - - 291h CCPR1L Capture/Compare/PWM Register 1 (LSB) 292h CCPR1H Capture/Compare/PWM Register 1 (MSB) 293h CCP1CON P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 0000 0000 294h PWM1CON P1RSEN P1DC6 P1DC5 P1DC4 P1DC3 P1DC2 P1DC1 P1DC0 0000 0000 0000 0000 295h CCP1AS CCP1ASE CCP1AS2 CCP1AS1 CCP1AS0 PSS1AC1 296h PSTR1CON - - - STR1SYNC STR1D 297h - Unimplemented 298h CCPR2L(1) Capture/Compare/PWM Register 2 (LSB) 299h CCPR2H(1) Capture/Compare/PWM Register 2 (MSB) 29Ah CCP2CON(1) P2M1 P2M0 DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 0000 0000 0000 0000 29Bh PWM2CON(1) P2RSEN P2DC6 P2DC5 P2DC4 P2DC3 P2DC2 P2DC1 P2DC0 0000 0000 0000 0000 29Ch CCP2AS(1) CCP2ASE CCP2AS2 CCP2AS1 CCP2AS0 PSS2AC1 29Dh PSTR2CON(1) - - - STR2SYNC STR2D STR2C STR2B 29Eh CCPTMRS(1) C4TSEL1 C4TSEL0 C3TSEL1 C3TSEL0 C2TSEL1 C2TSEL0 C1TSEL1 29Fh - Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as `0'. PIC16F/LF1827 PIC16F/LF1827 only. These registers can be addressed from any bank. Note 1: 2: xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu PSS1AC0 PSS1BD1 PSS1BD0 0000 0000 0000 0000 STR1C STR1A -0 0001 -0 0001 - - xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu PSS2AC0 PSS2BD1 PSS2BD0 0000 0000 0000 0000 Unimplemented © 2009 Microchip Technology Inc. STR1B STR2A -0 0001 -0 0001 C1TSEL0 0000 0000 0000 0000 - Preliminary DS41391B-page 35 - PIC16F/LF1826/27 PIC16F/LF1826/27 TABLE 3-8: Address SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other resets Bank 6 300h(2) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 301h(2) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 302h(2) PCL Program Counter (PC) Least Significant Byte 303h(2) STATUS 304h(2) FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu 305h(2) FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000 306h(2) FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu 307h(2) FSR1H Indirect Data Memory Address 1 High Pointer 308h(2) BSR 309h(2) WREG 30Ah(2) PCLATH - 30Bh(2) INTCON GIE - - - - - 0000 0000 0000 0000 TO - PD Z DC C -1 1000 -q quuu 0000 0000 0000 0000 BSR4 BSR3 BSR2 BSR1 BSR0 Working Register -0 0000 -0 0000 0000 0000 uuuu uuuu Write Buffer for the upper 7 bits of the Program Counter PEIE TMR0IE INTE IOCIE -000 0000 -000 0000 TMR0IF INTF IOCIF 0000 000x 0000 000u 30Ch - Unimplemented - - 30Dh - Unimplemented - - 30Eh - Unimplemented - - 30Fh - Unimplemented - - 310h - Unimplemented - - 311h CCPR3L(1) Capture/Compare/PWM Register 3 (LSB) 312h CCPR3H(1) Capture/Compare/PWM Register 3 (MSB) 313h CCP3CON(1) 314h - Unimplemented - - 315h - Unimplemented - - 316h - Unimplemented - - 317h - Unimplemented - - 318h CCPR4L(1) Capture/Compare/PWM Register 4 (LSB) 319h CCPR4H(1) Capture/Compare/PWM Register 4 (MSB) 31Ah CCP4CON(1) 31Bh - Unimplemented - - 31Ch - Unimplemented - - 31Dh - Unimplemented - - 31Eh - Unimplemented - - 31Fh - Unimplemented - - Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as `0'. PIC16F/LF1827 PIC16F/LF1827 only. These registers can be addressed from any bank. Note 1: 2: DS41391B-page 36 - - - - DC3B1 DC4B1 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu DC3B0 CCP3M3 CCP3M2 CCP3M1 CCP3M0 -00 0000 -00 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu DC4B0 CCP4M3 Preliminary CCP4M2 CCP4M1 CCP4M0 -00 0000 -00 0000 © 2009 Microchip Technology Inc. PIC16F/LF1826/27 PIC16F/LF1826/27 TABLE 3-8: Address Name SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other resets Bank 7 380h(2) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 381h(2) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 382h(2) PCL Program Counter (PC) Least Significant Byte 383h(2) STATUS 384h(2) FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu 385h(2) FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000 386h(2) FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu 387h(2) FSR1H Indirect Data Memory Address 1 High Pointer 388h(2) BSR 389h(2) WREG 38Ah(2) PCLATH - 38Bh(2) INTCON GIE - - - - - 0000 0000 0000 0000 TO - PD Z DC C -1 1000 -q quuu 0000 0000 0000 0000 BSR4 BSR3 BSR2 BSR1 BSR0 Working Register -0 0000 -0 0000 0000 0000 uuuu uuuu Write Buffer for the upper 7 bits of the Program Counter PEIE TMR0IE INTE IOCIE -000 0000 -000 0000 TMR0IF INTF IOCIF 0000 000x 0000 000u 38Ch - Unimplemented - - 38Dh - Unimplemented - - 38Eh - Unimplemented - - 38Fh - Unimplemented - - 390h - Unimplemented - - 391h - Unimplemented - - 392h - Unimplemented - - 393h - Unimplemented - - 394h IOCBP IOCBP7 IOCBP6 IOCBP5 IOCBP4 IOCBP3 IOCBP2 IOCBP1 IOCBP0 0000 0000 0000 0000 395h IOCBN IOCBN7 IOCBN6 IOCBN5 IOCBN4 IOCBN3 IOCBN2 IOCBN1 IOCBN0 0000 0000 0000 0000 396h IOCBF IOCBF7 IOCBF6 IOCBF5 IOCBF4 IOCBF3 IOCBF2 IOCBF1 IOCBF0 0000 0000 0000 0000 397h - Unimplemented - - 398h - Unimplemented - - 399h - Unimplemented - - 39Ah CLKRCON CLKREN CLKROE CLKRSLR CLKRDC1 CLKRDC0 MDSLR MDOPOL - - - MDBIT 0010 -0 0010 -0 CLKRDIV2 CLKRDIV1 CLKRDIV0 0011 0000 0011 0000 39Bh - 39Ch MDCON MDEN 39Dh MDSRC MDMSODIS - - - MDMS3 MDMS2 MDMS1 MDMS0 x- xxxx u- uuuu 39Eh MDCARL MDCLODIS MDCLPOL MDCLSYNC - MDCL3 MDCL2 MDCL1 MDCL0 xxx- xxxx uuu- uuuu 39Fh MDCARH MDCHODIS MDCHPOL MDCHSYNC - MDCH3 MDCH2 MDCH1 MDCH0 xxx- xxxx uuu- uuuu Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as `0'. PIC16F/LF1827 PIC16F/LF1827 only. These registers can be addressed from any bank. Note 1: 2: Unimplemented © 2009 Microchip Technology Inc. - MDOE Preliminary DS41391B-page 37 - PIC16F/LF1826/27 PIC16F/LF1826/27 TABLE 3-8: Address Name SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other resets Bank 8 400h(2) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 401h(2) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 402h(2) PCL Program Counter (PC) Least Significant Byte 403h(2) STATUS 404h(2) FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu 405h(2) FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000 406h(2) FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu 407h(2) FSR1H Indirect Data Memory Address 1 High Pointer 408h(2) BSR 409h(2) WREG 40Ah(2) PCLATH - 40Bh(2) INTCON GIE - - - - - 0000 0000 0000 0000 TO - PD Z DC C -1 1000 -q quuu 0000 0000 0000 0000 BSR4 BSR3 BSR2 BSR1 BSR0 Working Register -0 0000 -0 0000 0000 0000 uuuu uuuu Write Buffer for the upper 7 bits of the Program Counter PEIE TMR0IE INTE IOCIE -000 0000 -000 0000 TMR0IF INTF IOCIF 0000 000x 0000 000u 40Ch - Unimplemented - - 40Dh - Unimplemented - - 40Eh - Unimplemented - - 40Fh - Unimplemented - - 410h - Unimplemented - - 411h - Unimplemented - - 412h - Unimplemented - - 413h - Unimplemented - - 414h - Unimplemented - - 415h TMR4(1) Timer4 Module Register 416h PR4(1) Timer4 Period Register 417h T4CON(1) - T4OUTPS3 0000 0000 0000 0000 1111 1111 1111 1111 T4OUTPS2 T4OUTPS1 T4OUTPS0 TMR4ON T4CKPS1 T4CKPS0 -000 0000 -000 0000 418h - Unimplemented - - 419h - Unimplemented - - 41Ah - Unimplemented - - 41Bh - Unimplemented - - 41Ch TMR6(1) Timer6 Module Register 41Dh PR6(1) Timer6 Period Register 41Eh T6CON(1) 41Fh - Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as `0'. PIC16F/LF1827 PIC16F/LF1827 only. These registers can be addressed from any bank. Note 1: 2: DS41391B-page 38 - T6OUTPS3 0000 0000 0000 0000 1111 1111 1111 1111 T6OUTPS2 T6OUTPS1 T6OUTPS0 TMR6ON Unimplemented T6CKPS1 T6CKPS0 -000 0000 -000 0000 - Preliminary © 2009 Microchip Technology Inc. - PIC16F/LF1826/27 PIC16F/LF1826/27 TABLE 3-8: Address Name SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other resets Banks 9-30 x00h/ x80h(2) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) xxxx xxxx xxxx xxxx x00h/ x81h(2) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) xxxx xxxx xxxx xxxx x02h/ x82h(2) PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000 x03h/ x83h(2) STATUS x04h/ x84h(2) FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu x05h/ x85h(2) FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000 x06h/ x86h(2) FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu x07h/ x87h(2) FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000 x08h/ x88h(2) BSR x09h/ x89h(2) WREG x0Ah/ x8Ah(2) PCLATH - x0Bh/ x8Bh(2) INTCON GIE x0Ch/ x8Ch - x1Fh/ x9Fh - Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as `0'. PIC16F/LF1827 PIC16F/LF1827 only. These registers can be addressed from any bank. Note 1: 2: - - - - - TO - BSR4 PD BSR3 Z BSR2 DC BSR1 C -1 1000 -q quuu BSR0 Working Register 0000 0000 uuuu uuuu Write Buffer for the upper 7 bits of the Program Counter PEIE TMR0IE INTE IOCIE -000 0000 -000 0000 TMR0IF Unimplemented © 2009 Microchip Technology Inc. -0 0000 -0 0000 INTF IOCIF 0000 000x 0000 000u - Preliminary DS41391B-page 39 - PIC16F/LF1826/27 PIC16F/LF1826/27 TABLE 3-8: Address SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other resets Bank 31 F80h(2) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) xxxx xxxx xxxx xxxx F81h(2) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) xxxx xxxx xxxx xxxx F82h(2) PCL Program Counter (PC) Least Significant Byte F83h(2) STATUS F84h(2) FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu F85h(2) FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000 F86h(2) FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu F87h(2) FSR1H Indirect Data Memory Address 1 High Pointer F88h(2) BSR F89h(2) WREG F8Ah(2) PCLATH - F8Bh(2) INTCON GIE F8Ch - FE3h - FE4h - - - - - 0000 0000 0000 0000 TO - PD Z DC C 0000 0000 0000 0000 BSR4 BSR3 BSR2 BSR1 BSR0 Working Register Write Buffer for the upper 7 bits of the Program Counter PEIE - -0 0000 -0 0000 0000 0000 uuuu uuuu TMR0IE INTE IOCIE -000 0000 -000 0000 TMR0IF INTF IOCIF Unimplemented STATUS_ -1 1000 -q quuu 0000 000x 0000 000u - - - - - Z DC C - - -xxx - -uuu SHAD FE5h WREG_ Working Register Shadow 0000 0000 uuuu uuuu SHAD FE6h BSR_ - - - Bank Select Register Shadow -x xxxx -u uuuu SHAD FE7h PCLATH_ - Program Counter Latch High Register Shadow -xxx xxxx uuuu uuuu SHAD FE8h FSR0L_ Indirect Data Memory Address 0 Low Pointer Shadow xxxx xxxx uuuu uuuu Indirect Data Memory Address 0 High Pointer Shadow xxxx xxxx uuuu uuuu Indirect Data Memory Address 1 Low Pointer Shadow xxxx xxxx uuuu uuuu Indirect Data Memory Address 1 High Pointer Shadow xxxx xxxx uuuu uuuu SHAD FE9h FSR0H_ SHAD FEAh FSR1L_ SHAD FEBh FSR1H_ SHAD FECh - Unimplemented - FEDh STKPTR FEEh TOSL FEFh TOSH Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as `0'. PIC16F/LF1827 PIC16F/LF1827 only. These registers can be addressed from any bank. Note 1: 2: DS41391B-page 40 - - - Current Stack pointer Top-of-Stack Low byte - - -1 1111 -1 1111 xxxx xxxx uuuu uuuu Top-of-Stack High byte -xxx xxxx -uuu uuuu Preliminary © 2009 Microchip Technology Inc. PIC16F/LF1826/27 PIC16F/LF1826/27 3.3 3.3.3 PCL and PCLATH COMPUTED FUNCTION CALLS The Program Counter (PC) is 15 bits wide. The low byte comes from the PCL register, which is a readable and writable register. The high byte (PC) is not directly readable or writable and comes from PCLATH. On any Reset, the PC is cleared. Figure 3-4 shows the five situations for the loading of the PC. A computed function CALL allows programs to maintain tables of functions and provide another way to execute state machines or look-up tables. When performing a table read using a computed function CALL, care should be exercised i