PIC16C9XX PIC16C923 PIC16C924 RD7/SEG31/COM1 RD6/SEG30/COM2 RD5/SEG29/COM3 - Datasheet Archive

 

8-Bit CMOS Microcontroller with LCD Driver Devices included in this data sheet: Available in Die Form · PIC16C923 ·

 

PIC16C9XX PIC16C9XX 8-Bit CMOS Microcontroller with LCD Driver Devices included in this data sheet: Available in Die Form · PIC16C923 PIC16C923 · PIC16C924 PIC16C924 Microcontroller Core Features: · · · · · · · · · · High performance RISC CPU Only 35 single word instructions to learn 4K x 14 on-chip EPROM program memory 176 x 8 general purpose registers (SRAM) 57 special function registers (60 for PIC16C924 PIC16C924) All single cycle instructions (500 ns) except for program branches which are two-cycle Operating speed: DC - 8 MHz clock input DC - 500 ns instruction cycle Interrupt capability Eight level deep hardware stack Direct, indirect and relative addressing modes Peripheral Features: · · · · 25 I/O pins with individual direction control 25-27 input only pins Timer0: 8-bit timer/counter with 8-bit prescaler Timer1: 16-bit timer/counter. TMR1 can be incremented during sleep via external crystal/clock · Timer2: 8-bit timer/counter with 8-bit period register, prescaler and postscaler · One pin that can be configured a capture input, PWM output, or compare output - Capture is 16-bit, max. resolution 31.25 ns - Compare is 16-bit, max. resolution 500 ns - PWM resolution is 1- to 10-bits. Maximum PWM frequency @ 8-bit resolution = 32 kHz, @ 10-bit resolution = 8 kHz · Programmable LCD timing module - Multiple LCD timing sources available - Can drive LCD panel while in Sleep mode - Static, 1/2, 1/3, 1/4 multiplex - Static drive and 1/3 bias capability - 16 bytes of dedicated LCD RAM - Up to 32 segments, up to 4 commons Common Segment Pixels 1 32 32 2 31 62 3 30 90 4 29 116 · Synchronous Serial Port (SSP) with SPITM and I2CTM · 8-bit multichannel Analog to Digital converter (PIC16C924 PIC16C924 only) Special Microcontroller Features · Power-on Reset (POR) · Power-up Timer (PWRT) and Oscillator Start-up Timer (OST) · Watchdog Timer (WDT) with its own on-chip RC oscillator for reliable operation · Programmable code-protection · Power saving SLEEP mode · Selectable oscillator options · Serial in-system programming (via two pins) CMOS Technology · Low-power, high-speed CMOS EPROM technology · Fully static design · Wide operating voltage range: 3.0V to 6.0V · Commercial and Industrial temperature ranges · Low-power consumption: - < 2 mA @ 5.5V, 4 MHz - 22.5 µA typical @ 4V, 32 kHz - < 1 µA typical standby current @ 3.0V I2C is a trademark of Philips Corporation. SPI is a trademark of Motorola Corporation. © 1996 Microchip Technology Inc. Advance Information This document was created with FrameMaker 4 0 4 DS30444B-page 1 PIC16C9XX PIC16C9XX RA3 RA2 VSS RA1 RA0 RB2 RB3 MCLR/VPP N/C RB4 RB5 RB7 RB6 VDD COM0 RD7/SEG31/COM1 RD7/SEG31/COM1 RD6/SEG30/COM2 RD6/SEG30/COM2 Pin Diagrams 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 PLCC 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 Shrink PDIP(1) (750 mil) PIC16C923 PIC16C923 RD5/SEG29/COM3 RD5/SEG29/COM3 RG6/SEG26 RG6/SEG26 RG5/SEG25 RG5/SEG25 RG4/SEG24 RG4/SEG24 RG3/SEG23 RG3/SEG23 RG2/SEG22 RG2/SEG22 RG1/SEG21 RG1/SEG21 RG0/SEG20 RG0/SEG20 RG7/SEG28 RG7/SEG28 RF7/SEG19 RF7/SEG19 RF6/SEG18 RF6/SEG18 RF5/SEG17 RF5/SEG17 RF4/SEG16 RF4/SEG16 RF3/SEG15 RF3/SEG15 RF2/SEG14 RF2/SEG14 RF1/SEG13 RF1/SEG13 RF0/SEG12 RF0/SEG12 RC1/T1OSI RC2/CCP1 VLCD1 VLCDADJ RD0/SEG00 RD0/SEG00 RD1/SEG01 RD1/SEG01 RD2/SEG02 RD2/SEG02 RD3/SEG03 RD3/SEG03 RD4/SEG04 RD4/SEG04 RE7/SEG27 RE7/SEG27 RE0/SEG05 RE0/SEG05 RE1/SEG06 RE1/SEG06 RE2/SEG07 RE2/SEG07 RE3/SEG08 RE3/SEG08 RE4/SEG09 RE4/SEG09 RE5/SEG10 RE5/SEG10 RE6/SEG11 RE6/SEG11 RB4 RB5 RB7 RB6 VDD COM0 RD7/SEG31/COM1 RD7/SEG31/COM1 RD6/SEG30/COM2 RD6/SEG30/COM2 RD5/SEG29/COM3 RD5/SEG29/COM3 RG6/SEG26 RG6/SEG26 RG5/SEG25 RG5/SEG25 RG4/SEG24 RG4/SEG24 RG3/SEG23 RG3/SEG23 RG2/SEG22 RG2/SEG22 RG1/SEG21 RG1/SEG21 RG0/SEG20 RG0/SEG20 RF7/SEG19 RF7/SEG19 RF6/SEG18 RF6/SEG18 RF5/SEG17 RF5/SEG17 RF4/SEG16 RF4/SEG16 RF3/SEG15 RF3/SEG15 RF2/SEG14 RF2/SEG14 RF1/SEG13 RF1/SEG13 RF0/SEG12 RF0/SEG12 RE6/SEG11 RE6/SEG11 RE5/SEG10 RE5/SEG10 RE4/SEG09 RE4/SEG09 RE3/SEG08 RE3/SEG08 RE2/SEG07 RE2/SEG07 RE1/SEG06 RE1/SEG06 RE0/SEG05 RE0/SEG05 RD4/SEG04 RD4/SEG04 RA3 RA2 VSS RA1 RA0 RB2 RB3 MCLR/VPP RB4 RB5 RB7 RB6 VDD COM0 RD7/SEG31/COM1 RD7/SEG31/COM1 RD6/SEG30/COM2 RD6/SEG30/COM2 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 TQFP 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 PIC16C923 PIC16C923 MCLR/VPP RB3 RB2 RA0 RA1 VSS RA2 RA3 RA4/T0CKI RA5/SS RB1 RB0/INT RC3/SCK/SCL RC4/SDI/SDA RC5/SDO C1 C2 VLCD2 VLCD3 VDD VSS OSC1/CLKIN OSC2/CLKOUT RC0/T1OSO/T1CKI RC1/T1OSI RC2/CCP1 VLCD1 VLCDADJ RD0/SEG00 RD0/SEG00 RD1/SEG01 RD1/SEG01 RD2/SEG02 RD2/SEG02 RD3/SEG03 RD3/SEG03 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 RA4/T0CKI RA5/SS RB1 RB0/INT RC3/SCK/SCL RC4/SDI/SDA RC5/SDO C1 C2 VLCD2 VLCD3 VDD VDD VSS OSC1/CLKIN OSC2/CLKOUT RC0/T1OSO/T1CKI 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PIC16C923 PIC16C923 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 RD5/SEG29/COM3 RD5/SEG29/COM3 RG6/SEG26 RG6/SEG26 RG5/SEG25 RG5/SEG25 RG4/SEG24 RG4/SEG24 RG3/SEG23 RG3/SEG23 RG2/SEG22 RG2/SEG22 RG1/SEG21 RG1/SEG21 RG0/SEG20 RG0/SEG20 RF7/SEG19 RF7/SEG19 RF6/SEG18 RF6/SEG18 RF5/SEG17 RF5/SEG17 RF4/SEG16 RF4/SEG16 RF3/SEG15 RF3/SEG15 RF2/SEG14 RF2/SEG14 RF1/SEG13 RF1/SEG13 RF0/SEG12 RF0/SEG12 LEGEND: Input Pin Output Pin Input/Output Pin Digital Input/LCD Output Pin LCD Output Pin DS30444B-page 2 RC1/T1OSI RC2/CCP1 VLCD1 VLCDADJ RD0/SEG00 RD0/SEG00 RD1/SEG01 RD1/SEG01 RD2/SEG02 RD2/SEG02 RD3/SEG03 RD3/SEG03 RD4/SEG04 RD4/SEG04 RE0/SEG05 RE0/SEG05 RE1/SEG06 RE1/SEG06 RE2/SEG07 RE2/SEG07 RE3/SEG08 RE3/SEG08 RE4/SEG09 RE4/SEG09 RE5/SEG10 RE5/SEG10 RE6/SEG11 RE6/SEG11 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 RA4/T0CKI RA5/SS RB1 RB0/INT RC3/SCK/SCL RC4/SDI/SDA RC5/SDO C1 C2 VLCD2 VLCD3 VDD VSS OSC1/CLKIN OSC2/CLKOUT RC0/T1OSO/T1CKI Note 1: Please contact your local Microchip representative for availability of this package. Advance Information © 1996 Microchip Technology Inc. PIC16C9XX PIC16C9XX RA3/AN3/VREF RA2/AN2 VSS RA1/AN1 RA0/AN0 RB2 RB3 MCLR/VPP N/C RB4 RB5 RB7 RB6 VDD COM0 RD7/SEG31/COM1 RD7/SEG31/COM1 RD6/SEG30/COM2 RD6/SEG30/COM2 Pin Diagrams (Cont.'d) 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 PLCC 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 RA4/T0CKI RA5/AN4/SS RB1 RB0/INT RC3/SCK/SCL RC4/SDI/SDA RC5/SDO C1 C2 VLCD2 VLCD3 AVDD VDD VSS OSC1/CLKIN OSC2/CLKOUT RC0/T1OSO/T1CKI PIC16C924 PIC16C924 RD5/SEG29/COM3 RD5/SEG29/COM3 RG6/SEG26 RG6/SEG26 RG5/SEG25 RG5/SEG25 RG4/SEG24 RG4/SEG24 RG3/SEG23 RG3/SEG23 RG2/SEG22 RG2/SEG22 RG1/SEG21 RG1/SEG21 RG0/SEG20 RG0/SEG20 RG7/SEG28 RG7/SEG28 RF7/SEG19 RF7/SEG19 RF6/SEG18 RF6/SEG18 RF5/SEG17 RF5/SEG17 RF4/SEG16 RF4/SEG16 RF3/SEG15 RF3/SEG15 RF2/SEG14 RF2/SEG14 RF1/SEG13 RF1/SEG13 RF0/SEG12 RF0/SEG12 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 Shrink PDIP(1) (750 mil) 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 RC1/T1OSI RC2/CCP1 VLCD1 VLCDADJ RD0/SEG00 RD0/SEG00 RD1/SEG01 RD1/SEG01 RD2/SEG02 RD2/SEG02 RD3/SEG03 RD3/SEG03 RD4/SEG04 RD4/SEG04 RE7/SEG27 RE7/SEG27 RE0/SEG05 RE0/SEG05 RE1/SEG06 RE1/SEG06 RE2/SEG07 RE2/SEG07 RE3/SEG08 RE3/SEG08 RE4/SEG09 RE4/SEG09 RE5/SEG10 RE5/SEG10 RE6/SEG11 RE6/SEG11 RB4 RB5 RB7 RB6 VDD COM0 RD7/SEG31/COM1 RD7/SEG31/COM1 RD6/SEG30/COM2 RD6/SEG30/COM2 RD5/SEG29/COM3 RD5/SEG29/COM3 RG6/SEG26 RG6/SEG26 RG5/SEG25 RG5/SEG25 RG4/SEG24 RG4/SEG24 RG3/SEG23 RG3/SEG23 RG2/SEG22 RG2/SEG22 RG1/SEG21 RG1/SEG21 RG0/SEG20 RG0/SEG20 RF7/SEG19 RF7/SEG19 RF6/SEG18 RF6/SEG18 RF5/SEG17 RF5/SEG17 RF4/SEG16 RF4/SEG16 RF3/SEG15 RF3/SEG15 RF2/SEG14 RF2/SEG14 RF1/SEG13 RF1/SEG13 RF0/SEG12 RF0/SEG12 RE6/SEG11 RE6/SEG11 RE5/SEG10 RE5/SEG10 RE4/SEG09 RE4/SEG09 RE3/SEG08 RE3/SEG08 RE2/SEG07 RE2/SEG07 RE1/SEG06 RE1/SEG06 RE0/SEG05 RE0/SEG05 RD4/SEG04 RD4/SEG04 RA3/AN3/VREF RA2/AN2 VSS RA1/AN1 RA0/AN0 RB2 RB3 MCLR/VPP RB4 RB5 RB7 RB6 VDD COM0 RD7/SEG31/COM1 RD7/SEG31/COM1 RD6/SEG30/COM2 RD6/SEG30/COM2 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 TQFP 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 PIC16C924 PIC16C924 MCLR/VPP RB3 RB2 RA0/AN0 RA1/AN1 VSS RA2/AN2 RA3/AN3/VREF RA4/T0CKI RA5/AN4/SS RB1 RB0/INT RC3/SCK/SCL RC4/SDI/SDA RC5/SDO C1 C2 VLCD2 VLCD3 VDD VSS OSC1/CLKIN OSC2/CLKOUT RC0/T1OSO/T1CKI RC1/T1OSI RC2/CCP1 VLCD1 VLCDADJ RD0/SEG00 RD0/SEG00 RD1/SEG01 RD1/SEG01 RD2/SEG02 RD2/SEG02 RD3/SEG03 RD3/SEG03 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PIC16C924 PIC16C924 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 RD5/SEG29/COM3 RD5/SEG29/COM3 RG6/SEG26 RG6/SEG26 RG5/SEG25 RG5/SEG25 RG4/SEG24 RG4/SEG24 RG3/SEG23 RG3/SEG23 RG2/SEG22 RG2/SEG22 RG1/SEG21 RG1/SEG21 RG0/SEG20 RG0/SEG20 RF7/SEG19 RF7/SEG19 RF6/SEG18 RF6/SEG18 RF5/SEG17 RF5/SEG17 RF4/SEG16 RF4/SEG16 RF3/SEG15 RF3/SEG15 RF2/SEG14 RF2/SEG14 RF1/SEG13 RF1/SEG13 RF0/SEG12 RF0/SEG12 RC1/T1OSI RC2/CCP1 VLCD1 VLCDADJ RD0/SEG00 RD0/SEG00 RD1/SEG01 RD1/SEG01 RD2/SEG02 RD2/SEG02 RD3/SEG03 RD3/SEG03 RD4/SEG04 RD4/SEG04 RE0/SEG05 RE0/SEG05 RE1/SEG06 RE1/SEG06 RE2/SEG07 RE2/SEG07 RE3/SEG08 RE3/SEG08 RE4/SEG09 RE4/SEG09 RE5/SEG10 RE5/SEG10 RE6/SEG11 RE6/SEG11 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 RA4/T0CKI RA5/AN4/SS RB1 RB0/INT RC3/SCK/SCL RC4/SDI/SDA RC5/SDO C1 C2 VLCD2 VLCD3 VDD VSS OSC1/CLKIN OSC2/CLKOUT RC0/T1OSO/T1CKI LEGEND: Input Pin Output Pin Input/Output Pin Digital Input/LCD Output Pin LCD Output Pin © 1996 Microchip Technology Inc. Note 1: Please contact your local Microchip representative for availability of this package. Advance Information DS30444B-page 3 PIC16C9XX PIC16C9XX Table of Contents 1.0 General Description . 5 2.0 PIC16C9XX PIC16C9XX Device Varieties. 7 3.0 Architectural Overview . 9 4.0 Memory Organization. 17 5.0 Ports. 31 6.0 Overview of Timer Modules . 47 7.0 Timer0 Module . 49 8.0 Timer1 Module . 55 9.0 Timer2 Module . 59 10.0 Capture/Compare/PWM (CCP) Module . 61 11.0 Synchronous Serial Port (SSP) Module. 67 12.0 Analog-to-Digital Converter (A/D) Module . 83 13.0 LCD Module . 93 14.0 Special Features of the CPU . 105 15.0 Instruction Set Summary. 121 16.0 Development Support . 135 17.0 Electrical Characteristics. 139 18.0 Packaging Information . 161 Appendix A: . 165 Appendix B: Compatibility . 165 Appendix C: What's New. 166 Appendix D: What's Changed . 166 Appendix E: PIC16/17 PIC16/17 Microcontrollers . 167 Index . 177 List of Examples. 181 LIst of Figures . 181 List of Tables. 182 Reader Response . 186 Product Identification System. 187 To Our Valued Customers We constantly strive to improve the quality of all our products and documentation. We have spent an exceptional amount of time to ensure that these documents are correct. However, we realize that we may have missed a few things. If you find any information that is missing or appears in error, please use the reader response form in the back of this data sheet to inform us. We appreciate your assistance in making this a better document. DS30444B-page 4 Advance Information © 1996 Microchip Technology Inc. PIC16C9XX PIC16C9XX 1.0 GENERAL DESCRIPTION The PIC16C9XX PIC16C9XX is a family of low-cost, high-performance, CMOS, fully-static, 8-bit microcontrollers with an integrated LCD Driver module, in the PIC16CXX PIC16CXX mid-range family. All PIC16/17 PIC16/17 microcontrollers employ an advanced RISC architecture. The PIC16CXX PIC16CXX microcontroller family has enhanced core features, eight-level deep stack, and multiple internal and external interrupt sources. The separate instruction and data buses of the Harvard architecture allow a 14-bit wide instruction word with the separate 8-bit wide data. The two stage instruction pipeline allows all instructions to execute in a single cycle, except for program branches (which require two cycles). A total of 35 instructions (reduced instruction set) are available. Additionally, a large register set gives some of the architectural innovations used to achieve a very high performance. PIC16CXX PIC16CXX microcontrollers typically achieve a 2:1 code compression and a 4:1 speed improvement over other 8-bit microcontrollers in their class. The PIC16C923 PIC16C923 devices have 176 bytes of RAM and 25 I/O pins. In addition several peripheral features are available including: three timer/counters, one Capture/Compare/PWM module, one serial port and one LCD module. The Synchronous Serial Port can be configured as either a 3-wire Serial Peripheral Interface (SPI) or the two-wire Inter-Integrated Circuit (I 2C) bus. The LCD module features programmable multiplex mode (static, 1/2, 1/3 and 1/4) and drive bias (static and 1/3). It is capable of driving up to 32 segments and up to 4 commons. It can also drive the LCD panel while in SLEEP mode. The PIC16C924 PIC16C924 devices have 176 bytes of RAM and 25 I/O pins. In addition several peripheral features are available including: three timer/counters, one Capture/Compare/PWM module, one serial port and one LCD module. The Synchronous Serial Port can be configured as either a 3-wire Serial Peripheral Interface (SPI) or the two-wire Inter-Integrated Circuit (I 2C) bus. The LCD module features programmable multiplex mode (static, 1/2, 1/3 and 1/4) and drive bias (static and 1/3). It is capable of driving up to 32 segments and up to 4 commons. It can also drive the LCD panel while in SLEEP mode. The PIC16C924 PIC16C924 also has an 5-channel high-speed 8-bit A/D. The 8-bit resolution is ideally suited for applications requiring low-cost analog interface, e.g. thermostat control, pressure sensing, and meters. mode. The user can wake up the chip from SLEEP through several external and internal interrupts and reset(s). A highly reliable Watchdog Timer with its own on-chip RC oscillator provides recovery in the event of a software lock-up. A UV erasable CERQUAD (compatible with PLCC) packaged version is ideal for code development while the cost-effective One-Time-Programmable (OTP) version is suitable for production in any volume. The PIC16C9XX PIC16C9XX family fits perfectly in applications ranging from handheld meters, thermostats, to home security products. The EPROM technology makes customization of application programs (LCD panels, calibration constants, sensor interfaces, etc.) extremely fast and convenient. The small footprint packages make this microcontroller series perfect for all applications with space limitations. Low cost, low power, high performance, ease of use and I/O flexibility make the PIC16C9XX PIC16C9XX very versatile even in areas where no microcontroller use has been considered before (e.g. timer functions, capture and compare, PWM functions and coprocessor applications). 1.1 Family and Upward Compatibility Users familiar with the PIC16C5X PIC16C5X microcontroller family will realize that this is an enhanced version of the PIC16C5X PIC16C5X architecture. Please refer to Appendix A for a detailed list of enhancements. Code written for the PIC16C5X PIC16C5X can be easily ported to the PIC16CXX PIC16CXX family of devices (Appendix B). 1.2 Development Support The PIC16C9XX PIC16C9XX family will be supported by a full-featured macro assembler, a software simulator, an in-circuit emulator, a low-cost development programmer and a full-featured programmer. A "C" compiler and fuzzy logic support tools are also in development. The PIC16C9XX PIC16C9XX family has special features to reduce external components, thus reducing cost, enhancing system reliability and reducing power consumption. There are four oscillator options, of which the single pin RC oscillator provides a low-cost solution, the LP oscillator minimizes power consumption, XT is a standard crystal, and the HS is for High Speed crystals. The SLEEP (power-down) feature provides a power saving © 1996 Microchip Technology Inc. Advance Information This document was created with FrameMaker 4 0 4 DS30444B-page 5 DS30444B-page 6 Advance Information 4K 8 PIC16C924 PIC16C924 Note M em y or ( le u od T) R SA s el n an Features 176 TMR0, 1 SPI/I2C TMR1, TMR2 176 TMR0, 1 SPI/I2C TMR1, TMR2 - - 5 - 4 Com 32 Seg 4 Com 32 Seg 9 8 25 25 27 27 3.0-6.0 3.0-6.0 Yes Yes - - 64-pin SDIP(1), TQFP, 68-pin PLCC, DIE 64-pin SDIP(1), TQFP, 68-pin PLCC, DIE All PIC16/17 PIC16/17 Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current capability. All PIC16CXX PIC16CXX Family devices use serial programming with clock pin RB6 and data pin RB7. 1: Please contact your local Microchip representative for availability of this package. 4K 8 PIC16C923 PIC16C923 (M Peripherals s) g in M m h m am ,U M 2C C ) r ra ts t) W og tes) o t ol bi og I/I /P Pr y or cy 8t (V ) Pr re (SP es n s P l (b e r( se rc pa s) ia ue e e( y ng rte m le ou ul ( er eq Re or av t a e o l u S s t s Fr R od or tS /C nv in od em lS pt ins ou ge e M ui M re al P um M M lle nCo tP O ka rru ag irc i m P tu er i c D r ra ta R lt p D te pu ow m -C ax Pa Se In A/ LC Pa I/O In Vo Da Ti EP M In Br Ca ra pe fO n tio Memory TABLE 1-1: ) Hz Clock PIC16C9XX PIC16C9XX PIC16C9XX PIC16C9XX FAMILY OF DEVICES © 1996 Microchip Technology Inc. PIC16C9XX PIC16C9XX 2.0 PIC16C9XX PIC16C9XX DEVICE VARIETIES A variety of frequency ranges and packaging options are available. Depending on application and production requirements, the proper device option can be selected using the information in the PIC16C9XX PIC16C9XX Product Selection System section at the end of this data sheet. When placing orders, please use that page of the data sheet to specify the correct part number. For the PIC16C9XX PIC16C9XX family, there are two device "types" as indicated in the device number: 1. 2. 2.1 C, as in PIC16C924 PIC16C924. These devices have EPROM type memory and operate over the standard voltage range. LC, as in PIC16LC924 PIC16LC924. These devices have EPROM type memory and operate over an extended voltage range. UV Erasable Devices The UV erasable version, offered in CERQUAD package, is optimal for prototype development and pilot programs. The UV erasable version can be erased and reprogrammed to any of the configuration modes. Microchip's PICSTARTTM Plus and PRO MATETM II programmers both support the PIC16C9XX PIC16C9XX. Third party programmers also are available; refer to the Microchip Third Party Guide for a list of sources. 2.2 2.3 Quick-Turnaround-Production (QTP) Devices Microchip offers a QTP Programming Service for factory production orders. This service is made available for users who choose not to program a medium to high quantity of units and whose code patterns have stabilized. The devices are identical to the OTP devices but with all EPROM locations and configuration options already programmed by the factory. Certain code and prototype verification procedures apply before production shipments are available. Please contact your local Microchip Technology sales office for more details. 2.4 Serialized Quick-Turnaround Production (SQTPSM) Devices Microchip offers a unique programming service where a few user-defined locations in each device are programmed with different serial numbers. The serial numbers may be random, pseudo-random or sequential. Serial programming allows each device to have a unique number which can serve as an entry-code, password or ID number. One-Time-Programmable (OTP) Devices The availability of OTP devices is especially useful for customers who need the flexibility for frequent code updates and small volume applications. The OTP devices, packaged in plastic packages, permit the user to program them once. In addition to the program memory, the configuration bits must also be programmed. © 1996 Microchip Technology Inc. Advance Information This document was created with FrameMaker 4 0 4 DS30444B-page 7 PIC16C9XX PIC16C9XX NOTES: DS30444B-page 8 Advance Information © 1996 Microchip Technology Inc. PIC16C9XX PIC16C9XX 3.0 ARCHITECTURAL OVERVIEW The high performance of the PIC16CXX PIC16CXX family can be attributed to a number of architectural features commonly found in RISC microprocessors. To begin with, the PIC16CXX PIC16CXX uses a Harvard architecture, in which, program and data are accessed from separate memories using separate buses. This improves bandwidth over traditional von Neumann architecture where program and data are fetched from the same memory using the same bus. Separating program and data buses further allows instructions to be sized differently than the 8-bit wide data word. Instruction opcodes are 14-bits wide making it possible to have all single word instructions. A 14-bit wide program memory access bus fetches a 14-bit instruction in a single cycle. A two-stage pipeline overlaps fetch and execution of instructions (Example 3-1). Consequently, all instructions execute in a single cycle (500 ns @ 8 MHz) except for program branches. The PIC16C923 PIC16C923 and PIC16C924 PIC16C924 both address 4K x 14 of program memory and 176 x 8 of data memory. PIC16CXX PIC16CXX devices contain an 8-bit ALU and working register. The ALU is a general purpose arithmetic unit. It performs arithmetic and Boolean functions between the data in the working register and any register file. The ALU is 8-bits wide and capable of addition, subtraction, shift and logical operations. Unless otherwise mentioned, arithmetic operations are two's complement in nature. In two-operand instructions, typically one operand is the working register (W register). The other operand is a file register or an immediate constant. In single operand instructions, the operand is either the W register or a file register. The W register is an 8-bit working register used for ALU operations. It is not an addressable register. Depending on the instruction executed, the ALU may affect the values of the Carry (C), Digit Carry (DC), and Zero (Z) bits in the STATUS register. The C and DC bits operate as a borrow bit and a digit borrow out bit, respectively, in subtraction. See the SUBLW and SUBWF instructions for examples. The PIC16CXX PIC16CXX can directly or indirectly address its register files or data memory. All special function registers, including the program counter, are mapped in the data memory. The PIC16CXX PIC16CXX has an orthogonal (symmetrical) instruction set that makes it possible to carry out any operation on any register using any addressing mode. This symmetrical nature and lack of `special optimal situations' make programming with the PIC16CXX PIC16CXX simple yet efficient, thus significantly reducing the learning curve. © 1996 Microchip Technology Inc. Advance Information This document was created with FrameMaker 4 0 4 DS30444B-page 9 PIC16C9XX PIC16C9XX FIGURE 3-1: PIC16C923 PIC16C923 BLOCK DIAGRAM 13 Program Memory Program Bus 14 PORTA RA0 RA1 RA2 RA3 RA4/T0CKI RA5/SS RAM File Registers 176 x 8 8 Level Stack (13-bit) 4K x 14 8 Data Bus Program Counter EPROM RAM Addr PORTB 9 Addr MUX Instruction reg RB0/INT 7 Direct Addr 8 Indirect Addr RB1-RB7 FSR reg STATUS reg 8 3 Power-up Timer Instruction Decode & Control Timing Generation Oscillator Start-up Timer Power-on Reset PORTC RC0/T1OSO/T1CKI RC1/T1OSI RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO MUX ALU PORTD 8 Watchdog Timer W reg RD0-RD4/SEGnn OSC1/CLKIN OSC2/CLKOUT RD5-RD7/SEGnn/COMn MCLR VDD, VSS PORTE RE0-RE7/SEGnn PORTF RF0-RF7/SEGnn PORTG RG0-RG7/SEGnn Timer1, Timer2, CCP1 Timer0 Synchronous Serial Port LCD DS30444B-page 10 Advance Information COM0 VLCD1 VLCD2 VLCD3 C1 C2 VLCDADJ © 1996 Microchip Technology Inc. PIC16C9XX PIC16C9XX FIGURE 3-2: PIC16C924 PIC16C924 BLOCK DIAGRAM 13 Program Memory Program Bus 14 PORTA RA0/AN0 RA1/AN1 RA2/AN2 RA3/AN3/VREF RA4/T0CKI RA5/AN4/SS RAM File Registers 176 x 8 8 Level Stack (13-bit) 4K x 14 8 Data Bus Program Counter EPROM RAM Addr PORTB 9 Addr MUX Instruction reg RB0/INT 7 Direct Addr 8 Indirect Addr RB1-RB7 FSR reg STATUS reg 8 3 Power-up Timer Oscillator Start-up Timer Instruction Decode & Control Power-on Reset Timing Generation PORTC RC0/T1OSO/T1CKI RC1/T1OSI RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO MUX ALU PORTD 8 Watchdog Timer W reg RD0-RD4/SEGnn OSC1/CLKIN OSC2/CLKOUT RD5-RD7/SEGnn/COMn MCLR VDD, VSS PORTE RE0-RE7/SEGnn PORTF RF0-RF7/SEGnn PORTG RG0-RG7/SEGnn Timer0 A/D Timer1, Timer2, CCP1 Synchronous Serial Port LCD © 1996 Microchip Technology Inc. Advance Information COM0 VLCD1 VLCD2 VLCD3 C1 C2 VLCDADJ DS30444B-page 11 PIC16C9XX PIC16C9XX TABLE 3-1: PIC16C9XX PIC16C9XX PINOUT DESCRIPTION DIP Pin# PLCC Pin# TQFP Pin# Pin Type Buffer Type OSC1/CLKIN 22 24 14 I ST/CMOS OSC2/CLKOUT 23 25 15 O - Oscillator crystal output. Connects to crystal or resonator in crystal oscillator mode. In RC mode, OSC2 pin outputs CLKOUT which has 1/4 the frequency of OSC1, and denotes the instruction cycle rate. MCLR/VPP 1 2 57 I/P ST Master clear (reset) input/programming voltage input. This pin is an active low reset to the device. Pin Name Description Oscillator crystal input/external clock source input. This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise. PORTA is a bi-directional I/O port. The AN and VREF multiplexed functions are used by the PIC16C924 PIC16C924 only. RA0/AN0 4 5 60 I/O TTL Analog input0 RA1/AN1 5 6 61 I/O TTL Analog input1 RA2/AN2 7 8 63 I/O TTL Analog input2 RA3/AN3/VREF 8 9 64 I/O TTL Analog input3/A/D Voltage Reference RA4/T0CKI 9 10 1 I/O ST RA4 can also be selected to be the clock input to the Timer0 timer/counter. Output is open drain type. RA5/AN4/SS 10 11 2 I/O TTL RA5 can also be the slave select for the synchronous serial port. PORTB is a bi-directional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs. RB0/INT 12 13 4 I/O TTL/ST RB0 can also be selected as an external interrupt pin. This buffer is a Schmitt Trigger input when configured as an external interrupt. RB1 11 12 3 I/O TTL RB2 3 4 59 I/O TTL RB3 2 3 58 I/O TTL RB4 64 68 56 I/O TTL Interrupt on change pin. RB5 63 67 55 I/O TTL Interrupt on change pin. RB6 61 65 53 I/O TTL/ST Interrupt on change pin. Serial programming clock. This buffer is a Schmitt Trigger input when used in serial programming mode. RB7 62 66 54 I/O TTL/ST Interrupt on change pin. Serial programming data. This buffer is a Schmitt Trigger input when used in serial programming mode. RC0/T1OSO/T1CKI 24 26 16 I/O ST RC0 can also be selected as a Timer1 oscillator output or a Timer1 clock input. RC1/T1OSI 25 27 17 I/O ST RC1 can also be selected as a Timer1 oscillator input. RC2/CCP1 26 28 18 I/O ST RC2 can also be selected as a Capture input/Compare output/PWM output. RC3/SCK/SCL 13 14 5 I/O ST RC3 can also be selected as the synchronous serial clock input/output for both SPI and I2C modes. RC4/SDI/SDA 14 15 6 I/O ST RC4 can also be selected as the SPI Data In (SPI mode) or data I/O (I2C mode). RC5/SDO 15 16 7 I/O ST PORTC is a bi-directional I/O port. Legend: I = input - = Not used DS30444B-page 12 RC5 can also be selected as the SPI Data Out (SPI mode). O = output P = power L = LCD Driver TTL = TTL input ST = Schmitt Trigger input Advance Information © 1996 Microchip Technology Inc. PIC16C9XX PIC16C9XX TABLE 3-1: PIC16C9XX PIC16C9XX PINOUT DESCRIPTION (Cont.'d) DIP Pin# PLCC Pin# TQFP Pin# Pin Type C1 16 22 12 P C2 17 23 13 P LCD Voltage Generation COM0 59 63 51 L Common Driver0 Pin Name Buffer Type Description LCD Voltage Generation PORTD is a digital input/output port. These pins are also used as LCD Segment and/or Common Drivers. Segment Driver00/Digital Input/Output RD0/SEG00 RD0/SEG00 29 31 21 I/O/L ST RD1/SEG01 RD1/SEG01 30 32 22 I/O/L ST Segment Driver01/Digital Input/Output RD2/SEG02 RD2/SEG02 31 33 23 I/O/L ST Segment Driver02/Digital Input/Output RD3/SEG03 RD3/SEG03 32 34 24 I/O/L ST Segment Driver03/Digital Input/Output RD4/SEG04 RD4/SEG04 33 35 25 I/O/L ST Segment Driver04/Digital Input/Output RD5/SEG29/COM3 RD5/SEG29/COM3 56 60 48 I/L ST Segment Driver29/Common Driver3/Digital Input RD6/SEG30/COM2 RD6/SEG30/COM2 57 61 49 I/L ST Segment Driver30/Common Driver2/Digital Input RD7/SEG31/COM1 RD7/SEG31/COM1 58 62 50 I/L ST Segment Driver31/Common Driver1/Digital Input RE0/SEG05 RE0/SEG05 34 37 26 I/L ST PORTE is a digital input or LCD Segment Driver port. Segment Driver05 RE1/SEG06 RE1/SEG06 35 38 27 I/L ST Segment Driver06 RE2/SEG07 RE2/SEG07 36 39 28 I/L ST Segment Driver07 RE3/SEG08 RE3/SEG08 37 40 29 I/L ST Segment Driver08 RE4/SEG09 RE4/SEG09 38 41 30 I/L ST Segment Driver09 RE5/SEG10 RE5/SEG10 39 42 31 I/L ST Segment Driver10 RE6/SEG11 RE6/SEG11 40 43 32 I/L ST Segment Driver11 RE7/SEG27 RE7/SEG27 - 36 - I/L ST Segment Driver27 (Not available on 64-pin devices) PORTF is a digital input or LCD Segment Driver port. Segment Driver12 RF0/SEG12 RF0/SEG12 41 44 33 I/L ST RF1/SEG13 RF1/SEG13 42 45 34 I/L ST Segment Driver13 RF2/SEG14 RF2/SEG14 43 46 35 I/L ST Segment Driver14 RF3/SEG15 RF3/SEG15 44 47 36 I/L ST Segment Driver15 RF4/SEG16 RF4/SEG16 45 48 37 I/L ST Segment Driver16 RF5/SEG17 RF5/SEG17 46 49 38 I/L ST Segment Driver17 RF6/SEG18 RF6/SEG18 47 50 39 I/L ST Segment Driver18 RF7/SEG19 RF7/SEG19 48 51 40 I/L ST Segment Driver19 RG0/SEG20 RG0/SEG20 49 53 41 I/L ST RG1/SEG21 RG1/SEG21 50 54 42 I/L ST Segment Driver21 RG2/SEG22 RG2/SEG22 51 55 43 I/L ST Segment Driver22 RG3/SEG23 RG3/SEG23 52 56 44 I/L ST Segment Driver23 RG4/SEG24 RG4/SEG24 53 57 45 I/L ST Segment Driver24 RG5/SEG25 RG5/SEG25 54 58 46 I/L ST Segment Driver25 RG6/SEG26 RG6/SEG26 55 59 47 I/L ST Segment Driver26 RG7/SEG28 RG7/SEG28 - 52 - I/L ST Segment Driver28 (Not available on 64-pin devices) VLCDADJ 28 30 20 P LCD Voltage Generation AVDD - 21 - P Analog Power VLCD1 27 Legend: I = input - = Not used PORTG is a digital input or LCD Segment Driver port. Segment Driver20 29 19 P LCD Voltage O = output P = power L = LCD Driver TTL = TTL input ST = Schmitt Trigger input © 1996 Microchip Technology Inc. Advance Information DS30444B-page 13 PIC16C9XX PIC16C9XX TABLE 3-1: Pin Name PIC16C9XX PIC16C9XX PINOUT DESCRIPTION (Cont.'d) DIP Pin# PLCC Pin# TQFP Pin# Pin Type Buffer Type Description 18 19 10 P - LCD Voltage VLCD2 VLCD3 19 20 11 P - LCD Voltage VDD 20, 60 22, 64 12, 52 P - Digital power VSS 6, 21 7, 23 13, 62 P - Ground reference NC - 1 - - - Legend: I = input - = Not used DS30444B-page 14 These pins are not internally connected. These pins should be left unconnected. O = output P = power L = LCD Driver TTL = TTL input ST = Schmitt Trigger input Advance Information © 1996 Microchip Technology Inc. PIC16C9XX PIC16C9XX Clocking Scheme/Instruction Cycle 3.1 3.2 The clock input (from OSC1) is internally divided by four to generate four non-overlapping quadrature clocks namely Q1, Q2, Q3 and Q4. Internally, the program counter (PC) is incremented every Q1, the instruction is fetched from the program memory and latched into the instruction register in Q4. The instruction is decoded and executed during the following Q1 through Q4. The clocks and instruction execution flow is shown in Figure 3-3. Instruction Flow/Pipelining An "Instruction Cycle" consists of four Q cycles (Q1, Q2, Q3 and Q4). The instruction fetch and execute are pipelined such that fetch takes one instruction cycle while decode and execute takes another instruction cycle. However, due to the pipelining, each instruction effectively executes in one cycle. If an instruction causes the program counter to change (e.g. GOTO) then two cycles are required to complete the instruction (Example 3-1). A fetch cycle begins with the program counter (PC) incrementing in Q1. In the execution cycle, the fetched instruction is latched into the "Instruction Register" in cycle Q1. This instruction is then decoded and executed during the Q2, Q3, and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination write). FIGURE 3-3: CLOCK/INSTRUCTION CYCLE Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 Q1 Q2 Internal phase clock Q3 Q4 PC OSC2/CLKOUT (RC mode) EXAMPLE 3-1: PC PC+1 Fetch INST (PC) Execute INST (PC-1) PC+2 Fetch INST (PC+1) Execute INST (PC) Fetch INST (PC+2) Execute INST (PC+1) INSTRUCTION PIPELINE FLOW Tcy0 1. MOVLW 55h Tcy1 Fetch 1 Execute 1 2. MOVWF PORTB 3. CALL SUB_1 4. BSF PORTA, BIT3 (Forced NOP) Fetch 2 Tcy2 Tcy3 Tcy4 Tcy5 Execute 2 Fetch 3 Execute 3 Fetch 4 Flush Fetch SUB_1 Execute SUB_1 5. Instruction @ address SUB_1 All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is "flushed" from the pipeline while the new instruction is being fetched and then executed. © 1996 Microchip Technology Inc. Advance Information DS30444B-page 15 PIC16C9XX PIC16C9XX NOTES: DS30444B-page 16 Advance Information © 1996 Microchip Technology Inc. PIC16C9XX PIC16C9XX 4.0 MEMORY ORGANIZATION 4.1 Program Memory Organization The PIC16C9XX PIC16C9XX family has a 13-bit program counter capable of addressing an 8K x 14 program memory space. Only the first 4K x 14 (0000h-0FFFh) is physically implemented. Accessing a location above the physically implemented addresses will cause a wraparound. The reset vector is at 0000h and the interrupt vector is at 0004h. FIGURE 4-1: PROGRAM MEMORY MAP AND STACK PC CALL, RETURN RETFIE, RETLW 13 Data Memory Organization The data memory is partitioned into four Banks which contain the General Purpose Registers and the Special Function Registers. Bits RP1 and RP0 are the bank select bits. RP1:RP0 (STATUS) 11 = Bank 3 (180h-1FFh) 10 = Bank 2 (100h-17Fh) 01 = Bank 1 (80h-FFh) 00 = Bank 0 (00h-7Fh) The lower locations of each Bank are reserved for the Special Function Registers. Above the Special Function Registers are General Purpose Registers implemented as static RAM. All four banks contain special function registers. Some "high use" special function registers are mirrored in other banks for code reduction and quicker access. 4.2.1 Stack Level 1 GENERAL PURPOSE REGISTER FILE The register file can be accessed either directly, or indirectly through the File Select Register FSR (Section 4.5). Stack Level 8 The following General Purpose Registers are not physically implemented: Reset Vector 0000h Interrupt Vector 0004h 0005h On-chip Program Memory (Page 0) 4.2 · F0h-FFh of Bank 1 · 170h-17Fh of Bank 2 · 1F0h-1FFh of Bank 3 These locations are used for common access across banks. 07FFh On-chip Program Memory (Page 1) 0800h 0FFFh 1000h 1FFFh © 1996 Microchip Technology Inc. Advance Information This document was created with FrameMaker 4 0 4 DS30444B-page 17 PIC16C9XX PIC16C9XX FIGURE 4-2: REGISTER FILE MAP File Address Indirect addr.(1) TMR0 PCL STATUS FSR PORTA PORTB PORTC PORTD PORTE PCLATH INTCON PIR1 TMR1L TMR1H T1CON TMR2 T2CON SSPBUF SSPCON CCPR1L CCPR1H CCP1CON ADRES(2) ADCON0(2) 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h Indirect addr.(1) 80h 81h OPTION 82h PCL 83h STATUS 84h FSR 85h TRISA 86h TRISB 87h TRISC TRISD 88h TRISE 89h 8Ah PCLATH 8Bh INTCON 8Ch PIE1 8Dh 8Eh PCON 8Fh 90h 91h 92h PR2 93h SSPADD 94h SSPSTAT 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh ADCON1(2) A0h Indirect addr.(1) 100h 101h TMR0 102h PCL 103h STATUS 104h FSR 105h 106h PORTB 107h PORTF 108h PORTG 109h 10Ah PCLATH 10Bh INTCON 10Ch 10Dh LCDSE 10Eh LCDPS 10Fh LCDCON 110h LCDD00 LCDD00 111h LCDD01 LCDD01 112h LCDD02 LCDD02 113h LCDD03 LCDD03 114h LCDD04 LCDD04 115h LCDD05 LCDD05 116h LCDD06 LCDD06 117h LCDD07 LCDD07 118h LCDD08 LCDD08 119h LCDD09 LCDD09 11Ah LCDD10 LCDD10 11Bh LCDD11 LCDD11 11Ch LCDD12 LCDD12 11Dh LCDD13 LCDD13 11Eh LCDD14 LCDD14 11Fh LCDD15 LCDD15 120h EFh 7Fh Mapped in Bank 0 70h-7Fh Bank 1 Note DS30444B-page 18 File Address File Address Indirect addr.(1) OPTION PCL STATUS FSR TRISB TRISF TRISG PCLATH INTCON 180h 181h 182h 183h 184h 185h 186h 187h 188h 189h 18Ah 18Bh 18Ch 18Dh 18Eh 18Fh 190h 191h 192h 193h 194h 195h 196h 197h 198h 199h 19Ah 19Bh 19Ch 19Dh 19Eh 19Fh 1A0h General Purpose Register General Purpose Register Bank 0 File Address F0h FFh Mapped in Bank 0 70h-7Fh Bank 2 16F 170 17F 1EFh Mapped in Bank 0 70h-7Fh 1F0h 1FFh Bank 3 Unimplemented data memory locations, read as '0'. 1: Not a physical register. 2: These registers are not implemented on the PIC16C923 PIC16C923. Advance Information © 1996 Microchip Technology Inc. PIC16C9XX PIC16C9XX 4.2.2 SPECIAL FUNCTION REGISTERS The Special Function Registers are registers used by the CPU and Peripheral Modules for controlling the desired operation of the device. These registers are implemented as static RAM. TABLE 4-1: Address Name The special function registers can be classified into two sets (core and peripheral). Those registers associated with the "core" functions are described in this section, and those related to the operation of the peripheral features are described in the section of that peripheral feature. SPECIAL FUNCTION REGISTER SUMMARY Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Power-on Reset Value on all other resets 0000 0000 Bank 0 00h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 01h TMR0 Timer0 module's register xxxx xxxx uuuu uuuu 02h PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000 03h STATUS 04h FSR 05h PORTA 06h PORTB 07h PORTC 08h PORTD 09h PORTE 0Ah PCLATH IRP RP1 RP0 TO PD Z DC C 0001 1xxx 000q quuu xxxx xxxx uuuu uuuu (4) (4) xxxx xxxx uuuu uuuu -xx xxxx -uu uuuu PORTD Data Latch when written: PORTD pins when read 0000 0000 0000 0000 PORTE pins when read 0000 0000 0000 0000 -0 0000 -0 0000 Indirect data memory address pointer 0Bh INTCON 0Ch PIR1 - - PORTA Data Latch when written: PORTA pins when read PORTB Data Latch when written: PORTB pins when read - - - PORTC Data Latch when written: PORTC pins when read - - Write Buffer for the upper 5 bits of the Program Counter GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u LCDIF ADIF(2) - - SSPIF CCP1IF TMR2IF TMR1IF 00- 0000 00- 0000 0Dh - 0Eh TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register 0Fh TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 register 10h T1CON 11h TMR2 12h T2CON 13h SSPBUF 14h SSPCON 15h CCPR1L Capture/Compare/PWM Register (LSB) Capture/Compare/PWM Register (MSB) 16h CCPR1H 17h CCP1CON Unimplemented - - - T1CKPS0 T1OSCEN xxxx xxxx TMR1CS TMR1ON Timer2 module's register - TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 Synchronous Serial Port Receive Buffer/Transmit Register WCOL SSPOV - - SSPEN CCP1X CKP SSPM3 SSPM2 SSPM1 SSPM0 uuuu uuuu -00 0000 -uu uuuu 0000 0000 -000 0000 -000 0000 xxxx xxxx T1SYNC uuuu uuuu 0000 0000 T1CKPS1 - xxxx xxxx uuuu uuuu 0000 0000 0000 0000 xxxx xxxx uuuu uuuu xxxx xxxx CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 uuuu uuuu -00 0000 -00 0000 18h - Unimplemented - - 19h - Unimplemented - - 1Ah - Unimplemented - - 1Bh - Unimplemented - - 1Ch - Unimplemented - - 1Dh - Unimplemented - - xxxx xxxx uuuu uuuu 0000 00-0 0000 00-0 1Eh(1) ADRES 1Fh(1) ADCON0 Legend: Note 1: 2: 3: 4: A/D Result Register ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE - ADON x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0', shaded locations are unimplemented, read as `0'. Registers ADRES, ADCON0, and ADCON1 are not implemented in the PIC16C923 PIC16C923, read as '0'. These bits are reserved on the PIC16C923 PIC16C923, always maintain these bits clear. These pixels do not display, but can be used as general purpose RAM. PIC16C923 PIC16C923 reset values for PORTA: -xx xxxx for a POR, and -uu uuuu for all other resets, PIC16C924 PIC16C924 reset values for PORTA: -0x 0000 for a POR, and -0u 0000 for all other resets. © 1996 Microchip Technology Inc. Advance Information DS30444B-page 19 PIC16C9XX PIC16C9XX TABLE 4-1: Address Name SPECIAL FUNCTION REGISTER SUMMARY (Cont.'d) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Power-on Reset Value on all other resets Bank 1 80h INDF 81h OPTION 82h PCL 83h STATUS 84h FSR 85h TRISA 86h TRISB 87h TRISC 88h TRISD 89h TRISE 8Ah PCLATH Addressing this location uses contents of FSR to address data memory (not a physical register) RBPU INTEDG T0CS PSA PS2 PS1 PS0 PD Z DC C Program Counter's (PC) Least Significant Byte IRP RP1 RP0 TO 8Bh INTCON PIE1 8Dh - 8Eh PCON 8Fh - 90h - 91h - 0000 0000 1111 1111 0000 0000 0001 1xxx 000q quuu xxxx xxxx uuuu uuuu -11 1111 -11 1111 1111 1111 1111 1111 -11 1111 -11 1111 PORTD Data Direction Register 1111 1111 1111 1111 PORTE Data Direction Register 1111 1111 1111 1111 -0 0000 -0 0000 Indirect data memory address pointer 8Ch 0000 0000 1111 1111 0000 0000 T0SE - - PORTA Data Direction Register PORTB Data Direction Register - - - PORTC Data Direction Register - - Write Buffer for the upper 5 bits of the PC GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u LCDIE ADIE(2) - - SSPIE CCP1IE TMR2IE TMR1IE 00- 0000 00- 0000 Unimplemented - - - -0- - -u- Unimplemented - - Unimplemented - - Unimplemented - - 1111 1111 1111 1111 - - - - 92h PR2 SSPADD SSPSTAT POR - Synchronous Serial Port (I2C mode) Address Register 94h - Timer2 Period Register 93h - SMP CKE D/A P 0000 0000 S R/W UA BF 0000 0000 0000 0000 0000 0000 95h - Unimplemented - - 96h - Unimplemented - - 97h - Unimplemented - - 98h - Unimplemented - - 99h - Unimplemented - - 9Ah - Unimplemented - - 9Bh - Unimplemented - - 9Ch - Unimplemented - - 9Dh - Unimplemented - - 9Eh - Unimplemented - - - -000 - -000 9Fh(1) ADCON1 Legend: Note 1: 2: 3: 4: - - - - - PCFG2 PCFG1 PCFG0 x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0', shaded locations are unimplemented, read as `0'. Registers ADRES, ADCON0, and ADCON1 are not implemented in the PIC16C923 PIC16C923, read as '0'. These bits are reserved on the PIC16C923 PIC16C923, always maintain these bits clear. These pixels do not display, but can be used as general purpose RAM. PIC16C923 PIC16C923 reset values for PORTA: -xx xxxx for a POR, and -uu uuuu for all other resets, PIC16C924 PIC16C924 reset values for PORTA: -0x 0000 for a POR, and -0u 0000 for all other resets. DS30444B-page 20 Advance Information © 1996 Microchip Technology Inc. PIC16C9XX PIC16C9XX TABLE 4-1: Address Name SPECIAL FUNCTION REGISTER SUMMARY (Cont.'d) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Power-on Reset Value on all other resets Bank 2 100h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000 101h TMR0 Timer0 module's register xxxx xxxx uuuu uuuu 102h PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000 103h STATUS 0001 1xxx 000q quuu 104h FSR xxxx xxxx uuuu uuuu 105h IRP RP1 RP0 TO PD Z DC C Indirect data memory address pointer - Unimplemented - - 106h PORTB PORTB Data Latch when written: PORTB pins when read xxxx xxxx uuuu uuuu 107h PORTF PORTF pins when read 0000 0000 0000 0000 108h PORTG PORTG pins when read 0000 0000 0000 0000 109h - 10Ah PCLATH 10Bh INTCON 10Ch - 10Dh LCDSE Unimplemented - - - - GIE PEIE T0IE INTE RBIE T0IF INTF RBIF Unimplemented SE29 - -0 0000 Write Buffer for the upper 5 bits of the PC -0 0000 0000 000x 0000 000u - SE27 SE20 SE16 SE12 SE9 SE5 - SE0 1111 1111 1111 1111 10Eh LCDPS - - - - LP3 LP2 LP1 LP0 - 0000 - 0000 10Fh LCDCON LCDEN SLPEN - VGEN CS1 CS0 LMUX1 LMUX0 00-0 0000 00-0 0000 110h LCDD00 LCDD00 SEG07 SEG07 COM0 SEG06 SEG06 COM0 SEG05 SEG05 COM0 SEG04 SEG04 COM0 SEG03 SEG03 COM0 SEG02 SEG02 COM0 SEG01 SEG01 COM0 SEG00 SEG00 COM0 xxxx xxxx uuuu uuuu 111h LCDD01 LCDD01 SEG15 SEG15 COM0 SEG14 SEG14 COM0 SEG13 SEG13 COM0 SEG12 SEG12 COM0 SEG11 SEG11 COM0 SEG10 SEG10 COM0 SEG09 SEG09 COM0 SEG08 SEG08 COM0 xxxx xxxx uuuu uuuu 112h LCDD02 LCDD02 SEG23 SEG23 COM0 SEG22 SEG22 COM0 SEG21 SEG21 COM0 SEG20 SEG20 COM0 SEG19 SEG19 COM0 SEG18 SEG18 COM0 SEG17 SEG17 COM0 SEG16 SEG16 COM0 xxxx xxxx uuuu uuuu 113h LCDD03 LCDD03 SEG31 SEG31 COM0 SEG30 SEG30 COM0 SEG29 SEG29 COM0 SEG28 SEG28 COM0 SEG27 SEG27 COM0 SEG26 SEG26 COM0 SEG25 SEG25 COM0 SEG24 SEG24 COM0 xxxx xxxx uuuu uuuu 114h LCDD04 LCDD04 SEG07 SEG07 COM1 SEG06 SEG06 COM1 SEG05 SEG05 COM1 SEG04 SEG04 COM1 SEG03 SEG03 COM1 SEG02 SEG02 COM1 SEG01 SEG01 COM1 SEG00 SEG00 COM1 xxxx xxxx uuuu uuuu 115h LCDD05 LCDD05 SEG15 SEG15 COM1 SEG14 SEG14 COM1 SEG13 SEG13 COM1 SEG12 SEG12 COM1 SEG11 SEG11 COM1 SEG10 SEG10 COM1 SEG09 SEG09 COM1 SEG08 SEG08 COM1 xxxx xxxx uuuu uuuu 116h LCDD06 LCDD06 SEG23 SEG23 COM1 SEG22 SEG22 COM1 SEG21 SEG21 COM1 SEG20 SEG20 COM1 SEG19 SEG19 COM1 SEG18 SEG18 COM1 SEG17 SEG17 COM1 SEG16 SEG16 COM1 xxxx xxxx uuuu uuuu 117h LCDD07 LCDD07 SEG31 SEG31 COM1(3) SEG30 SEG30 COM1 SEG29 SEG29 COM1 SEG28 SEG28 COM1 SEG27 SEG27 COM1 SEG26 SEG26 COM1 SEG25 SEG25 COM1 SEG24 SEG24 COM1 xxxx xxxx uuuu uuuu 118h LCDD08 LCDD08 SEG07 SEG07 COM2 SEG06 SEG06 COM2 SEG05 SEG05 COM2 SEG04 SEG04 COM2 SEG03 SEG03 COM2 SEG02 SEG02 COM2 SEG01 SEG01 COM2 SEG00 SEG00 COM2 xxxx xxxx uuuu uuuu 119h LCDD09 LCDD09 SEG15 SEG15 COM2 SEG14 SEG14 COM2 SEG13 SEG13 COM2 SEG12 SEG12 COM2 SEG11 SEG11 COM2 SEG10 SEG10 COM2 SEG09 SEG09 COM2 SEG08 SEG08 COM2 xxxx xxxx uuuu uuuu 11Ah LCDD10 LCDD10 SEG23 SEG23 COM2 SEG22 SEG22 COM2 SEG21 SEG21 COM2 SEG20 SEG20 COM2 SEG19 SEG19 COM2 SEG18 SEG18 COM2 SEG17 SEG17 COM2 SEG16 SEG16 COM2 xxxx xxxx uuuu uuuu 11Bh LCDD11 LCDD11 SEG31 SEG31 COM2(3) SEG30 SEG30 COM2(3) SEG29 SEG29 COM2 SEG28 SEG28 COM2 SEG27 SEG27 COM2 SEG26 SEG26 COM2 SEG25 SEG25 COM2 SEG24 SEG24 COM2 xxxx xxxx uuuu uuuu 11Ch LCDD12 LCDD12 SEG07 SEG07 COM3 SEG06 SEG06 COM3 SEG05 SEG05 COM3 SEG04 SEG04 COM3 SEG03 SEG03 COM3 SEG02 SEG02 COM3 SEG01 SEG01 COM3 SEG00 SEG00 COM3 xxxx xxxx uuuu uuuu 11Dh LCDD13 LCDD13 SEG15 SEG15 COM3 SEG14 SEG14 COM3 SEG13 SEG13 COM3 SEG12 SEG12 COM3 SEG11 SEG11 COM3 SEG10 SEG10 COM3 SEG09 SEG09 COM3 SEG08 SEG08 COM3 xxxx xxxx uuuu uuuu 11Eh LCDD14 LCDD14 SEG23 SEG23 COM3 SEG22 SEG22 COM3 SEG21 SEG21 COM3 SEG20 SEG20 COM3 SEG19 SEG19 COM3 SEG18 SEG18 COM3 SEG17 SEG17 COM3 SEG16 SEG16 COM3 xxxx xxxx uuuu uuuu 11Fh LCDD15 LCDD15 SEG31 SEG31 COM3(3) SEG30 SEG30 COM3(3) SEG29 SEG29 COM3(3) SEG28 SEG28 COM3 SEG27 SEG27 COM3 SEG26 SEG26 COM3 SEG25 SEG25 COM3 SEG24 SEG24 COM3 xxxx xxxx uuuu uuuu Legend: Note 1: 2: 3: 4: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0', shaded locations are unimplemented, read as `0'. Registers ADRES, ADCON0, and ADCON1 are not implemented in the PIC16C923 PIC16C923, read as '0'. These bits are reserved on the PIC16C923 PIC16C923, always maintain these bits clear. These pixels do not display, but can be used as general purpose RAM. PIC16C923 PIC16C923 reset values for PORTA: -xx xxxx for a POR, and -uu uuuu for all other resets, PIC16C924 PIC16C924 reset values for PORTA: -0x 0000 for a POR, and -0u 0000 for all other resets. © 1996 Microchip Technology Inc. Advance Information DS30444B-page 21 PIC16C9XX PIC16C9XX TABLE 4-1: Address Name SPECIAL FUNCTION REGISTER SUMMARY (Cont.'d) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Power-on Reset Value on all other resets Bank 3 180h INDF 181h OPTION 182h PCL 183h STATUS 184h FSR Addressing this location uses contents of FSR to address data memory (not a physical register) RBPU INTEDG T0CS PS2 PS1 PS0 PD Z DC C Program Counter's (PC) Least Significant Byte IRP RP1 RP0 TO Indirect data memory address pointer 185h - 186h TRISB 187h 188h 189h - 0000 0000 1111 1111 0000 0000 0001 1xxx 000q quuu uuuu uuuu - - PORTB Data Direction Register 1111 1111 1111 1111 TRISF PORTF Data Direction Register 1111 1111 1111 1111 TRISG PORTG Data Direction Register 1111 1111 1111 1111 18Ah PCLATH 18Bh INTCON Unimplemented 0000 0000 0000 0000 PSA 1111 1111 xxxx xxxx T0SE Unimplemented - - - - GIE PEIE T0IE INTE RBIE T0IF INTF RBIF - -0 0000 Write Buffer for the upper 5 bits of the PC -0 0000 0000 000x 0000 000u 18Ch - Unimplemented - - 18Dh - Unimplemented - - 18Eh - Unimplemented - - 18Fh - Unimplemented - - 190h - Unimplemented - - 191h - Unimplemented - - 192h - Unimplemented - - 193h - Unimplemented - - 194h - Unimplemented - - 195h - Unimplemented - - 196h - Unimplemented - - 197h - Unimplemented - - 198h - Unimplemented - - 199h - Unimplemented - - 19Ah - Unimplemented - - 19Bh - Unimplemented - - 19Ch - Unimplemented - - 19Dh - Unimplemented - - 19Eh - Unimplemented - - 19Fh - Unimplemented - - Legend: Note 1: 2: 3: 4: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0', shaded locations are unimplemented, read as `0'. Registers ADRES, ADCON0, and ADCON1 are not implemented in the PIC16C923 PIC16C923, read as '0'. These bits are reserved on the PIC16C923 PIC16C923, always maintain these bits clear. These pixels do not display, but can be used as general purpose RAM. PIC16C923 PIC16C923 reset values for PORTA: -xx xxxx for a POR, and -uu uuuu for all other resets, PIC16C924 PIC16C924 reset values for PORTA: -0x 0000 for a POR, and -0u 0000 for all other resets. DS30444B-page 22 Advance Information © 1996 Microchip Technology Inc. PIC16C9XX PIC16C9XX 4.2.2.1 It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the STATUS register because these instructions do not affect the Z, C or DC bits from the STATUS register. For other instructions, not affecting any status bits, see the "Instruction Set Summary." STATUS REGISTER The STATUS register, shown in Figure 4-3, contains the arithmetic status of the ALU, the RESET status and the bank select bits for data memory. The STATUS register can be the destination for any instruction, as with any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not writable. Therefore, the result of an instruction with the STATUS register as destination may be different than intended. Note 1: The C and DC bits operate as a borrow and digit borrow bit, respectively, in subtraction. See the SUBLW and SUBWF instructions for examples. For example, CLRF STATUS will clear the upper-three bits and set the Z bit. This leaves the STATUS register as 000u u1uu (where u = unchanged). FIGURE 4-3: R/W-0 IRP STATUS REGISTER (ADDRESS 03h, 83h, 103h, 183h) R/W-0 RP1 R/W-0 RP0 R-1 TO R-1 PD R/W-x Z R/W-x DC bit7 bit 7: R/W-x C bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR reset IRP: Register Bank Select bit (used for indirect addressing) 1 = Bank 2, 3 (100h - 1FFh) 0 = Bank 0, 1 (00h - FFh) bit 6-5: RP1:RP0: Register Bank Select bits (used for direct addressing) 11 = Bank 3 (180h - 1FFh) 10 = Bank 2 (100h - 17Fh) 01 = Bank 1 (80h - FFh) 00 = Bank 0 (00h - 7Fh) bit 4: TO: Time-out bit 1 = After power-up, CLRWDT instruction, or SLEEP instruction 0 = A WDT time-out occurred bit 3: PD: Power-down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction bit 2: Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero bit 1: DC: Digit carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) (for borrow the polarity is reversed) 1 = A carry-out from the 4th low order bit of the result occurred 0 = No carry-out from the 4th low order bit of the result bit 0: C: Carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) (for borrow the polarity is reversed) 1 = A carry-out from the most significant bit of the result occurred 0 = No carry-out from the most significant bit of the result occurred Note: A subtraction is executed by adding the two's complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of the source register. © 1996 Microchip Technology Inc. Advance Information DS30444B-page 23 PIC16C9XX PIC16C9XX 4.2.2.2 OPTION REGISTER Note: The OPTION register is a readable and writable register which contains various control bits to configure the TMR0/WDT prescaler, the external INT interrupt, TMR0, and the weak pull-ups on PORTB. FIGURE 4-4: To achieve a 1:1 prescaler assignment for the TMR0 register, assign the prescaler to the Watchdog Timer. OPTION REGISTER (ADDRESS 81h, 181h) R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 bit7 bit0 bit 7: RBPU: PORTB Pull-up Enable bit 1 = PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values bit 6: INTEDG: Interrupt Edge Select bit 1 = Interrupt on rising edge of RB0/INT pin 0 = Interrupt on falling edge of RB0/INT pin bit 5: T0CS: TMR0 Clock Source Select bit 1 = Transition on RA4/T0CKI pin 0 = Internal instruction cycle clock (CLKOUT) bit 4: T0SE: TMR0 Source Edge Select bit 1 = Increment on high-to-low transition on RA4/T0CKI pin 0 = Increment on low-to-high transition on RA4/T0CKI pin bit 3: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR reset PSA: Prescaler Assignment bit 1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the Timer0 module bit 2-0: PS2:PS0: Prescaler Rate Select bits Bit Value 000 001 010 011 100 101 110 111 DS30444B-page 24 TMR0 Rate 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 WDT Rate 1:1 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 Advance Information © 1996 Microchip Technology Inc. PIC16C9XX PIC16C9XX 4.2.2.3 INTCON REGISTER Note: The INTCON Register is a readable and writable register which contains various enable and flag bits for the TMR0 register overflow, RB Port change and external RB0/INT pin interrupts. FIGURE 4-5: Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON). INTCON REGISTER (ADDRESS 0Bh, 8Bh, 10Bh, 18Bh) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x GIE PEIE T0IE INTE RBIE T0IF INTF RBIF bit7 bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR reset bit 7: GIE: Global Interrupt Enable bit 1 = Enables all un-masked interrupts 0 = Disables all interrupts bit 6: PEIE: Peripheral Interrupt Enable bit 1 = Enables all un-masked peripheral interrupts 0 = Disables all peripheral interrupts bit 5: T0IE: TMR0 Overflow Interrupt Enable bit 1 = Enables the TMR0 interrupt 0 = Disables the TMR0 interrupt bit 4: INTE: RB0/INT External Interrupt Enable bit 1 = Enables the RB0/INT external interrupt 0 = Disables the RB0/INT external interrupt bit 3: RBIE: RB Port Change Interrupt Enable bit 1 = Enables the RB port change interrupt 0 = Disables the RB port change interrupt bit 2: T0IF: TMR0 Overflow Interrupt Flag bit 1 = TMR0 register has overflowed (must be cleared in software) 0 = TMR0 register did not overflow bit 1: INTF: RB0/INT External Interrupt Flag bit 1 = The RB0/INT external interrupt occurred (must be cleared in software) 0 = The RB0/INT external interrupt did not occur bit 0: RBIF: RB Port Change Interrupt Flag bit 1 = When at least one of the RB7:RB4 pins changed state (see Section 5.2 to clear interrupt) 0 = None of the RB7:RB4 pins have changed state © 1996 Microchip Technology Inc. Advance Information DS30444B-page 25 PIC16C9XX PIC16C9XX 4.2.2.4 PIE1 REGISTER Note: This register contains the individual enable bits for the peripheral interrupts. FIGURE 4-6: Bit PEIE (INTCON) must be set to enable any peripheral interrupt. PIE1 REGISTER (ADDRESS 8Ch) R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 LCDIE ADIE(1) - - SSPIE CCP1IE TMR2IE TMR1IE bit7 bit0 bit 7: LCDIE: LCD Interrupt Enable bit 1 = Enables the LCD interrupt 0 = Disables the LCD interrupt bit 6: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR reset ADIE: A/D Converter Interrupt Enable bit(1) 1 = Enables the A/D converter interrupt 0 = Disables the A/D converter interrupt bit 5-4: Unimplemented: Read as '0' bit 3: SSPIE: Synchronous Serial Port Interrupt Enable bit 1 = Enables the SSP interrupt 0 = Disables the SSP interrupt bit 2: CCP1IE: CCP1 Interrupt Enable bit 1 = Enables the CCP1 interrupt 0 = Disables the CCP1 interrupt bit 1: TMR2IE: TMR2 to PR2 Match Interrupt Enable bit 1 = Enables the TMR2 to PR2 match interrupt 0 = Disables the TMR2 to PR2 match interrupt bit 0: TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt Note 1: Bit ADIE is reserved on the PIC16C923 PIC16C923, always maintain this bit clear. DS30444B-page 26 Advance Information © 1996 Microchip Technology Inc. PIC16C9XX PIC16C9XX 4.2.2.5 PIR1 REGISTER Note: This register contains the individual flag bits for the peripheral interrupts. FIGURE 4-7: Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. PIR1 REGISTER (ADDRESS 0Ch) R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 LCDIF ADIF(1) - - SSPIF CCP1IF TMR2IF TMR1IF bit7 bit0 bit 7: LCDIF: LCD Interrupt Flag bit 1 = LCD interrupt occurred (must be cleared in software) 0 = LCD interrupt did not occur bit 6: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR reset ADIF: A/D Converter Interrupt Flag bit(1) 1 = An A/D conversion completed (must be cleared in software) 0 = The A/D conversion is not complete bit 5-4: Unimplemented: Read as '0' bit 3: SSPIF: Synchronous Serial Port Interrupt Flag bit 1 = The transmission/reception is complete (must be cleared in software) 0 = Waiting to transmit/receive bit 2: CCP1IF: CCP1 Interrupt Flag bit Capture Mode 1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred Compare Mode 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred PWM Mode Unused in this mode bit 1: TMR2IF: TMR2 to PR2 Match Interrupt Flag bit 1 = TMR2 to PR2 match occurred (must be cleared in software) 0 = No TMR2 to PR2 match occurred bit 0: TMR1IF: TMR1 Overflow Interrupt Flag bit 1 = TMR1 register overflowed (must be cleared in software) 0 = TMR1 register did not overflow Note 1: Bit ADIF is reserved on the PIC16C923 PIC16C923, always maintain this bit clear. © 1996 Microchip Technology Inc. Advance Information DS30444B-page 27 PIC16C9XX PIC16C9XX 4.2.2.6 For various reset conditions see Table 14-4 and Table 14-5. PCON REGISTER The Power Control (PCON) register contains a flag bit to allow differentiation between a Power-on Reset (POR) to an external MCLR Reset or WDT Reset. FIGURE 4-8: PCON REGISTER (ADDRESS 8Eh) U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 U-0 - - - - - - POR - bit7 bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR reset bit 7-2: Unimplemented: Read as '0' bit 1: POR: Power-on Reset Status bit 1 = No Power-on Reset occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) bit 0: Unimplemented: Read as '0' DS30444B-page 28 Advance Information © 1996 Microchip Technology Inc. PIC16C9XX PIC16C9XX 4.3 PCL and PCLATH The program counter (PC) is 13-bits wide. The low byte comes from the PCL register, which is a readable and writable register. The high byte (PC) is not directly readable or writable and comes from PCLATH. On any reset, the PC is cleared. Figure 4-9 shows the two situations for the loading of the PC. The upper example in the figure shows how the PC is loaded on a write to PCL (PCLATH PCH). The lower example in the figure shows how the PC is loaded during a CALL or GOTO instruction (PCLATH PCH). FIGURE 4-9: LOADING OF PC IN DIFFERENT SITUATIONS PCH PCL 12 8 7 0 PC 5 8 PCLATH Instruction with PCL as Destination ALU result PCLATH PCH 12 11 10 PCL 8 0 7 PC GOTO, CALL 2 PCLATH 11 Opcode PCLATH 4.3.1 COMPUTED GOTO Note 1: There are no status bits to indicate stack overflow or stack underflow conditions. Note 2: There are no instructions/mnemonics called PUSH or POP. These are actions that occur from the execution of the CALL, RETURN, RETLW, and RETFIE instructions, or the vectoring to an interrupt address. 4.4 Program Memory Paging The PIC16C9XX PIC16C9XX has 4K of program memory, but the CALL and GOTO instructions only have a 11-bit address range. This 11-bit address range allows a branch within a 2K program memory page size. To allow CALL and GOTO instructions to address the entire 4K program memory address range, there must be another bit to specify the program memory page. This paging bit comes from the PCLATH bit (Figure 4-9). When doing a CALL or GOTO instruction, the user must ensure that this page bit (PCLATH) is programmed so that the desired program memory page is addressed. If a return from a CALL instruction (or interrupt) is executed, the entire 13-bit PC is PUSHed onto the stack. Therefore, manipulation of the PCLATH is not required for the return instructions (which POPs the address from the stack). Note 1: The PIC16C9XX PIC16C9XX ignores paging bit (PCLATH), which is used to access program memory pages 2 and 3 (1000h 1FFFh). The use of PCLATH as a general purpose read/write bit is not recommended since this may affect upward compatibility with future products. A computed GOTO is accomplished by adding an offset to the program counter (ADDWF PCL). When doing a table read using a computed GOTO method, care should be exercised if the table location crosses a PCL memory boundary (each 256 byte block). Refer to the application note "Implementing a Table Read" (AN556 AN556). 4.3.2 STACK The PIC16CXX PIC16CXX family has an 8 level deep x 13-bit wide hardware stack. The stack space is not part of either program or data space and the stack pointer is not readable or writable. The PC is PUSHed onto the stack when a CALL instruction is executed or an interrupt causes a branch. The stack is POPed in the event of a RETURN, RETLW or a RETFIE instruction execution. PCLATH is not affected by a PUSH or POP operation. The stack operates as a circular buffer. This means that after the stack has been PUSHed eight times, the ninth push overwrites the value that was stored from the first push. The tenth push overwrites the second push (and so on). © 1996 Microchip Technology Inc. Advance Information DS30444B-page 29 PIC16C9XX PIC16C9XX Example 4-1 shows the calling of a subroutine in page 1 of the program memory. This example assumes that PCLATH is saved and restored by the interrupt service routine (if interrupts are used). 4.5 EXAMPLE 4-1: Indirect addressing is possible by using the INDF register. Any instruction using the INDF register actually accesses the register pointed to by the File Select Register (FSR). Reading the INDF register itself indirectly (FSR = '0') will produce 00h. Writing to the INDF register indirectly results in a no-operation (although status bits may be affected). An effective 9-bit address is obtained by concatenating the 8-bit FSR register and the IRP bit (STATUS), as shown in Figure 4-10. ORG 0x500 BSF PCLATH,3 CALL SUB1_P1 : : : ORG 0x900 SUB1 P1: : : RETURN Indirect Addressing, INDF and FSR Registers The INDF register is not a physical register. Addressing the INDF register will cause indirect addressing. CALL OF A SUBROUTINE IN PAGE 1 FROM PAGE 0 ;Select page 1 (800h-FFFh) ;Call subroutine in ;page 1 (800h-FFFh) ;called subroutine ;page 1 (800h-FFFh) A simple program to clear RAM locations 20h-2Fh using indirect addressing is shown in Example 4-2. ;return to Call subroutine ;in page 0 (000h-7FFh) EXAMPLE 4-2: movlw movwf clrf incf btfss goto NEXT INDIRECT ADDRESSING 0x20 FSR INDF FSR,F FSR,4 NEXT ;initialize pointer ;to RAM ;clear INDF register ;inc pointer ;all done? ;no clear next CONTINUE : ;yes continue FIGURE 4-10: DIRECT/INDIRECT ADDRESSING Direct Addressing from opcode RP1:RP0 6 bank select Indirect Addressing location select 0 IRP 7 bank select 00 01 10 FSR register 0 location select 11 00h 00h Data Memory 7Fh 7Fh Bank 0 Bank 1 Bank 2 Bank 3 For memory map detail see Figure 4-2. DS30444B-page 30 Advance Information © 1996 Microchip Technology Inc. PIC16C9XX PIC16C9XX 5.0 PORTS For the PIC16C924 PIC16C924 only, other PORTA pins are multiplexed with analog inputs and the analog VREF input. The operation of each pin is selected by clearing/setting the control bits in the ADCON1 register (A/D Control Register1). Some pins for these ports are multiplexed with an alternate function for the peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used in its normal pin function. Note: 5.1 PORTA and TRISA Register On a Power-on Reset, these pins are configured as analog inputs and read as '0'. The RA4/T0CKI pin is a Schmitt Trigger input and an open drain output. All other RA port pins have TTL input levels and full CMOS output drivers. All RA pins have data direction bits (TRISA register) which can configure these pins as output or input. The TRISA register controls the direction of the RA pins, even when they are being used as analog inputs. The user must ensure the bits in the TRISA register are maintained set when using them as analog inputs. Setting a bit in the TRISA register puts the corresponding output driver in a hi-impedance mode. Clearing a bit in the TRISA register puts the contents of the output latch on the selected pin. EXAMPLE 5-1: INITIALIZING PORTA CLRF BCF BSF MOVLW MOVWF Reading the PORTA register reads the status of the pins whereas writing to it will write to the port latch. All write operations are read-modify-write operations. Therefore, a write to a port implies that the port pins are read, this value is modified, and then written to the port data latch. PORTA STATUS, RP1 STATUS, RP0 0xCF TRISA ; ; ; ; ; ; ; ; ; ; Initialize PORTA Select Bank 1 Value used to initialize data direction Set RA as inputs RA as outputs RA are always read as '0'. Pin RA4 is multiplexed with the Timer0 module clock input to become the RA4/T0CKI pin. FIGURE 5-1: BLOCK DIAGRAM OF PINS RA3:RA0 AND RA5 Data bus D Q VDD WR PORT Q CK P Data Latch I/O pin(2) D WR TRIS Q CK Q N VSS Analog(1) input mode TRIS Latch TTL input buffer RD TRIS Q D EN EN RD PORT To A/D Converter(1) Note 1: These functions are enabled on the PIC16C924 PIC16C924 only. 2: I/O pin has protection diodes to VDD and VSS. © 1996 Microchip Technology Inc. Advance Information This document was created with FrameMaker 4 0 4 DS30444B-page 31 PIC16C9XX PIC16C9XX FIGURE 5-2: BLOCK DIAGRAM OF RA4/T0CKI PIN Data Bus D CK WR PORT Q Q RA4/T0CKI pin N Data Latch VSS D CK WR TRIS Q Q ST buffer TRIS Latch RD TRIS Q D EN EN RD PORT TMR0 clock input Note: I/O pin has protection diodes to VSS only. TABLE 5-1: Name PORTA FUNCTIONS Bit# Buffer Function RA0/AN0(1) bit0 TTL Input/output or analog input (1) RA1/AN1 bit1 TTL Input/output or analog input RA2/AN2(1) bit2 TTL Input/output or analog input RA3/AN3/VREF(1) bit3 TTL Input/output or analog input/VREF RA4/T0CKI bit4 ST Input/output or external clock input for Timer0 Output is open drain type RA5/AN4/SS (1) bit5 TTL Input/output or slave select input for synchronous serial port, or analog input Legend: TTL = TTL input, ST = Schmitt Trigger input Note 1: The AN and VREF functions are for the A/D module and are only implemented on the PIC16C924 PIC16C924. TABLE 5-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Power-on Reset Value on all other resets PORTA - - RA5 RA4 RA3 RA2 RA1 RA0 (2) (2) 85h TRISA - - TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 -11 1111 -11 1111 9Fh(1) ADCON1 - - - - - PCFG2 PCFG1 PCFG0 - -000 - -000 Address Name 05h Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by PORTA. Note 1: The ADCON1 register is implemented on the PIC16C924 PIC16C924 only. 2: PIC16C923 PIC16C923 reset values for PORTA: -xx xxxx for a POR, and -uu uuuu for all other resets, PIC16C924 PIC16C924 reset values for PORTA: -0x 0000 for a POR, and -0u 0000 for all other resets. DS30444B-page 32 Advance Information © 1996 Microchip Technology Inc. PIC16C9XX PIC16C9XX PORTB and TRISB Register 5.2 PORTB is an 8-bit wide bi-directional port. The corresponding data direction register is TRISB. Setting a bit in the TRISB register puts the corresponding output driver in a hi-impedance input mode. Clearing a bit in the TRISB register puts the contents of the output latch on the selected pin(s). EXAMPLE 5-2: INITIALIZING PORTB CLRF BCF BSF MOVLW PORTB STATUS, RP1 STATUS, RP0 0xCF MOVWF TRISB ; ; ; ; ; ; ; ; ; Initialize PORTB Select Bank 1 Value used to initialize data direction Set RB as inputs RB as outputs RB as inputs BLOCK DIAGRAM OF RB3:RB0 PINS weak P pull-up Data Latch D Q The interrupt on change feature is recommended for wake-up on key depression operation and operations where PORTB is only used for the interrupt on change feature. Polling of PORTB is not recommended while using the interrupt on change feature. FIGURE 5-4: Data bus WR Port I/O pin(1) CK TRIS Latch D Q WR TRIS A mismatch condition will continue to set flag bit RBIF. Reading PORTB will end the mismatch condition, and allow flag bit RBIF to be cleared. weak P pull-up Data Latch D Q I/O pin(1) CK TRIS Latch D Q WR TRIS TTL Input Buffer CK BLOCK DIAGRAM OF RB7:RB4 PINS RBPU(2) VDD WR Port b) Any read or write of PORTB. This will end the mismatch condition. Clear flag bit RBIF. VDD RBPU(2) Data bus a) This interrupt on mismatch feature, together with software configurable pull-ups on these four pins allow easy interface to a key pad and make it possible for wake-up on key-depression. Refer to the Embedded Control Handbook, "Implementing Wake-Up on Key Stroke" (AN552 AN552). Each of the PORTB pins has a weak internal pull-up. A single control bit can turn on all the pull-ups. This is done by clearing bit RBPU (OPTION). The weak pull-up is automatically turned off when the port pin is configured as an output. The pull-ups are also disabled on a Power-on Reset. FIGURE 5-3: This interrupt can wake the device from SLEEP. The user, in the interrupt service routine, can clear the interrupt in the following manner: TTL Input Buffer CK RD TRIS Q RD TRIS Q D Latch D EN RD Port ST Buffer Q1 Set RBIF RD Port EN From other RB7:RB4 pins RB0/INT Schmitt Trigger Buffer Q D RD Port EN RD Port Q3 RB7:RB6 in serial programming mode Note 1: I/O pins have diode protection to VDD and VSS. 2: TRISB = '1' enables weak pull-up if RBPU = '0' (OPTION). Note 1: I/O pins have diode protection to VDD and VSS. 2: TRISB = '1' enables weak pull-up if RBPU = '0' (OPTION). Four of PORTB's pins, RB7:RB4, have an interrupt on change feature. Only pins configured as inputs can cause this interrupt to occur (i.e. any RB7:RB4 pin configured as an output is excluded from the interrupt on change comparison). The input pins (of RB7:RB4) are compared with the old value latched on the last read of PORTB. The "mismatch" outputs of RB7:RB4 are OR'ed together to generate the RB Port Change Interrupt with flag bit RBIF (INTCON). © 1996 Microchip Technology Inc. Advance Information DS30444B-page 33 PIC16C9XX PIC16C9XX TABLE 5-3: Name PORTB FUNCTIONS Bit# Buffer Function RB0/INT bit0 TTL/ST Input/output pin or external interrupt input. Internal software programmable weak pull-up. This buffer is a Schmitt Trigger input when configured as the external interrupt. RB1 bit1 TTL Input/output pin. Internal software programmable weak pull-up. RB2 bit2 TTL Input/output pin. Internal software programmable weak pull-up. RB3 bit3 TTL Input/output pin. Internal software programmable weak pull-up. RB4 bit4 TTL Input/output pin (with interrupt on change). Internal software programmable weak pull-up. RB5 bit5 TTL Input/output pin (with interrupt on change). Internal software programmable weak pull-up. RB6 bit6 TTL/ST Input/output pin (with interrupt on change). Internal software programmable weak pull-up. Serial programming clock. This buffer is a Schmitt Trigger input when used in serial programming mode. RB7 bit7 TTL/ST Input/output pin (with interrupt on change). Internal software programmable weak pull-up. Serial programming data. This buffer is a Schmitt Trigger input when used in serial programming mode. Legend: TTL = TTL input, ST = Schmitt Trigger TABLE 5-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Power-on Reset Value on all other resets 06h, 106h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx uuuu uuuu 86h, 186h TRISB 1111 1111 1111 1111 81h, 181h OPTION 1111 1111 1111 1111 TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTB. DS30444B-page 34 Advance Information © 1996 Microchip Technology Inc. PIC16C9XX PIC16C9XX 5.3 PORTC and TRISC Register EXAMPLE 5-3: INITIALIZING PORTC PORTC is an 6-bit bi-directional port. Each pin is individually configurable as an input or output through the TRISC register. PORTC is multiplexed with several peripheral functions (Table 5-5). PORTC pins have Schmitt Trigger input buffers. CLRF BCF BSF MOVLW PORTC STATUS, RP1 STATUS, RP0 0xCF When enabling peripheral functions, care should be taken in defining TRIS bits for each PORTC pin. Some peripherals override the TRIS bit to make a pin an output, while other peripherals override the TRIS bit to make a pin an input. Since the TRIS bit override is in effect while the peripheral is enabled, read-modify-write instructions (BSF, BCF, XORWF) with TRISC as destination should be avoided. The user should refer to the corresponding peripheral section for the correct TRIS bit settings. MOVWF TRISC FIGURE 5-5: ; ; ; ; ; ; ; ; ; Initialize PORTC Select Bank 1 Value used to initialize data direction Set RC as inputs RC as outputs RC always read 0 PORTC BLOCK DIAGRAM (PERIPHERAL OUTPUT OVERRIDE) PORT/PERIPHERAL Select(1) Peripheral Data-out 0 VDD 1 Data Bus D WR PORT Q CK Q P Data Latch D WR TRIS CK I/O pin(3) Q Q N TRIS Latch Peripheral OE(2) VSS RD TRIS Schmitt Trigger Q D RD PORT EN EN Peripheral input Note 1: Port/Peripheral select signal selects between port data and peripheral output. 2: Peripheral OE (output enable) is only activated if peripheral select is active. 3: I/O pins have diode protection to VDD and VSS. © 1996 Microchip Technology Inc. Advance Information RD PORT DS30444B-page 35 PIC16C9XX PIC16C9XX TABLE 5-5: PORTC FUNCTIONS Name Bit# Buffer Type Function RC0/T1OSO/T1CKI bit0 ST Input/output port pin or Timer1 oscillator output or Timer1 clock input RC1/T1OSI bit1 ST Input/output port pin or Timer1 oscillator input RC2/CCP1 bit2 ST Input/output port pin or Capture input/Compare output/PWM output RC3/SCK/SCL bit3 ST Input/output port pin or the synchronous serial clock for both SPI and I2C modes. RC4/SDI/SDA bit4 ST Input/output port pin or the SPI Data In (SPI mode) or data I/O (I2C mode). RC5/SDO bit5 ST Input/output port pin or Synchronous Serial Port data out Legend: ST = Schmitt Trigger input TABLE 5-6: Address Name SUMMARY OF REGISTERS ASSOCIATED WITH PORTC Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Power-on Reset Value on all other resets RC5 RC4 RC3 RC2 RC1 RC0 -xx xxxx -uu uuuu -11 1111 -11 1111 07h PORTC - - 87h TRISC - - TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. DS30444B-page 36 Advance Information © 1996 Microchip Technology Inc. PIC16C9XX PIC16C9XX 5.4 PORTD and TRISD Registers EXAMPLE 5-4: PORTD is an 8-bit port with Schmitt Trigger input buffers. The first five pins are configurable as general purpose I/O pins or LCD segment drivers. Pins RD5, RD6 and RD7 can be digital inputs or LCD segment or common drivers. TRISD controls the direction of pins RD0 through RD4 when PORTD is configured as a digital port. Note: STATUS,RP0 STATUS,RP1 LCDSE,SE29 LCDSE,SE0 STATUS,RP0 STATUS,RP1 0x07 TRISD ;Select Bank 2 ; ;Make RD digital ;Make RD digital ;Select Bank 1 ; ;Make RD outputs ;Make RD inputs On a Power-on Reset these pins are configured as LCD segment drivers. Note: BCF BSF BCF BCF BSF BCF MOVLW MOVWF INITIALIZING PORTD To configure the pins as a digital port, the corresponding bits in the LCDSE register must be cleared. Any bit set in the LCDSE register overrides any bit settings in the corresponding TRIS register. FIGURE 5-6: PORTD BLOCK DIAGRAM LCD Segment Data LCD Segment Output Enable Data Bus WR PORT D Q I/O pin CK Data Latch D WR TRIS Q CK Schmitt Trigger input buffer TRIS Latch LCDSE RD TRIS Q D EN EN RD PORT © 1996 Microchip Technology Inc. Advance Information DS30444B-page 37 PIC16C9XX PIC16C9XX FIGURE 5-7: PORTD BLOCK DIAGRAM LCD Segment Data LCD Segment Output Enable LCD Common Data Digital Input/ LCD Output pin LCD Common Output Enable LCDSE Schmitt Trigger input buffer Data Bus Q D EN EN RD PORT VDD RD TRIS TABLE 5-7: PORTD FUNCTIONS Name Bit# Buffer Type RD0/SEG00 RD0/SEG00 bit0 ST Input/output port pin or Segment Driver00 RD1/SEG01 RD1/SEG01 bit1 ST Input/output port pin or Segment Driver01 RD2/SEG02 RD2/SEG02 bit2 ST Input/output port pin or Segment Driver02 RD3/SEG03 RD3/SEG03 bit3 ST Input/output port pin or Segment Driver03 RD4/SEG04 RD4/SEG04 bit4 ST Input/output port pin or Segment Driver04 RD5/SEG29/COM3 RD5/SEG29/COM3 bit5 ST Digital input pin or Segment Driver29 or Common Driver3 RD6/SEG30/COM2 RD6/SEG30/COM2 bit6 ST Digital input pin or Segment Driver30 or Common Driver2 RD7/SEG31/COM1 RD7/SEG31/COM1 bit7 ST Legend: ST = Schmitt Trigger input Digital input pin or Segment Driver31 or Common Driver1 TABLE 5-8: Function SUMMARY OF REGISTERS ASSOCIATED WITH PORTD Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Power-on Reset Value on all other resets 08h PORTD RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 0000 0000 0000 0000 88h TRISD 1111 1111 1111 1111 10Dh LCDSE 1111 1111 1111 1111 TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 SE29 SE27 SE20 SE16 SE12 SE9 SE5 SE0 Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. DS30444B-page 38 Advance Information © 1996 Microchip Technology Inc. PIC16C9XX PIC16C9XX 5.5 PORTE and TRISE Register EXAMPLE 5-5: PORTE is an digital input only port. Each pin is multiplexed with an LCD segment driver. These pins have Schmitt Trigger input buffers. Note: STATUS,RP0 STATUS,RP1 LCDSE,SE27 LCDSE,SE5 LCDSE,SE9 ;Select Bank 2 ; ;Make all PORTE ;and PORTG ;digital inputs On a Power-on Reset these pins are configured as LCD segment drivers. Note: BCF BSF BCF BCF BCF INITIALIZING PORTE To configure the pins as a digital port, the corresponding bits in the LCDSE register must be cleared. Any bit set in the LCDSE register overrides any bit settings in the corresponding TRIS register. FIGURE 5-8: PORTE BLOCK DIAGRAM LCD Segment Data Digital Input/ LCD Output pin LCD Segment Output Enable LCDSE Schmitt Trigger input buffer Data Bus Q D EN EN RD PORT VDD RD TRIS TABLE 5-9: PORTE FUNCTIONS Name Bit# Buffer Type RE0/SEG05 RE0/SEG05 bit0 ST Digital input or Segment Driver05 RE1/SEG06 RE1/SEG06 bit1 ST Digital input or Segment Driver06 RE2/SEG07 RE2/SEG07 bit2 ST Digital input or Segment Driver07 RE3/SEG08 RE3/SEG08 bit3 ST Digital input or Segment Driver08 RE4/SEG09 RE4/SEG09 bit4 ST Digital input or Segment Driver09 RE5/SEG10 RE5/SEG10 bit5 ST Digital input or Segment Driver10 RE6/SEG11 RE6/SEG11 bit6 ST Digital input or Segment Driver11 RE7/SEG27 RE7/SEG27 bit7 ST Legend: ST = Schmitt Trigger input © 1996 Microchip Technology Inc. Function Digital input or Segment Driver27 (not available on 64-pin devices) Advance Information DS30444B-page 39 PIC16C9XX PIC16C9XX TABLE 5-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Power-on Reset Value on all other resets 09h PORTE RE7 RE6 RE5 RE4 RE3 RE2 RE1 RE0 0000 0000 0000 0000 89h TRISE 1111 1111 1111 1111 10Dh LCDSE 1111 1111 1111 1111 TRISE7 TRISE6 TRISE5 TRISE4 TRISE3 TRISE2 TRISE1 TRISE0 SE29 SE27 SE20 SE16 SE12 SE9 SE5 SE0 Legend: - = unimplemented read as '0'. Shaded cells are not used by PORTE. DS30444B-page 40 Advance Information © 1996 Microchip Technology Inc. PIC16C9XX PIC16C9XX 5.6 PORTF and TRISF Register EXAMPLE 5-6: PORTF is an digital input only port. Each pin is multiplexed with an LCD segment driver. These pins have Schmitt Trigger input buffers. Note: On a Power-on Reset these pins are configured as LCD segment drivers. Note: BCF BSF BCF BCF STATUS,RP0 STATUS,RP1 LCDSE,SE16 LCDSE,SE12 INITIALIZING PORTF ;Select Bank 2 ; ;Make all PORTF ;digital inputs To configure the pins as a digital port, the corresponding bits in the LCDSE register must be cleared. Any bit set in the LCDSE register overrides any bit settings in the corresponding TRIS register. FIGURE 5-9: PORTF BLOCK DIAGRAM LCD Segment Data Digital Input/ LCD Output pin LCD Segment Output Enable LCDSE Schmitt Trigger input buffer Data Bus Q D EN EN RD PORT VDD RD TRIS TABLE 5-11: PORTF FUNCTIONS Name Bit# Buffer Type RF0/SEG12 RF0/SEG12 bit0 ST Digital input or Segment Driver12 RF1/SEG13 RF1/SEG13 bit1 ST Digital input or Segment Driver13 RF2/SEG14 RF2/SEG14 bit2 ST Digital input or Segment Driver14 RF3/SEG15 RF3/SEG15 bit3 ST Digital input or Segment Driver15 RF4/SEG16 RF4/SEG16 bit4 ST Digital input or Segment Driver16 RF5/SEG17 RF5/SEG17 bit5 ST Digital input or Segment Driver17 RF6/SEG18 RF6/SEG18 bit6 ST Digital input or Segment Driver18 RF7/SEG19 RF7/SEG19 bit7 ST Legend: ST = Schmitt Trigger input Digital input or Segment Driver19 © 1996 Microchip Technology Inc. Function Advance Information DS30444B-page 41 PIC16C9XX PIC16C9XX TABLE 5-12: SUMMARY OF REGISTERS ASSOCIATED WITH PORTF Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Power-on Reset Value on all other resets 107h PORTF RF7 RF6 RF5 RF4 RF3 RF2 RF1 RF0 0000 0000 0000 0000 187h TRISF 1111 1111 1111 1111 10Dh LCDSE 1111 1111 1111 1111 TRISF7 TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 TRISF0 SE29 SE27 SE20 SE16 SE12 SE9 SE5 SE0 Legend: - = unimplemented read as '0'. Shaded cells are not used by PORTF. DS30444B-page 42 Advance Information © 1996 Microchip Technology Inc. PIC16C9XX PIC16C9XX 5.7 PORTG and TRISG Register EXAMPLE 5-7: PORTG is an digital input only port. Each pin is multiplexed with an LCD segment driver. These pins have Schmitt Trigger input buffers. Note: On a Power-on Reset these pins are configured as LCD segment drivers. Note: BCF BSF BCF BCF STATUS,RP0 STATUS,RP1 LCDSE,SE27 LCDSE,SE20 INITIALIZING PORTG ;Select Bank 2 ; ;Make all PORTG ;and PORTE ;digital inputs To configure the pins as a digital port, the corresponding bits in the LCDSE register must be cleared. Any bit set in the LCDSE register overrides any bit settings in the corresponding TRIS register. FIGURE 5-10: PORTG BLOCK DIAGRAM LCD Segment Data Digital Input/ LCD Output pin LCD Segment Output Enable LCDSE Schmitt Trigger input buffer Data Bus Q D EN EN RD PORT VDD RD TRIS TABLE 5-13: PORTG FUNCTIONS Name Bit# Buffer Type RG0/SEG20 RG0/SEG20 bit0 ST Digital input or Segment Driver20 RG1/SEG21 RG1/SEG21 bit1 ST Digital input or Segment Driver21 RG2/SEG22 RG2/SEG22 bit2 ST Digital input or Segment Driver22 RG3/SEG23 RG3/SEG23 bit3 ST Digital input or Segment Driver23 RG4/SEG24 RG4/SEG24 bit4 ST Digital input or Segment Driver24 RG5/SEG25 RG5/SEG25 bit5 ST Digital input or Segment Driver25 RG6/SEG26 RG6/SEG26 bit6 ST Digital input or Segment Driver26 RG7/SEG28 RG7/SEG28 bit7 ST Legend: ST = Schmitt Trigger input © 1996 Microchip Technology Inc. Function Digital input or Segment Driver28 (not available on 64-pin devices) Advance Information DS30444B-page 43 PIC16C9XX PIC16C9XX TABLE 5-14: SUMMARY OF REGISTERS ASSOCIATED WITH PORTG Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Power-on Reset Value on all other resets 108h PORTG RG7 RG6 RG5 RG4 RG3 RG2 RG1 RG0 0000 0000 0000 0000 188h TRISG 1111 1111 1111 1111 10Dh LCDSE 1111 1111 1111 1111 TRISG7 TRISG6 TRISG5 TRISG4 TRISG3 TRISG2 TRISG1 TRISG0 SE29 SE27 SE20 SE16 SE12 SE9 SE5 SE0 Legend: - = unimplemented read as '0'. Shaded cells are not used by PORTG. DS30444B-page 44 Advance Information © 1996 Microchip Technology Inc. PIC16C9XX PIC16C9XX 5.8 I/O Programming Considerations 5.8.1 EXAMPLE 5-8: BI-DIRECTIONAL I/O PORTS Any instruction which writes, operates internally as a read followed by a write operation. The BCF and BSF instructions, for example, read the register into the CPU, execute the bit operation and write the result back to the register. Caution must be used when these instructions are applied to a port with both inputs and outputs defined. For example, a BSF operation on bit5 of PORTB will cause all eight bits of PORTB to be read into the CPU. Then the BSF operation takes place on bit5 and PORTB is written to the output latches. If another bit of PORTB is used as a bi-directional I/O pin (e.g., bit0) and it is defined as an input at this time, the input signal present on the pin itself would be read into the CPU and rewritten to the data latch of this particular pin, overwriting the previous content. As long as the pin stays in the input mode, no problem occurs. However, if bit0 is switched into output mode later on, the contents of the data latch may now be unknown. Reading the port register, reads the values of the port pins. Writing to the port register writes the value to the port latch. When using read-modify-write instructions (ex. BCF, BSF) on a port, the value of the port pins is read, the desired operation is done to this value, and this value is then written to the port latch. Example 5-8 shows the effect of two sequential read-modify-write instructions on an I/O port. READ-MODIFY-WRITE INSTRUCTIONS ON AN I/O PORT ;Initial PORT settings: PORTB Inputs ; PORTB Outputs ;PORTB have external pull-ups and are ;not connected to other circuitry ; ; PORT latch PORT pins ; - -BCF PORTB, 7 ; 01pp pppp 11pp pppp BCF PORTB, 6 ; 10pp pppp 11pp pppp BCF STATUS, RP1 ; BSF STATUS, RP0 ; BCF TRISB, 7 ; 10pp pppp 11pp pppp BCF TRISB, 6 ; 10pp pppp 10pp pppp ; ;Note that the user may have expected the ;pin values to be 00pp ppp. The 2nd BCF ;caused RB7 to be latched as the pin value ;(high). A pin actively outputting a Low or High should not be driven from external devices at the same time in order to change the level on this pin ("wired-or", "wired-and"). The resulting high output currents may damage the chip. 5.8.2 SUCCESSIVE OPERATIONS ON I/O PORTS The actual write to an I/O port happens at the end of an instruction cycle, whereas for reading, the data must be valid at the beginning of the instruction cycle (Figure 5-11). Therefore, care must be exercised if a write followed by a read operation is carried out on the same I/O port. The sequence of instructions should be such to allow the pin voltage to stabilize (load dependent) before the next instruction which causes that file to be read into the CPU is executed. Otherwise, the previous state of that pin may be read into the CPU rather than the new state. When in doubt, it is better to separate these instructions with a NOP or another instruction not accessing this I/O port. FIGURE 5-11: SUCCESSIVE I/O OPERATION Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PC Instruction fetched PC PC + 2 NOP PC + 1 MOVWF PORTB MOVF PORTB,W write to PORTB PC + 3 NOP This example shows a write to PORTB followed by a read from PORTB. Note that: data setup time = (0.25TCY 25TCY - TPD) RB7:RB0 where TCY = instruction cycle TPD = propagation delay Port pin sampled here TPD Instruction executed NOP MOVWF PORTB write to PORTB © 1996 Microchip Technology Inc. Note: MOVF PORTB,W Advance Information Therefore, at higher clock frequencies,