PIC16C745/765 PIC16C765 PIC16C745 DS33023 DS30000A DS30000 PIC16CXX PIC16C5X - Datasheet Archive

 

PIC16C745/765 8-Bit CMOS Microcontrollers with USB Devices included in this data sheet: Pin Diagrams · PIC16C765 28-Pin

 

745cov.book Page 1 Wednesday, August 2, 2000 8:24 AM PIC16C745/765 PIC16C745/765 8-Bit CMOS Microcontrollers with USB Devices included in this data sheet: Pin Diagrams · PIC16C765 PIC16C765 28-Pin DIP, SOIC Microcontroller Core Features: · High-performance RISC CPU · Only 35 single word instructions Memory Program x14 Data x8 Pins A/D Resolution A/D Channels PIC16C745 PIC16C745 8K 256 28 8 5 PIC16C765 PIC16C765 8K 256 40 8 8 Device · All single cycle instructions except for program branches which are two cycle · Interrupt capability (up to 12 internal/external interrupt sources) · Eight level deep hardware stack · Direct, indirect and relative addressing modes · Power-on Reset (POR) · Power-up Timer (PWRT) and Oscillator Start-up Timer (OST) · Watchdog Timer (WDT) with its own on-chip RC oscillator for reliable operation · Brown-out detection circuitry for Brown-out Reset (BOR) · Programmable code-protection · Power saving SLEEP mode · Selectable oscillator options - EC - External clock (24 MHz) - E4 - External clock with PLL (6 MHz) - HS - Crystal/Resonator (24 MHz) - H4 - Crystal/Resonator with PLL (6 MHz) · Processor clock of 24 MHz derived from 6 MHz crystal or resonator · Fully static low-power, high-speed CMOS · In-Circuit Serial Programming (ICSP) · Operating voltage range - 4.35 to 5.25V · High Sink/Source Current 25/25 mA · Wide temperature range - Industrial (-40°C - 85°C) · Low-power consumption: - ~ 16 mA @ 5V, 24 MHz - 100 µA typical standby current 2000 Microchip Technology Inc. MCLR/VPP RA0/AN0 RA1/AN1 RA2/AN2 RA3/AN3/VREF RA4/T0CKI RA5/AN4 Vss OSC1/CLKIN OSC2/CLKOUT RC0/T1OSO/T1CKI RC1/T1OSI/CCP2 RC2/CCP1 VUSB ·1 2 3 4 5 6 7 8 9 10 11 12 13 14 PIC16C745 PIC16C745 · PIC16C745 PIC16C745 28 27 26 25 24 23 22 21 20 19 18 17 16 15 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0/INT VDD Vss RC7/RX/DT RC6/TX/CK D+ D- Peripheral Features: · Universal Serial Bus (USB 1.1) - Soft attach/detach · 64 bytes of USB dual port RAM · 22 (PIC16C745 PIC16C745) or 33 (PIC16C765 PIC16C765) I/O pins - Individual direction control - 1 high voltage open drain (RA4) - 8 PORTB pins with: - Interrupt-on-change control (RB only) - Weak pull-up control - 3 pins dedicated to USB · Timer0: 8-bit timer/counter with 8-bit prescaler · Timer1: 16-bit timer/counter with prescaler can be incremented during SLEEP via external crystal/clock · Timer2: 8-bit timer/counter with 8-bit period register, prescaler and postscaler · 2 Capture, Compare and PWM modules - Capture is 16-bit, max. resolution is 10.4 ns - Compare is 16-bit, max. resolution is 167 ns - PWM maximum resolution is 10-bit · 8-bit multi-channel Analog-to-Digital converter · Universal Synchronous Asynchronous Receiver Transmitter (USART/SCI) · Parallel Slave Port (PSP) 8-bits wide, with external RD, WR and CS controls (PIC16C765 PIC16C765 only) Preliminary DS41124C-page 1 745cov.book Page 2 Wednesday, August 2, 2000 8:24 AM RC6/TX/CK D+ DRD3/PSP3 RD2/PSP2 RD1/PSP1 RD0/PSP0 VUSB RC2/CCP1 RC1/T1OSI/CCP2 NC 44-Pin TQFP PIC16C765 PIC16C765 RB3 RB2 RB1 RB0/INT VDD VSS RD7/PSP7 RD6/PSP6 RD5/PSP5 RD4/PSP4 RC7/RX/DT 39 38 37 36 35 34 33 32 31 30 29 1 2 3 4 5 6 7 8 9 10 11 PIC16C765 PIC16C765 33 32 31 30 29 28 27 26 25 24 23 NC RC0/T1OSO/T1CKI OSC2/CLKOUT OSC1/CLKIN VSS VDD RE2/CS/AN7 RE1/WR/AN6 RE0/RD/AN5 RA5/AN4 RA4/T0CKI NC NC RB4 RB5 RB6 RB7 MCLR/VPP RA0/AN0 RA1/AN1 RA2/AN2 RA3/AN3/VREF RC1/T1OSI/CCP2 RC2/CCP1 VUSB RD0/PSP0 RD1/PSP1 RD2/PSP2 RD3/PSP3 DD+ RC6/TX/CK NC RC7/RX/DT RD4/PSP4 RD5/PSP5 RD6/PSP6 RD7/PSP7 VSS VDD RB0/INT RB1 RB2 RB3 12 13 14 15 16 17 18 19 20 21 22 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 RA4/T0CKI RA5/AN4 RE0/RD/AN5 RE1/WR/AN6 RE2/CS/AN7 VDD VSS OSC1/CLKIN OSC2/CLKOUT RC0/T1OSO/T1CKI NC 44 43 42 41 40 39 38 37 36 35 34 6 5 4 3 2 1 44 43 42 41 40 44-Pin PLCC RA3/AN3/VREF RA2/AN2 RA1/AN1 RA0/AN0 MCLR/VPP NC RB7 RB6 RB5 RB4 NC PIC16C745/765 PIC16C745/765 MCLR/VPP RA0/AN0 RA1/AN1 RA2/AN2 RA3/AN3/VREF RA4/T0CKI RA5/AN4 RE0/RD/AN5 RE1/WR/AN6 RE2/CS/AN7 VDD VSS OSC1/CLKIN OSC2/CLKOUT RC0/T1OSO/T1CKI RC1/T1OSI/CCP2 RC2/CCP1 VUSB RD0/PSP0 RD1/PSP1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 PIC16C765 PIC16C765 40-Pin DIP 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0/INT VDD VSS RD7/PSP7 RD6/PSP6 RD5/PSP5 RD4/PSP4 RC7/RX/DT RC6/TX/CK D+ DRD3/PSP3 RD2/PSP2 Key Features PICmicroTM Mid-Range Reference Manual (DS33023 DS33023) PIC16C745 PIC16C745 PIC16C765 PIC16C765 Operating Frequency 6 MHz or 24 MHz Resets (and Delays) POR, BOR (PWRT, OST) 6 MHz or 24 MHz POR, BOR (PWRT, OST) Program Memory (14-bit words) 8K 8K Data Memory (bytes) 256 256 Dual Port Ram 64 64 Interrupt Sources 11 12 I/O Ports 22 (Ports A, B, C) 33 (Ports A, B, C, D, E) Timers 3 3 Capture/Compare/PWM modules 2 2 Analog-to-Digital Converter Module 5 channel x 8 bit 8 channel x 8 bit Parallel Slave Port - Yes Serial Communication USB, USART/SCI USB, USART/SCI Brown-out Detect Reset Yes Yes DS41124C-page 2 Preliminary 2000 Microchip Technology Inc. 745cov.book Page 3 Wednesday, August 2, 2000 8:24 AM PIC16C745/765 PIC16C745/765 Table of Contents 1.0 General Description . 5 2.0 PIC16C745/765 PIC16C745/765 Device Varieties . 7 3.0 Architectural Overview . 9 4.0 Memory Organization. 15 5.0 I/O Ports. 31 6.0 Timer0 Module . 43 7.0 Timer1 Module . 45 8.0 Timer2 Module . 49 9.0 Capture/Compare/PWM Modules . 51 10.0 Universal Serial Bus. 57 11.0 Universal Synchronous Asynchronous Receiver Transmitter (USART) . 77 12.0 Analog-to-Digital Converter (A/D) Module . 91 13.0 Special Features of the CPU . 99 14.0 Instruction Set Summary. 113 15.0 Development Support . 121 16.0 Electrical Characteristics. 127 17.0 DC and AC Characteristics Graphs and Tables . 145 18.0 Packaging Information . 147 Index . 157 On-Line Support. 161 Reader Response . 162 Product Identification System . 163 To Our Valued Customers Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number. e.g., DS30000A DS30000A is version A of document DS30000 DS30000. New Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products. Errata An errata sheet may exist for current devices, describing minor operational differences (from the data sheet) and recommended workarounds. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: · Microchip's Worldwide Web site; http://www.microchip.com · Your local Microchip sales office (see last page) · The Microchip Corporate Literature Center; U.S. FAX: (480) 786-7277 When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include literature number) you are using. Corrections to this Data Sheet We constantly strive to improve the quality of all our products and documentation. We have spent a great deal of time to ensure that this document is correct. However, we realize that we may have missed a few things. If you find any information that is missing or appears in error, please: · Fill out and mail in the reader response form in the back of this data sheet. · E-mail us at webmaster@microchip.com. We appreciate your assistance in making this a better document. 2000 Microchip Technology Inc. Preliminary DS41124C-page 3 745cov.book Page 4 Wednesday, August 2, 2000 8:24 AM PIC16C745/765 PIC16C745/765 NOTES: DS41124C-page 4 Preliminary 2000 Microchip Technology Inc. 745cov.book Page 5 Wednesday, August 2, 2000 8:24 AM PIC16C745/765 PIC16C745/765 1.0 GENERAL DESCRIPTION The PIC16C745/765 PIC16C745/765 devices are low cost, high-performance, CMOS, fully-static, 8-bit microcontrollers in the PIC16CXX PIC16CXX mid-range family. All PICmicro® microcontrollers employ an advanced RISC architecture. The PIC16C745/765 PIC16C745/765 microcontroller family has enhanced core features, eight-level deep stack and multiple internal and external interrupt sources. The separate instruction and data buses of the Harvard architecture allow a 14-bit wide instruction word with the separate 8-bit wide data. The two stage instruction pipeline allows all instructions to execute in a single cycle, except for program branches, which require two cycles. A total of 35 instructions (reduced instruction set) are available. Additionally, a large register set gives some of the architectural innovations used to achieve a very high performance. The PIC16C745 PIC16C745 device has 22 I/O pins. The PIC16C765 PIC16C765 device has 33 I/O pins. Each device has 256 bytes of RAM. In addition, several peripheral features are available including: three timer/counters, two Capture/Compare/PWM modules and two serial ports. The Universal Serial Bus (USB 1.1) low speed peripheral provides bus communications. The Universal Synchronous Asynchronous Receiver Transmitter (USART) is also known as the Serial Communications Interface or SCI. Also, a 5-channel high-speed 8-bit A/D is provided on the PIC16C745 PIC16C745, while the PIC16C765 PIC16C765 offers 8 channels. The 8-bit resolution is ideally suited for applications requiring a low cost analog interface (e.g., thermostat control, pressure sensing, etc.). The PIC16C745/765 PIC16C745/765 devices have special features to reduce external components, thus reducing cost, enhancing system reliability and reducing power consumption. There are 4 oscillator options, of which EC is for the external regulated clock source, E4 is for the external regulated clock source with the PLL enabled, HS is for the high speed crystals/resonators and H4 is for high speed crystals/resonators with the PLL enabled. The SLEEP (power-down) feature provides a power-saving mode. The user can wake-up the chip from SLEEP through several external and internal interrupts and RESETS. 2000 Microchip Technology Inc. A highly reliable Watchdog Timer (WDT), with a dedicated on-chip RC oscillator, provides protection against software lock-up, and also provides one way of waking the device from SLEEP. A UV erasable CERDIP packaged version is ideal for code development, while the cost-effective One-TimeProgrammable (OTP) version is suitable for production in any volume. The PIC16C745/765 PIC16C745/765 devices fit nicely in many applications ranging from security and remote sensors to appliance controls and automotives. The EPROM technology makes customization of application programs (data loggers, industrial controls, UPS) extremely fast and convenient. The small footprint packages make this microcontroller series perfect for all applications with space limitations. Low-cost, lowpower, high-performance, ease of use and I/O flexibility make the PIC16C745/765 PIC16C745/765 devices very versatile, even in areas where no microcontroller use has been considered before (e.g., timer functions, serial communication, capture and compare, PWM functions and coprocessor applications). 1.1 Family and Upward Compatibility Users familiar with the PIC16C5X PIC16C5X microcontroller family will realize that this is an enhanced version of the PIC16C5X PIC16C5X architecture. Code written for the PIC16C5X PIC16C5X can be easily ported to the PIC16C745/765 PIC16C745/765 family of devices. 1.2 Development Support PICmicro® devices are supported by the complete line of Microchip Development tools. Please refer to Section 15.0 for more details about Microchip's development tools. Preliminary DS41124C-page 5 745cov.book Page 6 Wednesday, August 2, 2000 8:24 AM PIC16C745/765 PIC16C745/765 NOTES: DS41124C-page 6 Preliminary 2000 Microchip Technology Inc. 745cov.book Page 7 Wednesday, August 2, 2000 8:24 AM PIC16C745/765 PIC16C745/765 2.0 PIC16C745/765 PIC16C745/765 DEVICE VARIETIES 2.3 A variety of frequency ranges and packaging options are available. Depending on application and production requirements, the proper device option can be selected using the information in the PIC16C745/765 PIC16C745/765 Product Identification System section at the end of this data sheet. When placing orders, please use that page of the data sheet to specify the correct part number. 2.1 UV Erasable Devices The UV erasable version, offered in windowed CERDIP packages, is optimal for prototype development and pilot programs. This version can be erased and reprogrammed to any of the supported oscillator modes. Microchip's PICSTART Plus and PRO MATE II programmers both support programming of the PIC16C745/765 PIC16C745/765. 2.2 Quick-Turnaround-Production (QTP) Devices Microchip offers a QTP Programming Service for factory production orders. This service is made available for users who choose not to program a medium to high quantity of units and whose code patterns have stabilized. The devices are identical to the OTP devices but with all EPROM locations and configuration options already programmed by the factory. Certain code and prototype verification procedures apply before production shipments are available. Please contact your local Microchip Technology sales office for more details. 2.4 Serialized Quick-Turnaround Production (SQTPSM) Devices Microchip offers a unique programming service where a few user-defined locations in each device are programmed with different serial numbers. The serial numbers may be random, pseudo-random or sequential. Serial programming allows each device to have a unique number, which can serve as an entry-code, password or ID number. One-Time-Programmable (OTP) Devices The availability of OTP devices is especially useful for customers who need the flexibility for frequent code updates and small volume applications. The OTP devices, packaged in plastic packages, permit the user to program them once. In addition to the program memory, the configuration bits must also be programmed. 2000 Microchip Technology Inc. Preliminary DS41124C-page 7 745cov.book Page 8 Wednesday, August 2, 2000 8:24 AM PIC16C745/765 PIC16C745/765 NOTES: DS41124C-page 8 Preliminary 2000 Microchip Technology Inc. 745cov.book Page 9 Wednesday, August 2, 2000 8:24 AM PIC16C745/765 PIC16C745/765 3.0 ARCHITECTURAL OVERVIEW The high performance of the PIC16C745/765 PIC16C745/765 family can be attributed to a number of architectural features commonly found in RISC microprocessors. To begin with, the PIC16C745/765 PIC16C745/765 uses a Harvard architecture, in which program and data are accessed from separate memories using separate buses. This improves bandwidth over traditional von Neumann architecture in which program and data are fetched from the same memory using the same bus. Separating program and data buses further allows instructions to be sized differently than the 8-bit wide data word. Instruction opcodes are 14-bits wide making it possible to have all single word instructions. A 14-bit wide program memory access bus fetches a 14-bit instruction in a single cycle. A two-stage pipeline overlaps fetch and execution of instructions (Example 3-1). Consequently, most instructions execute in a single cycle (166.6667 ns @ 24 MHz) except for program branches. Memory Device A/D A/D Resolution Channels Program x14 Data x8 Pins PIC16C745 PIC16C745 8K 256 28 8 8K 256 40 8 The ALU is 8-bits wide and capable of addition, subtraction, shift and logical operations. Unless otherwise mentioned, arithmetic operations are two's complement in nature. In two-operand instructions, typically one operand is the working register (W register). The other operand is a file register or an immediate constant. In single operand instructions, the operand is either the W register or a file register. The W register is an 8-bit working register used for ALU operations. It is not an addressable register. Depending on the instruction executed, the ALU may affect the values of the Carry (C), Digit Carry (DC), and Zero (Z) bits in the STATUS register. The C and DC bits operate as a borrow bit and a digit borrow out bit, respectively, in subtraction. See the SUBLW and SUBWF instructions for examples. 5 PIC16C765 PIC16C765 PIC16C745/765 PIC16C745/765 devices contain an 8-bit ALU and working register. The ALU is a general purpose arithmetic unit. It performs arithmetic and Boolean functions between the data in the working register and any register file. 8 The PIC16C745/765 PIC16C745/765 can directly or indirectly address its register files or data memory. All special function registers, including the program counter, are mapped in the data memory. The PIC16C745/765 PIC16C745/765 has an orthogonal (symmetrical) instruction set that makes it possible to carry out any operation on any register using any addressing mode. This symmetrical nature and lack of `special optimal situations' make programming with the PIC16C745/765 PIC16C745/765 simple yet efficient. In addition, the learning curve is reduced significantly. 2000 Microchip Technology Inc. Preliminary DS41124C-page 9 745cov.book Page 10 Wednesday, August 2, 2000 8:24 AM PIC16C745/765 PIC16C745/765 FIGURE 3-1: PIC16C745/765 PIC16C745/765 BLOCK DIAGRAM 13 Program Memory Program Bus PORTA RA0/AN0 RA1/AN1 RA2/AN2 RA3/AN3/VREF RA4/T0CKI RA5/AN4 RAM File Registers 256 x 8 8 Level Stack (13 bit) 8K x 14 8 Data Bus Program Counter EPROM 14 RAM Addr(1) PORTB 9 Addr MUX Instruction reg Direct Addr 7 8 RB0/INT Indirect Addr RB FSR reg STATUS reg 8 PORTC 3 Power-up Timer Instruction Decode & Control OSC1/ CLKIN OSC2/ CLKOUT Timing Generation x4 PLL Oscillator Start-up Timer RC0/T1OSO/T1CKI RC1/T1OSI/CCP2 RC2/CCP1 RC6/TX/CK RC7/RX/DT MUX ALU Power-on Reset 8 Watchdog Timer Brown-out Reset PORTD W reg RD3:0/PSP3:0(2) RD4/PSP4(2) RD5/PSP5(2) RD6/PSP6(2) RD7/PSP7(2) Parallel Slave Port(2) MCLR Timer0 Timer1 CCP2 CCP1 VDD, V SS Timer2 PORTE RE0/AN5/RD(2) RE1/AN6/WR(2) RE2/AN7/CS (2) 8-bit A/D Dual Port RAM 64 x 8 USART USB XCVR VUSB DD+ Note 1: Higher order bits are from the STATUS register. 2: Not available on PIC16C745 PIC16C745. DS41124C-page 10 Preliminary 2000 Microchip Technology Inc. 745cov.book Page 11 Wednesday, August 2, 2000 8:24 AM PIC16C745/765 PIC16C745/765 TABLE 3-1: PIC16C745/765 PIC16C745/765 PINOUT DESCRIPTION Name MCLR/VPP OSC1/CLKIN OSC2/CLKOUT RA0/AN0 RA1/AN1 RA2/AN2 Input Type Output Type MCLR ST - Master Clear VPP Power - Programming Voltage OSC1 Xtal - Crystal/Resonator CLKIN ST - External Clock Input OSC2 - Xtal CLKOUT - CMOS Internal Clock (FINT/4) Output RA0 ST CMOS Bi-directional I/O AN0 AN - RA1 ST CMOS AN1 AN - RA2 ST CMOS Function RA3/AN3/VREF AN2 AN - RA3 ST CMOS Description Crystal/Resonator A/D Input Bi-directional I/O A/D Input Bi-directional I/O A/D Input Bi-directional I/O RA4/T0CKI RA5/AN4 RB0/INT AN3 AN - A/D Input VREF AN - A/D Positive Reference Bi-directional I/O RA4 ST OD T0CKI ST - RA5 ST AN4 AN - RB0 TTL CMOS Timer 0 Clock Input Bi-directional I/O A/D Input Bi-directional I/O(1) INT ST - RB1 RB1 TTL CMOS Bi-directional I/O(1) RB2 RB2 TTL CMOS Bi-directional I/O(1) RB3 RB3 TTL CMOS Bi-directional I/O(1) RB4 RB4 TTL CMOS Bi-directional I/O with Interrupt-on-Change(1) RB5 RB5 TTL CMOS Bi-directional I/O with Interrupt-on-Change(1) RB6 TTL CMOS Bi-directional I/O with Interrupt-on-Change(1) ICSPC ST RB7 TTL CMOS Bi-directional I/O with Interrupt-on-Change(1) ICSPD ST CMOS In-Circuit Serial Programming Data I/O Bi-directional I/O RB6/ICSPC RB7/ICSPD In-Circuit Serial Programming Clock Input RC0 CMOS - Xtal ST - RC1 RC1/T1OSI/CCP2(1) ST T1OSO T1CKI RC0/T1OSO/T1CKI ST CMOS T1OSI Xtal - CCP2 RC2/CCP1 RC2 Legend: Note 1: 2: ST CMOS D- Bi-directional I/O T1 Oscillator Input Bi-directional I/O Capture In/Compare Out/PWM Out 1 VUSB D- T1 Oscillator Output T1 Clock Input Capture In/Compare Out/PWM Out 2 CCP1 VUSB Interrupt Power Regulator Output Voltage USB USB USB Differential Bus D+ D+ USB OD = open drain, ST = Schmitt Trigger USB USB Differential Bus Weak pull-ups. PORT B pull-ups are byte wide programmable. PIC16C765 PIC16C765 only. 2000 Microchip Technology Inc. Preliminary DS41124C-page 11 745cov.book Page 12 Wednesday, August 2, 2000 8:24 AM PIC16C745/765 PIC16C745/765 TABLE 3-1: PIC16C745/765 PIC16C745/765 PINOUT DESCRIPTION (CONTINUED) Output Type ST CMOS Bi-directional I/O TX - CMOS USART Async Transmit ST CMOS USART Master Out/Slave In Clock RC7 RC7/RX/DT Input Type CK RC6/TX/CK Function RC6 Name ST CMOS Bi-directional I/O Description RD1/PSP1 RD2/PSP2 RD3/PSP3 RD4/PSP4 RD5/PSP5 ST - DT RD0/PSP0 RX ST CMOS USART Data I/O RD0 TTL CMOS Bi-directional I/O(2) PSP0 TTL - RD1 TTL CMOS PSP1 TTL - RD2 TTL CMOS PSP2 TTL - RD3 TTL CMOS PSP3 TTL - RD4 TTL CMOS PSP4 TTL - RD5 TTL CMOS RD7/PSP7 RE0/RD/AN5 TTL - RD6 TTL CMOS PSP6 TTL - RD7 TTL CMOS PSP7 TTL - RE0 RD6/PSP6 PSP5 ST CMOS RD TTL - AN5 AN - RE1 ST CMOS USART Async Receive Parallel Slave Port Data Input(2) Bi-directional I/O(2) Parallel Slave Port Data Input(2) Bi-directional I/O(2) Parallel Slave Port Data Input(2) Bi-directional I/O(2) Parallel Slave Port Data Input(2) Bi-directional I/O(2) Parallel Slave Port Data Input(2) Bi-directional I/O(2) Parallel Slave Port Data Input(2) Bi-directional I/O(2) Parallel Slave Port Data Input(2) Bi-directional I/O(2) Parallel Slave Port Data Input(2) Bi-directional I/O(2) Parallel Slave Port Control Input(2) A/D Input(2) Bi-directional I/O(2) WR TTL - Parallel Slave Port Control Input(2) AN6 AN - A/D Input(2) RE2 RE1/WR/AN6 ST CMOS Bi-directional I/O(2) CS TTL - Parallel Slave Port Data Input(2) AN7 AN - A/D Input(2) VDD Power - Power VSS VSS Power OD = open drain, ST = Schmitt Trigger - Ground RE2/CS/AN7 VDD Legend: Note 1: 2: Weak pull-ups. PORT B pull-ups are byte wide programmable. PIC16C765 PIC16C765 only. DS41124C-page 12 Preliminary 2000 Microchip Technology Inc. 745cov.book Page 13 Wednesday, August 2, 2000 8:24 AM PIC16C745/765 PIC16C745/765 3.1 Clocking Scheme/Instruction Cycle 3.2 The clock input feeds either an on-chip PLL, or directly drives (FINT). The clock output from either the PLL or direct drive (FINT) is internally divided by four to generate four non-overlapping quadrature clocks namely, Q1, Q2, Q3 and Q4. Internally, the program counter (PC) is incremented every Q1, the instruction is fetched from the program memory and latched into the instruction register in Q4. The instruction is decoded and executed during the following Q1 through Q4. The clocks and instruction execution flow is shown in Figure 3-2. Instruction Flow/Pipelining An "Instruction Cycle" consists of four Q cycles (Q1, Q2, Q3 and Q4). The instruction fetch and execute are pipelined such that fetch takes one instruction cycle, while decode and execute takes another instruction cycle. However, due to the pipelining, each instruction effectively executes in one cycle. If an instruction causes the program counter to change (e.g., GOTO), then two cycles are required to complete the instruction (Example 3-1). A fetch cycle begins with the program counter (PC) incrementing in Q1. In the execution cycle, the fetched instruction is latched into the "Instruction Register" (IR) in cycle Q1. This instruction is then decoded and executed during the Q2, Q3 and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination write). FIGURE 3-2: CLOCK/INSTRUCTION CYCLE Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 FINT Q1 Internal phase clock Q2 Q3 Q4 PC OSC2/CLKOUT (EC mode) EXAMPLE 3-1: PC PC+1 Fetch INST (PC) Execute INST (PC-1) Fetch INST (PC+1) Execute INST (PC) Fetch INST (PC+2) Execute INST (PC+1) INSTRUCTION PIPELINE FLOW TCY0 1. MOVLW 55h TCY1 Fetch 1 Execute 1 2. MOVWF PORTB 3. CALL SUB_1 4. BSF Fetch 2 TCY2 TCY3 TCY4 TCY5 Execute 2 Fetch 3 PORTA, BIT3 (Forced NOP) Execute 3 Fetch 4 Flush Fetch SUB_1 Execute SUB_1 5. Instruction @ address SUB_1 Note: PC+2 All instructions are single cycle, except for any program branches. These take two cycles, since the fetch instruction is "flushed" from the pipeline, while the new instruction is being fetched and then executed. 2000 Microchip Technology Inc. Preliminary DS41124C-page 13 745cov.book Page 14 Wednesday, August 2, 2000 8:24 AM PIC16C745/765 PIC16C745/765 NOTES: DS41124C-page 14 Preliminary 2000 Microchip Technology Inc. 745cov.book Page 15 Wednesday, August 2, 2000 8:24 AM PIC16C745/765 PIC16C745/765 4.0 MEMORY ORGANIZATION 4.2 4.1 Program Memory Organization The data memory is partitioned into multiple banks which contain the General Purpose Registers (GPR) and the Special Function Registers (SFR). Bits RP1 and RP0 are the bank select bits. The PIC16C745/765 PIC16C745/765 has a 13-bit program counter capable of addressing an 8K x 14 program memory space. All devices covered by this data sheet have 8K x 14 bits of program memory. The address range is 0000h - 1FFFh for all devices. The reset vector is at 0000h and the interrupt vector is at 0004h. FIGURE 4-1: PIC16C745/765 PIC16C745/765 PROGRAM MEMORY MAP AND STACK PC CALL, RETURN RETFIE, RETLW Data Memory Organization RP (STATUS) = 00 Bank0 = 01 Bank1 = 10 Bank2 = 11 Bank3 Each bank extends up to 7Fh (128 bytes). The lower locations of each bank are reserved for the SFRs. Above the SFRs are GPRs, implemented as static RAM. All implemented banks contain SFRs. Some "high use" SFRs from one bank may be mirrored in another bank for code reduction and quicker access. 13 Stack Level 1 4.2.1 GENERAL PURPOSE REGISTER FILE Stack Level 2 The register file can be accessed either directly or indirectly through the File Select Register (FSR) (Section 4.5). Stack Level 8 Reset Vector 0000h Interrupt Vector 0004h 0005h Page 0 07FFh 0800h On-chip Program Memory Page 1 0FFFh 1000h Page 2 17FFh 1800h Page 3 1FFFh 2000 Microchip Technology Inc. Preliminary DS41124C-page 15 745cov.book Page 16 Wednesday, August 2, 2000 8:24 AM PIC16C745/765 PIC16C745/765 FIGURE 4-2: Bank 0 DATA MEMORY MAP FOR PIC16C745/765 PIC16C745/765 File Address Bank 1 File Address Bank 2 File Address Bank 3 File Address Indirect addr.(*) 00h Indirect addr.(*) 80h Indirect addr.(*) 100h Indirect addr.(*) 180h TMR0 01h OPTION_REG 81h TMR0 101h OPTION_REG 181h PCL 02h PCL 82h PCL 102h PCL 182h STATUS 03h STATUS 83h STATUS 103h STATUS 183h FSR 04h FSR 84h FSR 104h FSR 184h PORTB 106h TRISB 186h PORTA 05h TRISA 85h PORTB 06h TRISB 86h PORTC 07h TRISC 87h 107h 187h PORTD(2) 08h TRISD(2) 88h 108h 188h PORTE(2) 09h TRISE(2) 89h 109h PCLATH 0Ah PCLATH 8Ah PCLATH 10Ah PCLATH INTCON 0Bh INTCON 8Bh INTCON 10Bh INTCON PIR1 0Ch PIE1 8Ch 10Ch 18Ch 105h 185h 189h 18Ah 18Bh PIR2 0Dh PIE2 8Dh 10Dh 18Dh TMR1L 0Eh PCON 8Eh 10Eh 18Eh TMR1H 0Fh 8Fh 10Fh T1CON 10h 90h 110h UIR TMR2 11h 91h 111h UIE 191h T2CON 12h 92h 112h UEIR 192h 13h 93h 113h UEIE 193h 14h 94h 114h USTAT 194h CCPR1L 15h 95h 115h UCTRL 195h CCPR1H 16h 96h 116h UADDR 196h CCP1CON 17h 97h 117h USWSTAT(1) 197h 198h PR2 18Fh 190h RCSTA 18h TXSTA 98h 118h UEP0 TXREG 19h SPBRG 99h 119h UEP1 199h RCREG 1Ah 9Ah 11Ah UEP2 19Ah CCPR2L 1Bh 9Bh 11Bh 19Bh(1) CCPR2H 1Ch 9Ch 11Ch 19Ch(1) CCP2CON 1Dh 9Dh 11Dh 19Dh(1) ADRES 1Eh 9Eh 11Eh 19Eh(1) ADCON0 1Fh ADCON1 9Fh 11Fh 19Fh(1) General Purpose Register 96 Bytes 20h General Purpose Register 80 Bytes A0h General Purpose Register 80 Bytes 120h USB Dual Port Memory 64 Bytes 1A0h 1DFh 1E0h EFh 7Fh accesses 70h-7Fh F0h FFh 16Fh accesses 70h-7Fh 170h 17Fh 1EFh accesses 70h-7Fh 1F0h 1FFh Unimplemented data memory locations, read as `0'. *Not a physical register. Note 1: Reserved registers may contain USB state information. 2: Parallel slave ports (PORTD and PORTE) not implemented on PIC16C745 PIC16C745; always maintain these bits clear. DS41124C-page 16 Preliminary 2000 Microchip Technology Inc. 745cov.book Page 17 Wednesday, August 2, 2000 8:24 AM PIC16C745/765 PIC16C745/765 4.2.2 SPECIAL FUNCTION REGISTERS The Special Function Registers are registers used by the CPU and Peripheral Modules for controlling the desired operation of the device. These registers are implemented as static RAM. TABLE 4-1: Address Name The Special Function Registers can be classified into two sets (core and peripheral). Those registers associated with the "core" functions are described in this section, and those related to the operation of the peripheral features are described in the section of that peripheral feature. SPECIAL FUNCTION REGISTER SUMMARY Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other resets (2) Bank 0 00h INDF(3) Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000 01h TMR0 Timer0 module's register xxxx xxxx uuuu uuuu 02h PCL(3) Program Counter's (PC) Least Significant Byte 03h STATUS(3) 04h FSR(3) IRP(2) RP1(2) RP0 TO 0000 0000 0000 0000 PD Z DC C 0001 1xxx 000q quuu Indirect data memory address pointer 05h PORTA 06h PORTB 07h PORTC 08h PORTD(4) 09h PORTE(4) - - - 0Ah PCLATH(1,3) - - - xxxx xxxx uuuu uuuu - - PORTA Data Latch when written: PORTA pins when read -0x 0000 -0u 0000 PORTB Data Latch when written: PORTB pins when read RC7 RC6 - - xxxx xxxx uuuu uuuu - RC2 RC1 RC0 PORTD Data Latch when written: PORTD pins when read - xx- -xxx uu- -uuu xxxx xxxx uuuu uuuu - RE2 RE1 RE0 Write Buffer for the upper 5 bits of the Program Counter 0Bh INTCON(3) 0Ch PIR1 0Dh PIR2 0Eh TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register 0Fh TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 register 10h T1CON 11h TMR2 12h T2CON - -xxx - -uuu -0 0000 -0 0000 GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u PSPIF(4) ADIF RCIF TXIF USBIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 - - - ­ - - - CCP2IF - -0 - -0 - - xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000 Timer2 module's register - TOUTPS3 -00 0000 -uu uuuu 0000 0000 0000 0000 13h - Unimplemented - - 14h - Unimplemented - - 15h CCPR1L Capture/Compare/PWM Register1 (LSB) 16h CCPR1H Capture/Compare/PWM Register1 (MSB) 17h CCP1CON 18h RCSTA 19h TXREG 1Ah 1Bh xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu - - DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 SPEN RX9 SREN CREN - FERR OERR RX9D -00 0000 -00 0000 0000 -00x 0000 -00x USART Transmit Data Register 0000 0000 0000 0000 RCREG USART Receive Data Register 0000 0000 0000 0000 CCPR2L Capture/Compare/PWM Register2 (LSB) xxxx xxxx uuuu uuuu 1Ch CCPR2H Capture/Compare/PWM Register2 (MSB) 1Dh CCP2CON 1Eh ADRES 1Fh ADCON0 - - xxxx xxxx uuuu uuuu DC2B1 DC2B1 CCP2M3 CCP2M2 CCP2M1 CCP2M0 CHS2 CHS1 CHS0 GO/DONE - ADON A/D Result Register ADCS1 ADCS0 -00 0000 -00 0000 xxxx xxxx uuuu uuuu 0000 00-0 0000 00-0 Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'. Shaded locations are unimplemented, read as `0'. Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC whose contents are transferred to the upper byte of the program counter. 2: Other (non power-up) RESETS include external RESET through MCLR and Watchdog Timer Reset. 3: These registers can be addressed from any bank. 4: The Parallel Slave Port (PORTD and PORTE) is not implemented on the PIC16C745 PIC16C745, always maintain these bits clear. 2000 Microchip Technology Inc. Preliminary DS41124C-page 17 745cov.book Page 18 Wednesday, August 2, 2000 8:24 AM PIC16C745/765 PIC16C745/765 TABLE 4-1: Address Name SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other resets (2) Bank 1 80h INDF(3) 81h OPTION 82h PCL(3) 83h STATUS(3) 84h FSR(3) Addressing this location uses contents of FSR to address data memory (not a physical register) RBPU INTEDG T0CS T0SE PSA PS2 PS1 0000 0000 0000 0000 PS0 Program Counter's (PC) Least Significant Byte IRP RP1 RP0 TO PD Z DC C Indirect data memory address pointer - - 1111 1111 1111 1111 0000 0000 0000 0000 0001 1xxx 000q quuu xxxx xxxx uuuu uuuu PORTA Data Direction Register 85h TRISA 86h TRISB 87h TRISC 88h TRISD(4) 89h TRISE(4) IBF OBF IBOV 8Ah PCLATH(1,3) - - - 8Bh INTCON(3) GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 8Ch PIE1 PSPIE(4) ADIE RCIE TXIE USBIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 8Dh PIE2 - - - - - - - CCP2IE - -0 - -0 8Eh PCON - - - - - - POR BOR - -qq - -uu 8Fh - Unimplemented - - 90h - Unimplemented - - 91h - Unimplemented - - 92h PR2 -11 1111 -11 1111 PORTB Data Direction Register TRISC7 TRISC8 - 1111 1111 1111 1111 - - TRISC2 TRISC1 TRISC0 PORTD Data Direction Register 11- -111 11- -111 1111 1111 1111 1111 PSPMODE - PORTE Data Direction Bits 0000 -111 0000 -111 Write Buffer for the upper 5 bits of the Program Counter -0 0000 -0 0000 Timer2 Period Register 1111 1111 1111 1111 93h - Unimplemented - - 94h - Unimplemented - - 95h - Unimplemented - - 96h - Unimplemented - - 97h - Unimplemented - - 98h TXSTA 99h SPBRG CSRC TX9 TXEN SYNC - BRGH TRMT TX9D Baud Rate Generator Register 0000 -010 0000 -010 0000 0000 0000 0000 9Ah - Unimplemented - - 9Bh - Unimplemented - - 9Ch - Unimplemented - - 9Dh - Unimplemented - - 9Eh - Unimplemented - - - -000 - -000 9Fh ADCON1 - - - - - PCFG2 PCFG1 PCFG0 Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'. Shaded locations are unimplemented, read as `0'. Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC whose contents are transferred to the upper byte of the program counter. 2: Other (non power-up) RESETS include external RESET through MCLR and Watchdog Timer Reset. 3: These registers can be addressed from any bank. 4: The Parallel Slave Port (PORTD and PORTE) is not implemented on the PIC16C745 PIC16C745, always maintain these bits clear. DS41124C-page 18 Preliminary 2000 Microchip Technology Inc. 745cov.book Page 19 Wednesday, August 2, 2000 8:24 AM PIC16C745/765 PIC16C745/765 TABLE 4-1: Address SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other resets (2) Bank 2 100h INDF(3) Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000 101h TMR0 Timer0 module's register xxxx xxxx uuuu uuuu 102h PCL(3) Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000 (3) 103h STATUS 104h FSR(3) IRP RP1 RP0 TO PD Z DC C 0001 1xxx 000q quuu Indirect data memory address pointer xxxx xxxx uuuu uuuu 105h - 106h PORTB 107h - Unimplemented - - 108h - Unimplemented - - 109h - Unimplemented - - 10Ah PCLATH(1,3) 10Bh INTCON(3) 10Ch11Fh - Unimplemented - PORTB Data Latch when written: PORTB pins when read - - - GIE PEIE T0IE Write Buffer for the upper 5 bits of the Program Counter INTE RBIE Unimplemented - xxxx xxxx uuuu uuuu T0IF INTF -0 0000 -0 0000 RBIF 0000 000x 0000 000u - - Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'. Shaded locations are unimplemented, read as `0'. Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC whose contents are transferred to the upper byte of the program counter. 2: Other (non power-up) RESETS include external RESET through MCLR and Watchdog Timer Reset. 3: These registers can be addressed from any bank. 4: The Parallel Slave Port (PORTD and PORTE) is not implemented on the PIC16C745 PIC16C745, always maintain these bits clear. 2000 Microchip Technology Inc. Preliminary DS41124C-page 19 745cov.book Page 20 Wednesday, August 2, 2000 8:24 AM PIC16C745/765 PIC16C745/765 TABLE 4-1: Address SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other resets (2) Bank 3 180h INDF(3) 181h OPTION_REG 182h PCL(3) 183h STATUS(3) 184h FSR(3) 185h 186h Addressing this location uses contents of FSR to address data memory (not a physical register) RBPU INTEDG T0CS T0SE PSA PS2 PS1 0000 0000 0000 0000 PS0 Program Counter's (PC) Least Significant Byte IRP RP1 RP0 TO PD Z DC C Indirect data memory address pointer - 0001 1xxx 000q quuu xxxx xxxx uuuu uuuu Unimplemented TRISB 1111 1111 1111 1111 0000 0000 0000 0000 - PORTB Data Direction Register - 1111 1111 1111 1111 187h - Unimplemented - - 188h - Unimplemented - - 189h - Unimplemented - - (1,3) 18Ah PCLATH 18Bh INTCON(3) 18Ch18Fh - - - - GIE PEIE T0IE Write Buffer for the upper 5 bits of the Program Counter INTE RBIE T0IF INTF -0 0000 -0 0000 RBIF Unimplemented 0000 000x 0000 000u - - 190h UIR - - STALL UIDLE TOK_DNE ACTIVITY UERR USB_RST -00 0000 -00 0000 191h UIE - - STALL UIDLE TOK_DNE ACTIVITY UERR USB_RST -00 0000 -00 0000 192h UEIR BTS_ERR OWN_ERR WRT_ERR BTO_ERR DFN8 CRC16 CRC16 CRC5 PID_ERR 0000 0000 0000 0000 193h UEIE BTS_ERR OWN_ERR WRT_ERR BTO_ERR DFN8 CRC16 CRC16 CRC5 PID_ERR 0000 0000 0000 0000 194h USTAT - - - ENDP1 ENDP0 IN - - -x xx- -u uu- 195h UCTRL - - SEO PKT_DIS DEV_ATT RESUME SUSPND - -x0 000- -xq qqq- 196h UADDR - ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0 -000 0000 -000 0000 197h USWSTAT SWSTAT5 SWSTAT4 SWSTAT3 SWSTAT2 198h UEP0 - - - - EP_CTL_DIS EP_OUT_EN EP_IN_EN EP_STALL - 0000 - 0000 199h UEP1 - - - - EP_CTL_DIS EP_OUT_EN EP_IN_EN EP_STALL - 0000 - 0000 19Ah UEP2 - - - - EP_CTL_DIS EP_OUT_EN EP_IN_EN EP_STALL - 0000 - 0000 19Bh19Fh Reserved SWSTAT7 SWSTAT6 Reserved, do not use. SWSTAT1 SWSTAT0 0000 0000 0000 0000 0000 0000 0000 0000 Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'. Shaded locations are unimplemented, read as `0'. Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC whose contents are transferred to the upper byte of the program counter. 2: Other (non power-up) RESETS include external RESET through MCLR and Watchdog Timer Reset. 3: These registers can be addressed from any bank. 4: The Parallel Slave Port (PORTD and PORTE) is not implemented on the PIC16C745 PIC16C745, always maintain these bits clear. DS41124C-page 20 Preliminary 2000 Microchip Technology Inc. 745cov.book Page 21 Wednesday, August 2, 2000 8:24 AM PIC16C745/765 PIC16C745/765 TABLE 4-2: Address Name 1A0h BD0OST 1A1h BD0OBC 1A2h BD0OAL 1A3h - 1A4h BD0IST 1A5h BD0IBC 1A6h BD0IAL 1A7h 1A8h - BD1OST 1A9h BD1OBC 1AAh BD1OAL 1ABh - 1ACh BD1IST 1ADh BD1IBC 1AEh BD1IAL 1AFh - USB DUAL PORT RAM Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 UOWN UOWN DATA0/1 DATA0/1 PID3 - PID2 - PID1 DTS PID0 BSTALL - - - - - - - - - UOWN UOWN DATA0/1 DATA0/1 PID3 - PID2 - - - - - PID3 - PID2 - Byte Count - - - - PID1 DTS PID0 BSTALL - - - - Byte Count xxxx xxxx uuuu uuuu - UOWN UOWN DATA0/1 DATA0/1 PID3 - PID2 - - - - - PID1 DTS PID0 BSTALL - - - - Byte Count xxxx xxxx uuuu uuuu Reserved - DATA0/1 DATA0/1 PID3 - PID2 - - - - PID1 DTS PID0 BSTALL - - - - Byte Count BD2IST BD2IBC BD2IAL - - 1B6h xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu Reserved 1B5h - xxxx xxxx uuuu uuuu Buffer Address Low 1B4h - xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu Buffer Address Low UOWN UOWN - xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu Reserved BD2OAL - xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu Buffer Address Low 1B2h 1B8h1DFh - - - DATA0/1 DATA0/1 - - - - xxxx xxxx uuuu uuuu UOWN UOWN BD2OBC 1B7h PID0 BSTALL Reserved BD2OST - PID1 DTS Buffer Address Low 1B1h xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu Reserved 1B0h Value on all other resets (1) xxxx xxxx uuuu uuuu Buffer Address Low UOWN UOWN 1B3h Byte Count Value on: POR, BOR DATA0/1 DATA0/1 PID3 - PID2 - - - - PID1 DTS PID0 BSTALL - - Byte Count Buffer Address Low - - - xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu Reserved - 40 byte USB Buffer - xxxx xxxx uuuu uuuu Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'. Shaded locations are unimplemented, read as `0'. Note 1: Other (non power-up) RESETS include external RESET through MCLR and Watchdog Timer Reset. 2000 Microchip Technology Inc. Preliminary DS41124C-page 21 745cov.book Page 22 Wednesday, August 2, 2000 8:24 AM PIC16C745/765 PIC16C745/765 4.2.2.1 STATUS REGISTER For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the STATUS register as 000u u1uu (where u = unchanged). The STATUS register, shown in Register 4-1, contains the arithmetic status of the ALU, the RESET status and the bank select bits for data memory. It is recommended that only BCF, BSF, SWAPF and MOVWF instructions be used to alter the STATUS register. These instructions do not affect the Z, C or DC bits in the STATUS register. For other instructions which do not affect status bits, see the "Instruction Set Summary." The STATUS register can be the destination for any instruction, as with any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not writable. Therefore, the result of an instruction with the STATUS register as destination may be different than intended. Note 1: The C and DC bits operate as borrow and digit borrow bits, respectively, in subtraction. See the SUBLW and SUBWF instructions for examples. REGISTER 4-1: STATUS REGISTER (STATUS: 03h, 83h, 103h, 183h) R/W-0 IRP bit7 bit 7: R/W-0 RP1 R/W-0 RP0 R-1 TO R-1 PD R/W-x Z R/W-x DC R/W-x C(1) bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR reset IRP: Register Bank Select bit (used for indirect addressing) 1 = Bank 2, 3 (100h - 1FFh) 0 = Bank 0, 1 (00h - FFh) bit 6-5: RP: Register Bank Select bits (used for direct addressing) 00 = Bank 0 (00h - 7Fh) 01 = Bank 1 (80h - FFh) 10 = Bank 2 (100h - 17Fh) 11 = Bank 3 (180h - 1FFh) bit 4: TO: Time-out bit 1 = After power-up, CLRWDT instruction, or SLEEP instruction 0 = A WDT time-out occurred bit 3: PD: Power-down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction bit 2: Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero bit 1: DC: Digit carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)(1) 1 = A carry-out from the 4th low order bit of the result occurred 0 = No carry-out from the 4th low order bit of the result bit 0: C: Carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)(1) 1 = A carry-out from the most significant bit of the result occurred 0 = No carry-out from the most significant bit of the result occurred Note 1: For borrow the polarity is reversed. A subtraction is executed by adding the two's complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of the source register. DS41124C-page 22 Preliminary 2000 Microchip Technology Inc. 745cov.book Page 23 Wednesday, August 2, 2000 8:24 AM PIC16C745/765 PIC16C745/765 4.2.2.2 OPTION REGISTER Note: The OPTION_REG register is a readable and writable register, which contains various control bits to configure the TMR0/WDT prescaler, the external INT Interrupt, TMR0 and the weak pull-ups on PORTB. REGISTER 4-2: R/W-1 RBPU To achieve a 1:1 prescaler assignment for the TMR0 register, assign the prescaler to the Watchdog Timer. OPTION REGISTER (OPTION_REG: 81h, 181h) R/W-1 INTEDG R/W-1 T0CS R/W-1 T0SE R/W-1 PSA R/W-1 PS2 R/W-1 PS1 bit7 R/W-1 PS0 bit0 bit 7: RBPU: PORTB Pull-up Enable bit 1 = PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values bit 6: INTEDG: Interrupt Edge Select bit 1 = Interrupt on rising edge of RB0/INT pin 0 = Interrupt on falling edge of RB0/INT pin bit 5: T0CS: TMR0 Clock Source Select bit 1 = Transition on RA4/T0CKI pin 0 = Internal instruction cycle clock (CLKOUT) bit 4: T0SE: TMR0 Source Edge Select bit 1 = Increment on high-to-low transition on RA4/T0CKI pin 0 = Increment on low-to-high transition on RA4/T0CKI pin bit 3: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR reset PSA: Prescaler Assignment bit 1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the Timer0 module bit 2-0: PS: Prescaler Rate Select bits Bit Value 000 001 010 011 100 101 110 111 TMR0 Rate 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 2000 Microchip Technology Inc. WDT Rate 1:1 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 Preliminary DS41124C-page 23 745cov.book Page 24 Wednesday, August 2, 2000 8:24 AM PIC16C745/765 PIC16C745/765 4.2.2.3 INTCON REGISTER Note: The INTCON register is a readable and writable register, which contains various enable and flag bits for the TMR0 register overflow, RB Port change and external RB0/INT pin interrupts. Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. REGISTER 4-3: INTERRUPT CONTROL REGISTER (INTCON: 10Bh, 18Bh) R/W-0 GIE bit7 R/W-0 PEIE R/W-0 T0IE R/W-0 INTE R/W-0 RBIE R/W-0 T0IF R/W-0 INTF R/W-x RBIF bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR reset bit 7: GIE: Global Interrupt Enable bit 1 = Enables all un-masked interrupts 0 = Disables all interrupts bit 6: PEIE: Peripheral Interrupt Enable bit 1 = Enables all un-masked peripheral interrupts 0 = Disables all peripheral interrupts bit 5: T0IE: TMR0 Overflow Interrupt Enable bit 1 = Enables the TMR0 interrupt 0 = Disables the TMR0 interrupt bit 4: INTE: RB0/INT External Interrupt Enable bit 1 = Enables the RB0/INT external interrupt 0 = Disables the RB0/INT external interrupt bit 3: RBIE: RB Port Change Interrupt Enable bit 1 = Enables the RB port change interrupt 0 = Disables the RB port change interrupt bit 2: T0IF: TMR0 Overflow Interrupt Flag bit 1 = TMR0 register has overflowed (must be cleared in software) 0 = TMR0 register did not overflow bit 1: INTF: RB0/INT External Interrupt Flag bit 1 = The RB0/INT external interrupt occurred (must be cleared in software) 0 = The RB0/INT external interrupt did not occur bit 0: RBIF: RB Port Change Interrupt Flag bit 1 = At least one of the RB pins changed state (must be cleared in software) 0 = None of the RB pins have changed state DS41124C-page 24 Preliminary 2000 Microchip Technology Inc. 745cov.book Page 25 Wednesday, August 2, 2000 8:24 AM PIC16C745/765 PIC16C745/765 4.2.2.4 PIE1 REGISTER Note: This register contains the individual enable bits for the peripheral interrupts. Bit PEIE (INTCON) must be set to enable any peripheral interrupt. REGISTER 4-4: PERIPHERAL INTERRUPT ENABLE1 REGISTER (PIE1: 8Ch) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PSPIE(1) ADIE RCIE TXIE USBIE CCP1IE R/W-0 R/W-0 TMR2IE TMR1IE bit7 bit0 bit 7: PSPIE(1): Parallel Slave Port Read/Write Interrupt Enable bit 1 = Enables the PSP read/write interrupt 0 = Disables the PSP read/write interrupt bit 6: ADIE: A/D Converter Interrupt Enable bit 1 = Enables the A/D interrupt 0 = Disables the A/D interrupt bit 5: RCIE: USART Receive Interrupt Enable bit 1 = Enables the USART receive interrupt 0 = Disables the USART receive interrupt bit 4: TXIE: USART Transmit Interrupt Enable bit 1 = Enables the USART transmit interrupt 0 = Disables the USART transmit interrupt bit 3: USBIE: Universal Serial Bus Interrupt Enable bit 1 = Enables the USB interrupt 0 = Disables the USB interrupt bit 2: CCP1IE: CCP1 Interrupt Enable bit 1 = Enables the CCP1 interrupt 0 = Disables the CCP1 interrupt bit 1: TMR2IE: TMR2 to PR2 Match Interrupt Enable bit 1 = Enables the TMR2 to PR2 match interrupt 0 = Disables the TMR2 to PR2 match interrupt bit 0: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR reset TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt Note 1: Parallel slave ports not implemented on the PIC16C745 PIC16C745; always maintain this bit clear. 2000 Microchip Technology Inc. Preliminary DS41124C-page 25 745cov.book Page 26 Wednesday, August 2, 2000 8:24 AM PIC16C745/765 PIC16C745/765 4.2.2.5 PIR1 REGISTER Note: This register contains the individual flag bits for the peripheral interrupts. Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. REGISTER 4-5: PERIPHERAL INTERRUPT REGISTER1 (PIR1: 0Ch) R/W-0 R/W-0 R-0 R-0 R/W-0 R/W-0 PSPIF(1) ADIF RCIF TXIF USBIF CCP1IF R/W-0 R/W-0 TMR2IF TMR1IF bit7 bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR reset bit 7: PSPIF(1): Parallel Slave Port Read/Write Interrupt Flag bit 1 = A read or a write operation has taken place (must be cleared in software) 0 = No read or write has occurred bit 6: ADIF: A/D Converter Interrupt Flag bit 1 = An A/D conversion completed (must be cleared in software) 0 = The A/D conversion is not complete bit 5: RCIF: USART Receive Interrupt Flag bit 1 = The USART receive buffer is full (clear by reading RCREG) 0 = The USART receive buffer is empty bit 4: TXIF: USART Transmit Interrupt Flag bit 1 = The USART transmit buffer is empty (clear by writing to TXREG) 0 = The USART transmit buffer is full bit 3: USBIF: Universal Serial Bus (USB) Interrupt Flag 1 = A USB interrupt condition has occurred. The specific cause can be found by examining the contents of the UIR and UIE registers. 0 = No USB interrupt conditions that are enabled have occurred. bit 2: CCP1IF: CCP1 Interrupt Flag bit Capture Mode 1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred Compare Mode 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred PWM Mode Unused in this mode bit 1: TMR2IF: TMR2 to PR2 Match Interrupt Flag bit 1 = TMR2 to PR2 match occurred (must be cleared in software) 0 = No TMR2 to PR2 match occurred bit 0: TMR1IF: TMR1 Overflow Interrupt Flag bit 1 = TMR1 register overflowed (must be cleared in software) 0 = TMR1 register did not overflow Note 1: Parallel slave ports not implemented on the PIC16C745 PIC16C745; always maintain this bit clear. DS41124C-page 26 Preliminary 2000 Microchip Technology Inc. 745cov.book Page 27 Wednesday, August 2, 2000 8:24 AM PIC16C745/765 PIC16C745/765 4.2.2.6 PIE2 REGISTER This register contains the individual enable bit for the CCP2 peripheral interrupt. REGISTER 4-6: PERIPHERAL INTERRUPT ENABLE 2 REGISTER (PIE2: 8Dh) U-0 - bit7 U-0 - U-0 - U-0 - U-0 - U-0 - U-0 - R/W-0 CCP2IE bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR reset bit 7-1: Unimplemented: Read as '0' bit 0: 4.2.2.7 CCP2IE: CCP2 Interrupt Enable bit 1 = Enables the CCP2 interrupt 0 = Disables the CCP2 interrupt PIR2 REGISTER This register contains the CCP2 interrupt flag bit. Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. REGISTER 4-7: U-0 - bit7 PERIPHERAL INTERRUPT REGISTER 2 (PIR2: 0Dh) U-0 - U-0 - U-0 - U-0 - U-0 - U-0 - R/W-0 CCP2IF bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR reset bit 7-1: Unimplemented: Read as '0' bit 0: CCP2IF: CCP2 Interrupt Flag bit Capture Mode 1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred Compare Mode 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred PWM Mode Unused 2000 Microchip Technology Inc. Preliminary DS41124C-page 27 745cov.book Page 28 Wednesday, August 2, 2000 8:24 AM PIC16C745/765 PIC16C745/765 4.2.2.8 PCON REGISTER Note: The Power Control (PCON) register contains flag bits to allow differentiation between a Power-on Reset (POR), a Brown-out Reset (BOR), a Watchdog Reset (WDT) and an external MCLR Reset. REGISTER 4-8: U-0 - U-0 - BOR is unknown on POR. It must be set by the user and checked on subsequent RESETS to see if BOR is clear, indicating a brown-out has occurred. POWER CONTROL REGISTER REGISTER (PCON: 8Eh) U-0 - U-0 - U-0 - U-0 - R/W-0 POR bit7 R/W-q BOR bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR reset bit 7-2: Unimplemented: Read as '0' bit 1: POR: Power-on Reset Status bit 1 = No Power-on Reset occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) bit 0: BOR: Brown-out Reset Status bit 1 = No Brown-out Reset occurred 0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs) DS41124C-page 28 Preliminary 2000 Microchip Technology Inc. 745cov.book Page 29 Wednesday, August 2, 2000 8:24 AM PIC16C745/765 PIC16C745/765 4.3 PCL and PCLATH The program counter (PC) is 13-bits wide. The low byte comes from the PCL register, which is a readable and writable register. The upper bits (PC) are not readable, but are indirectly writable through the PCLATH register. On any RESET, the upper bits of the PC will be cleared. Figure 4-3 shows the two situations for the loading of the PC. The upper example in the figure shows how the PC is loaded on a write to PCL (PCLATH PCH). The lower example in the figure shows how the PC is loaded during a CALL or GOTO instruction (PCLATH PCH). FIGURE 4-3: LOADING OF PC IN DIFFERENT SITUATIONS PCH PCL 12 8 7 0 PC 5 8 PCLATH Instruction with PCL as Destination ALU PCLATH PCH 12 11 10 7 0 PC GOTO,CALL 2 PCLATH 2: There are no instructions/mnemonics called PUSH or POP. These are actions that occur from the execution of the CALL, RETURN, RETLW, and RETFIE instructions, or the vectoring to an interrupt address. 4.4 Program Memory Paging PIC16CXX PIC16CXX devices are capable of addressing a continuous 8K word block of program memory. The CALL and GOTO instructions provide only 11 bits of address to allow branching within any 2K program memory page. When doing a CALL or GOTO instruction, the upper 2 bits of the address are provided by PCLATH. When doing a CALL or GOTO instruction, the user must ensure that the page select bits are programmed so that the desired program memory page is addressed. If a return from a CALL instruction (or interrupt) is executed, the entire 13-bit PC is pushed onto the stack. Therefore, manipulation of the PCLATH bits is not required for the return instructions (which POPs the address from the stack). Example 4-1 shows the calling of a subroutine in page 1 of the program memory. This example assumes that PCLATH is saved and restored by the interrupt service routine (if interrupts are used). PCL 8 Note 1: There are no status bits to indicate stack overflow or stack underflow conditions. 11 Opcode EXAMPLE 4-1: PCLATH 4.3.1 COMPUTED GOTO A computed GOTO is accomplished by adding an offset to the program counter (ADDWF PCL). When doing a table read using a computed GOTO method, care should be exercised if the table location crosses a PCL memory boundary (each 256 byte block). Refer to the application note "Implementing a Table Read" (AN556 AN556). 4.3.2 CALL OF A SUBROUTINE IN PAGE 1 FROM PAGE 0 ORG 0x500 BSF PCLATH,3 CALL SUB1_P1 : : ORG 0x900 SUB1_P1 : : : RETURN ;Select page 1 (800h-FFFh) ;Call subroutine in ;page 1 (800h-FFFh) ;page 1 (800h-FFFh) ;called subroutine ;page 1 (800h-FFFh) ;return to Call subroutine ;in page 0 (000h-7FFh) STACK The PIC16C745/765 PIC16C745/765 family has an 8-level deep x 13bit wide hardware stack. The stack space is not part of either program or data space and the stack pointer is not readable or writable. The PC is PUSHed onto the stack when a CALL instruction is executed or an interrupt causes a branch. The stack is POPed in the event of a RETURN,RETLW or a RETFIE instruction execution. PCLATH is not affected by a PUSH or POP operation. The stack operates as a circular buffer. This means that after the stack has been PUSHed eight times, the ninth push overwrites the value that was stored from the first push. The tenth push overwrites the second push (and so on). 2000 Microchip Technology Inc. Preliminary DS41124C-page 29 745cov.book Page 30 Wednesday, August 2, 2000 8:24 AM PIC16C745/765 PIC16C745/765 4.5 Indirect Addressing, INDF and FSR Registers EXAMPLE 4-2: The INDF register is not a physical register. Addressing the INDF register will cause indirect addressing. movlw movwf clrf incf btfss goto NEXT Indirect addressing is possible by using the INDF register. Any instruction using the INDF register actually accesses the register pointed to by the File Select Register, FSR. Reading the INDF register itself indirectly (FSR = '0') will read 00h. Writing to the INDF register indirectly results in a no-operation (although status bits may be affected). An effective 9-bit address is obtained by concatenating the 8-bit FSR register and the IRP bit (STATUS), as shown in Figure 4-4. INDIRECT ADDRESSING 0x20 FSR INDF FSR,F FSR,4 NEXT ;initialize pointer ;to RAM ;clear INDF register ;inc pointer ;all done? ;no clear next CONTINUE : ;yes continue A simple program to clear RAM locations 20h-2Fh using indirect addressing is shown in Example 4-2. FIGURE 4-4: DIRECT/INDIRECT ADDRESSING Direct Addressing Indirect Addressing from opcode RP 6 bank select location select 0 IRP 7 bank select 00 01 10 FSR register 0 location select 11 00h 80h 100h 180h 7Fh FFh 17Fh 1FFh Data Memory Bank 0 Note: Bank 1 Bank 2 Bank 3 For register file map detail see Figure 4-2. DS41124C-page 30 Preliminary 2000 Microchip Technology Inc. 745cov.book Page 31 Wednesday, August 2, 2000 8:24 AM PIC16C745/765 PIC16C745/765 5.0 I/O PORTS FIGURE 5-1: Some pins for these I/O ports are multiplexed with an alternate function for the peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin. Data Bus 5.1 WR Port PORTA and TRISA Registers PORTA is a 6-bit latch. BLOCK DIAGRAM OF RA AND RA5 PINS D Q VDD Q CK P Data Latch The RA4/T0CKI pin is a Schmitt Trigger input and an open drain output. All other RA port pins have TTL input levels and full CMOS output drivers. All pins have data direction bits (TRIS registers), which can configure these pins as output or input. D WR TRIS Setting a TRISA register bit puts the corresponding output driver in a hi-impedance mode. Clearing a bit in the TRISA register puts the contents of the output latch on the selected pin(s). VSS Q CK Pin RA4 is multiplexed with the Timer0 module clock input to become the RA4/T0CKI pin. On the PIC16C745/765 PIC16C745/765, PORTA pins are multiplexed with analog inputs and analog VREF input. The operation of each pin is selected by clearing/setting the control bits in the ADCON1 register (A/D Control Register1). Analog Input Mode TRIS Latch Q RD Port To A/D Converter FIGURE 5-2: BSF MOVLW MOVWF MOVLW STATUS, RP0 0x06 ADCON1 0xCF MOVWF TRISA ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; BLOCK DIAGRAM OF RA4/T0CKI PIN VDD Data Bus WR Port D Q CK Q N Data Latch D INITIALIZING PORTA (PIC16C745/765 PIC16C745/765) STATUS, RP1 STATUS, RP0 PORTA D EN The TRISA register controls the direction of the RA pins, even when they are being used as analog inputs. The user must ensure the bits in the TRISA register are maintained set when using them as analog inputs. BCF BCF CLRF Schmitt Trigger Input Buffer RD TRIS On all RESETS, pins with analog and digital functions are configured as analog inputs. EXAMPLE 5-1: WR TRIS Q CK Q Initialize PORTA by clearing output data latches Select Bank 1 Configure all pins as digital inputs Value used to initialize data direction Set RA as inputs RA as outputs TRISA are always read as '0'. Preliminary I/O pin VSS Schmitt Trigger Input Buffer TRIS Latch 2000 Microchip Technology Inc. I/O Pin N Q Reading the PORTA register reads the status of the pins, whereas writing to it will write to the port latch. All write operations are read-modify-write operations. Therefore, a write to a port implies that the port pins are read, the value is modified, and then written to the port data latch. Note: VDD RD TRIS Q D EN EN RD Port TMR0 Clock Input DS41124C-page 31 745cov.book Page 32 Wednesday, August 2, 2000 8:24 AM PIC16C745/765 PIC16C745/765 TABLE 5-1: PORTA FUNCTIONS Input Type Output Type RA0 ST CMOS AN0 AN - RA1 ST CMOS AN1 AN - RA2 Name ST CMOS Function RA0/AN0 RA1/AN1 RA2/AN2 AN2 AN - RA3 ST CMOS Description Bi-directional I/O A/D Input Bi-directional I/O A/D Input Bi-directional I/O A/D Input Bi-directional I/O AN3 A/D Input - A/D Positive Reference Bi-directional I/O RA4 ST OD ST - RA5 ST RA5/AN4 Timer 0 Clock Input Bi-directional I/O AN4 AN OD = open drain, ST = Schmitt Trigger TABLE 5-2: Address - AN T0CKI RA4/T0CKI Legend: AN VREF RA3/AN3/VREF - A/D Input SUMMARY OF REGISTERS ASSOCIATED WITH PORTA Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other resets RA5 RA4 RA3 RA2 RA1 RA0 -0x 0000 -0u 0000 -11 1111 -11 1111 PCFG2 PCFG1 PCFG0 - -000 - -000 05h PORTA - - 85h TRISA - - 9Fh ADCON1 - - PORTA Data Direction Register - - - Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by PORTA. DS41124C-page 32 Preliminary 2000 Microchip Technology Inc. 745cov.book Page 33 Wednesday, August 2, 2000 8:24 AM PIC16C745/765 PIC16C745/765 5.2 PORTB and TRISB Registers PORTB is an 8-bit wide bi-directional port. The corresponding data direction register is TRISB. Setting a bit in the TRISB register puts the corresponding output driver in a hi-impedance input mode. Clearing a bit in the TRISB register puts the contents of the output latch on the selected pin(s). Each of the PORTB pins has a weak internal pull-up. A single control bit can turn on all the pull-ups. This is performed by clearing bit RBPU (OPTION_REG). The weak pull-up is automatically turned off when the port pin is configured as an output. The pull-ups are disabled on a Power-on Reset. FIGURE 5-3: BLOCK DIAGRAM OF RB PINS VDD RBPU(1) Data Bus WR Port This interrupt-on-mismatch feature, together with software configureable pull-ups on these four pins, allow easy interface to a keypad and make it possible for wake-up on key depression. Refer to the Embedded Control Handbook, "Implementing Wake-Up on Key Stroke" (AN552 AN552). The interrupt-on-change feature is recommended for wake-up on key depression operation and operations where PORTB is only used for the interrupt-on-change feature. Polling of PORTB is not recommended while using the interrupt-on-change feature. RB0/INT is an external interrupt input pin and is configured using the INTEDG bit (OPTION_REG). RB0/INT is discussed in detail in Section 13.5.1. VDD weak P pull-up FIGURE 5-4: BLOCK DIAGRAM OF RB PINS Data Latch D Q I/O pin CK TRIS Latch D Q WR TRIS A mismatch condition will continue to set flag bit RBIF. Reading PORTB will end the mismatch condition, and allow flag bit RBIF to be cleared. VDD RBPU(1) Data Bus TTL Input Buffer CK WR Port VDD weak P pull-up Data Latch D Q I/O pin CK TRIS Latch D RD TRIS WR TRIS Q RD Port D Q TTL Input Buffer CK EN RD TRIS RB0/INT Latch Q Schmitt Trigger Buffer RD Port Set RBIF ST Buffer D EN RD Port Q1 Note 1: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION_REG). From other RB pins Four of PORTB's pins, RB, have an interrupt-onchange feature. Only pins configured as inputs can cause this interrupt to occur (i.e., any RB pin configured as an output is excluded from the interrupt-onchange comparison). The input pins (of RB) are compared with the value latched on the last read of PORTB. The "mismatch" outputs of RB are OR'ed together to generate the RB Port Change Interrupt with flag bit RBIF (INTCON). Q D RD Port EN Q3 RB in serial programming mode Note 1: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION_REG). This interrupt can wake the device from SLEEP. The user, in the interrupt service routine, can clear the interrupt in the following manner: a) b) Any read or write of PORTB. This will end the mismatch condition. Clear flag bit RBIF. 2000 Microchip Technology Inc. Preliminary DS41124C-page 33 745cov.book Page 34 Wednesday, August 2, 2000 8:24 AM PIC16C745/765 PIC16C745/765 TABLE 5-3: PORTB FUNCTIONS Function Input Type Output Type RB0 TTL CMOS INT ST - RB1 RB1 TTL CMOS Bi-directional I/O RB2 RB2 TTL CMOS Bi-directional I/O RB3 RB3 TTL CMOS Bi-directional I/O RB4 RB4 TTL CMOS Bi-directional I/O with Interrupt-on-Change RB5 RB5 TTL CMOS Bi-directional I/O with Interrupt-on-Change RB6 TTL CMOS Bi-directional I/O with Interrupt-on-Change ICSPC ST RB7 TTL CMOS Bi-directional I/O with Interrupt-on-Change ICSPD ST OD = open drain, ST = Schmitt Trigger CMOS In-Circuit Serial Programming Data I/O Name RB0/INT RB6/ICSPC RB7/ICSPD Legend: TABLE 5-4: Address Description Bi-directional I/O Interrupt In-Circuit Serial Programming Clock input SUMMARY OF REGISTERS ASSOCIATED WITH PORTB Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx uuuu uuuu 1111 1111 1111 1111 1111 1111 1111 1111 06h, 106h PORTB 86h, 186h TRISB PORTB Data Direction Register 81h, 181h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 Value on all other resets Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTB. DS41124C-page 34 Preliminary 2000 Microchip Technology Inc. 745cov.book Page 35 Wednesday, August 2, 2000 8:24 AM PIC16C745/765 PIC16C745/765 5.3 FIGURE 5-5: PORTC and TRISC Registers PORTC is a 5-bit bi-directional port. Each pin is individually configureable as an input or output through the TRISC register. PORTC is multiplexed with several peripheral functions (Table 5-5). PORTC pins have Schmitt Trigger input buffers. When enabling peripheral functions, care should be taken in defining TRIS bits for each PORTC pin. Some peripherals override the TRIS bit to make a pin an output, while other peripherals override the TRIS bit to make a pin an input. Since the TRIS bit override is in effect while the peripheral is enabled, read-modifywrite instructions (BSF, BCF, XORWF) with TRISC as destination should be avoided. The user should refer to the corresponding peripheral section for the correct TRIS bit settings. PORTC BLOCK DIAGRAM Port/Peripheral Select(1) Peripheral Data Out Data Bus WR Port VDD 0 D Q 1 CK VDD P Q Data Latch D WR TRIS CK I/O pin Q Q N TRIS Latch VSS Schmitt Trigger RD TRIS Peripheral OE(2) RD Port Peripheral Input Q D EN Note 1: Port/Peripheral select signal selects between port data and peripheral output. 2: Peripheral OE (output enable) is only activated if peripheral select is active. 2000 Microchip Technology Inc. Preliminary DS41124C-page 35 745cov.book Page 36 Wednesday, August 2, 2000 8:24 AM PIC16C745/765 PIC16C745/765 TABLE 5-5: PORTC FUNCTIONS Function Name Input Type Output Type RC0 ST CMOS T1OSO - Xtal T1CKI RC0/T1OSO/T1CKI ST - Description Bi-directional I/O T1 Oscillator Output T1 Clock Input RC1 ST CMOS T1OSI Xtal - T1 Oscillator Input CCP2 RC1/T1OSI/CCP2 Bi-directional I/O - - Capture In/Compare Out/PWM Out 2 RC2 ST CMOS CCP1 - - RC6 RC2/CCP1 ST CMOS Bi-directional I/O USART Async Transmit RC6/TX/CK Bi-directional I/O Capture In/Compare Out/PWM Out 1 TX Legend: CMOS ST CMOS USART Master Out/Slave In Clock RC7 ST CMOS Bi-directional I/O RX RC7/RX/DT - CK ST - DT ST OD = open drain, ST = Schmitt Trigger TABLE 5-6: CMOS USART Async Receive USART Data I/O SUMMARY OF REGISTERS ASSOCIATED WITH PORTC Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other resets 07h PORTC RC7 RC6 - - - RC2 RC1 RC0 xx- -xxx uu- -uuu 87h TRISC TRISC7 TRISC6 - - - TRISC2 TRISC1 TRISC0 11- -111 11- -111 Address Legend: x = unknown, u = unchanged. DS41124C-page 36 Preliminary 2000 Microchip Technology Inc. 745cov.book Page 37 Wednesday, August 2, 2000 8:24 AM PIC16C745/765 PIC16C745/765 5.4 PORTD and TRISD Registers FIGURE 5-6: PORTD BLOCK DIAGRAM VDD Note: The PIC16C745 PIC16C745 does not provide PORTD. The PORTD and TRISD registers are reserved. Always maintain these bits clear. Data Bus WR Port PORTD is an 8-bit port with Schmitt Trigger input buffers. Each pin is individually configured as an input or output. D Q I/O pin CK Data Latch PORTD can be configured as an 8-bit wide microprocessor port (parallel slave port) by setting control bit PSPMODE (TRISE). In this mode, the input buffers are TTL. D WR TRIS Q Schmitt Trigger Input Buffer CK TRIS Latch RD TRIS Q D EN EN RD Port TABLE 5-7: PORTD FUNCTIONS Function Name RD0 TTL CMOS TTL - RD1 RD1/PSP1 TTL CMOS PSP1 - TTL CMOS PSP2 TTL - RD3 RD3/PSP3 TTL RD2 RD2/PSP2 TTL CMOS PSP3 - TTL CMOS PSP4 TTL - RD5 RD5/PSP5 TTL RD4 RD4/PSP4 TTL CMOS PSP5 TTL - RD6 RD6/PSP6 TTL CMOS PSP6 TTL - RD7 RD7/PSP7 Note 1: Output Type PSP0 RD0/PSP0 Legend: Input Type TTL CMOS PSP7 TTL OD = open drain, ST = Schmitt Trigger - Description Bi-directional I/O(1) Parallel Slave Port Data Input(1) Bi-directional I/O(1) Parallel Slave Port Data Input(1) Bi-directional I/O(1) Parallel Slave Port Data Input(1) Bi-directional I/O(1) Parallel Slave Port Data Input(1) Bi-directional I/O(1) Parallel Slave Port Data Input(1) Bi-directional I/O(1) Parallel Slave Port Data Input(1) Bi-directional I/O(1) Parallel Slave Port Data Input(1) Bi-directional I/O(1) Parallel Slave Port Data Input(1) PIC16C765 PIC16C765 only. TABLE 5-8: SUMMARY OF REGISTERS ASSOCIATED WITH PORTD Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other resets 08h PORTD(1) RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxx xxxx uuuu uuuu 88h TRISD(1) 1111 1111 1111 1111 Address PORTD Data Direction Register Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by PORTD. Note 1: PIC16C765 PIC16C765 only. 2000 Microchip Technology Inc. Preliminary DS41124C-page 37 745cov.book Page 38 Wednesday, August 2, 2000 8:24 AM PIC16C745/765 PIC16C745/765 5.5 PORTE and TRISE Registers FIGURE 5-7: PORTE BLOCK DIAGRAM VDD Note 1: The PIC16C745 PIC16C745 does not provide PORTE. The PORTE and TRISE registers are reserved. Always maintain these bits clear. Data Bus WR Port PORTE has three pins, RE0/RD/AN5, RE1/WR/AN6 and RE2/CS/AN7, which are individually configured as inputs or outputs. These pins have Schmitt Trigger input buffers. D Q I/O pin CK Data Latch D WR TRIS I/O PORTE becomes control inputs for the microprocessor port when bit PSPMODE (TRISE) is set. In this mode, the user must make sure that the TRISE bits are set (pins are configured as digital inputs) and that register ADCON1 is configured for digital I/O. In this mode, the input buffers are TTL. Q Schmitt Trigger Input Buffer CK TRIS Latch RD TRIS Register 5-1 shows the TRISE register, which also controls the parallel slave port operation. Q D EN EN PORTE pins may be multiplexed with analog inputs (PIC16C765 PIC16C765 only). The operation of these pins is selected by control bits in the ADCON1 register. When selected as an analog input, these pins will read as '0's. RD Port To A/D Converter TRISE controls the direction of the RE pins, even when they are being used as analog inputs. The user must make sure to keep the pins configured as inputs when using them as analog inputs. TRISE bits are used to control the parallel slave port. Note: On a Power-on Reset, these pins are configured as analog inputs. TABLE 5-9: PORTE(1) FUNCTIONS Name Function Input Type Output Type Description RE0 ST CMOS RD TTL - AN5 AN - RE1 ST CMOS WR TTL - AN6 AN - RE2 ST CMOS CS TTL - Parallel Slave Port Data Input(1) AN7 AN OD = open drain, ST = Schmitt Trigger - A/D Input(1) RE0/RD/AN5 RE1/WR/AN6 RE2/CS/AN7 Legend: Note 1: Bi-directional I/O (1) Parallel Slave Port Control Input(1) A/D Input(1) Bi-directional I/O(1) Parallel Slave Port Control Input(1) A/D Input(1) Bi-directional I/O(1) PIC16C765 PIC16C765 only. DS41124C-page 38 Preliminary 2000 Microchip Technology Inc. 745cov.book Page 39 Wednesday, August 2, 2000 8:24 AM PIC16C745/765 PIC16C745/765 REGISTER 5-1: PORTE DATA DIRECTION CONTROL REGISTER(1) (TRISE: 89h) R-0 R-0 R/W-0 R/W-0 U-0 R/W-1 R/W-1 R/W-1 IBF OBF IBOV PSPMODE - TRISE2 TRISE1 TRISE0 bit7 bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR reset bit 7 : IBF: Input Buffer Full Status bit 1 = A word has been received and is waiting to be read by the CPU 0 = No word has been received bit 6: OBF: Output Buffer Full Status bit 1 = The output buffer still holds a previously written word 0 = The output buffer has been read bit 5: IBOV: Input Buffer Overflow Detect bit (in microprocessor mode) 1 = A write occurred when a previously input word has not been read (must be cleared in software) 0 = No overflow occurred bit 4: PSPMODE: Parallel Slave Port Mode Select bit 1 = Parallel slave port mode 0 = General purpose I/O mode bit 3: Unimplemented: Read as '0' PORTE Data Direction Bits bit 2: TRISE2: Direction Control bit for pin RE2/CS/AN7 1 = Input 0 = Output bit 1: TRISE1: Direction Control bit for pin RE1/WR/AN6 1 = Input 0 = Output bit 0: TRISE0: Direction Control bit for pin RE0/RD/AN5 1 = Input 0 = Output Note 1: PIC16C765 PIC16C765 only. TABLE 5-10: Address 09h SUMMARY OF REGISTERS ASSOCIATED WITH PORTE Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other resets PORTE(1) - - - - - RE2 RE1 RE0 - -xxx - -uuu (1) 89h TRISE IBF OBF IBOV PSPMODE - PORTE Data Direction Bits 0000 -111 0000 -111 9Fh ADCON1 - - - - - PCFG2 - -000 - -000 PCFG1 PCFG0 Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by PORTE. Note 1: PIC16C765 PIC16C765 only. 2000 Microchip Technology Inc. Preliminary DS41124C-page 39 745cov.book Page 40 Wednesday, August 2, 2000 8:24 AM PIC16C745/765 PIC16C745/765 5.6 Note: Parallel Slave Port (PSP) The PIC16C745 PIC16C745 does not provide a parallel slave port. The PORTD, PORTE, TRISD and TRISE registers are reserved. Always maintain these bits clear. PORTD operates as an 8-bit wide Parallel Slave Port (PSP), or microprocessor port when control bit PSPMODE (TRISE) is set. In slave mode, it is asynchronously readable and writable by the external world through RD control input pin RE0/RD/AN5 and WR control input pin RE1/WR/AN6. It can directly interface to an 8-bit microprocessor data bus. The external microprocessor can read or write the PORTD latch as an 8-bit latch. Setting bit PSPMODE enables port pin RE0/RD/AN5 to be the RD input, RE1/ WR/AN6 to be the WR input and RE2/CS/AN7 to be the CS (chip select) input. For this functionality, the corresponding data direction bits of the TRISE register (TRISE) must be configured as inputs (set) and the A/D port configuration bits PCFG (ADCON1) must be set, which will configure pins RE as digital I/O. There are actually two 8-bit latches; one for data-out (from the PICmicro® microcontroller) and one for data input. The user writes 8-bit data to PORTD data latch and reads data from the port pin latch (note that they have the same address). In this mode, the TRISD register is ignored, since the microprocessor is controlling the direction of data flow. An interrupt is generated and latched into flag bit PSPIF when a read or write operation is completed. PSPIF must be cleared by the user in firmware and the interrupt can be disabled by clearing the interrupt enable bit PSPIE (PIE1). FIGURE 5-8: PORTD AND PORTE BLOCK DIAGRAM (PARALLEL SLAVE PORT) VDD Data Bus D WR Port Q RDx pin CK TTL Q RD Port D EN EN One bit of PORTD Set interrupt flag A write to the PSP occurs when both the CS and WR lines are first detected low. When either the CS or WR lines become high (level triggered), then the Input Buffer Full (IBF) status flag bit (TRISE) is set on the Q4 clock cycle, following the next Q2 cycle, to signal the write is complete (Figure 5-9). The interrupt flag bit PSPIF (PIR1) is also set on the same Q4 clock cycle. IBF can only be cleared by reading the PORTD input latch. The Input Buffer Overflow (IBOV) status flag bit (TRISE) is set if a second write to the PSP is attempted when the previous byte has not been read out of the buffer. PSPIF (PIR1) Read TTL RD Chip Select TTL CS Write TTL WR A read from the PSP occurs when both the CS and RD lines are first detected low. The Output Buffer Full (OBF) status flag bit (TRISE) is cleared immediately (Figure 5-10) indicating that the PORTD latch is waiting to be read by the external bus. When either the CS or RD pin becomes high (level triggered), the interrupt flag bit PSPIF is set on the Q4 clock cycle, following the next Q2 cycle, indicating that the read is complete. OBF remains low until data is written to PORTD by the user firmware. When not in PSP mode, the IBF and OBF bits are held clear. However, if flag bit IBOV was previously set, it must be cleared in firmware. DS41124C-page 40 Preliminary 2000 Microchip Technology Inc. 745cov.book Page 41 Wednesday, August 2, 2000 8:24 AM PIC16C745/765 PIC16C745/765 FIGURE 5-9: PARALLEL SLAVE PORT WRITE WAVEFORMS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q4 Q1 Q2 Q3 Q4 CS WR RD PORTD IBF OBF PSPIF FIGURE 5-10: PARALLEL SLAVE PORT READ WAVEFORMS Q1 Q2 Q3 Q4 Q1 Q2 Q3 CS WR RD PORTD IBF OBF PSPIF TABLE 5-11: Address REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT Name Bit 7 Bit 6 Bit 5 Bit 4 Value on: POR, BOR Value on all other resets xxxx xxxx uuuu uuuu - -xxx - -uuu PORTE Data Direction Bits 0000 -111 0000 -111 Bit 3 Bit 2 Bit 1 Bit 0 RE2 RE1 RE0 08h PORTD(2) Port data latch when written: Port pins when read 09h PORTE(2) - - - - - 89h TRISE(2) IBF OBF IBOV PSPMODE - 0Ch PIR1 PSPIF(1) ADIF RCIF TXIF USBIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 8Ch PIE1 PSPIE(1) ADIE RCIE TXIE USBIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 9Fh ADCON1 - - - - - PCFG2 PCFG1 PCFG0 - -000 - -000 0Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the Parallel Slave Port. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C745 PIC16C745. Always maintain these bits clear. 2: PIC16C765 PIC16C765 only. 2000 Microchip Technology Inc. Preliminary DS41124C-page 41 745cov.book Page 42 Wednesday, August 2, 2000 8:24 AM PIC16C745/765 PIC16C745/765 NOTES: DS41124C-page 42 Preliminary 2000 Microchip Technology Inc. 745cov.book Page 43 Wednesday, August 2, 2000 8:24 AM PIC16C745/765 PIC16C745/765 6.0 TIMER0 MODULE Counter mode is selected by setting bit T0CS (OPTION_REG). In counter mode, Timer0 will increment either on every rising or falling edge of pin RA4/T0CKI. The incrementing edge is determined by the Timer0 Source Edge Select bit T0SE (OPTION_REG). Clearing bit T0SE selects the rising edge. Restrictions on the external clock input are discussed in detail in Section 6.2. The Timer0 module timer/counter has the following features: · · · · · · 8-bit timer/counter Readable and writable 8-bit software programmable prescaler Internal or external clock select Interrupt-on-overflow from FFh to 00h Edge select for external clock The prescaler is mutually exclusively shared between the Timer0 module and the watchdog timer. The prescaler is not readable or writable. Section 6.3 details the operation of the prescaler. Figure 6-1 is a block diagram of the Timer0 module and the prescaler shared with the WDT. 6.1 Additional information on the Timer0 module is available in the PICmicroTM Mid-Range MCU Family Reference Manual (DS33023 DS33023). The TMR0 interrupt is generated when the TMR0 register overflows from FFh to 00h. This overflow sets bit T0IF (INTCON). The interrupt can be masked by clearing bit T0IE (INTCON). Bit T0IF must be cleared in software by the Timer0 module interrupt service routine before re-enabling this interrupt. The TMR0 interrupt cannot awaken the processor from SLEEP, since the timer is shut off during SLEEP. Timer mode is selected by clearing bit T0CS (OPTION_REG). In timer mode, the Timer0 module will increment every instruction cycle (without prescaler). If the TMR0 register is written, the increment is inhibited for the following two instruction cycles. The user can work around this by writing an adjusted value to the TMR0 register. FIGURE 6-1: Timer0 Interrupt BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER FINT Data Bus 0 RA4/T0CKI Pin 8 M U X 1 M U X 0 1 SYNC 2 Cycles TMR0 reg T0SE TOCS Set flag bit T0IF on Overflow PSA PRESCALER 0 Watchdog Timer M U X 1 8-bit Prescaler 8 8 - to - 1MUX PS PSA WDT Enable bit 1 0 MUX PSA WDT Time-out Note: T0CS, T0SE, PSA, PS are (OPTION_REG). 2000 Microchip Technology Inc. Preliminary DS41124C-page 43 745cov.book Page 44 Wednesday, August 2, 2000 8:24 AM PIC16C745/765 PIC16C745/765 6.2 Using Timer0 with an External Clock The PSA and PS bits (OPTION_REG) determine the prescaler assignment and prescale ratio. When no prescaler is used, the external clock input is the same as the prescaler output. The synchronization of T0CKI with the internal phase clocks is accomplished by sampling the prescaler output on the Q2 and Q4 cycles of the internal phase clocks. Therefore, it is necessary for T0CKI to be high for at least 2Tosc (and a small RC delay of 20 ns) and low for at least 2Tosc (and a small RC delay of 20 ns). Refer to the electrical specification of the desired device. 6.3 When assigned to the Timer0 module, all instructions writing to the TMR0 register (e.g. CLRF 1, MOVWF 1, BSF 1,x.etc.) will clear the prescaler. When assigned to WDT, a CLRWDT instruction will clear the prescaler along with the watchdog timer. The prescaler is not readable or writable. Note: Prescaler There is only one prescaler available which is mutually exclusively shared between the Timer0 module and the watchdog timer. A prescaler assignment for the Timer0 module means that there is no prescaler for the watchdog timer, and vice-versa. This prescaler is not readable or writable (see Figure 6-1). EXAMPLE 6-1: Writing to TMR0, when the prescaler is assigned to Timer0, will clear the prescaler count, but will not change the prescaler assignment. To avoid an unintended device RESET, the following instruction sequence (shown in Example 6-1) must be executed when changing the prescaler assignment from Timer0 to the WDT. This sequence must be followed even if the WDT is disabled. CHANGING PRESCALER (TIMER0WDT) 1) Lines 2 and 3 do NOT have to be included if the final desired prescale value is other than 1:1. If 1:1 is the final desired value, then a temporary prescale value is set in lines 2 and 3 and the final prescale value will be set in lines 10 and 11. TABLE 6-1: Address 01h,101h STATUS, RP0 ;Bank1 MOVLW b'xx0x0xxx' ;Select clock source and prescale value of 3) MOVWF OPTION_REG ;other than 1:1 4) BCF STATUS, RP0 ;Bank0 5) CLRF TMR0 ;Clear TMR0 and prescaler 6) BSF STATUS, RP1 ;Bank1 7) MOVLW b'xxxx1xxx' ;Select WDT, do not change prescale value 8) MOVWF OPTION_REG ; 9) CLRWDT ;Clears WDT and prescaler 10) MOVLW b'xxxx1xxx' ;Select new prescale value and WDT 11) MOVWF OPTION_REG ; 12) BCF STATUS, RP0 ;Bank0 REGISTERS ASSOCIATED WITH TIMER0 Name TMR0 0Bh,8Bh, INTCON 10Bh,18Bh 81h,181h BSF 2) Bit 7 Bit 6 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Timer0 module's register GIE PEIE OPTION_REG RBPU INTEDG Value on: POR, BOR Value on all other resets xxxx xxxx Bit 5 uuuu uuuu T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by Timer0. DS41124C-page 44 Preliminary 2000 Microchip Technology Inc. 745cov.book Page 45 Wednesday, August 2, 2000 8:24 AM PIC16C745/765 PIC16C745/765 7.0 TIMER1 MODULE In timer mode, Timer1 increments every instruction cycle. In counter mode, it increments on every rising edge of the external clock input. The Timer1 module is a 16-bit timer/counter consisting of two 8-bit registers (TMR1H and TMR1L), which are readable and writable. The TMR1 Register pair (TMR1H:TMR1L) increments from 0000h to FFFFh and rolls over to 0000h. The TMR1 interrupt, if enabled, is generated on overflow, which is latched in interrupt flag bit TMR1IF (PIR1). This interrupt can be enabled/disabled by setting/clearing TMR1 interrupt enable bit TMR1IE (PIE1). Timer1 can be enabled/disabled by setting/clearing control bit TMR1ON (T1CON). Timer1 also has an internal "RESET input". This RESET can be generated by either of the two CCP modules (Section 9.0). Register 7-1 shows the Timer1 control register. When the Timer1 oscillator is enabled (T1OSCEN is set), the RC1/T1OSI/CCP2 and RC0/T1OSO/T1CKI pins become inputs. That is, the TRISC value is ignored. Timer1 can operate in one of two modes: · As a timer · As a counter Additional information on timer modules is available in the PICmicroTM Mid-Range MCU Family Reference Manual (DS33023 DS33023). The operating mode is determined by the clock select bit, TMR1CS (T1CON). REGISTER 7-1: TIMER1 CONTROL REGISTER (T1CON: 10h) U-0 - bit7 U-0 - R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR reset bit 7-6: Unimplemented: Read as '0' bit 5-4: T1CKPS: Timer1 Input Clock Prescale Select bits 11 = 1:8 Prescale value 10 = 1:4 Prescale value 01 = 1:2 Prescale value 00 = 1:1 Prescale value bit 3: T1OSCEN: Timer1 Oscillator Enable Control bit 1 = Oscillator is enabled 0 = Oscillator is shut off (The oscillator inverter is turned off to eliminate power drain) bit 2: T1SYNC: Timer1 External Clock Input Synchronization Control bit TMR1CS = 1 1 = Do not synchronize external clock input 0 = Synchronize external clock input TMR1CS = 0 This bit is ignor