DRPIC1655X PIC16C554 PIC16C558 PIC16C55X DFPIC165X DFPIC1655X DFPIC166X - Datasheet Archive
High Performance Configurable 8-bit RISC Microcontroller ver 2.16 OVERVIEW The DRPIC1655X is a low-cost, high performance, 8-bit,
DRPIC1655X DRPIC1655X High Performance Configurable 8-bit RISC Microcontroller ver 2.16 OVERVIEW The DRPIC1655X DRPIC1655X is a low-cost, high performance, 8-bit, fully static soft IP Core, dedicated for operation with fast (typically onchip) dual ported memory. The core has been designed with a special concern about low power consumption. DRPIC1655X DRPIC1655X soft core is softwarecompatible with the industry standard PIC16C554 PIC16C554 and PIC16C558 PIC16C558. It implements an enhanced Harvard architecture (i.e. separate instruction and data memories) with independent address and data buses. The 14 bit program memory and 8-bit dual port data memory allow instruction fetch and data operations to occur simultaneously. The advantage of this architecture is that instruction fetch and memory transfers can be overlapped by multi stage pipeline, so that the next instruction can be fetched from program memory while the current instruction is executed with data from the data memory. The DRPIC1655X DRPIC1655X architecture is 4 times faster compared to standard architecture. So most instructions are executed within 1 system clock period, except the instructions which directly operates on program counter PC (GOTO, CALL, RETURN), this situation require the pipeline to be cleared and subsequently refilled. This operation takes additional one clock cycle. The DRPIC1655X DRPIC1655X Microcontroller fits perfectly in applications ranging from highAll trademarks mentioned in this document are trademarks of their respective owners. speed automotive and appliance motor control to low-power remote transmitters/receivers, pointing devices and telecom processors. Built-in power save mode make this IP perfect for applications where power consumption is critical. DRPIC1655X DRPIC1655X is delivered with fully automated testbench and complete set of tests allowing easy package validation at each stage of SoC design flow CPU FEATURES Software compatible with industry standard PIC16C55X PIC16C55X Pipelined Harvard architecture 4 times faster compared to original implementation 35 instructions 14 bit wide instruction word Up to 32 K bytes of internal Data Memory Up to 64K bytes of Program Memory Configurable hardware stack Power saving SLEEP mode Fully synthesizable, static synchronous design with no internal tri-states Technology Code independent HDL Source 1.4 GHz virtual clock frequency in a 0.18u technological process http://www.DigitalCoreDesign.com http://www.dcd.pl Copyright 1999-2009 DCD Digital Core Design. All Rights Reserved. PERIPHERALS OPTIONAL PERIPHERALS Four 8 bit I/O ports 8-bit timer/counter There are also available an optional peripherals, not included in presented DRPIC1655X DRPIC1655X Microcontroller Core. The optional peripherals, can be implemented in microcontroller core upon customer request. Readable and Writable Timer 1 and Timer 2 8-bit software programmable prescaler Full duplex UART Internal or external clock select SPI Master and Slave Serial Peripheral Interface Four 8-bit corresponding TRIS registers Interrupt feature on PORTB(7:4) change Timer 0 Interrupt generation on timer overflow Edge select for external clock Mode fault error Watchdog Timer Configurable Time out period 7-bit software programmable prescaler Dedicated independent Watchdog Clock input Extended Interrupt Controller Three individually maskable Interrupt sources External interrupt INT Timer Overflow interrupt Port B[7:4] change interrupt Supports speeds up ¼ of system clock DoCDTM debug unit Processor execution control Run Write collision error Software selectable polarity and phase of serial clock SCK System errors detection Allows operation from a wide range of system clock frequencies (build-in 5-bit timer) Interrupt generation PWM Pulse Width Modulation Timer 2 independent 8-bit PWM channels, concatenated on one 16-bit PWM channel Software-selectable duty from 0% to 100% and pulse period Software-selectable Halt polarity of output waveform Step into instruction Skip instruction I2C bus controller - Master 7-bit and 10-bit addressing modes Read-write all processor contents Program Counter (PC) Program Memory NORMAL, FAST, HIGH speeds Multi-master systems supported Clock arbitration and synchronization Data Memory Special Function Registers (SFRs) Hardware Stack and Stack Pointer Hardware execution breakpoints User defined timings on I2C lines Wide range of system clock frequencies I2C bus controller - Slave Program Memory NORMAL, FAST and HIGH Speed modes Data Memory Wide range of system clock frequencies Special Function Registers (SFRs) User defined data setup time on I2C lines Three wire communication interface All trademarks mentioned in this document are trademarks of their respective owners. http://www.DigitalCoreDesign.com http://www.dcd.pl Copyright 1999-2009 DCD Digital Core Design. All Rights Reserved. LICENSING DELIVERABLES Source code: VHDL Source Code or/and VERILOG Source Code or/and Encrypted, or plain text EDIF netlist VHDL & VERILOG test bench environment Active-HDL automatic simulation macros ModelSim automatic simulation macros Tests with reference responses Technical documentation Installation notes HDL core specification Datasheet Synthesis scripts Example application Technical support IP Core implementation support 3 months maintenance Delivery the IP Core updates, minor and major versions changes Delivery the documentation updates Phone & email support Comprehensible and clearly defined licensing methods without royalty per chip fees make using of IP Core easy and simply. Single Site license option is dedicated for small and middle sized companies making its business in one place. Multi Sites license option is dedicated for corporate customers making its business in several places. Licensed product can be used in selected branches of corporate. In all cases number of IP Core instantiations within a project, and number of manufactured chips are unlimited. The license is royalty per chip free. There is no time of use restrictions. There are two formats of delivered IP Core VHDL, Verilog RTL synthesizable source code called HDL Source FPGA EDIF/NGO/NGD/QXP/VQM called Netlist SYMBOL CONFIGURATION The following parameters of the DRPIC1655X DRPIC1655X core can be easy adjusted to requirements of dedicated application and technology. Configuration of the core can be prepared by effortless changing appropriate constants in package file. There is no need to change any parts of the code. - 1-16 default 8 · Memories type - synchronous asynchronous · SLEEP mode - used unused · WATCHDOG Timer - used unused · PORTS A,B,C,D - used unused TM · DoCD Debug Unit - prgdata(13:0) prgaddr(15:0) ramdatai(7:0) ramdatao(7:0) rdaddr(14:0) wraddr(14:0) ramwe ramoe intr used unused · Interrupt system sleep used / width unused · Timer system clk clkwdt por mclr used unused · Number of hardware stack levels All trademarks mentioned in this document are trademarks of their respective owners. t0cki portai(7:0) portbi(7:0) portci(7:0) portdi(7:0) portao(7:0) portbo(7:0) portco(7:0) portdo(7:0) trisa(7:0) trisb(7:0) trisc(7:0) trisd(7:0) docddatai docddatao docdclk TM DoCD Interface prgdatao(13:0) prgwe http://www.DigitalCoreDesign.com http://www.dcd.pl Copyright 1999-2009 DCD Digital Core Design. All Rights Reserved. PINS DESCRIPTION PIN TYPE DESCRIPTION clk input Global clock clkwdt input Watchdog clock por input Global reset Power On Reset mclr input User reset prgdata[13:0] input Data bus from program memory ramdatai[7:0] input Data bus from int. data memory intr input External interrupt t0cki input Timer 0 input portxi[7:0] input Port A, B, C, D input docddatai input DoCDTM Debugger input prgaddr[15:0] output Program memory address bus ramdatao[7:0] output Data bus for internal data memory rdaddr[14:0] output RAM read address bus wraddr[14:0] output RAM write address bus ramwe output Data memory write ramoe output Data memory output enable sleep output Sleep signal portxo[7:0] the ninth push overwrites the value that was stored from the first push. RAM Controller It performs interface functions between Data memory and DRPIC1655X DRPIC1655X internal logic. It assures correct Data Memory addressing and data transfers. The DRPIC1655X DRPIC1655X supports two addressing modes: direct or indirect. In Direct Addressing the 9-bit direct address is computed from RP(1:0) bits (STATUS) and 7 least significant bits of instruction word. Indirect addressing is possible by using the INDF register. Any instruction using INDF register actually accesses data pointed to by the file select register FSR. Reading INDF register indirectly will produce 00h. Writing to the INDF register indirectly results in a nooperation. An effective 9-bit address is obtained by concatenating the IRP bit (STATUS) and the 8-bit FSR register. output Port A, B, C, D outputs trisx[7:0] output DoCDTM Debugger data output docdclk output DoCDTM Clock line prgdatao[13:0] output Program Memory data output prgwe Hardware Stack ALU output Ports A, B, C, D data direction pins docddatao clk por output Program Memory write enable mclr sleep prgdata prgaddr intr Control Unit Interrupt Controller BLOCK DIAGRAM ALU Arithmetic Logic Unit performs arithmetic and logic operations during execution of an instruction. This module contains work register (W) and Status register. Control Unit It performs the core synchronization and data flow control. This module manages execution of all instructions. Performs decode and control functions for all other blocks. It contains program counter (PC) and hardware stack. Hardware Stack it's a configurable hardware stack. The stack space is not a part of either program or data space and the stack pointer is not readable or writable. The PC is pushed onto the stack when CALL instruction is executed or an interrupt causes a branch. The stack is popped while RETURN, RETFIE and RETLW instruction execution. The stack operates as a circular buffer. This means that after the stack has been pushed eight times, All trademarks mentioned in this document are trademarks of their respective owners. t0cki RAM Controller Timer 0 clkwdt Watchdog Timer docddatai docddatao docdclk prgdatao prgwe I/O Ports ramdatai ramdatao rdaddr wraddr ramwe ramoe portai portbi portci portdi portao portbo portco portdo trisa trisb trisc trisd DoCDTM Debugger Interrupt Controller Interrupt Controller module is responsible for interrupt manage system for the external and internal interrupt sources. It contains interrupt related register called INTCON. There are three interrupt sources: External interrupt INT http://www.DigitalCoreDesign.com http://www.dcd.pl Copyright 1999-2009 DCD Digital Core Design. All Rights Reserved. TMR0 overflow interrupt PORTB change interrupt (pins B7:B4) The interrupt control register INTCON records individual interrupt requests in flag bits. A global interrupt enable bit, GIE enables all unmasked interrupts. Each interrupt source has an individual enable bit, which can enable or disable corresponding interrupt. When an interrupt is responded to, the GIE is cleared to disable any further interrupt, the return address is pushed into the stack and the PC is loaded with 0004h. The interrupt flag bits must be cleared in software before reenabling interrupts. Timer 0 Main system's timer and prescaler. This timer operates in two modes: 8-bit timer or 8-bit counter. In the "timer mode", timer registers are incremented every 4 CLK periods. When the prescaler is assigned into the TIMER prescale ration can be divided by 2, 4 . 256. In the "counter mode" the timer register is incremented every falling or rising edge of T0CKI pin, dependent on T0SE bit in OPTION register. capability of a whole SoC system. In contrast to other on-chip debuggers DoCDTM provides non-intrusive debugging of running application. It can halt, run, step into or skip an instruction, read/write any contents of microcontroller including all registers, internal, external, program memories, all SFRs including user defined peripherals. Hardware breakpoints can be set and controlled on program memory, internal and external data memories, as well as on SFRs. Hardware breakpoint is executed if any write/read occurred at particular address with certain data pattern or without pattern. The DoCDTM system includes three-wire interface and complete set of tools to communicate and work with core in real time debugging. It is built as scalable unit and some features can be turned off to save silicon and reduce power consumption. A special care on power consumption has been taken, and when debugger is not used it is automatically switched in power save mode. Finally whole debugger is turned off when debug option is no longer used. Watchdog Timer it's a free running timer. WDT has own clock input separate from system clock. It means that the WDT will run even if the system clock is stopped by execution of SLEEP instruction. During normal operation, a WDT time-out generates a Watchdog reset. If the device is in SLEEP mode the WDT time-out causes the device to wake-up and continue with normal operation. I/O Ports Block contains DRPIC1655X DRPIC1655X's general purpose I/O ports and data direction registers (TRIS). The DRPIC1655X DRPIC1655X has four 8-bit full bi-directional ports PORT A, PORT B, PORT C, PORT D. Each port's bit can be individually accessed by bit addressable instructions. Read and write accesses to the I/O port are performed via their corresponding SFR's PORTA, PORTB, PORTC, PORTD. The reading instruction always reads the status of Port pins. Writing instructions always write into the Port latches. Each port's pin has an corresponding bit in TRISA, B, C and D registers. When the bit of TRIS register is set this means that the corresponding bit of port is configured as an input (output drivers are set into the High Impedance). DoCDTM Debug Unit it's a real-time hardware debugger provides debugging All trademarks mentioned in this document are trademarks of their respective owners. http://www.DigitalCoreDesign.com http://www.dcd.pl Copyright 1999-2009 DCD Digital Core Design. All Rights Reserved. PERFORMANCE IMPROVEMENT The following table gives a survey about the Core area and performance in the ACTEL® devices after Place & Route (all key features have been included): Most instruction of DRPIC1655X DRPIC1655X is executed within 1 CLK period, except program branches that require 2 CLK periods. The table below shows sample instructions execution times: Device FUSION ProASIC3 ProASIC3e IGLOO IGLOOe Speed grade -2 -2 -2 STD STD TILES Fmax 1803 1968 1803 1968 1803 47 MHz 49 MHz 47MHz 25 MHz 25 MHz Mnemonic DRPIC1655X DRPIC1655X PIC16C554 PIC16C554 Impr. operands (CLK cycles) (CLK cycles) ADDWF 1 4 4 ANDWF 1 4 4 RLF 1 4 4 BCF 1 4 4 1 1 DECFSZ 1(2) 4(8) 4 INCFSZ 1(2)1 4(8)1 4 BTFSC 1(2)1 4(8)1 4 BTFSS 1(2)1 4(8)1 4 CALL 2 8 4 GOTO 2 8 4 RETFIE 2 8 4 RETLW 2 8 4 RETURN 2 8 4 * CPU consisted of ALU, Control Unit, Bus Controller, Hardware Stack, External INT pin Interrupt Controller, Extended interrupt controller,(512 Bytes RAM and 8kW of program memory) Core performance in ACTEL® devices 1 number of clock in case when result of operation is 0. DFPIC&DRPIC FAMILY OVERVIEW - - - - 5 5 5 5 1 5 1 5 2 8 8 8 8 - 2 2 2 4 4 - * Optional DFPIC & DRPIC family of High Performance Microcontroller Cores All trademarks mentioned in this document are trademarks of their respective owners. http://www.DigitalCoreDesign.com http://www.dcd.pl Copyright 1999-2009 DCD Digital Core Design. All Rights Reserved. Size (gate) - DoCDTM Debugger - External interrupts Internal Interrupts Levels of hardware stack Wake up on port pin change - Sleep Mode Watchdog Timer Timer 2 - Speed rate 33 35 35 35 35 USART 12 14 14 14 14 Timer 1 24 16 32 32 32 128 512 512 512 512 Timer 0 2k 64k 64k 64k 64k CCP1 DFPIC165X DFPIC165X DFPIC1655X DFPIC1655X DFPIC166X DFPIC166X DRPIC1655X DRPIC1655X DRPIC166X DRPIC166X I/O Ports Design Program Memory space Data Memory space Program word length Number of instructions The family of DCD DFPICXX & DRPICXX IP Cores combine a highperformance, low cost, and small compact size, offering the best price/performance ratio in the IP Market. The DCD's Cores are dedicated for use in cost-sensitive consumer products, computer peripherals, office automation, automotive control systems, security and telecommunication applications. DCD's DFPICXX & DRPICXX IP Cores family contains four 8-bit microcontroller Cores to best meet your needs: DFPIC165X DFPIC165X 12-bit program word, DFPIC1655X DFPIC1655X 14-bit program word, and DRPIC1655X DRPIC1655X and DRPIC166X DRPIC166X single cycle microcontrollers with 14-bit program word. All three microcontroller cores are binary compatible with widely accepted PIC16C5X PIC16C5X and PIC16CXXX PIC16CXXX. They employ a modified RISC architecture two or four times faster than the original ones. The DFPICXXX & DRPICXX IP Cores are written in pure VHDL/VERILOG HDL languages which make them technologically independent. All of the DFPICXX & DRPICXX family members supports a power saving SLEEP mode and allows the user to configure the watchdog time-out period and a number of hardware stack levels. DFPICXX & DRPICXX can be fully customized according to customer needs. 2 700 * 3 900 * * 4 800 * 6 700 CONTACTS For any modification or special request please contact to Digital Core Design or local distributors. Headquarters: Wroclawska 94 41-902 Bytom, POLAND n fo @ d c d .p l e-mail: firstname.lastname@example.org tel. : +48 32 282 82 66 fax : +48 32 282 74 37 Distributors: http://www.dcd.p apartn.php Please check http://www.dcd.pll//apartn.php All trademarks mentioned in this document are trademarks of their respective owners. http://www.DigitalCoreDesign.com http://www.dcd.pl Copyright 1999-2009 DCD Digital Core Design. All Rights Reserved.