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PI7C9X20303UL 1-877-PERICOM 132-PIN 32-BITS 16-BITS PI7C9X303UL 8B/10B IS24C04 - Datasheet Archive
PCI EXPRESS® PACKET SWITCH DATASHEET REVISION 1.1 August 2009 3545 North 1ST Street, San Jose, CA 95134 Telephone:
PI7C9X20303UL PI7C9X20303UL PCI EXPRESS® PACKET SWITCH DATASHEET REVISION 1.1 August 2009 3545 North 1ST Street, San Jose, CA 95134 Telephone: 1-877-PERICOM 1-877-PERICOM, (1-877-737-4266) FAX: 408-435-1100 Internet: http://www.pericom.com PI7C9X20303UL PI7C9X20303UL 3Port-3Lane PCI Express® Switch UltraLoTM Family Datasheet DISCLAIMER The information contained in this document is proprietary and confidential to Pericom Semiconductor Cooperation (PSC). No part of this document may be copied or reproduced in any form or by any means without prior written consent of PSC. The information in this document is subjected to change without notice. PSC retains the right to make changes to this document at any time without notice. While the information contained in this document has been checked for accuracy, such information is preliminary, and PSC does not warrant the accuracy and completeness of such information. PSC does not assume any liability or responsibility for damages arising from any use of the information contained in this document. LIFE SUPPORT POLICY Pericom Semiconductor Corporation's products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the manufacturer and an officer of PSC. 1) 2) Life support devices or system are devices or systems which: a) Are intended for surgical implant into the body or b) Support or sustain life and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. Pericom Semiconductor Corporation reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. Pericom Semiconductor does not assume any responsibility for use of any circuitry described other than the circuitry embodied in a Pericom Semiconductor product. The Company makes no representations that circuitry described herein is free from patent infringement or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent, patent rights or other rights, of Pericom Semiconductor Corporation. All other trademarks are of their respective companies. Page 2 of 77 August 2009 Revision 1.1 Pericom Semiconductor PI7C9X20303UL PI7C9X20303UL 3Port-3Lane PCI Express® Switch UltraLoTM Family Datasheet REVISION HISTORY Date 11/27/08 2/26/08 Revision Number 0.0 0.1 5/20/08 0.2 Description Preliminary datasheet drafted Corrected Chapter 5 Functional Description (multiple virtual channels) Updated Chapter 6 EEPROM (0Ch) Updated Chapter 6 EEPROM (A0h, A2h, A4h) Modified Chapter 7 Registers (7.2.2 Device ID Register, 7.2.50 Replay Time-Out Counter Bit[13:15], 7.2.52 Switch Operation Mode Bit[14:15], 7.2.64 PCI Express Capability Bit[24], 7.2.70 Link Status Bit[28], 7.2.99 Power Budgeting Data, 7.2.100 Power Budget Capability) Updated 9.5 JTAG Boundary Scan Register Order Updated Chapter 3.5 Power Pins (VDDC, VDDA, VDDAUX) Updated Chapter 6 EEPROM (A0h, A2h, A4h) Updated Chapter 1 Features (Power Dissipation) Updated Chapter 11.1 AC Specification (VDDAUX) Updated Chapter 11.2 DC Specification (Power Consumption, VDDAUX) Updated Chapter 10 Power Management (VDDAUX) Updated Figure 12-1 Package outline drawing (Revision B) Corrected 3.1 PCI EXPRESS INTERFACE SIGNALS (DWNRST_L), 3.3 MISCELLANEOUS SIGNALS (PORTERR, MRL_PDC, NC) Updated 4.1 PIN LIST of 132-PIN 132-PIN TQFN (A30, B5, B46) Modified 6.1.4 MAPPING EEPROM CONTENTS TO CONFIGURATION REGISTERS (0Ch: B0h, 0Eh: Revision ID) Corrected 7.2.52 Switch Operation Mode (Upstream Port) Bit[16:31], Corrected 7.2.53 Switch Operation Mode (Downstream Port) Bit[16:31] Updated 1 Features (typical latency, removed peer-to-peer switching, power consumption) Updated Chapter 3.1 PCI Express Interface Signals (REFCLKP, REFCLKN) Updated Chapter 3.3 Miscellaneous Signals (MRL_PDC to PRSNT) Updated 3.2 Port Configuration Signals (SLOT_IMP, MRL_PDC) Updated 4.1 Pin-List Modified 5.1 Physical Layer Circuit Updated Chapter 6.1.3 EEPROM Space Address Map (10h to 14h, 50h to 54h) Modified 6.1.4 Mapping EEPROM Contents To Configuration Registers (0Ch: Ordering Frozen, TX SOF Latency, Surprise Down Capability Enable, Power Management Data Select, 20h, 22h, 24h: Removed LPVC, Added PMCSR, 51h, 52h, 53h, 54h, 55h, 56h) Updated Chapter 7.2 Transparent Mode Configuration Registers (A4h, B4h, B8, BCh, C0h, C4h) Updated 7.2.5 Revision ID Register, 7.2.27 Interrupt Pin Register, 7.2.32 Power Management Data Register Bit[3], 7.2.46 Next Item Pointer Register, 7.2.50 Replay Time-Out Counter, 7.2.51 Acknowledge Latency Timer, 7.5.52 Switch Operation Mode, 7.2.53 Switch Operation Mode (Downstream Port) Bit[16:31], 7.2.54 XPIP CSR2, 7.2.55 SSID/SSVID Capability ID Register, 7.2.56 Next Item Pointer Register, 7.2.57 Subsystem Vendor ID Register, 7.2.58 Subsystem ID Register, 7.2.65 PCI Express Capabilities Register Bit[19:16], 7.2.69 Link Capabilities Register Bit 19, 7.2.86 Capability Version Bit[19:16], 7.2.93 VC Resource Control Register Bit [26:24], 7.2.97 Capability Version Bit[19:16] Updated 9.5 JTAG Boundary Scan Register Order Added Chapter 11.2 Power Consumption Corrected Chapter 11.3 DC Specifications Page 3 of 77 August 2009 Revision 1.1 Pericom Semiconductor PI7C9X20303UL PI7C9X20303UL 3Port-3Lane PCI Express® Switch UltraLoTM Family Datasheet 2008/7/10 0.3 9/30/08 0.4 11/24/08 1.0 8/12/09 1.1 Modified 1. Features (0.25W typical power dissipation) Modified 3.3 Miscellaneous Signals (DEQ[3] to P0_CTCDIS, HIDRV to P1_CTCDIS, P2_LODRV to CTCDIS[2], DTX[3] to TEST7, TEST2) Modified 4.1 Pin List (DEQ[3] to P0_CTCDIS, HIDRV to P1_CTCDIS, LODRV to P2_CTCDIS, DTX[3] to TEST7, TEST2) Modified 6.1.4 Mapping EEPROM Contents To Configuration Registers (0Ch, 10h, 12h, 14h) Corrected 7.2.27 Interrupt Pin Register Added 7.2.55 TL CSR Modified 11.2 Power Consumption (0.25W L0 Normal Mode with Power Saving) Updated Chapter 1 Features (updated Industrial Temperature Range, 0.30 W typical in L0 normal mode) Updated Chapter 3.5 Power Pints (added GND, thermal pad, to VSS) Updated Chapter 4.1 Pin List (added GND) Updated 11.1 Absolute Maximum Ratings: Ambient Temperature with power applied Modified 11.2 Power Consumption (0.30W L0 Normal Mode with Power Saving, 0.30W L1 Normal Mode without Power Saving) Updated Chapter 12 Package Information (added Figure 12-2 Package bottom view) Corrected Chapter 7.2 (8Ch - Next Item Pointer) Updated Chapter 13 Ordering Information Updated Header (UltraLoTM Family) Removed "Preliminary" and "Confidential" references Updated Chapter 3.1 PCI Express Interface Signals (WAKEUP_L changed to NC) Updated Chapter 3.2 Port Configuration Signals (SLOTCLK) Updated Chapter 3.3 Miscellaneous Signals (updated PWR_SAV pin, PRSNT, SMBCLK, SMBDATA, PWR_SAV, CTCDIS, EEPD) Updated Chapter 3.4 JTAG Boundary Scan Signals (TMS, TDI, TRST_L, WAKEUP_L) Updated Chapter 5.1 Physical Layer Circuit Updated Chapter 7.2.52 and 7.2.53 Switch Operation Mode (Bit[31:16]) Updated Chapter 10 Power Management Updated Figure 12-1 Package outline drawing Updated Table 11-4 Transmitter Characteristics Updated Table 11-5 Receiver Characteristics Updated Chapter 13 Ordering Information Page 4 of 77 August 2009 Revision 1.1 Pericom Semiconductor PI7C9X20303UL PI7C9X20303UL 3Port-3Lane PCI Express® Switch UltraLoTM Family Datasheet TABLE OF CONTENTS 1 FEATURES.10 2 GENERAL DESCRIPTION.11 3 PIN DESCRIPTION.12 3.1 3.2 3.3 3.4 3.5 4 PIN ASSIGNMENTS .15 4.1 5 PCI EXPRESS INTERFACE SIGNALS .12 PORT CONFIGURATION SIGNALS .12 MISCELLANEOUS SIGNALS.12 JTAG BOUNDARY SCAN SIGNALS .13 POWER PINS.14 PIN LIST OF 132-PIN 132-PIN TQFN .15 FUNCTIONAL DESCRIPTION.16 5.1 PHYSICAL LAYER CIRCUIT .16 5.2 DATA LINK LAYER (DLL).18 5.3 TRANSACTION LAYER RECEIVE BLOCK (TLP DECAPSULATION) .18 5.4 ROUTING .18 5.5 TC/VC MAPPING.19 5.6 QUEUE.19 5.6.1 PH .19 5.6.2 PD .19 5.6.3 NPHD .19 5.6.4 CPLH .19 5.6.5 CPLD .19 5.7 TRANSACTION ORDERING.20 5.8 PORT ARBITRATION .20 5.9 FLOW CONTROL .21 5.10 TRANSATION LAYER TRANSMIT BLOCK (TLP ENCAPSULATION) .21 6 EEPROM INTERFACE AND SYSTEM MANAGEMENT BUS.22 6.1 EEPROM INTERFACE .22 6.1.1 AUTO MODE EERPOM ACCESS .22 6.1.2 EEPROM MODE AT RESET.22 6.1.3 EEPROM SPACE ADDRESS MAP .22 6.1.4 MAPPING EEPROM CONTENTS TO CONFIGURATION REGISTERS.24 6.2 SMBUS INTERFACE .29 7 REGISTER DESCRIPTION.30 7.1 REGISTER TYPES .30 7.2 TRANSPARENT MODE CONFIGURATION REGISTERS .30 7.2.1 VENDOR ID REGISTER OFFSET 00h .32 7.2.2 DEVICE ID REGISTER OFFSET 00h.32 7.2.3 COMMAND REGISTER OFFSET 04h.32 7.2.4 PRIMARY STATUS REGISTER OFFSET 04h.33 7.2.5 REVISION ID REGISTER OFFSET 08h .33 7.2.6 CLASS CODE REGISTER OFFSET 08h .33 7.2.7 CACHE LINE REGISTER OFFSET 0Ch.34 Page 5 of 77 August 2009 Revision 1.1 Pericom Semiconductor 7.2.8 7.2.9 7.2.10 7.2.11 7.2.12 7.2.13 7.2.14 7.2.15 7.2.16 7.2.17 7.2.18 7.2.19 7.2.20 7.2.21 7.2.22 7.2.23 7.2.24 7.2.25 7.2.26 7.2.27 7.2.28 7.2.29 7.2.30 7.2.31 7.2.32 7.2.33 7.2.34 7.2.35 7.2.36 7.2.37 7.2.38 7.2.39 7.2.40 7.2.41 7.2.42 7.2.43 7.2.44 7.2.45 7.2.46 7.2.47 7.2.48 7.2.49 7.2.50 7.2.51 7.2.52 7.2.53 7.2.54 7.2.55 7.2.56 7.2.57 7.2.58 7.2.59 7.2.60 PI7C9X20303UL PI7C9X20303UL 3Port-3Lane PCI Express® Switch UltraLoTM Family Datasheet PRIMARY LATENCY TIMER REGISTER OFFSET 0Ch .34 HEADER TYPE REGISTER OFFSET 0Ch.34 PRIMARY BUS NUMBER REGISTER OFFSET 18h .34 SECONDARY BUS NUMBER REGISTER OFFSET 18h .34 SUBORDINATE BUS NUMBER REGISTER OFFSET 18h .34 SECONDARY LATENCY TIMER REGISTER OFFSET 18h .35 I/O BASE ADDRESS REGISTER OFFSET 1Ch.35 I/O LIMIT ADDRESS REGISTER OFFSET 1Ch.35 SECONDARY STATUS REGISTER OFFSET 1Ch .35 MEMORY BASE ADDRESS REGISTER OFFSET 20h .36 MEMORY LIMIT ADDRESS REGISTER OFFSET 20h .36 PREFETCHABLE MEMORY BASE ADDRESS REGISTER OFFSET 24h.36 PREFETCHABLE MEMORY LIMIT ADDRESS REGISTER OFFSET 24h.36 PREFETCHABLE MEMORY BASE ADDRESS UPPER 32-BITS 32-BITS REGISTER OFFSET 28h .37 PREFETCHABLE MEMORY LIMIT ADDRESS UPPER 32-BITS 32-BITS REGISTER OFFSET 2Ch .37 I/O BASE ADDRESS UPPER 16-BITS 16-BITS REGISTER OFFSET 30h.37 I/O LIMIT ADDRESS UPPER 16-BITS 16-BITS REGISTER OFFSET 30h.37 CAPABILITY POINTER REGISTER OFFSET 34h .37 INTERRUPT LINE REGISTER OFFSET 3Ch.38 INTERRUPT PIN REGISTER OFFSET 3Ch .38 BRIDGE CONTROL REGISTER OFFSET 3Ch .38 POWER MANAGEMENT CAPABILITY ID REGISTER OFFSET 80h .39 NEXT ITEM POINTER REGISTER OFFSET 80h.39 POWER MANAGEMENT CAPABILITIES REGISTER OFFSET 80h.39 POWER MANAGEMENT DATA REGISTER OFFSET 84h .39 PPB SUPPORT EXTENSIONS OFFSET 84h.40 DATA REGISTER OFFSET 84h .40 MSI CAPABILITY ID REGISTER OFFSET 8Ch (Downstream Port Only) .40 NEXT ITEM POINTER REGISTER OFFSET 8Ch (Downstream Port Only) .41 MESSAGE CONTROL REGISTER OFFSET 8Ch (Downstream Port Only) .41 MESSAGE ADDRESS REGISTER OFFSET 90h (Downstream Port Only) .41 MESSAGE UPPER ADDRESS REGISTER OFFSET 94h (Downstream Port Only) .41 MESSAGE DATA REGISTER OFFSET 98h (Downstream Port Only) .41 VPD CAPABILITY ID REGISTER OFFSET 9Ch (Upstream Port Only).41 NEXT ITEM POINTER REGISTER OFFSET 9Ch (Upstream Port Only) .42 VPD REGISTER OFFSET 9Ch (Upstream Port Only).42 VPD DATA REGISTER OFFSET A0h (Upstream Port Only).42 VENDOR SPECIFIC CAPABILITY ID REGISTER OFFSET A4h.42 NEXT ITEM POINTER REGISTER OFFSET A4h .43 LENGTH REGISTER OFFSET A4h .43 XPIP CSR0 OFFSET A8h (Test Purpose Only).43 XPIP CSR1 OFFSET ACh (Test Purpose Only) .43 REPLAY TIME-OUT COUNTER OFFSET B0h.43 ACKNOWLEDGE LATENCY TIMER OFFSET B0h.44 SWITCH OPERATION MODE OFFSET B4h (Upstream Port).44 SWITCH OPERATION MODE OFFSET B4h (Downstream Port) .45 XPIP CSR2 OFFSET B8h (Test Purpose Only).46 TL CSR OFFSET BCh .46 SSID/SSVID CAPABILITY ID REGISTER OFFSET C0h.46 NEXT ITEM POINTER REGISTER OFFSET C0h .46 SUBSYSTEM VENDOR ID REGISTER OFFSET C4h .46 SUBSYSTEM ID REGISTER OFFSET C4h.47 GPIO CONTROL REGISTER OFFSET D8h (Upstream Port Only).47 Page 6 of 77 August 2009 Revision 1.1 Pericom Semiconductor PI7C9X20303UL PI7C9X20303UL 3Port-3Lane PCI Express® Switch UltraLoTM Family Datasheet 7.2.61 EEPROM CONTROL REGISTER OFFSET DCh (Upstream Port Only).48 7.2.62 EEPROM ADDRESS REGISTER OFFSET DCh (Upstream Port Only).49 7.2.63 EEPROM DATA REGISTER OFFSET DCh (Upstream Port Only).49 7.2.64 PCI EXPRESS CAPABILITY ID REGISTER OFFSET E0h .49 7.2.65 NEXT ITEM POINTER REGISTER OFFSET E0h .49 7.2.66 PCI EXPRESS CAPABILITIES REGISTER OFFSET E0h.49 7.2.67 DEVICE CAPABILITIES REGISTER OFFSET E4h .50 7.2.68 DEVICE CONTROL REGISTER OFFSET E8h.51 7.2.69 DEVICE STATUS REGISTER OFFSET E8h.51 7.2.70 LINK CAPABILITIES REGISTER OFFSET ECh.52 7.2.71 LINK CONTROL REGISTER OFFSET F0h.53 7.2.72 LINK STATUS REGISTER OFFSET F0h .53 7.2.73 SLOT CAPABILITIES REGISTER (Downstream Port Only) OFFSET F4h .54 7.2.74 SLOT CONTROL REGISTER (Downstream Port Only) OFFSET F8h.55 7.2.75 SLOT STATUS REGISTER (Downstream Port Only) OFFSET F8h .56 7.2.76 PCI EXPRESS ADVANCED ERROR REPORTING CAPABILITY ID REGISTER OFFSET 100h.57 7.2.77 CAPABILITY VERSION OFFSET 100h .57 7.2.78 NEXT ITEM POINTER REGISTER OFFSET 100h.57 7.2.79 UNCORRECTABLE ERROR STATUS REGISTER OFFSET 104h .57 7.2.80 UNCORRECTABLE ERROR MASK REGISTER OFFSET 108h .58 7.2.81 UNCORRECTABLE ERROR SEVERITY REGISTER OFFSET 10Ch.59 7.2.82 CORRECTABLE ERROR STATUS REGISTER OFFSET 110 h.59 7.2.83 CORRECTABLE ERROR MASK REGISTER OFFSET 114 h .60 7.2.84 ADVANCE ERROR CAPABILITIES AND CONTROL REGISTER OFFSET 118h.60 7.2.85 HEADER LOG REGISTER OFFSET From 11Ch to 128h .61 7.2.86 PCI EXPRESS VIRTUAL CHANNEL CAPABILITY ID REGISTER OFFSET 140h (Upstream Only) 61 7.2.87 CAPABILITY VERSION OFFSET 140h (Upstream Only) .61 7.2.88 NEXT ITEM POINTER REGISTER OFFSET 140h (Upstream Only).61 7.2.89 PORT VC CAPABILITY REGISTER 1 OFFSET 144h (Upstream Only) .61 7.2.90 PORT VC CAPABILITY REGISTER 2 OFFSET 148h (Upstream Only) .62 7.2.91 PORT VC CONTROL REGISTER OFFSET 14Ch (Upstream Only).62 7.2.92 PORT VC STATUS REGISTER OFFSET 14Ch (Upstream Only).62 7.2.93 VC RESOURCE CAPABILITY REGISTER (0) OFFSET 150h (Upstream Only).63 7.2.94 VC RESOURCE CONTROL REGISTER (0) OFFSET 154h (Upstream Only) .63 7.2.95 VC RESOURCE STATUS REGISTER (0) OFFSET 158h (Upstream Only).64 7.2.96 PORT ARBITRATION TABLE REGISTER (0) OFFSET 180h-1BCh (Upstream Only).64 7.2.97 PCI EXPRESS POWER BUDGETING CAPABILITY ID REGISTER OFFSET 20Ch .64 7.2.98 CAPABILITY VERSION OFFSET 20Ch.64 7.2.99 NEXT ITEM POINTER REGISTER OFFSET 20Ch .65 7.2.100 DATA SELECT REGISTER OFFSET 210h .65 7.2.101 POWER BUDGETING DATA REGISTER OFFSET 214h .65 7.2.102 POWER BUDGET CAPABILITY REGISTER OFFSET 218h .66 8 CLOCK SCHEME .67 9 IEEE 1149.1 COMPATIBLE JTAG CONTROLLER.68 9.1 9.2 9.3 9.4 9.5 INSTRUCTION REGISTER .68 BYPASS REGISTER .68 DEVICE ID REGISTER.68 BOUNDARY SCAN REGISTER.69 JTAG BOUNDARY SCAN REGISTER ORDER.69 10 POWER MANAGEMENT .71 Page 7 of 77 August 2009 Revision 1.1 Pericom Semiconductor PI7C9X20303UL PI7C9X20303UL 3Port-3Lane PCI Express® Switch UltraLoTM Family Datasheet 11 ELECTRICAL AND TIMING SPECIFICATIONS .72 11.1 11.2 11.3 11.4 ABSOLUTE MAXIMUM RATINGS .72 POWER CONSUMPTION.72 DC SPECIFICATIONS .72 AC SPECIFICATIONS .73 12 PACKAGE INFORMATION.75 13 ORDERING INFORMATION.77 Page 8 of 77 August 2009 Revision 1.1 Pericom Semiconductor PI7C9X20303UL PI7C9X20303UL 3Port-3Lane PCI Express® Switch UltraLoTM Family Datasheet TABLE OF FIGURES FIGURE 6-1 SMBUS ARCHITECTURE IMPLEMENTATION ON PI7C9X20303UL PI7C9X20303UL.29 FIGURE 12-1 PACKAGE OUTLINE DRAWING .75 FIGURE 12-2 PACKAGE BOTTOM VIEW.76 LIST OF TABLES TABLE 5-1 NOMINAL DRIVER CURRENT VALUES (INOM).16 TABLE 5-2 RATIO OF ACTUAL CURRENT AND NOMINAL CURRENT .16 TABLE 5-3 DE-EMPHASIS LEVEL VERSUS DEQ [3:0].17 TABLE 5-4 SUMMARY OF PCI EXPRESS ORDERING RULES .20 TABLE 6-1 SMBUS ADDRESS PIN CONFIGURATION .29 TABLE 7-1 TABLE ENTRY SIZE IN 4 BITS .64 TABLE 8-1 INPUT CLOCK REQUIREMENTS .67 TABLE 9-1 INSTRUCTION REGISTER CODES .68 TABLE 9-2 JTAG DEVICE ID REGISTER .68 TABLE 9-3 JTAG BOUNDARY SCAN REGISTER DEFINITION .69 TABLE 11-1 ABSOLUTE MAXIMUM RATINGS .72 TABLE 11-2 PI7C9X303UL PI7C9X303UL POWER DISSIPATION .72 TABLE 11-3 DC ELECTRICAL CHARACTERISTICS .72 TABLE 11-4 TRANSMITTER CHARACTERISTICS.73 TABLE 11-5 RECEIVER CHARACTERISTICS .74 Page 9 of 77 August 2009 Revision 1.1 Pericom Semiconductor PI7C9X20303UL PI7C9X20303UL 3Port-3Lane PCI Express® Switch UltraLoTM Family Datasheet 1 Features 3-lane PCI Express Switch with 3 PCI Express ports Non-blocking full-wired switching capability at 12 Gbps when all 3 ports are enabled Supports "Cut-through"(Default) as well as "Store and Forward" mode for packet switching 150 ns typical latency for packet routed through Switch without blocking Strapped pins configurable with optional EEPROM or SMBus SMBus interface support Compliant with System Management (SM) Bus, Version 1.0 Compliant with PCI Express Base Specification Revision 1.1 Compliant with PCI Express CEM Specification Revision 1.1 Compliant with PCI-to-PCI Bridge Architecture Specification Revision 1.2 Compliant with Advanced Configuration Power Interface (ACPI) Specification Reliability, Availability and Serviceability - Supports Data Poisoning and End-to-End CRC - Advanced Error Reporting and Logging - IEEE 1149.6 JTAG interface support Advanced Power Saving - Empty downstream ports are set to idle state to minimize power consumption Link Power Management - Supports L0, L0s, L1, L2, L2/L3Ready and L3 link power states - Active state power management for L0s and L1 states Device State Power Management - Supports D0, D3Hot and D3Cold device power states - 3.3V Aux Power support in D3Cold power state Port Arbitration: Round Robin (RR), Weighted RR and Time-based Weighted RR Supports up to 256-byte maximum payload size Programmable driver current and de-emphasis level at each individual port Low Power Dissipation at 0.30 W typical in L0 normal mode, 0.15 W typical in L1 standby mode Industrial Temperature Range -40o to 85oC 132-pin TQFN 10mm x 10mm package Page 10 of 77 August 2009 Revision 1.1 Pericom Semiconductor PI7C9X20303UL PI7C9X20303UL 3Port-3Lane PCI Express® Switch UltraLoTM Family Datasheet 2 GENERAL DESCRIPTION Similar to the role of PCI/PCIX Bridge in PCI/PCIX bus architecture, the function of PCI Express (PCIE) Switch is to expand the connectivity to allow more end devices to be reached by host controllers in PCIE serial interconnect architecture. The 3-lane PCIE Switch can be configured as 3-port type combinations. It provides users the flexibility to expand or fan-out the PCI Express lanes based on their application needs. For some systems that do not need all the 3 lanes, the unused lanes can be disabled to reduce power consumption. In the PCI Express Architecture, the PCIE Switch forwards posted and non-posted requests and completion packets in either downstream or upstream direction concurrently as if a virtual PCI Bridge is in operation on each port. By visualizing the port as a virtual Bridge, the Switch can be logically viewed as two-level cascaded multiple virtual PCI-to-PCI Bridges, where one upstream-port Bridge sits on all downstream-port Bridges. Similar to a PCI Bridge during enumeration, each port is given a unique bus number, device number, and function number by the initiating software. The bus number, device number, and function number are combined to form a destination ID for each specific port. In addition to that, the memory-map and IO address ranges are exclusively allocated to each port as well. After the software enumeration is finished, the packets are routed to the dedicated port based on the embedded address or destination ID. To ensure the packet integrity during forwarding, the Switch is not allowed to split the packets to multiple small packets or merge the received packets into a large transmit packet. Also, the IDs of the requesters and completers are kept unchanged along the path between ingress and egress port. The Switch employs the architecture of Combined Input and Output Queue (CIOQ) in implementation. The main reason for choosing CIOQ is that the required memory bandwidth of input queue equals to the bandwidth of ingress port rather than increasing proportionally with port numbers as an output queue Switch does. The CIOQ at each ingress port contains separate dedicated queues to store packets. The packets are arbitrated to the egress port based on the PCIe transaction-ordering rule. For the packets without ordering information, they are permitted to pass over each other in case that the addressed egress port is available to accept them. As to the packets required to follow the ordering rule, the Head-Of-Line (HOL) issue becomes unavoidable for packets destined to different egress ports since the operation of producer-consumer model has to be retained; otherwise the system might occur hang-up problem. On the other hand, the Switch places replay buffer at each egress port to defer the packets before sending it out. This can assure the maximum throughput being achieved and therefore the Switch works efficiently. Another advantage of implementing CIOQ in PCIe Switch is that the credit announcement to the counterpart is simplified and streamlined because of the credit-based flow control protocol. The protocol requires that each ingress port maintains the credits independently without checking other ports' credit availability, which is otherwise required by pure output queue architecture. Page 11 of 77 August 2009 Revision 1.1 Pericom Semiconductor PI7C9X20303UL PI7C9X20303UL 3Port-3Lane PCI Express® Switch UltraLoTM Family Datasheet 3 PIN DESCRIPTION 3.1 PCI EXPRESS INTERFACE SIGNALS NAME REFCLKP REFCLKN PIN B42, B43 TYPE I DESCRIPTION Reference Clock Input Pairs: Connect to external 100MHz differential clock. The input clock signals must be delivered to the clock buffer cell through an AC-coupled interface so that only the AC information of the clock is received, converted, and buffered. It is recommended that a 0.1uF be used in the AC-coupling. PCI Express Data Serial Input Pairs: Differential data receive signals in three ports. PERP [2:0] I PERN [2:0] B57, A64, B48 I PETP [2:0] B56, B52, A60 O PCI Express Data Serial Output Pairs: Differential data transmit signals in three ports. PETN [2:0] A66, A62, A61 O PERST_L A25 I DWNRST_L [2:1] 3.2 A68, B53, A58 B44, A52 O Port 0 (Upstream Port) is PETP[0] and PETN[0] Port 1 (Downstream Port) is PETP[1] and PETN[1] Port 2 (Downstream Port) is PETP[2] and PETN[2] System Reset (Active LOW): When PERST_L is asserted, the internal states of whole chip except sticky logics are initialized. Downstream Device Reset (Active LOW): It provides a reset signal to the devices connected to the downstream ports of Switch. The signal is active when either PERST_L is asserted or the device is just plugged into the Switch. DWNRST_L [x] corresponds to Portx, where x= 1,2. PORT CONFIGURATION SIGNALS NAME SLOTCLK 3.3 Port 0 (Upstream Port) is PERP[0] and PERN[0] Port 1 (Downstream Port) is PERP[1] and PERN[1] Port 2 (Downstream Port) is PERP[2] and PERN[2] PIN B59 TYPE I DESCRIPTION Slot Clock Configuration: It determines if the downstream component uses the same physical reference clock that the platform provides on the connector. When SLOTCLK is high, the platform reference clock is employed. By default, all downstream ports use the same physical reference clock provided by platform. The pin has internal pull-down. MISCELLANEOUS SIGNALS NAME EECLK EEPD PIN A23 B19 TYPE O I/O SMBCLK B7 I SMBDATA B8 I/O SCAN_EN A31 I/O PORTERR [2:0] B24, A27, A26 O DESCRIPTION EEPROM Clock: Clock signal to the EEPROM interface. EEPROM Data: Bi-directional serial data interface to and from the EEPROM. The pin is set to 1 by default. The pin has internal pull-up. SMBus Clock: System management Bus Clock. The pin has internal pull-up. SMBus Data: Bi-directional System Management Bus Data. The pin has internal pull-up. Full-Scan Enable Control: For normal operation, SCAN_EN is an output with a value of "0". SCAN_EN becomes an input during manufacturing testing. Port PHY Error Status: These pins are used to display the PHY Error status of the ports. When PORTERR is flashing (alternating high and low signals), it indicates that a PHY error is detected. When it is low, no PHY error is detected. PORTERR [x] is correspondent to Port x, where x=0,1,2. Page 12 of 77 August 2009 Revision 1.1 Pericom Semiconductor PI7C9X20303UL PI7C9X20303UL 3Port-3Lane PCI Express® Switch UltraLoTM Family Datasheet NAME PRSNT [2:1] GPIO [7:0] B13, A15, B12, A14, B11, A13, A12, B10 PWR_SAV A10 I P0_CTCDIS P1_CTCDIS P2_CTCDIS TEST1/3/4/5/6/7 B9 B15 A18 A17, A8, B6, A7, A70, B18 I TEST2 A38 I NC 3.4 PIN A5, A71 TYPE I A1, A2, A3, A16, A19, A20, A24, A30, A35, A36, A37, A39, A40, A42, A46, A48, A49, A50, A53, A54, A55, A56, A59, A72, B4, B5, B28, B33, B34, B39, B40, B46 I/O I DESCRIPTION Present: When asserted low, it represents the device is present in the slot of downstream ports. Otherwise, it represents the absence of the device. PRSNT [x] is correspondent to Port x, where x=1,2. The pins have internal pull-down. General Purpose Input and Output: These eight general-purpose pins are programmed as either input-only or bi-directional pins by writing the GPIO output enable control register. When SMBus is implemented, GPIO[7:5] act as the SMBus address pins, which set Bit 2 to 0 of the SMBus address. Power Saving Mode: PWR_SAV is a strapping pin. When this pin is pulled high when system is reset, the Power Saving Mode is enabled. When this pin is pulled low when system is reset, the Power Saving Mode is disabled. When this pin is pulled low, it should be tied to ground through a pull-down resistor. When this pin is pulled high, a pull-up resistor should be used. The suggested value for the pull-up and pull-down resistor is 5.1K. Pin has an internal pull-down. P0/P1/P2 CTC Disable: These pins should be tied to ground through a pull-down resistor. The suggested value for the pull-down resistor is 5.1K. The pins have internal pull-down. Test1/3/4/5/6/7: These pins are for internal test purpose. Test1/3/4/5/6/7 should be tied to ground through a pull-down resistor. The suggested value for the pull-down resistor is 5.1K. Test2: This pin is for internal test purpose. Test2 should be tied to 3.3V through a pull-up resistor. The suggested value for the pull-up resistor is 5.1K. Not Connected: These pins can be left floating. JTAG BOUNDARY SCAN SIGNALS NAME TCK PIN B27 TYPE I TMS A34 I TDO A32 O TDI B29 I TRST_L B31 I DESCRIPTION Test Clock: Used to clock state information and data into and out of the chip during boundary scan. When JTAG boundary scan function is not implemented, this pin should be left open (NC). Test Mode Select: Used to control the state of the Test Access Port controller. The pin has internal pull-up. When JTAG boundary scan function is not implemented, this pin should be pulled low through a 5.1K pull-down resistor. Test Data Output: When SCAN_EN is high, it is used (in conjunction with TCK) to shift data out of the Test Access Port (TAP) in a serial bit stream. When JTAG boundary scan function is not implemented, this pin should be left open (NC). Test Data Input: When SCAN_EN is high, it is used (in conjunction with TCK) to shift data and instructions into the TAP in a serial bit stream. The pin has internal pull-up. When JTAG boundary scan function is not implemented, this pin should be left open (NC). Test Reset (Active LOW): Active LOW signal to reset the TAP controller into an initialized state. The pin has internal pull-up. When JTAG boundary scan function is not implemented, this pin should be pulled low through a 5.1K pull-down resistor. Page 13 of 77 August 2009 Revision 1.1 Pericom Semiconductor PI7C9X20303UL PI7C9X20303UL 3Port-3Lane PCI Express® Switch UltraLoTM Family Datasheet 3.5 POWER PINS NAME VDDC VDDR VDDA VDDAUX VAUX VTT VSS PIN A9, A21, A28, A29, A33, A41, A47, A57, A67, A69, B2, B14, B20, B22, B49 A6, A11, A22, B17, B23, B26, B47, B58 A44, A45, A51, A65, B37, B54 A43, A63, B3 A4 B35, B38, B51, B55 TYPE P DESCRIPTION VDDC Supply (1.0V): Used as digital core power pins. P VDDR Supply (3.3V): Used as digital I/O power pins. P VDDA Supply (1.0V): Used as analog power pins. P P P B1, B16, B21, B25, B30, B32, B36, B41, B45, B50, B60, GND P VDDAUX Supply (1.0V): Used as auxiliary core power pins. VAUX Supply (3.3V): Used as auxiliary I/O power pins. Transmit Termination Voltage (1.5V): Provides driver termination voltage at transmitter. Should be given the same consideration as VDDAUX. VSS Ground: Used as ground pins. GND: The central thermal pad underneath the package should be connected to ground. Page 14 of 77 August 2009 Revision 1.1 Pericom Semiconductor PI7C9X20303UL PI7C9X20303UL 3Port-3Lane PCI Express® Switch UltraLoTM Family Datasheet 4 PIN ASSIGNMENTS 4.1 PIN LIST of 132-PIN 132-PIN TQFN PIN A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 GND NAME NC NC NC VAUX PRSNT[2] VDDR TEST5 TEST3 VDDC PWR_SAV VDDR GPIO[1] GPIO[2] GPIO[4] GPIO[6] NC TEST1 P2_CTCDIS NC NC VDDC VDDR EECLK NC PERST_L PORTERR[0] PORTERR[1] VDDC VDDC NC SCAN_EN TDO VDDC VSS PIN A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 A49 A50 A51 A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62 A63 A64 A65 A66 NAME TMS NC NC NC TEST2 NC NC VDDC NC VDDAUX VDDA VDDA NC VDDC NC NC NC VDDA DWNRST_L[1] NC NC NC NC VDDC PERP[0] NC PETP[0] PETN[0] PETN[1] VDDAUX PERN[1] VDDA PETN[2] PIN A67 A68 A69 A70 A71 A72 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 Page 15 of 77 August 2009 Revision 1.1 Pericom Semiconductor NAME VDDC PERP[2] VDDC TEST6 PRSNT[1] NC VSS VDDC VDDAUX NC NC TEST4 SMBCLK SMBDATA P0_CTCDIS GPIO[0] GPIO[3] GPIO[5] GPIO[7] VDDC P1_CTCDIS VSS VDDR TEST7 EEPD VDDC VSS VDDC VDDR PORTERR[2] VSS VDDR TCK PIN B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40 B41 B42 B43 B44 B45 B46 B47 B48 B49 B50 B51 B52 B53 B54 B55 B56 B57 B58 B59 B60 NAME NC TDI VSS TRST_L VSS NC NC VTT VSS VDDA VTT NC NC VSS REFCLKP REFCLKN DWNRST_L[2] VSS NC VDDR PERN[0] VDDC VSS VTT PETP[1] PERP[1] VDDA VTT PETP[2] PERN[2] VDDR SLOTCLK VSS PI7C9X20303UL PI7C9X20303UL 3Port-3Lane PCI Express® Switch UltraLoTM Family Datasheet 5 FUNCTIONAL DESCRIPTION Multiple virtual PCI-to-PCI Bridges (VPPB), connected by a virtual PCI bus, reside in the Switch. Each VPPB contains the complete PCIe architecture layers that consist of the physical, data link, and transaction layer. The packets entering the Switch via one of VPPBs are first converted from serial bit-stream into parallel bus signals in physical layer, stripped off the link-related header by data link layer, and then relayed up to the transaction layer to extract out the transaction header. According to the address or ID embedded in the transaction header, the entire transaction packets are forwarded to the destination VPPB for formatting as a serial-type PCIe packet through the transmit circuits in the data link layer and physical layer. The following sections describe these function elements for processing PCIe packets within the Switch. 5.1 PHYSICAL LAYER CIRCUIT The physical layer circuit design is based on the PHY Interface for PCI Express Architecture (PIPE). It contains Physical Media Attachment (PMA) and Physical Coding Sub-layer (PCS) blocks. PMA includes Serializer/ Deserializer (SERDES), PLL1, Clock Recovery module, receiver detection circuits, electrical idle detector, and input/output buffers. PCS consists of framer, 8B/10B 8B/10B encoder/decoder, receiver elastic buffer, and PIPE PHY control/status circuitries. To provide the flexibility for port configuration, each lane has its own control and status signals for MAC to access individually. In addition, a pair of PRBS generator and checker is included for PHY built-in self test. The main functions of physical layer circuits include the conversion between serial-link and parallel bus, provision of clock source for the Switch, resolving clock difference in receiver end, and detection of physical layer errors. In order to meet the different application needs, the driving current and equalization of each transmitting channels can be adjusted using EEPROM individually. The driver current of each channel is set to 20mA in default mode. To change the current value, the user can program the EEPROM for nominal value (HIDRV, LODRV) or actual value (DTX [3:0]), which is a scaled multiple of Inom. The following tables illustrate the possible transmitted current values the chip provides. Table 5-1 Nominal Driver Current Values (Inom) HIDRV 0 0 1 1 LODRV 0 1 0 1 NOMINAL DRIVER CURENT 20 mA 10 mA 28 mA Reserved Table 5-2 Ratio of Actual Current and Nominal Current DTX [3:0] 0000 0001 0010 0011 0100 0101 0110 1 ACTUAL CURRENT / NOMINAL CURRENT 1.00 1.05 1.10 1.15 1.20 1.25 1.30 Multiple lanes could share the PLL. Page 16 of 77 August 2009 Revision 1.1 Pericom Semiconductor DTX [3:0] 0111 1000 1001 1010 1011 1100 1101 1110 1111 PI7C9X20303UL PI7C9X20303UL 3Port-3Lane PCI Express® Switch UltraLoTM Family Datasheet ACTUAL CURRENT / NOMINAL CURRENT 1.35 0.60 0.65 0.70 0.75 0.80 0.85 0.90 0.95 The equalization function of transmitting channels can optimize the driver current for different back-plane lengths and materials. The table shown below lists the combinations of de-emphasized driver current (ITX IEQ) to non-deemphasized driver current (ITX) for different values of DEQ [3:0]. Table 5-3 De-emphasis Level versus DEQ [3:0] DEQ [3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 (ITX IEQ) / ITX 1.00 0.96 0.92 0.88 0.84 0.80 0.76 0.72 0.68 0.64 0.60 0.56 0.52 0.48 0.44 0.40 De-emphasis (dB) 0.00 -0.35 -0.72 -1.11 -1.51 -1.94 -2.38 -2.85 -3.35 -3.88 -4.44 -5.04 -5.68 -6.38 -7.13 -7.96 By default, the DEQ is set to "1000" to conform to the PCI Express specification, which calls for a de-emphasis level of between 3 dB and 4 dB. In order to improve the data stream integrity across the channels, the receiver of each port of the Switch includes a reception equalizer to mitigate the effects of ISI. The reception equalizer is implemented as a selectable high-pass filter at the input node, and it is capable of removing as much as 0.4UI of ISI related jitter. The following table shows a simple guideline for selecting the appropriate value to adapt with different lengths or connector numbers in various applications. Table 5-4 Rx Equalizer Settings (RXEQCTL) RXEQCTL [1] 0 RXEQCTL [0] 0 Rx Eq Setting Max Rx Eq Input Jitter > 0.25 UI 0 1 Min Rx Eq 1 X Between 0.1 UI and 0.25 UI < 0.1 UI Page 17 of 77 August 2009 Revision 1.1 Pericom Semiconductor Channel Length > 20" and two or more connectors Between 8'' and 20" and up to two connectors 8" or less, up to one connector PI7C9X20303UL PI7C9X20303UL 3Port-3Lane PCI Express® Switch UltraLoTM Family Datasheet 5.2 DATA LINK LAYER (DLL) The Data Link Layer (DLL) provides a reliable data transmission between two PCI Express points. An ACK/NACK protocol is employed to guarantee the integrity of the packets delivered. Each Transaction Layer Packet (TLP) is protected by a 32-bit LCRC for error detection. The DLL receiver performs LCRC calculation to determine if the incoming packet is corrupted in the serial link. If an LCRC error is found, the DLL transmitter would issue a NACK data link layer packet (DLLP) to the opposite end to request a re-transmission, otherwise an ACK DLLP would be sent out to acknowledge on reception of a good TLP. In the transmitter, a retry buffer is implemented to store the transmitted TLPs whose corresponding ACK/NACK DLLP have not been received yet. When an ACK is received, the TLPs with sequence number equals to and smaller than that carried in the ACK would be flushed out from the buffer. If a NACK is received or no ACK/NACK is returned from the link partner after the replay timer expires, then a replay mechanism built in DLL transmitter is triggered to re-transmit the corresponding packet that receives NACK or time-out and any other TLP transmitted after that packet. Meanwhile, the DLL is also responsible for the initialization, updating, and monitoring of the flow-control credit. All of the flow control information is carried by DLLP to the other end of the link. Unlike TLP, DLLP is guarded by 16-bit CRC to detect if data corruption occurs. In addition, the Media Access Control (MAC) block, which is consisted of LTSSM, multiple lanes deskew, scrambler/de-scrambler, clock correction from inserting skip order-set, and PIPE-related control/status circuits, is implemented to interface physical layer with data link layer. 5.3 TRANSACTION LAYER RECEIVE BLOCK (TLP DECAPSULATION) The receiving end of the transaction layer performs header information retrieval and TC/VC mapping (see section 5.5), and it validates the correctness of the transaction type and format. If the TLP is found to contain illegal header or the indicated packet length mismatches with the actual packet length, then a Malformed TLP is reported as an error associated with the receiving port. To ensure end-to-end data integrity, a 32-bit ECRC is checked against the TLP at the receiver if the digest bit is set in header. 5.4 ROUTING The transaction layer implements three types of routing protocols: ID-based, address-based, and implicit routing. For configuration reads, configuration writes, transaction completion, and user-defined messages, the packets are routed by their destination ID constituted of bus number, device number, and function number. Address routing is employed to forward I/O or memory transactions to the destination port, which is located within the address range indicated by the address field carried in the packet header. The packet header indicates the packet types including memory read, memory write, IO read, IO write, Message Signaling Interrupt (MSI) and user-defined message. Implicit routing is mainly used to forward system message transactions such as virtual interrupt line, power management, and so on. The message type embedded in the packet header determines the routing mechanism. If the incoming packet can not be forwarded to any other port due to a miss to hit the defined address range or targeted ID, this is considered as Unsupported Request (UR) packet, which is similar to a master abort event in PCI protocol. Page 18 of 77 August 2009 Revision 1.1 Pericom Semiconductor PI7C9X20303UL PI7C9X20303UL 3Port-3Lane PCI Express® Switch UltraLoTM Family Datasheet 5.5 TC/VC MAPPING The 3-bit TC field defined in the header identifies the traffic class of the incoming packets. To enable the differential service, a TC/VC mapping table at destination port that is pre-programmed by system software or EEPROM pre-load is utilized to cast the TC labeled packets into the desired virtual channel. Note that all the traffic classes are mapped to VC0, since only VC0 is available on the Switch. After the TC/VC mapping, the receive block dispatches the incoming request, completion, or data into the VC0 queues. 5.6 QUEUE In PCI Express, it defines six different packet types to represent request, completion, and data. They are respectively Posted Request Header (PH), Posted Request Data payload (PD), Non-Posted Request Header (NPH), Non-Posted Data Payload (NPD), Completion Header (CPLH) and Completion Data payload (CPLD). Each packet with different type would be put into a separate queue in order to facilitate the following ordering processor. Since NPD usually contains one DW, it can be merged with the corresponding NPH into a common queue named NPHD. 5.6.1 PH PH queue provides TLP header spaces for posted memory writes and various message request headers. Each header space occupies sixteen bytes to accommodate 3 DW or 4 DW headers. 5.6.2 PD PD queue is used for storing posted request data. If the received TLP is of the posted request type and is determined to have payload coming with the header, the payload data would be put into PD queue. 5.6.3 NPHD NPHD queue provides TLP header spaces for non-posted request packets, which include memory read, IO read, IO write, configuration read, and configuration write. Each header space takes twenty bytes to accommodate a 3-DW header, s 4-DW header, s 3-WD header with 1-DW data, and a 4-DW header with 1-DW data. 5.6.4 CPLH CPLH queue provides TLP header space for completion packets. Each header space takes twelve bytes to accommodate a 3-DW header. Please note that there is no 4-DW completion headers. 5.6.5 CPLD CPLD queue is used for storing completion data. If the received TLP is of the completion type and is determined to have payload coming with the header, the payload data would be put into CPLD queue. Page 19 of 77 August 2009 Revision 1.1 Pericom Semiconductor PI7C9X20303UL PI7C9X20303UL 3Port-3Lane PCI Express® Switch UltraLoTM Family Datasheet 5.7 TRANSACTION ORDERING Within a VPPB, a set of ordering rules is defined to regulate the transactions on the PCI Express Switch including Memory, IO, Configuration and Messages, in order to avoid deadlocks and to support the Producer-Consumer model. The ordering rules defined in table 5-4 apply within a single Traffic Class (TC). There is no ordering requirement among transactions within different TC labels. Table 5-4 Summary of PCI Express Ordering Rules Row Pass Column Posted Request Read Request Non-posted Write Request Read Completion Non-Posted Write Completion Posted Request Yes/No1 No2 No2 Yes/No3 Yes4 Read Request Yes5 Yes Yes Yes Yes Non-posted Write Request Yes5 Yes Yes Yes Yes Read Completion Yes5 Yes Yes Yes Yes Non-posted Write Completion Yes5 Yes Yes Yes Yes 1. When the Relaxed Ordering Attribute bit is cleared, the Posted Request transactions including memory write and message request must complete on the egress bus of VPPB in the order in which they are received on the ingress bus of VPPB. If the Relaxed Ordering Attribute bit is set, the Posted Request is permitted to pass over other Posted Requests occurring before it. 2. A Read Request transmitting in the same direction as a previously queued Posted Request transaction must push the posted write data ahead of it. The Posted Request transaction must complete on the egress bus before the Read Request can be attempted on the egress bus. The Read transaction can go to the same location as the Posted data. Therefore, if the Read transaction were to pass the Posted transaction, it would return stale data. 3. When the Relaxed Ordering Attribute bit is cleared, a Read completion must ``pull'' ahead of previously queued posted data transmitting in the same direction. In this case, the read data transmits in the same direction as the posted data, and the requestor of the read transaction is on the same side of the VPPB as the completer of the posted transaction. The posted transaction must deliver to the completer before the read data is returned to the requestor. If the Relaxed Ordering Attribute bit is set, then a read completion is permitted to pass a previously queued Memory Write or Message Request. 4. Non-Posted Write Completions are permitted to pass a previous Memory Write or Message Request transaction. Such transactions are actually transmitting in the opposite directions and hence have no ordering relationship. 5. Posted Request transactions must be given opportunities to pass Non-posted Read and Write Requests as well as Completions. Otherwise, deadlocks may occur when some older Bridges that do not support delayed transactions are mixed with PCIe Switch in the same system. A fairness algorithm is used to arbitrate between the Posted Write queue and the Non-posted transaction queue. 5.8 PORT ARBITRATION Among multiple ingress ports, the port arbitration built in the egress port determines which input traffic to be forwarded to the output port. The arbitration algorithm contains hardware fixed Round Robin, 128-phase Weighted Round-Robin and programmable 128-phase time-based WRR. The port arbitration is held within the same VC channel. Each port has port arbitration circuitries for traffic handling in VC0. At upstream port, in addition to the traffic from inter-port, the intra-port packet such as configurations completion would also join the arbitration loop to get the service in Virtual Channel 0. Page 20 of 77 August 2009 Revision 1.1 Pericom Semiconductor PI7C9X20303UL PI7C9X20303UL 3Port-3Lane PCI Express® Switch UltraLoTM Family Datasheet 5.9 FLOW CONTROL PCI Express employs Credit-Based Flow Control mechanism to make buffer utilization more efficient. The transaction layer transmitter ensures that it does not transmit a TLP to an opposite receiver unless the receiver has enough buffer space to accept the TLP. The transaction layer receiver has the responsibility to advertise the free buffer space to an opposite transmitter to avoid packet stale. In this switch, each port has separate queues for different traffic types and the credits are on the fly sent to data link layer, which compares the current available credits with the monitored one and reports the updated credit to the counterpart. If no new credit is acquired, the credit reported is scheduled for every 30 us to prevent from link entering retrain. On the other hand, the receiver at each egress port gets the usable credits from the opposite end in a link. It would broadcast them to all the other ingress ports for gating the packet transmission. 5.10 TRANSATION LAYER TRANSMIT BLOCK (TLP ENCAPSULATION) The transmit portion of transaction layer performs the following functions. They are to construct the all types of forwarded TLP generated from VC arbiter, respond with the completion packet when the local resource (i.e. configuration register) is accessed and regenerate the message that terminated at receiver to RC if acts as an upstream port. Page 21 of 77 August 2009 Revision 1.1 Pericom Semiconductor PI7C9X20303UL PI7C9X20303UL 3Port-3Lane PCI Express® Switch UltraLoTM Family Datasheet 6 EEPROM INTERFACE AND SYSTEM MANAGEMENT BUS The EEPROM interface consists of two pins: EECLK (EEPROM clock output) and EEPD (EEPROM bidirectional serial data). The Switch may control an ISSI IS24C04 IS24C04 or compatible parts using into 512x8 bits. The EEPROM is used to initialize a number of registers before enumeration. This is accomplished after PRST# is deasserted, at which time the data from the EEPROM is loaded. The EEPROM interface is organized into a 16-bit base, and the Switch supplies a 7-bit EEPROM word address. The Switch does not control the EEPROM address input. It can only access the EEPROM with address input set to 0. The System Management Bus interface consists of two pins: SMBCLK (System Management Bus Clock input) and SMBDATA (System Management Bus Data input/ output). 6.1 EEPROM INTERFACE 6.1.1 AUTO MODE EERPOM ACCESS The Switch may access the EEPROM in a WORD format by utilizing the auto mode through a hardware sequencer. The EEPROM start-control, address, and read/write commands can be accessed through the configuration register. Before each access, the software should check the Autoload Status bit before issuing the next start. 6.1.2 EEPROM MODE AT RESET During a reset, the Switch will automatically load the information/data from the EEPROM if the automatic load condition is met. The first offset in the EEPROM contains a signature. If the signature is recognized, the autoload initiates right after the reset. During the autoload, the Bridge will read sequential words from the EEPROM and write to the appropriate registers. Before the Bridge registers can be accessed through the host, the autoload condition should be verified by reading bit [3] offset DCh (EEPROM Autoload Status). The host access is allowed only after the status of this bit is set to '0' which indicates that the autoload initialization sequence is complete. 6.1.3 EEPROM SPACE ADDRESS MAP 15 8 70 EEPROM Signature (1516h) Vendor ID Device ID Extended VC Count / Link Capability / Switch Mode Operation / Interrupt pin for Port 1 ~ 2 Subsystem Vender ID Subsystem ID Max_Payload_Size Support / ASPM Support / Role_Base Error Reporting / RefClk ppm Difference Reserved Revision ID NFTS / Scramble for Port0 NFTS / Scramble for Port1 NFTS / Scramble for Port2 Reserved Reserved Reserved Reserved Page 22 of 77 August 2009 Revision 1.1 Pericom Semiconductor BYTE OFFSET 00h 02h 04h 06h 08h 0Ah 0Ch 0Eh 10h 12h 14h 16h 18h 1Ah 1Ch PI7C9X20303UL PI7C9X20303UL 3Port-3Lane PCI Express® Switch UltraLoTM Family Datasheet 15 8 70 Reserved TC/VC Map for Port 0 (VC0) Slot Clock / LPVC Count / Port Num, Port 0 TC/VC Map for Port 1(VC0) Slot Implemented / Slot Clock / LPVC Count / Port Num, Port 1 TC/VC Map for Port 2 (VC0) Slot Implemented / Slot Clock / LPVC Count / Port Num, Port 2 Reserved Reserved Reserved Reserved Reserved Reserved Slot Capability 0 for Port 1 Slot Capability 0 for Port 2 Reserved Reserved Reserved Reserved Reserved Reserved Slot Capability 1 for Port 1 Slot Capability 1 for Port 2 Reserved Reserved Reserved Reserved Reserved PM Data for Port 0 PM Capability for Port 0 PM Data for Port 1 PM Capability for Port 1 PM Data for Port 2 PM Capability for Port 2 Reserved Reserved Reserved Reserved Reserved Power Budgeting Capability Register for Port 0 Power Budgeting Capability Register for Port 1 Power Budgeting Capability Register for Port 2 Reserved Reserved Reserved Reserved Reserved Replay Time-out Counter for Port 0 Replay Time-out Counter for Port 1 Replay Time-out Counter for Port 2 Reserved Reserved Reserved Reserved Reserved Acknowledge Latency Timer for Port 0 Acknowledge Latency Timer for Port 1 Acknowledge Latency Timer for Port 2 Reserved Reserved Reserved Reserved Reserved PHY Parameter for Port 0 PHY Parameter for Port 1 PHY Parameter for Port 2 Page 23 of 77 August 2009 Revision 1.1 Pericom Semiconductor BYTE OFFSET 1Eh 20h 22h 24h 26h 28h 2Ah 2Ch 2Eh 30h 32h 34h 36h 38h 3Ah 3Ch 3Eh 40h 42h 44h 46h 48h 4Ah 4Ch 4Eh 50h 52h 54h 56h 58h 5Ah 5Ch 5Eh 60h 62h 64h 66h 68h 6Ah 6Ch 6Eh 70h 72h 74h 76h 78h 7Ah 7Ch 7Eh 80h 82h 84h 86h 88h 8Ah 8Ch 8Eh 90h 92h 94h PI7C9X20303UL PI7C9X20303UL 3Port-3Lane PCI Express® Switch UltraLoTM Family Datasheet 15 8 70 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved PM Control Para/Rx Polarity for Port 0 PM Control Para/Rx Polarity for Port 1 PM Control Para/Rx Polarity for Port 2 Reserved BYTE OFFSET 96h 98h 9Ah 9Ch 9Eh A0h A2h A4h A6h 6.1.4 MAPPING EEPROM CONTENTS TO CONFIGURATION REGISTERS ADDRESS 00h 02h 04h 06h PCI CFG OFFSET 00h ~ 01h 02h ~ 03h 144h (Port 0~2) 144h: Bit [0] DESCRIPTION EEPROM signature 1516h Vendor ID Device ID Extended VC Count for Port 0 ~ 2 Bit [0]: It represents the supported VC count other than the default VC ECh (Port 0~2) ECh: Bit [14:12] ECh: Bit [17:15] B4h (Port 0~2) B4h:Bit [5] Bit [6] Bit [0] Bit [2:1] Bit [3] Bit [4] Switch Mode Operation for Port 0 Bit [8]: no ordering on packets for different egress port mode Bit [9]: no ordering on different tag of completion mode Bit [10]: Store and Forward Bit [12:11]: Cut-through Threshold Bit [13] : Port arbitrator Mode Bit [14]: Credit Update Mode 3Ch (Port 1~2) 3Ch: Bit [8]] C4h: Bit [15:0] C4h: Bit [31:16] E4h(Port 0~2) E4h: Bit 0 Interrupt pin for Port 1 ~ 2 Bit [15]: Set when INTA is requested for interrupt resource Subsystem Vender ID Subsystem ID Max_Payload_Size Support for Port 0 ~ 2 Bit [0]: Indicated the maximum payload size that the device can support for the TLP ECh(Port 0~2) ECh: Bit[11:10] ASPM Support for Port 0 ~ 2 Bit [2:1] : Indicate the level of ASPM supported on the PCIe link E4h(Port 0~2) E4h: Bit[15] Role_Base Error Reporting for Port 0 ~ 2 Bit [3] : Indicate implement the role-base error reporting B0h(port 0~2) B0h : Bit [14] MSI Capability Disable for Port 0~2 Bit [4] : Disable MSI capability B0h(port 0~2) B0h : Bit [15] AER Capability Disable for Port 0~2 Bit [5] : Disable AER capability B4h(port 0~2) B4h : Bit [15] Compliance Pattern Parity Control Disable for Port 0~2 Bit [6] : Disable compliance pattern parity B0h(port 0~2) B0h : Bit [13] Power Management Capability Disable for Port 0~2 Bit [7] : Disable Power Management Capability B4h(Port 0~2) B4h: Bit [7] Ordering Frozen for Port 0~2 Bit [10]: Freeze the ordering feature BCh(Port 0~2) 08h 0Ah 0Ch Link Capability for Port 0 ~ 2 Bit [3:1]: It represents L0s Exit Latency for all ports Bit [6:4]: It represents L1 Exit Latency for all ports TX SOF Latency Mode for Port 0~2 Page 24 of 77 August 2009 Revision 1.1 Pericom Semiconductor PI7C9X20303UL PI7C9X20303UL 3Port-3Lane PCI Express® Switch UltraLoTM Family Datasheet ADDRESS Surprise Down Capability Enable for Port 0~2 Bit [12]: Enable Surprise Down Capability BCh(Port 0~2) BCh: Bit[1] Power Management's Data Select Register R/W Capability for Port 0~2 Bit [13]: Enable Data Select Register R/W BCh(Port 0~2) BCh: Bit[2] 10h DESCRIPTION Bit [11]: Set to zero to shorten latency ECh(port0~2) ECh : Bit [19] 0Eh PCI CFG OFFSET BCh: Bit[0] Flow Control Update Type for Port 0~2 Bit [14]: Select Flow Control Update Type BCh(Port 0~2) BCh: Bit[3] 08h: Bit[7:0] 4KB Boundary Check Enable Bit [15]: Enable 4KB Boundary Check Revision ID Bit [7:0]: Indicates the Revision ID of chip. FTS Number for Port 0 Bit [7:0]: FTS number at receiver side B8h (port 0) B8h : Bit[7:0] A8h(Port 0) A8h: Bit [14:13] RefClk ppm Difference for Port 1 Bit [9:8]: It represents RefClk ppm difference between the two ends in one link; 00: 0 ppm, 01: 100 ppm, 10: 200 ppm, 11: 300 ppm B8h (port1) B8h : Bit[11:10] B8h : Bit[12] B8h (port 2) B8h : Bit[7:0] Scrambler Control for Port 1 Bit [11:10]: scrambler control Bit [12]: L0s FTS Number for Port 2 Bit [7:0]: FTS number at receiver side RefClk ppm Difference for Port 2 Bit [9:8]: It represents RefClk ppm difference between the two ends in one link; 00: 0 ppm, 01: 100 ppm, 10: 200 ppm, 11: 300 ppm B8h (port2) B8h : Bit[11:10] B8h : Bit[12] F0h (Port 0) F0h: Bit [28] Scrambler Control for Port 2 Bit [11:10]: scrambler control Bit [12]: L0s Slot Clock Configuration for Port 0 Bit [1]: When set, the component uses the clock provided on the connector 80h (Port 0) 80h: Bit[21] Device specific Initialization for Port 0 Bit [2]: When set, the DSI is required ECh (Port 0) ECh: Bit [25:24] Port Number for Port 0 Bit [5:4]: It represents the logic port numbering for physical port 0 84h (Port 0) 84h: Bit [14:13] 154h (Port 0) 154h: Bit [7:1] 20h Scrambler Control for Port 0 Bit [11:10]: scrambler control Bit [12]: L0s FTS Number for Port 1 Bit [7:0]: FTS number at receiver side A8h(Port 2) A8h: Bit [14:13] 14h B8h (port0) B8h : Bit[11:10] B8h : Bit[12] B8h (port 1) B8h : Bit[7:0] A8h(Port 1) A8h: Bit [14:13] 12h RefClk ppm Difference for Port 0 Bit [9:8]: It represents RefClk ppm difference between the two ends in one link; 00: 0 ppm, 01: 100 ppm, 10: 200 ppm, 11: 300 ppm PMCSR Data Scale for Port 0 Bit [7:6]: It represents the PMCSR Data Scale for physical port 0 VC0 TC/VC Map for Port 0 Bit [15:9]: When set, it indicates the corresponding TC is mapped into VC0 Page 25 of 77 August 2009 Revision 1.1 Pericom Semiconductor PI7C9X20303UL PI7C9X20303UL 3Port-3Lane PCI Express® Switch UltraLoTM Family Datasheet ADDRESS 22h DESCRIPTION PCIe Capability Slot Implemented for Port 1 Bit [0]: When set, the slot is implemented for Port 1 F0h (Port 1) F0h: Bit [28] Slot Clock Configuration for Port 1 Bit [1]: When set, the component uses the clock provided on the Connector 80h (Port 1) 80h: Bit[21] Device specific Initialization for Port 1 Bit [2]: When set, the DSI is required ECh (Port 1) ECh: Bit [25:24] Port Number for Port 1 Bit [5:4]: It represents the logic port numbering for physical port 1 84h (Port 1) 84h: Bit [14:13] 154h (Port 1) 154h: Bit [7:1] 24h PCI CFG OFFSET E0h (Port1) E0h: Bit [24] PMCSR Data Scale for Port 1 Bit [7:6]: It represents the PMCSR Data Scale for physical port 1 VC0 TC/VC Map for Port 1 Bit [15:9]: When set, it indicates the corresponding TC is mapped into VC0 PCIe Capability Slot Implemented for Port 2 Bit [0]: When set, the slot is implemented for Port 2 E0h (Port 2) E0h: Bit [24] F0h (Port 2) F0h: Bit [28] 80h (Port 2) 80h: Bit[21] 42h 44h 50h Port Number for Port 2 Bit [5:4]: It represents the logic port numbering for physical port 2 84h (Port 2) 84h: Bit [14:13] 154h (Port 2) 154h: Bit [7:1] 34h Device specific Initialization for Port 2 Bit [2]: When set, the DSI is required ECh (Port 2) ECh: Bit [25:24] 32h Slot Clock Configuration for Port 2 Bit [1]: When set, the component uses the clock provided on the Connector PMCSR Data Scale for Port 2 Bit [7:6]: It represents the PMCSR Data Scale for physical port 2 VC0 TC/VC Map for Port 2 Bit [15:9]: When set, it indicates the corresponding TC is mapped into VC0 Slot Capability 0 of Port 1 Bit [15:0]: Mapping to the low word of slot capability register Slot Capability 0 of Port 2 Bit [15:0]: Mapping to the low word of slot capability register Slot Capability 1 of Port 1 Bit [15:0]: Mapping to the high word of slot capability register Slot Capability 1 of Port 2 Bit [15:0]: Mapping to the high word of slot capability register No_Soft_Reset for Port 0 Bit [0]: No_Soft_Reset. F4h (Port 1) F4h: Bit [15:0] F4h (Port 2) F4h: Bit [15:0] F4h (Port 1) F4h: Bit [31:16] F4h (Port 2) F4h: Bit [31:16] 84h (Port 0) 84h: Bit [3] 80h (Port 0) 80h: Bit [24:22] 80h: Bit [25] 80h: Bit [26] 51h 80h: Bit [29:28] 84h (Port 0) 84h: Bit [31:24] Power Management Capability for Port 0 Bit [3:1]: AUX Current. Bit [4]: read only as 1 to indicate Bridge supports the D1 power management state Bit [5]: read only as 1 to indicate Bridge supports the D2 power management state Bit [7:6]: PME Support for D2 and D1 states Power Management Data for Port 0 Bit [15:8]: read only as Data register Page 26 of 77 August 2009 Revision 1.1 Pericom Semiconductor PI7C9X20303UL PI7C9X20303UL 3Port-3Lane PCI Express® Switch UltraLoTM Family Datasheet ADDRESS 52h PCI CFG OFFSET 84h (Port 1) 84h: Bit [3] DESCRIPTION No_Soft_Reset for Port 1 Bit [0]: No_Soft_Reset. 80h (Port 1) 80h: Bit [24:22] 80h: Bit [25] Power Management Capability for Port 1 Bit [3:1]: AUX Current. Bit [4]: read only as 1 to indicate Bridge supports the D1 power management state Bit [5]: read only as 1 to indicate Bridge supports the D2 power management state Bit [7:6]: PME Support for D2 and D1 states Power Management Data for Port 1 Bit [15:8]: read only as Data register No_Soft_Reset for Port 2 Bit [0]: No_Soft_Reset 80h: Bit [26] 53h 54h 80h: Bit [29:28] 84h (Port 1) 84h: Bit [31:24] 84h (Port 2) 84h: Bit [3] 80h (Port 2) 80h: Bit [24:22] 80h: Bit [25] 80h: Bit [26] 55h 60h 62h 64h 70h 72h 74h 80h 82h 84h 90h 92h 94h 80h: Bit [29:28] 84h (Port 2) 84h: Bit [31:24] 214h (Port 0) 214h Bit [7:0] 214h Bit [9:8] 214h Bit [14:13] 218h Bit [0] 214h (Port 1) 214h Bit [7:0] 214h Bit [9:8] 214h Bit [14:13] 218h Bit [0] 214h (Port 2) 214h Bit [7:0] 214h Bit [9:8] 214h Bit [14:13] 218h Bit [0] B0h (Port 0) B0h Bit [15:0] B0h (Port 1) B0h Bit [15:0] B0h (Port 2) B0h Bit [15:0] B0h (Port 0) B0h Bit [31:16] B0h (Port 1) B0h Bit [31:16] B0h (Port 2) B0h Bit [31:16] B4h (Port 0) B4h: Bit [31:16] B4h (Port 1) B4h: Bit [31:16] B4h (Port 2) B4h: Bit [31:16] Power Management Capability for Port 2 Bit [3:1]: AUX Current Bit [4]: read only as 1 to indicate Bridge supports the D1 power management state Bit [5]: read only as 1 to indicate Bridge supports the D2 power management state Bit [7:6]: PME Support for D2 and D1 states Power Management Data for Port 2 Bit [15:8] read only as Data register Power Budget Register for Port 0 Bit [7:0]: Base Power Bit [9:8]: Data Scale Bit [11:10]: PM State Bit [15]: System Allocated Power Budget Register for Port 1 Bit [7:0]: Base Power Bit [9:8]: Data Scale Bit [11:10]: PM State Bit [15]: System Allocated Power Budget Register for Port 2 Bit [7:0]: Base Power Bit [9:8]: Data Scale Bit [11:10]: PM State Bit [15]: System Allocated Replay Time-out Counter for Port 0 Bit [15:0]: Relay Time-out Counter Replay Time-out Counter for Port 1 Bit [15:0]: Relay Time-out Counter Replay Time-out Counter for Port 2 Bit [15:0]: Relay Time-out Counter Acknowledge Latency Timer for Port 0 Bit [31:16]: Acknowledge Latency Timer Acknowledge Latency Timer for Port 1 Bit [31:16]: Acknowledge Latency Timer Acknowledge Latency Timer for Port 2 Bit [31:16]: Acknowledge Latency Timer PHY Parameter for Port 0 Bit [31:16]: PHY Parameter PHY Parameter for Port 1 Bit [31:16]: PHY Parameter PHY Parameter for Port 2 Bit [31:16]: PHY Parameter Page 27 of 77 August 2009 Revision 1.1 Pericom Semiconductor PI7C9X20303UL PI7C9X20303UL 3Port-3Lane PCI Express® Switch UltraLoTM Family Datasheet ADDRESS A0h PM Control Parameter for Port 0 Bit [5:4] : L0s enable Bit [3:2] : L1 delay count select Bit [1:0] : D3 enters L1 B4h (Port 0) B4h : Bit [14] B0h (Port1) B0h: Bit[31] Rx Polarity Inversion Disable for port 0 Bit [6] : Disable Rx polarity capability Decode VGA for Port1 Bit [7] B4h (Port 1) B4h: Bit [13:8] PM Control Parameter for Port 1 Bit [5:4] : L0s enable Bit [3:2] : L1 delay count select Bit [1:0] : D3 enters L1 B4h (Port 1) B4h : Bit [14] B0h (Port2) B0h: Bit[31] Rx Polarity Inversion Disable for port 1 Bit [6] : Disable Rx polarity capability Decode VGA for Port2 Bit [7] B4h (Port 2) B4h: Bit [13:8] PM Control Parameter for Port 2 Bit [5:4] : L0s enable Bit [3:2] : L1 delay count select Bit [1:0] : D3 enters L1 B4h (Port 2) B4h : Bit [14] A4h DESCRIPTION Decode VGA for Port0 Bit [7] B4h (Port 0) B4h: Bit [13:8] A2h PCI CFG OFFSET B0h (Port0) B0h: Bit[31] Rx Polarity Inversion Disable for port 2 Bit [6] : Disable Rx polarity capability Page 28 of 77 August 2009 Revision 1.1 Pericom Semiconductor PI7C9X20303UL PI7C9X20303UL 3Port-3Lane PCI Express® Switch UltraLoTM Family Datasheet 6.2 SMBus INTERFACE The PI7C9X20303UL PI7C9X20303UL provides the System Management Bus (SMBus), a two-wire interface through which a simple device can communicate with the rest of the system. The SMBus interface on the PI7C9X20303UL PI7C9X20303UL is a bidirectional slave interface. It can receive data from the SMBus master or send data to the master. The interface allows full access to the configuration registers. A SMBus master, such as the processor or other SMBus devices, can read or write to every RW configuration register (read/write register). In addition, the RO and HwInt registers (read-only and hardware initialized registers) that can be auto-loaded by the EEPROM interface can also be read and written by the SMBus interface. This feature allows increases in the system expandability and flexibility in system implementation. Figure 6-1 SMBus Architecture Implementation on PI7C9X20303UL PI7C9X20303UL Processor (SMBus Master) PI7C9X20303UL PI7C9X20303UL Other SMBus Devices SMBCLK SMBDATA The SMBus interface on the PI7C9X20303UL PI7C9X20303UL consists of one SMBus clock pin (SMBCLK), a SMBus data pin (SMBDATA), and 3 SMBus address pins (GPIO[5:7]). The SMBus clock pin provides or receives the clock signal. The SMBus data pin facilitates the data transmission and reception. Both of the clock and data pins are bidirectional. The SMBus address pins determine the address to which the PI7C9X20303UL PI7C9X20303UL responds to. The SMBus address pins generate addresses according to the following table: Table 6-1 SMBus Address Pin Configuration BIT 0 1 2 3 4 5 6 SMBus Address GPIO[5] GPIO[6] GPIO[7] 1 0 1 1 Page 29 of 77 August 2009 Revision 1.1 Pericom Semiconductor PI7C9X20303UL PI7C9X20303UL 3Port-3Lane PCI Express® Switch UltraLoTM Family Datasheet 7 REGISTER DESCRIPTION 7.1 REGISTER TYPES REGISTER TYPE HwInt RO RW RWC RWCS RWS ROS 7.2 DEFINITION Hardware Initialization Read Only Read / Write Read / Write 1 to Clear Sticky - Read Only / Write 1 to Clear Sticky - Read / Write Sticky Read Only TRANSPARENT MODE CONFIGURATION REGISTERS When the port of switch is set to operate at the transparent mode, it is represented by a logical PCI-toPCI bridge that implements type 1 configuration space header. The following table details the allocation of the register fields of the PCI 2.3 compatible type 1 configuration space header. 31 24 23 16 15 - 8 Device ID Primary Status 7 0 Vendor ID Command Revision ID Primary Latency Timer Cache Line Size Reserved Secondary Latency Subordinate Bus Secondary Bus Primary Bus Number Timer Number Number Secondary Status I/O Limit Address I/O Base Address Memory Limit Address Memory Base Address Prefetchable Memory Limit Address Prefetchable Memory Base Address Prefetchable Memory Base Address Upper 32-bit Prefetchable Memory Limit Address Upper 32-bit I/O Limit Address Upper 16-bit I/O Base Address Upper 16-bit Reserved Capability Pointer to 80h Reserved Bridge Control Interrupt Pin Interrupt Line Reserved Power Management Capabilities Next Item Pointer=8C Capability ID=01 PM Data PPB Support Power Management Data Extensions Message Control Next Item Pointer=A4 Capability ID=05 Message Address Message Upper Address Reserved Message Data VPD Register Next Item Pointer=A4 Capability ID=03 VPD Data Register Length in Bytes (14h) Next Item Pointer=C0 Capability ID=09 XPIP_CSR0 XPIP_CSR1 ACK Latency Timer Replay Time-out Counter PHY Parameters Switch Operation Mode XPIP_CSR2 TL_CSR Reserved Next Item Pointer=E0 SSID/SSVID Capability ID=0D SSID SSVID Reserved Class Code Header Type Page 30 of 77 August 2009 Revision 1.1 Pericom Semiconductor BYTE OFFSET 00h 04h 08h 0Ch 10h 17h 18h 1Ch 20h 24h 28h 2Ch 30h 34h 38h 3Ch 40h 7Fh 80h 84h 8Ch 90h 94h 98h 9Ch A0h A4h A8h ACh B0h B4h B8h BCh C0h C4h 31 24 23 16 15 - 8 PI7C9X20303UL PI7C9X20303UL 3Port-3Lane PCI Express® Switch UltraLoTM Family Datasheet 7 0 BYTE OFFSET Reserved GPIO Data and Control EEPROM Data EEPROM Address EEPROM Control PCI Express Capabilities Register Next Item Pointer=00 Capability ID=10 Device Capabilities Device Status Device Control Link Capabilities Link Status Link Control Slot Capabilities Slot Status Slot Control Reserved C8h D7h D8h DCh E0h E4h E8h ECh F0h F4h F8h FCh Other than the PCI 2.3 compatible configuration space header, the Switch also implements PCI express extended configuration space header, which includes advanced error reporting, virtual channel, and power budgeting capability registers. The following table details the allocation of the register fields of PCI express extended capability space header. The first extended capability always begins at offset 100h with a PCI Express Enhanced Capability header and the rest of capabilities are located at an offset greater than 0FFh relative to the beginning of PCI compatible configuration space. 31 24 23 16 15 - 8 Next Capability Offset 7 0 Cap. PCI Express Extended Capability ID=0001h Version Uncorrectable Error Status Register Uncorrectable Error Mask Register Uncorrectable Error Severity Register Correctable Error Status Register Correctable Error Mask Register Advanced Error Capabilities and Control Register Header Log Register Reserved Next Capability Offset=20Ch Cap. PCI Express Extended Capability ID=0002h Version Port VC Capability Register 1 VC Arbitration Table Port VC Capability Register 2 Offset=3 Port VC Status Register Port VC Control Register Port Arbitration Table VC Resource Capability Register (0) Offset=4 VC Resource Control Register (0) VC Resource Status Register (0) Reserved Reserved Port Arbitration Table with 128 Phases for VC0 Reserved Reserved Next Capability Offset=000h Cap. PCI Express Extended Capability ID=0004h Version Reserved Data Select Register Data Register Reserved Power Budget Capability Register Page 31 of 77 August 2009 Revision 1.1 Pericom Semiconductor BYTE OFFSET 100h 104h 108h 10Ch 110h 114h 118h 11Ch 128h 12Ch 13Fh 140h 144h 148h 14Ch 150h 154h 158h 15Ch-17Ch 180h 1BCh 1C0h 1FCh 200h 20Bh 20Ch 210h 214h 218h PI7C9X20303UL PI7C9X20303UL 3Port-3Lane PCI Express® Switch UltraLoTM Family Datasheet 7.2.1 VENDOR ID REGISTER OFFSET 00h BIT 15:0 FUNCTION Vendor ID TYPE RO DESCRIPTION Identifies Pericom as the vendor of this device. The default value may be changed by SMBus or auto-loading from EEPROM. Reset to 12D8h. 7.2.2 DEVICE ID REGISTER OFFSET 00h BIT 31:16 FUNCTION Device ID TYPE RO DESCRIPTION Identifies this device as the PI7C9X20303UL PI7C9X20303UL. The default value may be changed by SMBus or auto-loading from EEPROM. Resets to 0303h. 7.2.3 COMMAND REGISTER OFFSET 04h BIT FUNCTION 0 I/O Space Enable 1 Memory Space Enable TYPE RW RW 2 Bus Master Enable RW 3 Special Cycle Enable Memory Write And Invalidate Enable VGA Palette Snoop Enable RO 4 5 RO RO 6 Parity Error Response Enable RW 7 Wait Cycle Control RO 8 SERR# enable RW 9 Fast Back-to-Back Enable 10 Interrupt Disable RO RW DESCRIPTION 0b: Ignores I/O transactions on the primary interface 1b: Enables responses to I/O transactions on the primary interface Resets to 0b. 0b: Ignores memory transactions on the primary interface 1b: Enables responses to memory transactions on the primary interface Reset to 0b. 0b: Does not initiate memory or I/O transactions on the upstream port and handles as an Unsupported Request (UR) to memory and I/O transactions on the downstream port. For Non-Posted Requests, a completion with UR completion status must be returned 1b: Enables the Switch Port to forward memory and I/O Read/Write transactions in the upstream direction Reset to 0b. Does not apply to PCI Express. Must be hardwired to 0b. Does not apply to PCI Express. Must be hardwired to 0b. Does not apply to PCI Express. Must be hardwired to 0b. 0b: Switch may ignore any parity errors that it detects and continue normal operation 1b: Switch must take its normal action when a parity error is detected Reset to 0b. Does not apply to PCI Express. Must be hardwired to 0. 0b: Disables the reporting of Non-fatal and Fatal errors detected by the Switch to the Root Complex b1: Enables the Non-fatal and Fatal error reporting to Root Complex Reset to 0b. Does not apply to PCI Express. Must be hardwired to 0b. Controls the ability of a PCI Express device to generate INTx Interrupt Messages. In the Switch, this bit does not affect the forwarding of INTx messages from the downstream ports. Reset to 0b. Page 32 of 77 August 2009 Revision 1.1 Pericom Semiconductor PI7C9X20303UL PI7C9X20303UL 3Port-3Lane PCI Express® Switch UltraLoTM Family Datasheet BIT 15:11 7.2.4 FUNCTION Reserved TYPE RO DESCRIPTION Reset to 0b. PRIMARY STATUS REGISTER OFFSET 04h BIT 18:16 FUNCTION Reserved 19 Interrupt Status RO 20 Capabilities List RO 21 22 66MHz Capable Reserved Fast Back-to-Back Capable RO RO 23 TYPE RO RO DESCRIPTION Reset to 000b. Indicates that an INTx Interrupt Message is pending internally to the device. In the Switch, the forwarding of INTx messages from the downstream device of the Switch port is not reflected in this bit. Must be hardwired to 0b. Set to 1 to enable support for the capability list (offset 34h is the pointer to the data structure). Reset to 1b. Does not apply to PCI Express. Must be hardwired to 0b. Reset to 0b. Does not apply to PCI Express. Must be hardwired to 0b. Set to 1 (by a requester) whenever a Parity error is detected or forwarded on the primary side of the port in a Switch. 24 Master Data Parity Error RWC 26:25 DEVSEL# timing RO 27 Signaled Target Abort RO 28 29 30 31 Received Target Abort Received Master Abort Signaled System Error Detected Parity Error RO RO RWC RWC If the Parity Error Response Enable bit is cleared, this bit is never set. Reset to 0b. Does not apply to PCI Express. Must be hardwired to 0b. Set to 1 (by a completer) whenever completing a request on the primary side using the Completer Abort Completion Status. Reset to 0b. Set to 1 (by a requestor) whenever receiving a Completion with Completer Abort Completion Status on the primary side. Reset to 0b. Set to 1 (by a requestor) whenever receiving a Completion with Unsupported Request Completion Status on primary side. Reset to 0b. Set to 1 when the Switch sends an ERR_FATAL or ERR_NONFATAL Message, and the SERR Enable bit in the Command register is 1. Reset to 0b. Set to 1 whenever the primary side of the port in a Switch receives a Poisoned TLP. Reset to 0b. 7.2.5 REVISION ID REGISTER OFFSET 08h BIT 7:0 7.2.6 FUNCTION Revision TYPE RO DESCRIPTION Indicates revision number of device. Hardwired to 03h. CLASS CODE REGISTER OFFSET 08h BIT 15:8 23:16 31:24 FUNCTION Programming Interface Sub-Class Code Base Class Code TYPE RO RO RO DESCRIPTION Read as 00h to indicate no programming interfaces have been defined for PCI-to-PCI Bridges. Read as 04h to indicate device is a PCI-to-PCI Bridge. Read as 06h to indicate device is a Bridge device. Page 33 of 77 August 2009 Revision 1.1 Pericom Semiconductor PI7C9X20303UL PI7C9X20303UL 3Port-3Lane PCI Express® Switch UltraLoTM Family Datasheet 7.2.7 CACHE LINE REGISTER OFFSET 0Ch BIT FUNCTION 7:0 Cache Line Size TYPE RW DESCRIPTION The cache line size register is set by the system firmware and the operating system cache line size. This field is implemented by PCI Express devices as a RW field for legacy compatibility, but it has no impact on any PCI Express device functionality. Reset to 0b. 7.2.8 PRIMARY LATENCY TIMER REGISTER OFFSET 0Ch BIT 15:8 7.2.9 FUNCTION Primary Latency timer TYPE RO HEADER TYPE REGISTER OFFSET 0Ch BIT FUNCTION TYPE 23:16 7.2.10 DESCRIPTION Does not apply to PCI Express. Must be hardwired to 00h. Header Type RO DESCRIPTION Read as 01h to indicate that the register layout conforms to the standard PCIto-PCI Bridge layout. PRIMARY BUS NUMBER REGISTER OFFSET 18h BIT FUNCTION 7:0 Primary Bus Number TYPE RW DESCRIPTION Indicates the number of the PCI bus to which the primary interface is connected. The value is set in software during configuration. Reset to 00h. 7.2.11 SECONDARY BUS NUMBER REGISTER OFFSET 18h BIT FUNCTION 15:8 Secondary Bus Number TYPE RW DESCRIPTION Indicates the number of the PCI bus to which the secondary interface is connected. The value is set in software during configuration. Reset to 00h. 7.2.12 SUBORDINATE BUS NUMBER REGISTER OFFSET 18h BIT FUNCTION 23:16 Subordinate Bus Number TYPE RW DESCRIPTION Indicates the number of the PCI bus with the highest number that is subordinate to the Bridge. The value is set in software during configuration. Reset to 00h. Page 34 of 77 August 2009 Revision 1.1 Pericom Semiconductor PI7C9X20303UL PI7C9X20303UL 3Port-3Lane PCI Express® Switch UltraLoTM Family Datasheet 7.2.13 SECONDARY LATENCY TIMER REGISTER OFFSET 18h BIT 31:24 7.2.14 FUNCTION Secondary Latency Timer TYPE RO DESCRIPTION Does not apply to PCI Express. Must be hardwired to 00h. I/O BASE ADDRESS REGISTER OFFSET 1Ch BIT 3:0 FUNCTION 32-bit Indicator 7:4 I/O Base Address [15:12] TYPE RO RW DESCRIPTION Read as 01h to indicate 32-bit I/O addressing. Defines the bottom address of the I/O address range for the Bridge to determine when to forward I/O transactions from one interface to the other. The upper 4 bits correspond to address bits [15:12] and are writable. The lower 12 bits corresponding to address bits [11:0] are assumed to be 0. The upper 16 bits corresponding to address bits [31:16] are defined in the I/O base address upper 16 bits address register. Reset to 0h. 7.2.15 I/O LIMIT ADDRESS REGISTER OFFSET 1Ch BIT 11:8 FUNCTION 32-bit Indicator 15:12 I/O Limit Address [15:12] TYPE RO RW DESCRIPTION Read as 01h to indicate 32-bit I/O addressing. Defines the top address of the I/O address range for the Bridge to determine when to forward I/O transactions from one interface to the other. The upper 4 bits correspond to address bits [15:12] and are writable. The lower 12 bits corresponding to address bits [11:0] are assumed to be FFFh. The upper 16 bits corresponding to address bits [31:16] are defined in the I/O limit address upper 16 bits address register. Reset to 0h. 7.2.16 SECONDARY STATUS REGISTER OFFSET 1Ch BIT 20:16 21 22 23 FUNCTION Reserved 66MHz Capable Reserved Fast Back-to-Back Capable TYPE RO RO RO RO DESCRIPTION Reset to 00000b. Does not apply to PCI Express. Must be hardwired to 0b. Reset to 0b. Does not apply to PCI Express. Must be hardwired to 0b. Set to 1 (by a requester) whenever a Parity error is detected or forwarded on the secondary side of the port in a Switch. 24 Master Data Parity Error RWC 26:25 DEVSEL_L timing RO 27 Signaled Target Abort RO 28 Received Target Abort RO If the Parity Error Response Enable bit is cleared, this bit is never set. Reset to 0b. Does not apply to PCI Express. Must be hardwired to 0b. Set to 1 (by a completer) whenever completing a request in the secondary side using Completer Abort Completion Status. Reset to 0b. Set to 1 (by a requestor) whenever receiving a Completion with Completer Abort Completion Status in the secondary side. Reset to 0b. Page 35 of 77 August 2009 Revision 1.1 Pericom Semiconductor PI7C9X20303UL PI7C9X20303UL 3Port-3Lane PCI Express® Switch UltraLoTM Family Datasheet BIT FUNCTION 29 Received Master Abort 30 31 Received System Error Detected Parity Error TYPE RO RWC RWC DESCRIPTION Set to 1 (by a requestor) whenever receiving a Completion with Unsupported Request Completion Status in secondary side. Reset to 0b. Set to 1 when the Switch sends an ERR_FATAL or ERR_NONFATAL Message, and the SERR Enable bit in the Bridge Control register is 1. Reset to 0b. Set to 1 whenever the secondary side of the port in a Switch receives a Poisoned TLP. Reset to 0b. 7.2.17 MEMORY BASE ADDRESS REGISTER OFFSET 20h BIT 3:0 FUNCTION Reserved 15:4 Memory Base Address [15:4] TYPE RO RW DESCRIPTION Reset to 0h. Defines the bottom address of an address range for the Bridge to determine when to forward memory transactions from one interface to the other. The upper 12 bits correspond to address bits [31:20] and are able to be written to. The lower 20 bits corresponding to address bits [19:0] are assumed to be 0. Reset to 000h. 7.2.18 MEMORY LIMIT ADDRESS REGISTER OFFSET 20h BIT 19:16 FUNCTION Reserved 31:20 Memory Limit Address [31:20] TYPE RO RW DESCRIPTION Reset to 0h. Defines the top address of an address range for the Bridge to determine when to forward memory transactions from one interface to the other. The upper 12 bits correspond to address bits [31:20] and are writable. The lower 20 bits corresponding to address bits [19:0] are assumed to be FFFFFh. Reset to 000h. 7.2.19 PREFETCHABLE MEMORY BASE ADDRESS REGISTER OFFSET 24h BIT 3:0 FUNCTION 64-bit addressing 15:4 Prefetchable Memory Base Address [31:20] TYPE RO RW DESCRIPTION Read as 0001b to indicate 64-bit addressing. Defines the bottom address of an address range for the Bridge to determine when to forward memory read and write transactions from one interface to the other. The upper 12 bits correspond to address bits [31:20] and are writable. The lower 20 bits are assumed to be 0. The memory base register upper 32 bits contain the upper half of the base address. Reset to 000h. 7.2.20 PREFETCHABLE MEMORY LIMIT ADDRESS REGISTER OFFSET 24h BIT 19:16 FUNCTION 64-bit addressing TYPE RO DESCRIPTION Read as 0001b to indicate 64-bit addressing. Page 36 of 77 August 2009 Revision 1.1 Pericom Semiconductor PI7C9X20303UL PI7C9X20303UL 3Port-3Lane PCI Express® Switch UltraLoTM Family Datasheet BIT FUNCTION 31:20 Prefetchable Memory Limit Address [31:20] TYPE RW DESCRIPTION Defines the top address of an address range for the Bridge to determine when to forward memory read and write transactions from one interface to the other. The upper 12 bits correspond to address bits [31:20] and are writable. The lower 20 bits are assumed to be FFFFFh. The memory limit upper 32 bits register contains the upper half of the limit address. Reset to 000h. 7.2.21 PREFETCHABLE MEMORY BASE ADDRESS UPPER 32-BITS 32-BITS REGISTER OFFSET 28h BIT FUNCTION 31:0 Prefetchable Memory Base Address, Upper 32-bits [63:32] TYPE RW DESCRIPTION Defines the upper 32-bits of a 64-bit bottom address of an address range for the Bridge to determine when to forward memory read and write transactions from one interface to the other. Reset to 00000000h. 7.2.22 PREFETCHABLE MEMORY LIMIT ADDRESS UPPER 32-BITS 32-BITS REGISTER OFFSET 2Ch BIT 31:0 7.2.23 FUNCTION Prefetchable Memory Limit Address, Upper 32-bits [63:32] TYPE RW DESCRIPTION Defines the upper 32-bits of a 64-bit top address of an address range for the Bridge to determine when to forward memory read and write transactions from one interface to the other. Reset to 00000000h. I/O BASE ADDRESS UPPER 16-BITS 16-BITS REGISTER OFFSET 30h BIT FUNCTION 15:0 I/O Base Address, Upper 16-bits [31:16] TYPE RW DESCRIPTION Defines the upper 16-bits of a 32-bit bottom address of an address range for the Bridge to determine when to forward I/O transactions from one interface to the other. Reset to 0000h. 7.2.24 I/O LIMIT ADDRESS UPPER 16-BITS 16-BITS REGISTER OFFSET 30h BIT FUNCTION 31:16 I/O Limit Address, Upper 16-bits [31:16] TYPE RW DESCRIPTION Defines the upper 16-bits of a 32-bit top address of an address range for the Bridge to determine when to forward I/O transactions from one interface to the other. Reset to 0000h. 7.2.25 CAPABILITY POINTER REGISTER OFFSET 34h BIT FUNCTION 7:0 Capability Pointer TYPE RO DESCRIPTION Pointer points to the PCI power management registers (80h). Page 37 of 77 August 2009 Revision 1.1 Pericom Semiconductor PI7C9X20303UL PI7C9X20303UL 3Port-3Lane PCI Express® Switch UltraLoTM Family Datasheet BIT 7.2.26 TYPE DESCRIPTION Reset to 80h. INTERRUPT LINE REGISTER OFFSET 3Ch BIT 7