NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
PI7C8150B 1-877-PERICOM PI7C8150B33 M66EN PI7C8150BI 208-PIN 256-BALL 32-BITS - Datasheet Archive
Asynchronous 2-Port PCI-to-PCI Bridge REVISION 1.08 3545 North First Street, San Jose, CA 95134 Telephone: 1-877-PERICOM,
PI7C8150B PI7C8150B Asynchronous 2-Port PCI-to-PCI Bridge REVISION 1.08 3545 North First Street, San Jose, CA 95134 Telephone: 1-877-PERICOM 1-877-PERICOM, (1-877-737-4266) Fax: 408-435-1100 solutions@pericom.com Email: Internet: http://www.pericom.com PI7C8150B PI7C8150B ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION LIFE SUPPORT POLICY Pericom Semiconductor Corporation's products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the manufacturer and an officer of PSC. 1) Life support devices or system are devices or systems which: a) Are intended for surgical implant into the body or b) Support or sustain life and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2) A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. Pericom Semiconductor Corporation reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. Pericom Semiconductor does not assume any responsibility for use of any circuitry described other than the circuitry embodied in a Pericom Semiconductor product. The Company makes no representations that circuitry described herein is free from patent infringement or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent, patent rights or other rights, of Pericom Semiconductor Corporation. All other trademarks are of their respective companies. Page 2 of 109 April 2009 Revision 1.08 PI7C8150B PI7C8150B ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION REVISION HISTORY Date 03/26/03 05/14/03 Revision Number 1.00 1.01 06/10/03 1.02 Added reset condition to offset 4Ch, bits [31:28] Revised descriptions and added ordering information for PI7C8150B33 PI7C8150B33 (33MHz) device 06/25/03 1.03 Revised temperature support to industrial temperature Revised temperature support back to extended commercial range (0C to 85C) 07/31/03 1.031 Description First Release of Data Sheet Correction to description for bit[0] at offset 48h. Changed from Memory Read Flow Through Disable to Memory Read Flow Through Enable. Corrected pin descriptions for S_M66EN M66EN, P_M66EN M66EN, and S_CLKOUT. Corrected MS0 and MS1 pin assignments on Table 2.4. MS0 should be B14 and MS1 should be R16. Added PBGA pin assignments to signal descriptions in Section 2.2. Revised power consumption specifications in section 17.6 10/20/03 02/13/04 1.04 1.05 05/20/04 1.06 07/06/04 1.061 07/07/05 04/06/09 1.07 1.08 Revised TDELAY specifications in sections 17.4 and 17.5 Modified spacing on a few chapters. No changes to content. Corrected VDD and VSS pin assignments on Table 2.2.7. Removed pins 106 and 155 (R16 and B14) as these should be MS1 and MS0 respectively. Added Industrial temp and Pb-free parts in the Ordering Information Added Ambient Temperature spec for PI7C8150BI PI7C8150BI Added industrial temp and Pb-free descriptions to the features section in the introduction Modified TDO and TDI JTAG Pin Description Added Industrial temp support of PI7C8150B PI7C8150B in Absolute Maximum Rating and Ordering Information Page 3 of 109 April 2009 Revision 1.08 PI7C8150B PI7C8150B ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION This page intentionally left blank. Page 4 of 109 April 2009 Revision 1.08 PI7C8150B PI7C8150B ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION TABLE OF CONTENTS 1 INTRODUCTION . 11 2 SIGNAL DEFINITIONS . 12 2.1 SIGNAL TYPES . 12 2.2 SIGNALS . 12 2.2.1 PRIMARY BUS INTERFACE SIGNALS . 12 2.2.3 CLOCK SIGNALS . 15 2.2.4 MISCELLANEOUS SIGNALS. 16 2.2.5 GENERAL PURPOSE I/O INTERFACE SIGNALS . 17 2.2.6 JTAG BOUNDARY SCAN SIGNALS . 17 2.2.7 POWER AND GROUND. 18 2.3 PIN LIST 208-PIN 208-PIN FQFP . 18 2.4 PIN LIST 256-BALL 256-BALL PBGA . 20 3 PCI BUS OPERATION . 22 3.1 TYPES OF TRANSACTIONS. 22 3.2 SINGLE ADDRESS PHASE . 23 3.3 DEVICE SELECT (DEVSEL_L) GENERATION . 23 3.4 DATA PHASE . 23 3.5 WRITE TRANSACTIONS . 23 3.5.1 MEMORY WRITE TRANSACTIONS. 24 3.5.2 MEMORY WRITE AND INVALIDATE . 25 3.5.3 DELAYED WRITE TRANSACTIONS. 25 3.5.4 WRITE TRANSACTION ADDRESS BOUNDARIES. 26 3.5.5 BUFFERING MULTIPLE WRITE TRANSACTIONS. 26 3.5.6 FAST BACK-TO-BACK TRANSACTIONS . 27 3.6 READ TRANSACTIONS. 27 3.6.1 PREFETCHABLE READ TRANSACTIONS. 27 3.6.2 NON-PREFETCHABLE READ TRANSACTIONS. 27 3.6.3 READ PREFETCH ADDRESS BOUNDARIES . 28 3.6.4 DELAYED READ REQUESTS . 29 3.6.5 DELAYED READ COMPLETION WITH TARGET . 29 3.6.6 DELAYED READ COMPLETION ON INITIATOR BUS. 29 3.6.7 FAST BACK-TO-BACK READ TRANSACTION . 30 3.7 CONFIGURATION TRANSACTIONS . 30 3.7.1 TYPE 0 ACCESS TO PI7C8150B PI7C8150B. 31 3.7.2 TYPE 1 TO TYPE 0 CONVERSION . 31 3.7.3 TYPE 1 TO TYPE 1 FORWARDING. 33 3.7.4 SPECIAL CYCLES . 34 3.8 TRANSACTION TERMINATION . 34 3.8.1 MASTER TERMINATION INITIATED BY PI7C8150B PI7C8150B . 35 3.8.2 MASTER ABORT RECEIVED BY PI7C8150B PI7C8150B . 36 3.8.3 TARGET TERMINATION RECEIVED BY PI7C8150B PI7C8150B. 36 3.8.4 TARGET TERMINATION INITIATED BY PI7C8150B PI7C8150B. 39 4 ADDRESS DECODING. 41 4.1 ADDRESS RANGES . 41 4.2 I/O ADDRESS DECODING. 41 4.2.1 I/O BASE AND LIMIT ADDRESS REGISTER. 42 4.2.2 ISA MODE. 43 Page 5 of 109 April 2009 Revision 1.08 PI7C8150B PI7C8150B ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION 4.3 MEMORY ADDRESS DECODING . 43 4.3.1 MEMORY-MAPPED I/O BASE AND LIMIT ADDRESS REGISTERS . 44 4.3.2 PREFETCHABLE MEMORY BASE AND LIMIT ADDRESS REGISTERS . 44 4.4 VGA SUPPORT. 45 4.4.1 VGA MODE. 46 4.4.2 VGA SNOOP MODE. 46 5 TRANSACTION ORDERING. 46 5.1 5.2 5.3 5.4 6 TRANSACTIONS GOVERNED BY ORDERING RULES . 47 GENERAL ORDERING GUIDELINES . 47 ORDERING RULES. 48 DATA SYNCHRONIZATION . 49 ERROR HANDLING. 50 6.1 ADDRESS PARITY ERRORS . 50 6.2 DATA PARITY ERRORS . 51 6.2.1 CONFIGURATION WRITE TRANSACTIONS TO CONFIGURATION SPACE. 51 6.2.2 READ TRANSACTIONS . 51 6.2.3 DELAYED WRITE TRANSACTIONS. 52 6.2.4 POSTED WRITE TRANSACTIONS. 55 6.3 DATA PARITY ERROR REPORTING SUMMARY. 56 6.4 SYSTEM ERROR (SERR_L) REPORTING. 60 7 EXCLUSIVE ACCESS . 61 7.1 CONCURRENT LOCKS . 61 7.2 ACQUIRING EXCLUSIVE ACCESS ACROSS PI7C8150B PI7C8150B . 61 7.2.1 LOCKED TRANSACTIONS IN DOWNSTREAM DIRECTION . 61 7.2.2 LOCKED TRANSACTION IN UPSTREAM DIRECTION . 63 7.3 ENDING EXCLUSIVE ACCESS. 63 8 PCI BUS ARBITRATION. 64 8.1 PRIMARY PCI BUS ARBITRATION . 64 8.2 SECONDARY PCI BUS ARBITRATION. 64 8.2.1 SECONDARY BUS ARBITRATION USING THE INTERNAL ARBITER. 64 8.2.2 PREEMPTION . 66 8.2.3 SECONDARY BUS ARBITRATION USING AN EXTERNAL ARBITER. 66 8.2.4 BUS PARKING. 66 9 CLOCKS . 67 9.1 9.2 9.3 10 10.1 10.2 10.3 PRIMARY CLOCK INPUTS. 67 SECONDARY CLOCK OUTPUTS . 67 ASYNCHRONOUS MODE. 67 GENERAL PURPOSE I/O INTERFACE. 68 GPIO CONTROL REGISTERS. 68 SECONDARY CLOCK CONTROL . 69 LIVE INSERTION . 70 11 PCI POWER MANAGEMENT . 71 12 RESET. 72 12.1 12.2 12.3 PRIMARY INTERFACE RESET. 72 SECONDARY INTERFACE RESET. 72 CHIP RESET. 73 Page 6 of 109 April 2009 Revision 1.08 PI7C8150B PI7C8150B ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION 13 13.1 13.2 14 SUPPORTED COMMANDS. 73 PRIMARY INTERFACE . 73 SECONDARY INTERFACE. 74 CONFIGURATION REGISTERS. 76 14.1 CONFIGURATION REGISTER . 76 14.1.1 VENDOR ID REGISTER OFFSET 00h. 77 14.1.2 DEVICE ID REGISTER OFFSET 00h . 77 14.1.3 COMMAND REGISTER OFFSET 04h. 77 14.1.4 STATUS REGISTER OFFSET 04h . 78 14.1.5 REVISION ID REGISTER OFFSET 08h . 79 14.1.6 CLASS CODE REGISTER OFFSET 08h. 79 14.1.7 CACHE LINE SIZE REGISTER OFFSET 0Ch . 79 14.1.8 PRIMARY LATENCY TIMER REGISTER OFFSET 0Ch . 79 14.1.9 HEADER TYPE REGISTER OFFSET 0Ch. 79 14.1.10 PRIMARY BUS NUMBER REGISTSER OFFSET 18h. 80 14.1.11 SECONDARY BUS NUMBER REGISTER OFFSET 18h . 80 14.1.12 SUBORDINATE BUS NUMBER REGISTER OFFSET 18h. 80 14.1.13 SECONDARY LATENCY TIMER REGISTER OFFSET 18h . 80 14.1.14 I/O BASE REGISTER OFFSET 1Ch. 80 14.1.15 I/O LIMIT REGISTER OFFSET 1Ch . 81 14.1.16 SECONDARY STATUS REGISTER OFFSET 1Ch. 81 14.1.17 MEMORY BASE REGISTER OFFSET 20h . 82 14.1.18 MEMORY LIMIT REGISTER OFFSET 20h. 82 14.1.19 PEFETCHABLE MEMORY BASE REGISTER OFFSET 24h . 82 14.1.20 PREFETCHABLE MEMORY LIMIT REGISTER OFFSET 24h . 82 14.1.21 PREFETCHABLE MEMORY BASE ADDRESS UPPER 32-BITS 32-BITS REGISTER OFFSET 28h . 83 14.1.22 PREFETCHABLE MEMORY LIMIT ADDRESS UPPER 32-BITS 32-BITS REGISTER OFFSET 2Ch. 83 14.1.23 I/O BASE ADDRESS UPPER 16-BITS 16-BITS REGISTER OFFSET 30h . 83 14.1.24 I/O LIMIT ADDRESS UPPER 16-BITS 16-BITS REGISTER OFFSET 30h. 83 14.1.25 ECP POINTER REGISTER OFFSET 34h. 83 14.1.26 INTERRUPT LINE REGISTER OFFSET 3Ch . 83 14.1.27 INTERRUPT PIN REGISTER OFFSET 3Ch. 84 14.1.28 BRIDGE CONTROL REGISTER OFFSET 3Ch . 84 14.1.29 DIAGNOSTIC / CHIP CONTROL REGISTER OFFSET 40h. 85 14.1.30 ARBITER CONTROL REGISTER OFFSET 40h. 86 14.1.31 EXTENDED CHIP CONTROL REGISTER OFFSET 48h. 87 14.1.32 UPSTREAM MEMORY CONTROL REGISTER OFFSET 48h . 87 14.1.33 SECONDARY BUS ARBITER PREEMPTION CONTROL REGISTER OFFSET 4Ch . 87 14.1.34 UPSTREAM (S TO P) MEMORY BASE REGISTER OFFSET 50h . 88 14.1.35 UPSTREAM (S TO P) MEMORY LIMIT REGISTER OFFSET 50h. 88 14.1.36 UPSTREAM (S TO P) MEMORY BASE UPPER 32-BITS 32-BITS REGISTER OFFSET 54h . 88 14.1.37 UPSTREAM (S TO P) MEMORY LIMIT UPPER 32-BITS 32-BITS REGISTER OFFSET 58h . 88 14.1.38 P_SERR_L EVENT DISABLE REGISTER OFFSET 64h. 88 14.1.39 GPIO DATA AND CONTROL REGISTER OFFSET 64h . 90 14.1.40 SECONDARY CLOCK CONTROL REGISTER OFFSET 68h . 90 14.1.41 P_SERR_L STATUS REGISTER OFFSET 68h . 91 14.1.42 PORT OPTION REGISTER OFFSET 74h . 91 Page 7 of 109 April 2009 Revision 1.08 PI7C8150B PI7C8150B ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION 14.1.43 14.1.44 14.1.45 14.1.46 14.1.47 14.1.48 14.1.49 14.1.50 14.1.51 14.1.52 14.1.53 14.1.54 14.1.55 15 RETRY COUNTER REGISTER OFFSET 78h . 93 PRIMARY MASTER TIMEOUT COUNTER OFFSET 80h . 93 SECONDARY MASTER TIMEOUT COUNTER OFFSET 80h . 93 CAPABILITY ID REGISTER OFFSET B0h . 93 NEXT POINTER REGISTER OFFSET B0h . 93 SLOT NUMBER REGISTER OFFSET B0h . 94 CHASSIS NUMBER REGISTER OFFSET B0h . 94 CAPABILITY ID REGISTER OFFSET DCh. 94 NEXT ITEM POINTER REGISTER OFFSET DCh . 94 POWER MANAGEMENT CAPABILITIES REGISTER OFFSET DCh . 94 POWER MANAGEMENT DATA REGISTER OFFSET E0h. 95 CAPABILITY ID REGISTER OFFSET E4h . 95 NEXT POINTER REGISTER OFFSET E4h . 95 BRIDGE BEHAVIOR. 96 15.1 BRIDGE ACTIONS FOR VARIOUS CYCLE TYPES . 96 15.2 ABNORMAL TERMINATION (INITIATED BY BRIDGE MASTER). 96 15.2.1 MASTER ABORT. 96 15.2.2 PARITY AND ERROR REPORTING . 96 15.2.3 REPORTING PARITY ERRORS . 97 15.2.4 SECONDARY IDSEL MAPPING . 97 16 IEEE 1149.1 COMPATIBLE JTAG CONTROLLER. 97 16.1 BOUNDARY SCAN ARCHITECTURE. 97 16.1.1 TAP PINS . 98 16.1.2 INSTRUCTION REGISTER . 98 16.2 BOUNDARY SCAN INSTRUCTION SET . 99 16.3 TAP TEST DATA REGISTERS. 100 16.4 BYPASS REGISTER . 100 16.5 BOUNDARY-SCAN REGISTER. 100 16.6 TAP CONTROLLER . 100 17 17.1 17.2 17.3 17.4 17.5 17.6 18 18.1 18.2 18.3 ELECTRICAL AND TIMING SPECIFICATIONS. 103 MAXIMUM RATINGS . 103 DC SPECIFICATIONS. 104 AC SPECIFICATIONS. 105 66MHZ 66MHZ TIMING. 105 33MHZ 33MHZ TIMING. 106 POWER CONSUMPTION . 106 PACKAGE INFORMATION. 107 208-PIN 208-PIN FQFP PACKAGE DIAGRAM . 107 256-BALL 256-BALL PBGA PACKAGE DIAGRAM . 108 PART NUMBER ORDERING INFORMATION. 108 Page 8 of 109 April 2009 Revision 1.08 PI7C8150B PI7C8150B ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION LIST OF TABLES Table 2-1. Pin List 208-pin FQFP. 18 Table 2-2. Pin List 256-pin PBGA. 20 Table 3-1. PCI Transactions . 22 Table 3-2. Write Transaction Forwarding . 23 Table 3-3. Write Transaction Disconnect Address Boundaries. 26 Table 3-4. Read Prefetch Address Boundaries. 28 Table 3-5. Read Transaction Prefetching. 28 Table 3-6. Device Number to IDSEL S_AD Pin Mapping. 32 Table 3-7. Delayed Write Target Termination Response . 37 Table 3-8. Response to Posted Write Target Termination. 37 Table 3-9. Response to Delayed Read Target Termination. 38 Table 5-1. Summary of Transaction Ordering . 48 Table 6-1. Setting the Primary Interface Detected Parity Error Bit . 56 Table 6-2. Setting Secondary Interface Detected Parity Error Bit. 57 Table 6-3. Setting Primary Interface Master Data Parity Error Detected Bit . 57 Table 6-4. Setting Secondary Interface Master Data Parity Error Detected Bit. 58 Table 6-5. Assertion of P_PERR_L . 58 Table 6-6. Assertion of S_PERR_L. 59 Table 6-7. Assertion of P_SERR_L for Data Parity Errors. 60 Table 10-1. GPIO Operation. 69 Table 10-2. GPIO Serial Data Format. 70 Table 11-1. Power Management Transitions . 71 Table 16-1. TAP Pins . 99 Table 16-2. JTAG Boundary Register Order. 101 LIST OF FIGURES Figure 8-1 Secondary Arbiter Example. 65 Figure 16-1 Test Access Port Block Diagram . 98 Figure 17-1 PCI Signal Timing Measurement Conditions . 105 Figure 18-1 208-pin FQFP Package Outline. 107 Figure 18-2 256-pin PBGA Package Outline. 108 Page 9 of 109 April 2009 Revision 1.08 PI7C8150B PI7C8150B ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION This page intentionally left blank. Page 10 of 109 April 2009 Revision 1.08 PI7C8150B PI7C8150B ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION 1 INTRODUCTION Product Description The PI7C8150B PI7C8150B is an enhanced PCI-to-PCI Bridge that will support asynchronous operation and is designed to be fully compliant with the PCI Local Bus Specification Revision 2.2. Both the primary and secondary interfaces are specified to run at 32-bits and up to 66MHz (33MHz for PI7C8150B-33 PI7C8150B-33). Product Features · · · · · · · 32-bit Primary and Secondary Ports run up to 66MHz (33MHz for PI7C8150B-33 PI7C8150B-33) Compliant with the PCI Local Bus Specification, Revision 2.2 Compliant with PCI-to-PCI Bridge Architecture Specification, Revision 1.1. All I/O and memory commands - Type 1 to Type 0 configuration conversion - Type 1 to Type 1 configuration forwarding - Type 1 configuration write to special cycle conversion Compliant with the Advanced Configuration Power Interface (ACPI) Specification. Compliant with the PCI Power Management Specification, Revision 1.0. Synchronous and Asynchronous operation support - - · · · · · · · · · Supported modes of asynchronous operation Primary (MHz) PI7C8150B PI7C8150B 25MHz to 66MHz PI7C8150B-33 PI7C8150B-33 25MHz to 33MHz Supported modes of synchronous operation Primary (MHz) PI7C8150B PI7C8150B 66 PI7C8150B PI7C8150B 66 PI7C8150B PI7C8150B 50 PI7C8150B PI7C8150B 50 PI7C8150B PI7C8150B 33 PI7C8150B-33 PI7C8150B-33 PI7C8150B PI7C8150B 25 PI7C8150B-33 PI7C8150B-33 Secondary (MHz) 25MHz to 66MHz 25MHz to 33MHz Secondary (MHz) 66 33 50 25 33 25 Provides internal arbitration for one set of nine secondary bus masters - Programmable 2-level priority arbiter - Disable control for use of external arbiter Supports posted write buffers in all directions Four 128 byte FIFO's for delay transactions Two 128 byte FIFO's for posted memory transactions Enhanced address decoding Temperature support - Industrial range -40°C to 85°C IEEE 1149.1 JTAG interface support 3.3V core; 3.3V and 5V signaling Packaging: 208-pin FQFP and 256-pin PBGA - Pb-free & Green Page 11 of 109 April 2009 Revision 1.08 PI7C8150B PI7C8150B ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION 2 SIGNAL DEFINITIONS 2.1 Signal Types Signal Type I O P TS STS Description Input Only Output Only Power Tri-State bi-directional Sustained Tri-State. Active LOW signal must be pulled HIGH for 1 cycle when deasserting. Open Drain OD 2.2 Signals Note: Signal names that end with "_L" are active LOW. 2.2.1 PRIMARY BUS INTERFACE SIGNALS Name P_AD[31:0] Pin # 49, 50, 55, 57, 58, 60, 61, 63, 67, 68, 70, 71, 73, 74, 76, 77, 93, 95, 96, 98, 99, 101, 107, 109, 112, 113, 115, 116, 118, 119, 121, 122 Pin # N3, T2, T4, N5, P5, T5, N6, R5, T6, P7, T7, R7, T8, P8, R8, T9, R12, P12, T14, R13, N12, T15, P16, N15, M14, M13, M15, L13, M16, L14, L15, L16 R6, R9, T13, N16 Type TS Description Primary Address / Data: Multiplexed address and data bus. Address is indicated by P_FRAME_L assertion. Write data is stable and valid when P_IRDY_L is asserted and read data is stable and valid when P_TRDY_L is asserted. Data is transferred on rising clock edges when both P_IRDY_L and P_TRDY_L are asserted. During bus idle, PI7C8150B PI7C8150B drives P_AD to a valid logic level when P_GNT_L is asserted. P_CBE[3:0] 64, 79, 92, 110 TS Primary Command/Byte Enables: Multiplexed command field and byte enable field. During address phase, the initiator drives the transaction type on these pins. After that, the initiator drives the byte enables during data phases. During bus idle, PI7C8150B PI7C8150B drives P_CBE[3:0] to a valid logic level when P_GNT_L is asserted. Primary Parity. Parity is even across P_AD[31:0], P_CBE[3:0], and P_PAR (i.e. an even number of 1's). P_PAR is an input and is valid and stable one cycle after the address phase (indicated by assertion of P_FRAME_L) for address parity. For write data phases, P_PAR is an input and is valid one clock after P_IRDY_L is asserted. For read data phase, P_PAR is an output and is valid one clock after P_TRDY_L is asserted. Signal P_PAR is tri-stated one cycle after the P_AD lines are tri-stated. During bus idle, PI7C8150B PI7C8150B drives P_PAR to a valid logic level when P_GNT_L is asserted. Primary FRAME (Active LOW). Driven by the initiator of a transaction to indicate the beginning and duration of an access. The de-assertion of P_FRAME_L indicates the final data phase requested by the initiator. Before being tri-stated, it is driven to a de-asserted state for one cycle. P_PAR 90 N11 TS P_FRAME_L 80 P9 STS Page 12 of 109 April 2009 Revision 1.08 PI7C8150B PI7C8150B ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION Name P_IRDY_L Pin # 82 Pin # T10 Type STS P_TRDY_L 83 R10 STS P_DEVSEL_L 84 P10 STS P_STOP_L 85 T11 STS P_LOCK_L 87 R11 STS P_IDSEL 65 P6 I P_PERR_L 88 T12 STS P_SERR_L 89 P11 OD P_REQ_L 47 P2 TS P_GNT_L 46 R1 I P_RESET_L 43 P1 I Description Primary IRDY (Active LOW). Driven by the initiator of a transaction to indicate its ability to complete current data phase on the primary side. Once asserted in a data phase, it is not de-asserted until the end of the data phase. Before tri-stated, it is driven to a de-asserted state for one cycle. Primary TRDY (Active LOW). Driven by the target of a transaction to indicate its ability to complete current data phase on the primary side. Once asserted in a data phase, it is not de-asserted until the end of the data phase. Before tri-stated, it is driven to a de-asserted state for one cycle. Primary Device Select (Active LOW). Asserted by the target indicating that the device is accepting the transaction. As a master, PI7C8150B PI7C8150B waits for the assertion of this signal within 5 cycles of P_FRAME_L assertion; otherwise, terminate with master abort. Before tri-stated, it is driven to a de-asserted state for one cycle. Primary STOP (Active LOW). Asserted by the target indicating that the target is requesting the initiator to stop the current transaction. Before tri-stated, it is driven to a de-asserted state for one cycle. Primary LOCK (Active LOW). Asserted by the master for multiple transactions to complete. Primary ID Select. Used as a chip select line for Type 0 configuration access to PI7C8150B PI7C8150B configuration space. Primary Parity Error (Active LOW). Asserted when a data parity error is detected for data received on the primary interface. Before being tri-stated, it is driven to a de-asserted state for one cycle. Primary System Error (Active LOW). Can be driven LOW by any device to indicate a system error condition. PI7C8150B PI7C8150B drives this pin on: Address parity error Posted write data parity error on target bus Secondary S_SERR_L asserted Master abort during posted write transaction Target abort during posted write transaction Posted write transaction discarded Delayed write request discarded Delayed read request discarded Delayed transaction master timeout This signal requires an external pull-up resistor for proper operation. Primary Request (Active LOW): This is asserted by PI7C8150B PI7C8150B to indicate that it wants to start a transaction on the primary bus. PI7C8150B PI7C8150B de-asserts this pin for at least 2 PCI clock cycles before asserting it again. Primary Grant (Active LOW): When asserted, PI7C8150B PI7C8150B can access the primary bus. During idle and P_GNT_L asserted, PI7C8150B PI7C8150B will drive P_AD, P_CBE, and P_PAR to valid logic levels. Primary RESET (Active LOW): When P_RESET_L is active, all PCI signals should be asynchronously tristated. Page 13 of 109 April 2009 Revision 1.08 PI7C8150B PI7C8150B ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION Name P_M66EN M66EN Pin # 102 Pin # R14 Type I Description Primary Interface 66MHz Operation. This input is used to specify if PI7C8150B PI7C8150B is capable of running at 66MHz. For 66MHz operation on the Primary bus, this signal should be pulled "HIGH". For 33MHz operation on the Primary bus, this signal should be pulled LOW. In synchronous mode, S_M66EN M66EN will be driven LOW, forcing the secondary bus to run at 33MHz also. Also, bit [21] offset 04h is determined by CFG66 CFG66. If P_M66EN M66EN is LOW, S_M66EN M66EN will not be driven LOW (please see S_M66EN M66EN pin description). In asynchronous mode, the logic value of P_M66EN M66EN is used to generate the value of bit[21] offset 04h. 2.2.2 SECONDARY BUS INTERFACE SIGNALS Name S_AD[31:0] S_CBE[3:0] Pin # 206, 204, 203, 201, 200, 198, 197, 195, 192, 191, 189, 188, 186, 185, 183, 182, 165, 164, 162, 161, 159, 154, 152, 150, 147, 146, 144, 143, 141, 140, 138, 137 194, 180, 167, 149 Pin # A4, D5, C5, A5, B5, D6, A6, C6, C7, A7, B7, C8, A8, B8, A9, C9, C12, D12, A14, B13, A15, B16, E13, C16, E14, D16, F13, E16, F14, F15, F16, G16 B6, B9, B12, E15 Type TS S_PAR 168 A13 TS S_FRAME_L 179 A10 STS S_IRDY_L 177 B10 STS S_TRDY_L 176 C10 STS TS Description Secondary Address/Data: Multiplexed address and data bus. Address is indicated by S_FRAME_L assertion. Write data is stable and valid when S_IRDY_L is asserted and read data is stable and valid when S_IRDY_L is asserted. Data is transferred on rising clock edges when both S_IRDY_L and S_TRDY_L are asserted. During bus idle, PI7C8150B PI7C8150B drives S_AD to a valid logic level when S_GNT_L is asserted respectively. Secondary Command/Byte Enables: Multiplexed command field and byte enable field. During address phase, the initiator drives the transaction type on these pins. The initiator then drives the byte enables during data phases. During bus idle, PI7C8150B PI7C8150B drives S_CBE[3:0] to a valid logic level when the internal grant is asserted. Secondary Parity: Parity is even across S_AD[31:0], S_CBE[3:0], and S_PAR (i.e. an even number of 1's). S_PAR is an input and is valid and stable one cycle after the address phase (indicated by assertion of S_FRAME_L) for address parity. For write data phases, S_PAR is an input and is valid one clock after S_IRDY_L is asserted. For read data phase, S_PAR is an output and is valid one clock after S_TRDY_L is asserted. Signal S_PAR is tri-stated one cycle after the S_AD lines are tri-stated. During bus idle, PI7C8150B PI7C8150B drives S_PAR to a valid logic level when the internal grant is asserted. Secondary FRAME (Active LOW): Driven by the initiator of a transaction to indicate the beginning and duration of an access. The de-assertion of S_FRAME_L indicates the final data phase requested by the initiator. Before being tri-stated, it is driven to a de-asserted state for one cycle. Secondary IRDY (Active LOW): Driven by the initiator of a transaction to indicate its ability to complete current data phase on the secondary side. Once asserted in a data phase, it is not de-asserted until the end of the data phase. Before tri-stated, it is driven to a de-asserted state for one cycle. Secondary TRDY (Active LOW): Driven by the target of a transaction to indicate its ability to complete current data phase on the secondary side. Once asserted in a data phase, it is not de-asserted until the end of the data phase. Before tri-stated, it is driven to a de-asserted state for one cycle. Page 14 of 109 April 2009 Revision 1.08 PI7C8150B PI7C8150B ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION Name S_DEVSEL_L Pin # 175 Pin # A11 Type STS S_STOP_L 173 B11 STS S_LOCK_L 172 C11 STS S_PERR_L 171 A12 STS S_SERR_L 169 D11 I S_REQ_L[8:0] 9, 8, 7, 6, 5, 4, 3, 2, 207 E4, E3, D2, C1, C2, D3, A2,B3, B4 I S_GNT_L[8:0] 19, 18, 17, 16, 15, 14, 13, 11, 10 G1, F1, F2, G3, F4, E1, E2,F3, D1 TS S_RESET_L 22 H1 O S_M66EN M66EN 153 D15 I/OD S_CFN_L 2.2.3 23 H2 I Description Secondary Device Select (Active LOW): Asserted by the target indicating that the device is accepting the transaction. As a master, PI7C8150B PI7C8150B waits for the assertion of this signal within 5 cycles of S_FRAME_L assertion; otherwise, terminate with master abort. Before tri-stated, it is driven to a de-asserted state for one cycle. Secondary STOP (Active LOW): Asserted by the target indicating that the target is requesting the initiator to stop the current transaction. Before tri-stated, it is driven to a de-asserted state for one cycle. Secondary LOCK (Active LOW): Asserted by the master for multiple transactions to complete. Secondary Parity Error (Active LOW): Asserted when a data parity error is detected for data received on the secondary interface. Before being tri-stated, it is driven to a de-asserted state for one cycle. Secondary System Error (Active LOW): Can be driven LOW by any device to indicate a system error condition. Secondary Request (Active LOW): This is asserted by an external device to indicate that it wants to start a transaction on the secondary bus. The input is externally pulled up through a resistor to VDD. Secondary Grant (Active LOW): PI7C8150B PI7C8150B asserts this pin to access the secondary bus. PI7C8150B PI7C8150B deasserts this pin for at least 2 PCI clock cycles before asserting it again. During idle and S_GNT_L asserted, PI7C8150B PI7C8150B will drive S_AD, S_CBE, and S_PAR. Secondary RESET (Active LOW): Asserted when any of the following conditions are met: 1. Signal P_RESET_L is asserted. 2. Secondary reset bit in bridge control register in configuration space is set. When asserted, all control signals are tri-stated and zeroes are driven on S_AD, S_CBE, and S_PAR. Secondary Interface 66MHz Operation: In synchronous mode, this input is used to specify if PI7C8150B PI7C8150B is running at 66MHz on the secondary side. When HIGH, the Secondary bus may run at 66MHz. When LOW, the Secondary bus may only run at 33MHz. If P_M66EN M66EN is pulled LOW, the S_M66EN M66EN is also driven LOW. In asynchronous mode, S_M66EN M66EN is an input pin and operates independently from P_M66EN M66EN. S_M66EN M66EN should be pulled up to a logic "1" when the secondary frequency is 66MHz, or pulled down to a logic "0" when the secondary frequency is 33MHz. Secondary Bus Central Function Control Pin: When tied LOW, it enables the internal arbiter. When tied HIGH, an external arbiter must be used. S_REQ_L[0] is reconfigured to be the secondary bus grant input, and S_GNT_L[0] is reconfigured to be the secondary bus request output. S_CFN_L has a weak internal pulldown resistor. CLOCK SIGNALS Name P_CLK Pin # 45 Pin # M4 Type I Description Primary Clock Input: Provides timing for all transactions on the primary interface. Page 15 of 109 April 2009 Revision 1.08 PI7C8150B PI7C8150B ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION Name S_CLKIN Pin # 21 Pin # H3 S_CLKOUT[9:0] 42, 41, 39, 38, 36, 35, 33, 32, 30, 29 M3, M2, N1, L4, L3, M1, L2, L1, K3, K2 Type I O Description Secondary Clock Input: Provides timing for all transactions on the secondary interface. Secondary Clock Output: Provides secondary clocks phase synchronous with the P_CLK in synchronous mode. When these clocks are used, one of the clock outputs must be fed back to S_CLKIN. Unused outputs may be disabled by: 1. Writing the secondary clock disable bits in the configuration space 2. Using the serial disable mask using the GPIO pins and MSK_IN 3. Terminating them electrically. In asynchronous mode, S_CLKOUT[5:0] are derived from MSK_IN / ASYNC_CLKIN (please see CFG66 CFG66 / SCAN_EN_H / CLK_RATE pin description). 2.2.4 MISCELLANEOUS SIGNALS Name MSK_IN / ASYNC_CLKIN Pin # 126 Pin # K15 Type I Description This is a multiplexed pin that is MSK_IN in synchronous mode and ASYNC_CLK_IN in asynchronous mode. This pin has a weak internal pulldown resistor. MSK_IN - Secondary Clock Disable Serial Input (synchronous mode): This pin is used by PI7C8150B PI7C8150B to disable secondary clock outputs. The serial stream is received by MSK_IN, starting when P_RESET is detected deasserted and S_RESET_L is detected as being asserted. The serial data is used for selectively disabling secondary clock outputs and is shifted into the secondary clock control configuration register. This pin can be tied LOW to enable all secondary clock outputs or tied HIGH to drive all the secondary clock outputs HIGH. P_VIO 124 K14 I S_VIO 135 G14 I BPCCE 44 N2 I ASYNC_CLKIN Secondary Clock Input (asynchronous mode): The asynchronous clock for the secondary interface should be connected to this pin in asynchronous mode. S_CLKOUT[9:0] will be derived from ASYNC_CLKIN. Primary I/O Voltage: This pin is used to determine either 3.3V or 5V signaling on the primary bus. P_VIO must be tied to 3.3V only when all devices on the primary bus use 3.3V signaling. Otherwise, P_VIO is tied to 5V. Secondary I/O Voltage: This pin is used to determine either 3.3V or 5V signaling on the secondary bus. S_VIO must be tied to 3.3V only when all devices on the secondary bus use 3.3V signaling. Otherwise, S_VIO is tied to 5V. Bus/Power Clock Control Management Pin: When this pin is tied HIGH and the PI7C8150B PI7C8150B is placed in the D3HOT power state, it enables the PI7C8150B PI7C8150B to place the secondary bus in the B2 power state. The secondary clocks are disabled and driven to 0. When this pin is tied LOW, there is no effect on the secondary bus clocks when the PI7C8150B PI7C8150B enters the D3HOT power state. Page 16 of 109 April 2009 Revision 1.08 PI7C8150B PI7C8150B ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION CFG66 CFG66 / SCAN_EN_H / CLK_RATE 125 K16 I This is a multiplexed pin that has 3 functions (2 in synchronous mode and 1 in asynchronous mode). CFG66 CFG66 - 66MHz Configuration (synchronous mode): This pin is used to designate 66MHz operation. Tie HIGH to enable 66MHz operation or tie LOW to designate 33MHz operation. SCAN_EN_H - Full-Scan Enable Control (synchronous mode): When SCAN_EN_H is LOW, full-scan is in shift operation. When SCAN_EN_H is HIGH, full-scan is in parallel operation. Note: Valid only in test mode. Pin is CFG66 CFG66 in normal operation. CLK_RATE S_CLKOUT divider (asynchronous mode): Determines the S_CLKOUT frequency relation to ASYNC_CLK_IN. 0: S_SCLKOUT is half the frequency of ASYNC_CLK_IN. MS0, MS1 155, 106 B14, R16 I 1: S_CLKOUT is the same frequency as ASYNC_CLK_IN. Mode Selection: Selector for Asynchronous or Synchronous mode. MS0 0 0 1 1 2.2.5 Description RESERVED RESERVED Synchronous Mode Asynchronous Mode GENERAL PURPOSE I/O INTERFACE SIGNALS Name GPIO[3:0] 2.2.6 MS1 0 1 0 1 Pin # 24, 25, 27, 28 Pin # J3, J2, J1, K1 Type TS Description General Purpose I/O Data Pins: The 4 generalpurpose signals are programmable as either input-only or bi-directional signals by writing the GPIO output enable control register in the configuration space. Description Test Clock. Used to clock state information and data into and out of the PI7C8150B PI7C8150B during boundary scan. Test Mode Select. Used to control the state of the Test Access Port controller. Test Data Output. Used as the serial output for the test instructions and data from the test logic. Test Data Input. Serial input for the JTAG instructions and test data. Test Reset. Active LOW signal to reset the Test Access Port (TAP) controller into an initialized state. JTAG BOUNDARY SCAN SIGNALS Name TCK Pin # 133 Pin # H15 Type I TMS 132 H14 I TDO 130 H16 O TDI 129 J15 I TRST_L 134 G15 I Page 17 of 109 April 2009 Revision 1.08 PI7C8150B PI7C8150B ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION 2.2.7 POWER AND GROUND Name VDD VSS 2.3 Pin # 1, 26, 34, 40, 51, 53, 56, 62, 69, 75, 81, 91, 97, 103, 105, 108, 114, 120, 131, 139, 145, 151, 155, 157, 163, 170, 178, 184, 190, 196, 202, 208 12, 20, 31, 37, 48, 52, 54, 59, 66, 72, 78, 86, 94, 100, 104, 106, 111, 117, 123, 136, 142, 148, 156, 158, 160, 166, 174, 181, 187, 193, 199, 205 Pin # A3, C4, C15, D7, D8, D9, D10, E6, E7, E8, E9, E10, E11, F5, F12, G4, G5, G12, G13, H4, H5, H12, H13, J4, J5, J12, J13, K4, K5, K12, K13, L5, L12, M6, M7, M8, M9, M10, M11, N7, N8, N9, N10, P13, P15, R3, T3 A1, A16, B1, B2, B15, C3, C13, C14, D4, D13, D14, E5, E12, F6, F7, F8, F9, F10, F11, G2, G6, G7, G8, G9, G10, G11, H6, H7, H8, H9, H10, H11, J6, J7, J8, J9, J10, J11, K6, K7, K8, K9, K10, K11, L6, L7, L8, L9, L10, L11, M5, M12, N4, N13, N14, P3, P4, P14, R2, R4, R15, T1, T16 Type P P Description Power: +3.3V Digital power. Ground: Digital ground. PIN LIST 208-PIN 208-PIN FQFP Table 2-1. Pin List 208-pin FQFP Pin Number 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 Name VDD S_REQ_L[2] S_REQ_L[4] S_REQ_L[6] S_REQ_L[8] S_GNT_L[1] S_GNT_L[2] S_GNT_L[4] S_GNT_L[6] S_GNT_L[8] S_CLKIN S_CFN_L GPIO[2] GPIO[1] S_CLKOUT[0] VSS Type P I I I I TS TS TS TS TS I I TS TS O P Pin Number 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 Name S_REQ_L[1] S_REQ_L[3] S_REQ_L[5] S_REQ_L[7] S_GNT_L[0] VSS S_GNT_L[3] S_GNT_L[5] S_GNT_L[7] VSS S_RESET_L GPIO[3] VDD GPIO[0] S_CLKOUT[1] S_CLKOUT[2] Type I I I I TS P TS TS TS P O TS P TS O O Page 18 of 109 April 2009 Revision 1.08 PI7C8150B PI7C8150B ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION Pin Number 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 Name S_CLKOUT[3] S_CLKOUT[4] VSS S_CLKOUT[7] S_CLKOUT[8] P_RESET_L P_CLK P_REQ_L P_AD[31] VDD VDD P_AD[29] P_AD[28] VSS P_AD[25] P_AD[24] P_IDSEL P_AD[23] VDD P_AD[20] P_AD[19] VDD P_AD[16] P_CBE[2] VDD P_TRDY_L P_STOP_L P_LOCK_L P_SERR_L VDD P_AD[15] P_AD[14] VDD P_AD[11] P_AD[10] VDD VDD P_AD[9] P_AD[8] VSS P_AD[6] P_AD[5] VSS P_AD[2] P_AD[1] VSS CFG66 CFG66 / SCAN_EN_H / CLK_RATE RESERVED TDI VDD TCK S_VIO S_AD[0] VDD S_AD[3] S_ADD[4] VDD S_AD[7] S_CBE[0] VDD S_M66EN M66EN MS0 Type O O P O O I I TS TS P P TS TS P TS TS I TS P TS TS P TS TS P STS STS STS STS P TS TS P TS TS P P TS TS P TS TS P TS TS P I Pin Number 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 I P I I TS P TS TS P TS TS P I/OD I 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 Name VDD S_CLKOUT[5] S_CLKOUT[6] VDD S_CLKOUT[9] BPCCE P_GNT_L VSS P_AD[30] VSS VSS VDD P_AD[27] P_AD[26] VDD P_CBE[3] VSS P_AD[22] P_AD[21] VSS P_AD[18] P_AD[17] VSS P_FRAME_L P_IRDY_L P_DEVSEL_L VSS P_PERR_L P_PAR P_CBE[1] VSS P_AD[13] P_AD[12] VSS P_M66EN M66EN VSS MS1 VDD P_CBE[0] P_AD[7] VDD P_AD[4] P_AD[3] VDD P_AD[0] P_VIO MSK_IN ASYNC_CLK_IN RESERVED TDO TMS TRST_L VSS S_AD[1] S_AD[2] VSS S_AD[5] S_AD[6] VSS S_AD[8] S_AD[9] S_AD[10] VSS Type P O O P O I I P TS P P P TS TS P TS P TS TS P TS TS P STS STS STS P STS STS TS P TS TS P I P I P TS TS P TS TS P TS I I O I I P TS TS P TS TS P TS TS TS P Page 19 of 109 April 2009 Revision 1.08 PI7C8150B PI7C8150B ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION Pin Number 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203 205 207 2.4 Name VDD S_AD[11] S_AD[12] VDD S_AD[15] S_CBE[1] S_SERR_L S_PERR_L S_STOP_L S_DEVSEL_L S_IRDY_L S_FRAME_L VSS S_AD[17] S_AD[18] VSS S_AD[21] S_AD[22] VSS S_AD[24] S_AD[25] VSS S_AD[28] S_AD[29] VSS S_REQ_L[0] Type P TS TS P TS TS I STS STS STS STS STS P TS TS P TS TS P TS TS P TS TS P I Pin Number 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204 206 208 Name VSS VSS S_AD[13] S_AD[14] VSS S_PAR VDD S_LOCK_L VSS S_TRDY_L VDD S_CBE[2] S_AD[16] VDD S_AD[19] S_AD[20] VDD S_AD[23] S_CBE[3] VDD S_AD[26] S_AD[27] VDD S_AD[30] S_AD[31] VDD Type P P TS TS P TS P STS P STS P TS TS P TS TS P TS TS P TS TS P TS TS P PIN LIST 256-BALL 256-BALL PBGA Table 2-2. Pin List 256-pin PBGA Pin Number A1 A4 A7 A10 A13 A16 B3 B6 B9 B12 B15 C2 C5 C8 C11 C14 D1 D4 D7 D10 D13 D16 E3 E6 E9 E12 E15 Name VSS S_AD[31] S_AD[22] S_FRAME_L S_PAR VSS S_REQ_L[1] S_CBE_L[3] S_CBE_L[2] S_CBE_L[1] VSS S_REQ_L[4] S_AD[29] S_AD[20] S_LOCK_L VSS S_GNT_L[0] VSS VDD VDD VSS S_AD[6] S_REQ_L[7] VDD VDD VSS S_CBE_L[0] Type P TS TS STS TS P I TS TS TS P I TS TS STS P TS P P P P TS I P P P TS Pin Number A2 A5 A8 A11 A14 B1 B4 B7 B10 B13 B16 C3 C6 C9 C12 C15 D2 D5 D8 D11 D14 E1 E4 E7 E10 E13 E16 Name Type S_REQ_L[2] S_AD[28] S_AD[19] S_DEVSEL_L S_AD[13] VSS S_REQ_L[0] S_AD[21] S_IRDY_L S_AD[12] S_AD[10] VSS S_AD[24] S_AD[16] S_AD[15] VDD S_REQ_L[6] S_AD[30] VDD S_SERR_L VSS S_GNT_L[3] S_REQ_L[8] VDD VDD S_AD[9] S_AD[4] I TS TS STS TS P I TS STS TS TS P TS TS TS P I TS P I P TS I P P TS TS Pin Number A3 A6 A9 A12 A15 B2 B5 B8 B11 B14 C1 C4 C7 C10 C13 C16 D3 D6 D9 D12 D15 E2 E5 E8 E11 E14 F1 Name VDD S_AD[25] S_AD[17] S_PERR_L S_AD[11] VSS S_AD[27] S_AD[18] S_STOP_L MS0 S_REQ_L[5] VDD S_AD[23] S_TRDY_L VSS S_AD[8] S_REQ_L[3] S_AD[26] VDD S_AD[14] S_M66EN M66EN S_GNT_L[2] VSS VDD VDD S_AD[7] S_GNT_L[7] Type P TS TS STS TS P TS TS STS P I P TS STS P TS I TS P TS I/OD TS P P P TS TS Page 20 of 109 April 2009 Revision 1.08 PI7C8150B PI7C8150B ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION Pin Number F2 F5 F8 F11 F14 G1 G4 G7 G10 G13 G16 H3 H6 H9 H12 H15 J2 J5 J8 J11 J14 K1 K4 K7 K10 K13 Name S_GNT_L[6] VDD VSS VSS S_AD[3] S_GNT_L[8] VDD VSS VSS VDD S_AD[0] S_CLKIN VSS VSS VDD TCK GPIO[2] VDD VSS VSS RESERVED GPIO[0] VDD VSS VSS VDD Name Type TS P P P TS TS P P P P TS I P P P I TS P P P TS P P P P Pin Number F3 F6 F9 F12 F15 G2 G5 G8 G11 G14 H1 H4 H7 H10 H13 H16 J3 J6 J9 J12 J15 K2 K5 K8 K11 K14 S_GNT_L[1] VSS VSS VDD S_AD[2] VSS VDD VSS VSS S_VIO S_RESET_L VDD VSS VSS VDD TDO GPIO[3] VSS VSS VDD TDI S_CLKOUT[0] VDD VSS VSS P_VIO I L1 O P P P TS TS O P P P TS I TS P TS P I P TS STS P TS P TS TS TS P TS TS TS STS TS Type Name Type TS P P P TS P P P P I O P P P P O TS P P P I O P P P I Pin Number F4 F7 F10 F13 F16 G3 G6 G9 G12 G15 H2 H5 H8 H11 H14 J1 J4 J7 J10 J13 J16 K3 K6 K9 K12 K15 S_GNT_L[4] VSS VSS S_AD[5] S_AD[1] S_GNT_L[5] VSS VSS VDD TRST_L S_CFN_L VDD VSS VSS TMS GPIO[1] VDD VSS VSS VDD RESERVED S_CLKOUT[1] VSS VSS VDD MSK_IN TS P P TS TS TS P P P I I P P P I TS P P P P O P P P I S_CLKOUT[2] O L2 S_CLKOUT[3] O L4 L7 S_CLKOUT[6] VSS O P L5 L8 VDD VSS P P L11 L14 M1 M4 M7 M10 M13 M16 N3 N6 N9 N12 N15 P2 P5 P8 P11 P14 R1 R4 R7 R10 R13 R16 T3 T6 T9 T12 T15 VSS P_AD[2] S_CLKOUT[4] P_CLK VDD VDD P_AD[6] P_AD[3] P_AD[31] P_AD[25] VDD P_AD[11] P_AD[8] P_REQ_L P_AD[27] P_AD[18] P_SERR_L VSS P_GNT_L VSS P_AD[20] P_TRDY_L P_AD[12] MS1 VDD P_AD[23] P_AD[16] P_PERR_L P_AD[10] P TS O I P P TS TS TS TS P TS TS TS TS TS OD P I P TS STS TS P P TS TS STS TS L12 L15 M2 M5 M8 M11 M14 N1 N4 N7 N10 N13 N16 P3 P6 P9 P12 P15 R2 R5 R8 R11 R14 T1 T4 T7 T10 T13 T16 ASYNC_CLK_IN K16 L3 L6 L9 L10 L13 L16 M3 M6 M9 M12 M15 N2 N5 N8 N11 N14 P1 P4 P7 P10 P13 P16 R3 R6 R9 R12 R15 T2 T5 T8 T11 T14 CFG66 CFG66 SCAN_EN_H CLK_RATE S_CLKOUT[5] VSS VSS VSS P_AD[4] P_AD[0] S_CLKOUT[9] VDD VDD VSS P_AD[5] BPCCE P_AD[28] VDD P_PAR VSS P_RESET_L VSS P_AD[22] P_DEVSEL_L VDD P_AD[9] VDD P_CBE_L[3] P_CBE_L[2] P_AD[15] VSS P_AD[30] P_AD[26] P_AD[19] P_STOP_L P_AD[13] VDD P_AD[1] S_CLKOUT[8] VSS VDD VDD P_AD[7] S_CLKOUT[7] VSS VDD VDD VSS P_CBE_L[0] VSS P_IDSEL P_FRAME_L P_AD[14] VDD VSS P_AD[24] P_AD[17] P_LOCK_L P_M66EN M66EN VSS P_AD[29] P_AD[21] P_IRDY_L P_CBE_L[1] VSS P TS O P P P TS O P P P P TS P I STS TS P P TS TS STS I P TS TS STS TS P Page 21 of 109 April 2009 Revision 1.08 PI7C8150B PI7C8150B ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION 3 PCI BUS OPERATION This Chapter offers information about PCI transactions, transaction forwarding across PI7C8150B PI7C8150B, and transaction termination. The PI7C8150B PI7C8150B has two 128-byte FIFO's for buffering of upstream and downstream transactions. These hold addresses, data, commands, and byte enables that are used for write transactions. The PI7C8150B PI7C8150B also has an additional four 128-byte FIFO's that hold addresses, data, commands, and byte enables for read transactions. 3.1 TYPES OF TRANSACTIONS This section provides a summary of PCI transactions performed by PI7C8150B PI7C8150B. Table 3-1 lists the command code and name of each PCI transaction. The Master and Target columns indicate support for each transaction when PI7C8150B PI7C8150B initiates transactions as a master, on the primary (P) and secondary (S) buses, and when PI7C8150B PI7C8150B responds to transactions as a target, on the primary (P) and secondary (S) buses. Table 3-1. PCI Transactions Types of Transactions 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Interrupt Acknowledge Special Cycle I/O Read I/O Write Reserved Reserved Memory Read Memory Write Reserved Reserved Configuration Read Configuration Write Memory Read Multiple Dual Address Cycle Memory Read Line Memory Write and Invalidate Initiates as Master Primary N Y Y Y N N Y Y N N N Y (Type 1 only) Y Y Y Y Secondary N Y Y Y N N Y Y N N Y Y Y Y Y Y Responds as Target Primary Secondary N N N N Y Y Y Y N N N N Y Y Y Y N N N N Y N Y Y (Type 1 only) Y Y Y Y Y Y Y Y As indicated in Table 3-1, the following PCI commands are not supported by PI7C8150B PI7C8150B: PI7C8150B PI7C8150B never initiates a PCI transaction with a reserved command code and, as a target, PI7C8150B PI7C8150B ignores reserved command codes. PI7C8150B PI7C8150B does not generate interrupt acknowledge transactions. PI7C8150B PI7C8150B ignores interrupt acknowledge transactions as a target. PI7C8150B PI7C8150B does not respond to special cycle transactions. PI7C8150B PI7C8150B cannot guarantee delivery of a special cycle transaction to downstream buses because of the broadcast nature of the special cycle command and the inability to control the transaction as a target. To generate special cycle transactions on other PCI buses, either upstream or downstream, Type 1 configuration write must be used. Page 22 of 109 April 2009 Revision 1.08 PI7C8150B PI7C8150B ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION PI7C8150B PI7C8150B neither generates Type 0 configuration transactions on the primary PCI bus nor responds to Type 0 configuration transactions on the secondary PCI buses. 3.2 SINGLE ADDRESS PHASE A 32-bit address uses a single address phase. This address is driven on P_AD[31:0], and the bus command is driven on P_CBE[3:0]. PI7C8150B PI7C8150B supports the linear increment address mode only, which is indicated when the lowest two address bits are equal to zero. If either of the lowest two address bits is nonzero, PI7C8150B PI7C8150B automatically disconnects the transaction after the first data transfer. 3.3 DEVICE SELECT (DEVSEL_L) GENERATION PI7C8150B PI7C8150B always performs positive address decoding (medium decode) when accepting transactions on either the primary or secondary buses. PI7C8150B PI7C8150B never does subtractive decode. 3.4 DATA PHASE The address phase of a PCI transaction is followed by one or more data phases. A data phase is completed when IRDY_L and either TRDY_L or STOP_L are asserted. A transfer of data occurs only when both IRDY_L and TRDY_L are asserted during the same PCI clock cycle. The last data phase of a transaction is indicated when FRAME_L is deasserted and both TRDY_L and IRDY_L are asserted, or when IRDY_L and STOP_L are asserted. See Section 3.8 for further discussion of transaction termination. Depending on the command type, PI7C8150B PI7C8150B can support multiple data phase PCI transactions. For detailed descriptions of how PI7C8150B PI7C8150B imposes disconnect boundaries, see Section 3.5.4 for write address boundaries and Section 3.6.3 read address boundaries. 3.5 WRITE TRANSACTIONS Write transactions are treated as either posted write or delayed write transactions. Table 3-2 shows the method of forwarding used for each type of write operation. Table 3-2. Write Transaction Forwarding Type of Transaction Memory Write Memory Write and Invalidate Memory Write to VGA memory I/O Write Type 1 Configuration Write Type of Forwarding Posted (except VGA memory) Posted Delayed Delayed Delayed Page 23 of 109 April 2009 Revision 1.08 PI7C8150B PI7C8150B ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION 3.5.1 MEMORY WRITE TRANSACTIONS Posted write forwarding is used for "Memory Write" and "Memory Write and Invalidate" transactions. When PI7C8150B PI7C8150B determines that a memory write transaction is to be forwarded across the bridge, PI7C8150B PI7C8150B asserts DEVSEL_L with medium timing and TRDY_L in the next cycle, provided that enough buffer space is available in the posted memory write queue for the address and at least one DWORD of data. Under this condition, PI7C8150B PI7C8150B accepts write data without obtaining access to the target bus. The PI7C8150B PI7C8150B can accept one DWORD of write data every PCI clock cycle. That is, no target wait state is inserted. The write data is stored in an internal posted write buffers and is subsequently delivered to the target. The PI7C8150B PI7C8150B continues to accept write data until one of the following events occurs: The initiator terminates the transaction by de-asserting FRAME# and IRDY#. An internal write address boundary is reached, such as a cache line boundary or an aligned 4KB boundary, depending on the transaction type. The posted write data buffer fills up. When one of the last two events occurs, the PI7C8150B PI7C8150B returns a target disconnect to the requesting initiator on this data phase to terminate the transaction. Once the posted write data moves to the head of the posted data queue, PI7C8150B PI7C8150B asserts its request on the target bus. This can occur while PI7C8150B PI7C8150B is still receiving data on the initiator bus. When the grant for the target bus is received and the target bus is detected in the idle condition, PI7C8150B PI7C8150B asserts FRAME_L and drives the stored write address out on the target bus. On the following cycle, PI7C8150B PI7C8150B drives the first DWORD of write data and continues to transfer write data until all write data corresponding to that transaction is delivered, or until a target termination is received. As long as write data exists in the queue, PI7C8150B PI7C8150B can drive one DWORD of write data each PCI clock cycle; that is, no master wait states are inserted. If write data is flowing through PI7C8150B PI7C8150B and the initiator stalls, PI7C8150B PI7C8150B will signal the last data phase for the current transaction at the target bus if the queue empties. PI7C8150B PI7C8150B will restart the follow-on transactions if the queue has new data. PI7C8150B PI7C8150B ends the transaction on the target bus when one of the following conditions is met: All posted write data has been delivered to the target. The target returns a target disconnect or target retry (PI7C8150B PI7C8150B starts another transaction to deliver the rest of the write data). The target returns a target abort (PI7C8150B PI7C8150B discards remaining write data). The master latency timer expires, and PI7C8150B PI7C8150B no longer has the target bus grant (PI7C8150B PI7C8150B starts another transaction to deliver remaining write data). Page 24 of 109 April 2009 Revision 1.08 PI7C8150B PI7C8150B ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION Section 3.8.3.2 provides detailed information about how PI7C8150B PI7C8150B responds to target termination during posted write transactions. 3.5.2 MEMORY WRITE AND INVALIDATE Posted write forwarding is used for Memory Write and Invalidate transactions. If offset 74h bits [8:7] = 11, the PI7C8150B PI7C8150B disconnects Memory Write and Invalidate commands at aligned cache line boundaries. The cache line size value in the cache line size register gives the number of DWORD in a cache line. If offset 74h bits [8:7] = 00, the PI7C8150b converts Memory Write and Invalidate transactions to Memory Write transactions at the destination. If the value in the cache line size register does meet the memory write and invalidate conditions, the PI7C8150B PI7C8150B returns a target disconnect to the initiator on a cache line boundary. 3.5.3 DELAYED WRITE TRANSACTIONS Delayed write forwarding is used for I/O write transactions and Type 1 configuration write transactions. A delayed write transaction guarantees that the actual target response is returned back to the initiator without holding the initiating bus in wait states. A delayed write transaction is limited to a single DWORD data transfer. When a write transaction is first detected on the initiator bus, and PI7C8150B PI7C8150B forwards it as a delayed transaction, PI7C8150B PI7C8150B claims the access by asserting DEVSEL_L and returns a target retry to the initiator. During the address phase, PI7C8150B PI7C8150B samples the bus command, address, and address parity one cycle later. After IRDY_L is asserted, PI7C8150B PI7C8150B also samples the first data DWORD, byte enable bits, and data parity. This information is placed into the delayed transaction queue. The transaction is queued only if no other existing delayed transactions have the same address and command, and if the delayed transaction queue is not full. When the delayed write transaction moves to the head of the delayed transaction queue and all ordering constraints with posted data are satisfied. The PI7C8150B PI7C8150B initiates the transaction on the target bus. PI7C8150B PI7C8150B transfers the write data to the target. If PI7C8150B PI7C8150B receives a target retry in response to the write transaction on the target bus, it continues to repeat the write transaction until the data transfer is completed, or until an error condition is encountered. If PI7C8150B PI7C8150B is unable to deliver write data after 224 (default) or 232 (maximum) attempts, PI7C8150B PI7C8150B will report a system error. PI7C8150B PI7C8150B also asserts P_SERR_L if the primary SERR_L enable bit is set in the command register. See Section 6.4 for information on the assertion of P_SERR_L. When the initiator repeats the same write transaction (same command, address, byte enable bits, and data), and the completed delayed transaction is at the head of the queue, the PI7C8150B PI7C8150B claims the access by asserting DEVSEL_L and returns TRDY_L to the initiator, to indicate that the write data was transferred. If the initiator requests multiple DWORD, PI7C8150B PI7C8150B also asserts STOP_L in conjunction with TRDY_L to signal a target disconnect. Note that only those bytes of write data with valid Page 25 of 109 April 2009 Revision 1.08 PI7C8150B PI7C8150B ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION byte enable bits are compared. If any of the byte enable bits are turned off (driven HIGH), the corresponding byte of write data is not compared. If the initiator repeats the write transaction before the data has been transferred to the target, PI7C8150B PI7C8150B returns a target retry to the initiator. PI7C8150B PI7C8150B continues to return a target retry to the initiator until write data is delivered to the target, or until an error condition is encountered. When the write transaction is repeated, PI7C8150B PI7C8150B does not make a new entry into the delayed transaction queue. Section 3.8.3.1 provides detailed information about how PI7C8150B PI7C8150B responds to target termination during delayed write transactions. PI7C8150B PI7C8150B implements a discard timer that starts counting when the delayed write completion is at the head of the delayed transaction completion queue. The initial value of this timer can be set to the retry counter register offset 78h. If the initiator does not repeat the delayed write transaction before the discard timer expires, PI7C8150B PI7C8150B discards the delayed write completion from the delayed transaction completion queue. PI7C8150B PI7C8150B also conditionally asserts P_SERR_L (see Section 6.4). 3.5.4 WRITE TRANSACTION ADDRESS BOUNDARIES PI7C8150B PI7C8150B imposes internal address boundaries when accepting write data. The aligned address boundaries are used to prevent PI7C8150B PI7C8150B from continuing a transaction over a device address boundary and to provide an upper limit on maximum latency. PI7C78150 PI7C78150 returns a target disconnect to the initiator when it reaches the aligned address boundaries under conditions shown in Table 3-3. Table 3-3. Write Transaction Disconnect Address Boundaries Type of Transaction Delayed Write Posted Memory Write Posted Memory Write Posted Memory Write and Invalidate Posted Memory Write and Invalidate Condition All Memory write disconnect control bit = 0(1) Memory write disconnect control bit = 1(1) Cache line size 1, 2, 4, 8, 16 Aligned Address Boundary Disconnects after one data transfer 4KB aligned address boundary Disconnects at cache line boundary 4KB aligned address boundary Cache line boundary if posted memory write data FIFO does not have enough space for the cache line Note 1. Memory write disconnect control bit is bit 1 of the chip control register at offset 40h in the configuration space. 3.5.5 Cache line size = 1, 2, 4, 8, 16 BUFFERING MULTIPLE WRITE TRANSACTIONS PI7C8150B PI7C8150B continues to accept posted memory write transactions as long as space for at least one DWORD of data in the posted write data buffer remains. If the posted write data buffer fills before the initiator terminates the write transaction, PI7C8150B PI7C8150B returns a target disconnect to the initiator. Delayed write transactions are posted as long as at least one open entry in the delayed transaction queue exists. Therefore, several posted and delayed write transactions can exist Page 26 of 109 April 2009 Revision 1.08 PI7C8150B PI7C8150B ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION in data buffers at the same time. See Chapter 6 for information about how multiple posted and delayed write transactions are ordered. 3.5.6 FAST BACK-TO-BACK TRANSACTIONS PI7C8150B PI7C8150B can recognize and post fast back-to-back write transactions. When PI7C8150B PI7C8150B cannot accept the second transaction because of buffer space limitations, it returns a target retry to the initiator. The fast back-to-back enable bit must be set in the command register for upstream write transactions, and in the bridge control register for downstream write transactions. 3.6 READ TRANSACTIONS Delayed read forwarding is used for all read transactions crossing PI7C8150B PI7C8150B. Delayed read transactions are treated as either prefetchable or non-prefetchable. Table 3-5 shows the read behavior, prefetchable or non-prefetchable, for each type of read operation. 3.6.1 PREFETCHABLE READ TRANSACTIONS A prefetchable read transaction is a read transaction where PI7C8150B PI7C8150B performs speculative DWORD reads, transferring data from the target before it is requested from the initiator. This behavior allows a prefetchable read transaction to consist of multiple data transfers. However, byte enable bits cannot be forwarded for all data phases as is done for the single data phase of the non-prefetchable read transaction. For prefetchable read transactions, PI7C8150B PI7C8150B forces all byte enable bits to be turned on for all data phases. Prefetchable behavior is used for memory read line and memory read multiple transactions, as well as for memory read transactions that fall into prefetchable memory space. The amount of data that is pre-fetched depends on the type of transaction. The amount of pre-fetching may also be affected by the amount of free buffer space available in PI7C8150B PI7C8150B, and by any read address boundaries encountered. Pre-fetching should not be used for those read transactions that have side effects in the target device, that is, control and status registers, FIFO's, and so on. The target device's base address register or registers indicate if a memory address region is prefetchable. 3.6.2 NON-PREFETCHABLE READ TRANSACTIONS A non-prefetchable read transaction is a read transaction where PI7C8150B PI7C8150B requests one and only one DWORD from the target and disconnects the initiator after delivery of the first DWORD of read data. Unlike prefetchable read transactions, PI7C8150B PI7C8150B forwards the read byte enable information for the data phase. Non-prefetchable behavior is used for I/O and configuration read transactions, as well as for memory read transactions that fall into non-prefetchable memory space. Page 27 of 109 April 2009 Revision 1.08 PI7C8150B PI7C8150B ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION If extra read transactions could have side effects, for example, when accessing a FIFO, use non-prefetchable read transactions to those locations. Accordingly, if it is important to retain the value of the byte enable bits during the data phase, use non-prefetchable read transactions. If these locations are mapped in memory space, use the memory read command and map the target into non-prefetchable (memory-mapped I/O) memory space to use non-prefetching behavior. 3.6.3 READ PREFETCH ADDRESS BOUNDARIES PI7C8150B PI7C8150B imposes internal read address boundaries on read pre-fetched data. When a read transaction reaches one of these aligned address boundaries, the PI7C8150B PI7C8150B stops prefetched data, unless the target signals a target disconnect before the read pre-fetched boundary is reached. When PI7C8150B PI7C8150B finishes transferring this read data to the initiator, it returns a target disconnect with the last data transfer, unless the initiator completes the transaction before all pre-fetched read data is delivered. Any leftover pre-fetched data is discarded. Prefetchable read transactions in flow-through mode pre-fetch to the nearest aligned 4KB address boundary, or until the initiator de-asserts FRAME_L. Section 3.6.6 describes flowthrough mode during read operations. Table 3-4 shows the read pre-fetch address boundaries for read transactions during nonflow-through mode. Table 3-4. Read Prefetch Address Boundaries Type of Transaction Address Space Configuration Read I/O Read Memory Read Memory Read Non-Prefetchable Prefetchable Cache Line (CLS) * * * CLS = 0 or 16 Size Memory Read Memory Read Line Prefetchable - CLS = 1, 2, 4, 8, 16 CLS = 0 or 16 Memory Read Line Memory Read Multiple - CLS = 1, 2, 4, 8, 16 CLS = 0 or 16 Memory Read Multiple CLS = 1, 2, 4, 8, 16 - does not matter if it is prefetchable or non-prefetchable * don't care Prefetch Aligned Address Boundary One DWORD (no prefetch) One DWORD (no prefetch) One DWORD (no prefetch) 16-DWORD 16-DWORD aligned address boundary Cache line address boundary 16-DWORD 16-DWORD aligned address boundary Cache line boundary 32-DWORD 32-DWORD aligned address boundary 2X of cache line boundary Table 3-5. Read Transaction Prefetching Type of Transaction I/O Read Configuration Read Read Behavior Prefetching never allowed Prefetching never allowed Downstream: Prefetching used if address is prefetchable space Memory Read Upstream: Prefetching used or programmable Memory Read Line Prefetching always used Memory Read Multiple Prefetching always used See Section 4.3 for detailed information about prefetchable and non-prefetchable address spaces. Page 28 of 109 April 2009 Revision 1.08 PI7C8150B PI7C8150B ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION 3.6.4 DELAYED READ REQUESTS PI7C8150B PI7C8150B treats all read transactions as delayed read transactions, which means that the read request from the initiator is posted into a delayed transaction queue. Read data from the target is placed in the read data queue directed toward the initiator bus interface and is transferred to the initiator when the initiator repeats the read transaction. When PI7C8150B PI7C8150B accepts a delayed read request, it first samples the read address, read bus command, and address parity. When IRDY_L is asserted, PI7C8150B PI7C8150B then samples the byte enable bits for the first data phase. This information is entered into the delayed transaction queue. PI7C8150B PI7C8150B terminates the transaction by signaling a target retry to the initiator. Upon reception of the target retry, the initiator is required to continue to repeat the same read transaction until at least one data transfer is completed, or until a target response (target abort or master abort) other than a target retry is received. 3.6.5 DELAYED READ COMPLETION WITH TARGET When delayed read request reaches the head of the delayed transaction queue, PI7C8150B PI7C8150B arbitrates for the target bus and initiates the read transaction only if all previously queued posted write transactions have been delivered. PI7C8150B PI7C8150B uses the exact read address and read command captured from the initiator during the initial delayed read request to initiate the read transaction. If the read transaction is a non-prefetchable read, PI7C8150B PI7C8150B drives the captured byte enable bits during the next cycle. If the transaction is a prefetchable read transaction, it drives all byte enable bits to zero for all data phases. If PI7C8150B PI7C8150B receives a target retry in response to the read transaction on the target bus, it continues to repeat the read transaction until at least one data transfer is completed, or until an error condition is encountered. If the transaction is terminated via normal master termination or target disconnect after at least one data transfer has been completed, PI7C8150B PI7C8150B does not initiate any further attempts to read more data. If PI7C8150B PI7C8150B is unable to obtain read data from the target after 224 (default) or 232 (maximum) attempts, PI7C8150B PI7C8150B will report system error. The number of attempts is programmable. PI7C8150B PI7C8150B also asserts P_SERR_L if the primary SERR_L enable bit is set in the command register. See Section 6.4 for information on the assertion of P_SERR_L. Once PI7C8150B PI7C8150B receives DEVSEL_L and TRDY_L from the target, it transfers the data read to the opposite direction read data queue, pointing toward the opposite inter-face, before terminating the transaction. For example, read data in response to a downstream read transaction initiated on the primary bus is placed in the upstream read data queue. The PI7C8150B PI7C8150B can accept one DWORD of read data each PCI clock cycle; that is, no master wait states are inserted. The number of DWORD's transferred during a delayed read transaction depends on the conditions given in Table 3-4 (assuming no disconnect is received from the target). 3.6.6 DELAYED READ COMPLETION ON INITIATOR BUS When the transaction has been completed on the target bus, and the delayed read data is at the head of the read data queue, and all ordering constraints with posted write transactions have been satisfied, the PI7C8150B PI7C8150B transfers the data to the initiator when the initiator Page 29 of 109 April 2009 Revision 1.08 PI7C8150B PI7C8150B ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION repeats the transaction. For memory read transactions, PI7C8150B PI7C8150B aliases the memory read, memory read line, and memory read multiple bus commands when matching the bus command of the transaction to the bus command in the delayed transaction queue. PI7C8150B PI7C8150B returns a target disconnect along with the transfer of the last DWORD of read data to the initiator. If PI7C8150B PI7C8150B initiator terminates the transaction before all read data has been transferred, the remaining read data left in data buffers is discarded. When the master repeats the transaction and starts transferring prefetchable read data from data buffers while the read transaction on the target bus is still in progress and before a read boundary is reached on the target bus, the read transaction starts operating in flow-through mode. Because data is flowing through the data buffers from the target to the initiator, long read bursts can then be sustained. In this case, the read transaction is allowed to continue until the initiator terminates the transaction, or until an aligned 4KB address boundary is reached, or until the buffer fills, whichever comes first. When the buffer empties, PI7C8150B PI7C8150B reflects the stalled condition to the initiator by disconnecting the initiator with data. The initiator may retry the transaction later if data are needed. If the initiator does not need any more data, the initiator will not continue the disconnected transaction. In this case, PI7C8150B PI7C8150B will start the master timeout timer. The remaining read data will be discarded after the master timeout timer expires. To provide better latency, if there are any other pending data for other transactions in the RDB (Read Data Buffer), the remaining read data will be discarded even though the master timeout timer has not expired. PI7C8150B PI7C8150B implements a master timeout timer that starts counting when the delayed read completion is at the head of the delayed transaction queue, and the read data is at the head of the read data queue. The initial value of this timer is programmable through configuration register. If the initiator does not repeat the read transaction and before the master timeout timer expires (215 default), PI7C8150B PI7C8150B discards the read transaction and read data from its queues. PI7C8150B PI7C8150B also conditionally asserts P_SERR_L (see Section 6.4). PI7C8150B PI7C8150B has the capability to post multiple delayed read requests, up to a maximum of four in each direction. If an initiator starts a read transaction that matches the address and read command of a read transaction that is already queued, the current read command is not posted as it is already contained in the delayed transaction queue. See Section 5 for a discussion of how delayed read transactions are ordered when crossing PI7C8150B PI7C8150B. 3.6.7 FAST BACK-TO-BACK READ TRANSACTION PI7C8150B PI7C8150B can recognize fast back-to-back read transactions. 3.7 CONFIGURATION TRANSACTIONS Configuration transactions are used to initialize a PCI system. Every PCI device has a configuration space that is accessed by configuration commands. All registers are accessible in configuration space only. In addition to accepting configuration transactions for initialization of its own configuration space, the PI7C8150B PI7C8150B also forwards configuration transactions for device initialization in hierarchical PCI systems, as well as for special cycle generation. Page 30 of 109 April 2009 Revision 1.08 PI7C8150B PI7C8150B ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION To support hierarchical PCI bus systems, two types of configuration transactions are specified: Type 0 and Type 1. Type 0 configuration transactions are issued when the intended target resides on the same PCI bus as the initiator. A Type 0 configuration transaction is identified by the configuration command and the lowest two bits of the address set to 00b. Type 1 configuration transactions are issued when the intended target resides on another PCI bus, or when a special cycle is to be generated on another PCI bus. A Type 1 configuration command is identified by the configuration command and the lowest two address bits set to 01b. The register number is found in both Type 0 and Type 1 formats and gives the DWORD address of the configuration register to be accessed. The function number is also included in both Type 0 and Type 1 formats and indicates which function of a multifunction device is to be accessed. For single-function devices, this value is not decoded. The addresses of Type 1 configuration transaction include a 5-bit field designating the device number that identifies the device on the target PCI bus that is to be accessed. In addition, the bus number in Type 1 transactions specifies the PCI bus to which the transaction is targeted. 3.7.1 TYPE 0 ACCESS TO PI7C8150B PI7C8150B The configuration space is accessed by a Type 0 configuration transaction on the primary interface. The configuration space cannot be accessed from the secondary bus. The PI7C8150B PI7C8150B responds to a Type 0 configuration transaction by asserting P_DEVSEL_L when the following conditions are met during the address phase: The bus command is a configuration read or configuration write transaction. Lowest two address bits P_AD[1:0] must be 00b. Signal P_IDSEL must be asserted. PI7C8150B PI7C8150B limits all configuration access to a single DWORD data transfer and returns target-disconnect with the first data transfer if additional data phases are requested. Because read transactions to configuration space do not have side effects, all bytes in the requested DWORD are returned, regardless of the value of the byte enable bits. Type 0 configuration write and read transactions do not use data buffers; that is, these transactions are completed immediately, regardless of the state of the data buffers. The PI7C8150B PI7C8150B ignores all Type 0 transactions initiated on the secondary interface. 3.7.2 TYPE 1 TO TYPE 0 CONVERSION Type 1 configuration transactions are used specifically for device configuration in a hierarchical PCI bus system. A PCI-to-PCI bridge is the only type of device that should respond to a Type 1 configuration command. Type 1 configuration commands are used when the configuration access is intended for a PCI device that resides on a PCI bus other than the one where the Type 1 transaction is generated. Page 31 of 109 April 2009 Revision 1.08 PI7C8150B PI7C8150B ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION PI7C8150B PI7C8150B performs a Type 1 to Type 0 translation when the Type 1 transaction is generated on the primary bus and is intended for a device attached directly to the secondary bus. PI7C8150B PI7C8150B must convert the configuration command to a Type 0 format so that the secondary bus device can respond to it. Type 1 to Type 0 translations are performed only in the downstream direction; that is, PI7C8150B PI7C8150B generates a Type 0 transaction only on the secondary bus, and never on the primary bus. PI7C8150B PI7C8150B responds to a Type 1 configuration transaction and translates it into a Type 0 transaction on the secondary bus when the following conditions are met during the address phase: The lowest two address bits on P_AD[1:0] are 01b. The bus number in address field P_AD[23:16] is equal to the value in the secondary bus number register in configuration space. The bus command on P_CBE[3:0] is a configuration read or configuration write transaction. When PI7C8150B PI7C8150B translates the Type 1 transaction to a Type 0 transaction on the secondary interface, it performs the following translations to the address: Sets the lowest two address bits on S_AD[1:0]. Decodes the device number and drives the bit pattern specified in Table 3-6 on S_AD[31:16] for the purpose of asserting the device's IDSEL signal. Sets S_AD[15:11] to 0. Leaves unchanged the function number and register number fields. PI7C8150B PI7C8150B asserts a unique address line based on the device number. These address lines may be used as secondary bus IDSEL signals. The mapping of the address lines depends on the device number in the Type 1 address bits P_AD[15:11]. presents the mapping that PI7C8150B PI7C8150B uses. Table 3-6. Device Number to IDSEL S_AD Pin Mapping Device Number 0h 1h 2h 3h 4h 5h 6h 7h 8h 9h Ah Bh Ch Dh Eh Fh 10h 1Eh P_AD[15:11] 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 11110 Secondary IDSEL S_AD[31:16] 0000 0000 0000 0001 0000 0000 0000 0010 0000 0000 0000 0100 0000 0000 0000 1000 0000 0000 0001 0000 0000 0000 0010 0000 0000 0000 0100 0000 0000 0000 1000 0000 0000 0001 0000 0000 0000 0010 0000 0000 0000 0100 0000 0000 0000 1000 0000 0000 0001 0000 0000 0000 0010 0000 0000 0000 0100 0000 0000 0000 1000 0000 0000 0000 0000 0000 0000 0000 S_AD 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 - Page 32 of 109 April 2009 Revision 1.08 PI7C8150B PI7C8150B ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION Device Number 1Fh P_AD[15:11] 11111 Secondary IDSEL S_AD[31:16] Generate special cycle (P_AD[7:2] > 00h) 0000 0000 0000 0000 (P_AD[7:2] = 00h) S_AD - PI7C8150B PI7C8150B can assert up to 9 unique address lines to be used as IDSEL signals for up to 9 devices on the secondary bus, for device numbers ranging from 0 through 8. Because of electrical loading constraints of the PCI bus, more than 9 IDSEL signals should not be necessary. However, if device numbers greater than 9 are desired, some external method of generating IDSEL lines must be used, and no upper address bits are then asserted. The configuration transaction is still translated and passed from the primary bus to the secondary bus. If no IDSEL pin is asserted to a secondary device, the transaction ends in a master abort. PI7C8150B PI7C8150B forwards Type 1 to Type 0 configuration read or write transactions as delayed transactions. Type 1 to Type 0 configuration read or write transactions are limited to a single 32-bit data transfer. 3.7.3 TYPE 1 TO TYPE 1 FORWARDING Type 1 to Type 1 transaction forwarding provides a hierarchical configuration mechanism when two or more levels of PCI-to-PCI bridges are used. When PI7C8150B PI7C8150B detects a Type 1 configuration transaction intended for a PCI bus downstream from the secondary bus, PI7C8150B PI7C8150B forwards the transaction unchanged to the secondary bus. Ultimately, this transaction is translated to a Type 0 configuration command or to a special cycle transaction by a downstream PCI-to-PCI bridge. Downstream Type 1 to Type 1 forwarding occurs when the following conditions are met during the address phase: The lowest two address bits are equal to 01b. The bus number falls in the range defined by the lower limit (exclusive) in the secondary bus number register and the upper limit (inclusive) in the subordinate bus number register. The bus command is a configuration read or write transaction. PI7C8150B PI7C8150B also supports Type 1 to Type 1 forwarding of configuration write transactions upstream to support upstream special cycle generation. A Type 1 configuration command is forwarded upstream when the following conditions are met: The lowest two address bits are equal to 01b. The bus number falls outside the range defined by the lower limit (inclusive) in the secondary bus number register and the upper limit (inclusive) in the subordinate bus number register. The device number in address bits AD[15:11] is equal to 11111b. The function number in address bits AD[10:8] is equal to 111b. The bus command is a configuration write transaction. Page 33 of 109 April 2009 Revision 1.08 PI7C8150B PI7C8150B ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION The PI7C8150B PI7C8150B forwards Type 1 to Type 1 configuration write transactions as delayed transactions. Type 1 to Type 1 configuration write transactions are limited to a single data transfer. 3.7.4 SPECIAL CYCLES The Type 1 configuration mechanism is used to generate special cycle transactions in hierarchical PCI systems. Special cycle transactions are ignored by acting as a target and are not forwarded across the bridge. Special cycle transactions can be generated from Type 1 configuration write transactions in either the upstream or the down-stream direction. PI7C8150B PI7C8150B initiates a special cycle on the target bus when a Type 1 configuration write transaction is being detected on the initiating bus and the following conditions are met during the address phase: The lowest two address bits on AD[1:0] are equal to 01b. The device number in address bits AD[15:11] is equal to 11111b. The function number in address bits AD[10:8] is equal to 111b. The register number in address bits AD[7:2] is equal to 000000b. The bus number is equal to the value in the secondary bus number register in configuration space for downstream forwarding or equal to the value in the primary bus number register in configuration space for upstream forwarding. The bus command on CBE_L is a configuration write command. When PI7C8150B PI7C8150B initiates the transaction on the target interface, the bus command is changed from configuration write to special cycle. The address and data are for-warded unchanged. Devices that use special cycles ignore the address and decode only the bus command. The data phase contains the special cycle message. The transaction is forwarded as a delayed transaction, but in this case the target response is not forwarded back (because special cycles result in a master abort). Once the transaction is completed on the target bus, through detection of the master abort condition, PI7C8150B PI7C8150B responds with TRDY_L to the next attempt of the con-figuration transaction from the initiator. If more than one data transfer is requested, PI7C8150B PI7C8150B responds with a target disconnect operation during the first data phase. 3.8 TRANSACTION TERMINATION This section describes how PI7C8150B PI7C8150B returns transaction termination conditions back to the initiator. The initiator can terminate transactions with one of the following types of termination: Page 34 of 109 April 2009 Revision 1.08 PI7C8150B PI7C8150B ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION Normal termination Normal termination occurs when the initiator de-asserts FRAME_L at the beginning of the last data phase, and de-asserts IRDY# at the end of the last data phase in conjunction with either TRDY_L or STOP_L assertion from the target. Master abort A master abort occurs when no target response is detected. When the initiator does not detect a DEVSEL_L from the target within five clock cycles after asserting FRAME_L, the initiator terminates the transaction with a master abort. If FRAME_L is still asserted, the initiator de-asserts FRAME_L on the next cycle, and then de-asserts IRDY_L on the following cycle. IRDY_L must be asserted in the same cycle in which FRAME_L deasserts. If FRAME_L is already de-asserted, IRDY_L can be de-asserted on the next clock cycle following detection of the master abort condition. The target can terminate transactions with one of the following types of termination: Normal termination TRDY_L and DEVSEL_L asserted in conjunction with FRAME_L de-asserted and IRDY_L asserted. Target retry STOP_L and DEVSEL_L asserted with TRDY_L de-asserted during the first data phase. No data transfers occur during the transaction. This transaction must be repeated. Target disconnect with data transfer STOP_L, DEVSEL_L and TRDY_L asserted. It signals that this is the last data transfer of the transaction. Target disconnect without data transfer STOP_L and DEVSEL_L asserted with TRDY_L de-asserted after previous data transfers have been made. Indicates that no more data transfers will be made during this transaction. Target abort STOP_L asserted with DEVSEL_L and TRDY_L de-asserted. Indicates that target will never be able to complete this transaction. DEVSEL_L must be asserted for at least one cycle during the transaction before the target abort is signaled. 3.8.1 MASTER TERMINATION INITIATED BY PI7C8150B PI7C8150B PI7C8150B PI7C8150B, as an initiator, uses normal termination if DEVSEL_L is returned by target within five clock cycles of PI7C8150B PI7C8150B's assertion of FRAME_L on the target bus. As an initiator, PI7C8150B PI7C8150B terminates a transaction when the following conditions are met: During a delayed write transaction, a single DWORD is delivered. During a non-prefetchable read transaction, a single DWORD is transferred from the target. During a prefetchable read transaction, a pre-fetch boundary is reached. For a posted write transaction, all write data for the transaction is trans