PI6C3420 - Datasheet Archive

 

Hardware Implementation Guide for the PI6C3420 By Rex Lu Introduction 2. When using a termination resistor, the series resistor

 

#89 Hardware Implementation Guide for the PI6C3420 PI6C3420 By Rex Lu Introduction 2. When using a termination resistor, the series resistor is calculated for a slightly over-damped condition by: RS ZL ­ R0, where R0 is output resistance of the source driver, ZL is characteristic impedance of the transmission line, and RS is the series resistor. 3. Trace lengths should be as short as possible. 4. Today's high-speed requirements are challenging hardware designers to a new level. With current speeds, any flaw in a design can mean the difference between a working system, and a non-working system. With any design, having the proper layout is one of the first and most important considerations. This application note discusses layout techniques to achieve the best performance when using the PI6C3420 PI6C3420. Avoid looping the clock signal if possible. If serpentine technique is required to maintain equal trace length, use arcs of 45 turns rather than 90 turns to avoid impedance discontinuities. 5. Vias should be kept to a minimum to avoid impedance discontinuity (which will increase skew and reflections). 6. Keep high-speed buses and logic away from clock devices to prevent noise coupling onto the clock signals. 7. Placement of the clock device should be at the center of all other components so that the clock signal traces are kept to a minimum. PI6C3420 PI6C3420 Pericom's PI6C3420 PI6C3420 is a spread spectrum clock synthesizer targeted for video and graphic applications. By using a 14.318 MHz reference clock or crystal as input, the PI6C3420 PI6C3420 can generate a 27 MHz reference clock output and a 27 MHz clock output with Spread Spectrum. Resistor & Capacitor Decoupling capacitors are very critical in terms of limiting noise. Without proper decoupling capacitors to minimize heavy VDD ripple and GND bounce, it can cause system-false triggering or complete system failure. VDD ripples and GND bounce can drastically increase skew and output jitter. Properly used decoupling capacitors keep RF energy from being injected into the power planes from high frequency components. Decoupling capacitors also provide a localized source of DC power for device or components. Trace termination also plays an important role in ensuring optimal signal integrity as well as minimizing creation of RF energy. Series termination is optimal when a lumped load or a single component is located at the end of a routed trace. The following are recommendations on using the PI6C3420 PI6C3420. It should be noted that the recommendations may vary by application. Schematic and Layout Recommendations 1. Two values of bypass capacitors are recommended. The selection of capacitance is different by at least 2 orders of magnitude. For example, 0.1 uF and 1 nF capacitors could be used. Decoupling capacitors should be connected between the VDD and GND for all VDD pins. Placement of the decoupling capacitors should be connected as close as possible to the VDD pin of the device. Page 1 AN89 11/01/05 EMI Design Recommendations Electromagnetic Interference (EMI) is caused by radiation of unwanted radio frequency signals that disrupt the expected radio spectrum. Electromagnetic Compatibility (EMC) is the ability of different items of electrical equipment to work together without suffering the effects of interference. There are two popular standards in the EMC test. One is Federal Communications Commissions (FCC) part 15, the other one is the International Electro technical Commission's International Special Committee on Radio Interference (CISPR) Publication 22 class B. In the United States, the FCC has defined strict rules about the maximum amount of EMI in an electronic system. These regulations mark the peak emissions at a particular frequency rather than average emissions. If any EMI emitted by a system exceeds the allowable FCC-type or CISPR-type limit, the product cannot be shipped or used. #89 Engineers can easily meet the requirement of EMC with a simple approximation model. The following equation shows the relationship of current, loop area, and the frequency to EMI: EMI (V/m) = k*I*A*f2 Where: k = constant I = current (A) = loop area (m2) * f = frequency (MHz) Note: * Loop area is defined as the area of current loop returning from ground plane, which is key to reducing EMI by minimizing the trace length. Application Information: 1. Connect all ground vias to all ground planes, and similarly, connect all power vias to all power planes at equal potential. 2. Place ground plane to minimize the loop area from signal path to return path. 3. Do not cross signal between different circuits. 4. Make the high-speed or sensitive signal loop path closest to the ground. 5. Have every signal pin surrounded by ground pins in all four directions. The following are some EMI design recommendations for the PI6C3420 PI6C3420. Clock Placement Board Stackup It's understood that current flow generates magnetic lines of flux, and no matter how well the PCB is designed, magnetic and electric fields exist. However, if we dispel magnetic lines of flux, the EMI will not exist. The easiest flux cancellation or minimization is by using the image plane. An image plane is a layer of copper (ground or power plane), physically adjacent to the signal plane. Use of image planes provides a low impedance and the shortest possible return path for signal currents. The guidelines below are general approaches to board stackup: 1. Design a system board with at least four layers, with two signal layers separated by a ground and power layer. 2. Use a solid image plane and avoid routing high speed clock signal traces in the image power or ground plane. 3. Any unused area of the top and bottom signal layers of the PCB can be filled with copper connected to the ground plane through vias. 4. Minimize the number of signal vias to reduce EMI. Grounding Grounding is a primary method of minimizing unwanted noise pickup and partitioning circuit segments. Proper implementation of PCB ground methods and cable shields prevents a majority of noise problems. Proper grounding requires minimizing inductance. The following guidelines help to reduce circuit inductance on the motherboard: Page 2 AN89 11/01/05 The PI6C3420 PI6C3420 should also be placed close to the loop of the destination to reduce the trace length. Termination network should be placed as close to the PI6C3420 PI6C3420 as possible to reduce EMI. Minimize trace lengths for improved signal integrity and EMI consideration, and place the PI6C3420 PI6C3420 away from any switching power supply. The guidelines below are general approaches to minimizing EMI: 1. Place high-current devices as close to the power sources as possible. 2. Arrange all components together closely that are associated with the clock. 3. Avoid using sockets which introduce impedance in high frequency applications. 4. Avoid placing crystal, oscillator, or clock generator near I/O port and board edge. 5. Mount crystals lying flat on board. 6. Strap the crystal chassis to the ground plane to avoid antenna behavior. mismatched #89 Spread Ratio Selection: VDD VDD 0.1uF 1nF 0.1uF 1nF 5 3,6 Strapping to low 2 VDD 5 3,6 Strapping to high 2 1. Spread ratio select pin (S0 and S1) strapping: Pin 3 (27M_SSC/S0) and Pin 6 (X2/S1) provide Logic state strapping function. When strapping resistor connects to VDD, the selection pins of S0, S1 will set to Logic High. When strapping resistor connects to Ground, the selection pins of S0, S1 will set to Logic Low. 2. Strapping logic for spread spectrum ratio: Refer to the Spread Spectrum Select Table on the PI6C3420 PI6C3420 datasheet. Crystal Load Capacitors If a crystal is used with PI6C3420 PI6C3420 as a reference, the external trim capacitors Ce should be used on pin 1 and pin 6 (X1 and X2). The load capacitors Ce are used to push or pull the crystal to its desired frequency. The Ce value can be derived from formula Ce = 2*CL ­ (Cs + Ci). Typical Ce = 33pF when Crystal Load = 20pF, Stray capacitance (Cs) = 2.8pF and XTAL pins capacitance = 4.5pF. Page 3 AN89 11/01/05 #89 Application Example: Graphic chip Circuit: VDD C1 C2 5 External Source: 14.318MHz CLK in ATi Graphic Chip VDD VDD 1 R3 X1/REF IN 27M_SSC/S0 3 R5 27MHz_MEM0 SSCK IN R4 VDD PI6C3420 PI6C3420 R1 6 R2 27M X2/ S1 R7 4 27MHz_GRAPHIC CLK IN R6 R8 GND 2 1. PI6C3420 PI6C3420 can accept two kinds of clock inputs; 14.31818 MHz clock signal can be derived from system clock generator or a 14.31818 MHz crystal connection. 2. Power pin decoupling capacitors C1 and C2 should be placed close to VDD pin 5 and avoid using via at VDD. 3. Pin 6 and pin 3 are spread spectrum ratio pins. R1, R2, R3, and R4 are strapping resistors connecting to Ground or VDD, providing four spreading functions. 4. Pin 3 and pin 4 are 27 MHz clock output with Spread Spectrum function and 27 MHz reference clock output respectively. Keep the signal trace length as short as possible and minimizing the number of signal vias will help to reduce EMI. 5. R5 and R6 are termination resisters. It's also helpful for EMI reduction with a slightly over-damped condition. 6. R7 and R8 are used as a voltage level shifter to accommodate the maximum voltage input to the graphic chip. References EMC and The Printed Circuit Board, Mark I. Montrose, IEEE Press, 1998. Page 4 AN89 11/01/05