PFM18030 PFM18030SM PFM18030F IS95A GRM39X7R332K100 GRM426X7R154K050AL

PFM18030 SPECIFICATION 18051880 MHz, 30W, 2Stage Power Module EnhancementMode Lateral MOSFETs This versatile DCS module provides

PRELIMINARY PFM18030 PFM18030 SPECIFICATION 18051880 MHz, 30W, 2Stage Power Module EnhancementMode Lateral MOSFETs This versatile DCS module provides excellent linearity and efficiency in a lowcost surface mount package. The PFM18030SM PFM18030SM includes two stages Package Type: Surface Mount of amplification, along with internal sense FETs that are on the same silicon die as the RF devices. These thermally coupled sense FETs PN: PFM18030SM PFM18030SM simplify the task of bias temperature compensation of the overall amplifier. The module includes RF input, interstage, and output matching elements. The source and load impedances required for optimum operation of the module are much higher (and simpler to realize) than for unmatched Si LDMOS transistors of similar performance. The surface mount package base is typically soldered to a conventional PCB pad with an array of via holes for grounding and thermal sinking of the module. Optimized internal construction supports low FET channel temperature for reliable operation. Package Type: Flange PN: PFM18030F PFM18030F · 29 dB Gain · 30 Watts Peak Output Power · Internal Tracking FETs (for improved bias control) · IS95 CDMA Performance 5 Watts Average Output Level 20% Power Added Efficiency 49 dBc ACPR Module Schematic Diagram Module Substrate Q1 Die Carrier Q2 Die Carrier Gate 1 RF IN Lead Input Match S1 Sense S1 Gate 2 Sense S2 D1 Drain 2 RF OUT Q2 Q1 Output Match Input Match Output Match Lead S2 Lead Lead Lead Lead Note: Additionally, there are 250 KOhm resistors connected in shunt with all leads, to enhance ESD protection. Page 1 of 13 Specifications subject to change without notice. U.S. Patent No. 6,822,321 http://www.cree.com/ Rev. 3 PFM18030 PFM18030 Electrical Specification Parameter Min Limits Typ Units Comments Max 1 Operating Frequency 1805 1880 MHz 2 Gain 27.5 29.5 32 dB Note 1. 3 Gain Compression at Pout =30 Watts 0.8 1.5 dB Pulsed CW compression measurement (12 msec pulse, 120 msec period, 10% duty cycle). ± 0.1 ± 0.3 dB Note 1. ± 0.8 ± 1.2 ° Note 1 3.1 3.7 nanosec 45 49 dBc 18 20 % 24 27 30 Volts Testing for conformance with RF specifications is at +27 V. 40 +115 °C Testing for conformance with RF specification is at +25 °C. 0.033 dB/°C Bias quiescent currents held constant. 30 Watts CW VSWR 10:1, all phase angles. No degradation in output power before & after test. 60 dBc 1.9 2.1 °C/W 4 5 6 7 8 9 10 11 Gain Flatness over any 30 MHz bandwidth Deviation from Linear Phase over any 30 MHz bandwidth Group Delay ACPR with IS95A IS95A CDMA Pave = 5 W Efficiency under IS95 Protocol, Pave = 5 W DC Drain Supply Voltage Operating Temperature Range (base temperature) Gain Variation versus Temperature 12 Output Mismatch Stress 13 Stability 14 Theta jc (channel) 15 16 17 Quiescent Currents a) Q1 b) Q2 Sense FET Periphery Ratio a) Stg 1 Track b) Stg 2 Track ESD Protection a) Human Body Model b) Machine Model 73 235 mA mA 3.0 1.7 % % Class 1 Class M3 Includes delay of test fixture (~0.6 nanosec.). Note 1 Note 4. Refer to applications data for performance with other protocols. Note 4. 0