PF1231-01 S1F78520 S1F78520M0A0 VOUT11 VOUT12 VOUT13 VOUT21 VOUT22 VOUT23 - Datasheet Archive

 

S1F78520 S1F78520 y r ina m Charge-pump Step Down Regulator with Power Saving Mode i rel P s DESCRIPTION The S1F78520 is a power

 

PF1231-01 PF1231-01 S1F78520 S1F78520 S1F78520 S1F78520 y r ina m Charge-pump Step Down Regulator with Power Saving Mode i rel P s DESCRIPTION The S1F78520 S1F78520 is a power IC which can generate two stabilized output voltages of 3.3 V (or 2.9 V or 2.5 V) and 2.5 V (or 2.0 V or 1.8 V) using the Li-ion battery. The 3.3 V range output is being generated through the LDO (series regulator). The 2.5 V range output is being generated through the charge pump type DC/DC converter consisting of built-in CMOS transistors. Since the voltages are being stabilized by adjustments of the charge pump DC/DC switching frequencies, higher conversion efficiencies as compared with the conventional series regulators can be acquired. Since the S1F78520 S1F78520 does not require external transistors, coils nor diodes, it is most suitable for the down sizing purpose and for reduction of the current consumption. s FEATURES q Supply voltage ························································· 3.6 V (TBD) 2.8 V to 5.5 V) single power input q Voltage conversion method ····································· < 3.3V range output > LDO (series regulator) < 2.5V range output > Voltage dropping type charge pump q Output voltages ························································ < 3.3V range output > 3.3 V or 2.9 V or 2.5 V ± 3% < 2.5V range output > 2.5 V or 2.0 V or 1.8 V ± 4% q Output current (Normal state/Standby state) ··········· < 3.3V range output > Max. (100 mA/1 mA) < 2.5V range output > Max. (80 mA/100 µA) q Conversion efficiency ··············································· < 3.3V range output > 90% < 2.5V range output > (TBD) 85% (Reference data: The conversion efficiency from 3.3 V to 2.0 V by the series regulator is 60%.) q Shut down current ···················································· 1 µA q Self-consumption current ········································· (TBD) 100 µA (under no load state) q Built-in self-consumption current suppressing function by use of standby (light load) signals Self-consumption current ········································· (TBD) 20 µA (under no load state) q Switching frequency ················································· < 2.5V range output > (TBD) 1 MHz q Built-in power good detector (equipped with the delay setting function) q Built-in low voltage detecting circuit (For setting of the detecting voltages, either of the internal setting fixed to the IC or the external pin setting is selectable.) q Shipping state ·························································· SSOP3­24pin q This IC is not of the radiation resistant design nor of the light resistance design. Rev. 1.0 1 S1F78520 S1F78520 s BLOCK DIAGRAM VSS3 VOUT1 VDD VO1LV1, VO1LV0 (4) LDO (series regulator) 2 VDD2 VO2LV1, VO2LV0 C1P 2 ROSC1 ROSC OSCIN (1) Oscillation circuit (3) Voltage dropping type charge pump XSTBY VSENS (2) Low voltage detection circuit C1N VSS2 C2P C2N VOUT2 VSEL (6) Bias circuit Reference current Reference voltage XPOFF XVDET (7) Shut down CPG (5) Power good detection circuit VSS PG Fig. 1 Block diagram 2 Rev. 1.0 S1F78520 S1F78520 s DESCRIPTIONS FOR THE BLOCK DIAGRAM (1) Oscillation circuit This is the circuit to make oscillations by connecting a resistance to the ROSC1 pin and by supplying a constant current. (2) Low voltage detection circuit This circuit makes low voltage detections by monitoring the input voltage through the VDD pin. Provision of a hysteresis width is effective to prevent occurrences of unstable outputs (causing oscillations) while performing low voltage detecting operations. For setting of the detecting voltages, use of either of the internal voltage setting fixed to the IC or the external voltage setting pin VSENS is selectable through the VSEL pin. (3) Voltage dropping type charge pump The specified voltage is being output by voltage drops effected by the charge pump upon the inputted supply voltage VDD* - VSS * and using the VSS * potential as the reference voltage. The specified voltage is selectable (2.5 V or 2.0 V or 1.8 V) through the external pins VO2LV1, VO2LV0. Also, the voltages are being stabilized by adjusting the switching frequencies of the charge pump. This circuit can drastically suppress the current consumption under the standby mode (light load). (4) LDO (series regulator) It stabilizes the voltage of the levels below the input supply voltage. The specified voltage is selectable (3.3 V or 2.9 V or 2.5 V) through the external pins VO1LV1, VO1LV0. (5) Power good detection circuit This circuit detects the power good signals when the output pins V OUT1 and VOUT2 are satisfying the specified voltage. Delay setting can be made for the power good signals by connecting a capacitor and a resistor to the external setting pin CPG. (6) Bias circuit This circuit generates the reference voltage and reference current which are necessary for this IC. (7) Shut down Operations of all the circuits can be interrupted by setting the shut down pin XPOFF to the VSS* level. VDD* = VDD , VDD2, VSS * = VSS, VSS2, VSS3 Rev. 1.0 3 S1F78520 S1F78520 s PIN ASSIGNMENT SSOP3­24pin S1F78520M0A0 S1F78520M0A0 24 13 1 12 Pin No. 1 2 3 4 Pin No. 13 14 15 16 Pin name XVDET VSENS V DD VSEL 5 6 7 8 9 C1P VOUT2 PG CPG ROSC1 17 18 19 20 21 VSS3 V OUT1 VDD2 C2P C2N 10 11 12 4 Pin name XPOFF VO2LV0 VO2LV1 C1N V SS OSCIN XSTBY 22 23 24 VO1LV1 VO1LV0 VSS2 Rev. 1.0 S1F78520 S1F78520 s PIN DESCRIPTION (1) Function pins Pin name VO1LV1 I/O I Pin No. Function 22 V OUT1 Output voltage level designating pin. VO1LV0 I 23 VO2LV1 I 3 VO2LV0 I 2 ROSC1 XSTBY O I 9 12 VSENS I 14 VSEL I 16 XPOFF I 1 CPG C1P I O 8 5 C1N O 4 C2P O 20 C2N O 21 XVDET O 13 PG O 7 Rev. 1.0 Pin setting VO1LV1 VO1LV0 VSS * level VSS* level Output voltage 3.3V VSS * level VDD* level 2.9V V DD* level VSS* level 2.5V V DD* level VDD* level Not for use V OUT2 Output voltage level designating pin. Pin setting Output VO2LV1 VO2LV0 voltage VSS * level VSS* level 2.5V VSS * level VDD* level 2.0V V DD* level VSS* level 1.8V V DD* level VDD* level Not for use Pin to connect the external resistor for adjustment of the oscillating current. This is the standby pin. Under the standby mode (light load), the internal structure of the IC can be operated by low current consumption when this signal is set to the V SS* level. Detecting voltage inputting pin for the low voltage detection circuit. This is effective only when the eternal setting is being selected. Detecting voltage selecting pin for the low voltage detection circuit. The detecting voltage inputting pin VSENS becomes valid when this pin is set to the VSS* level. The detection voltage generated inside the IC becomes valid when this pin is set to the VDD* level. This is the shut down pin. Set this pin to the VDD* level while the IC is in operation. Operations of all the circuits will be interrupted when this signal is set to the VSS* level, bringing the IC into the shut down state and making the output pins XVDET, PG to open state. Delay time setting pin for the power good signals. Positive side connection pin for the flying capacitor C1 for generation of the V OUT2 output voltage. Negative side connection pin for the flying capacitor C1 for generation of the VOUT2 output voltage. Positive side connection pin for the flying capacitor C2 for generation of the V OUT2 output voltage. Negative side connection pin for the flying capacitor C2 for generation of the VOUT2 output voltage. This is the detection result output pin for the low voltage detection circuit. The output state is Nch open drain. It outputs the VSS* level when the input power pin VDD is at the low voltage level. This is the power good signal pin for the output power pins POUT1 and POUT2. The output state is Nch open drain. It goes open when both of the above output power pins are satisfying the specified voltage. 5 S1F78520 S1F78520 (2) Power pins Pin name I/O Pin No. VDD VDD2 VSS VSS2 VSS3 I I I I I 15 19 10 24 17 Positive side input power pin. Positive side input power pin. Negative side input power pin. Negative side input power pin. Negative side input power pin. Function V OUT1 V OUT2 O O 18 6 LDO (series regulator) put0put power pin. Voltage dropping type charge pump output power pin. Connect the VDD and VDD2 each other externally and keep them at the same potential level. Connect the VSS < VSS2 and VSS3 each other externally and keep them at the same potential level. (3) Testing pin Pin name Pin No. OSCIN 6 I/O I 11 Function Normally open. Rev. 1.0 S1F78520 S1F78520 s FUNCTIONAL DESCRIPTION q Operational description By use of the standby input signals, high conversion efficiencies can be acquired under heavy loads, while low current consumption operations can be realized under light load state. Generating voltage levels are: · LDO (series regulator) output voltage [3.3 V or 2.9 V or 2.5 V]*1 (VOUT1) · Voltage dropping type charge pump output voltage [2.5 V or 2.0 V or 1.8 V]*2 (VOUT2) *1: Selection of 3.3 V or 2.9 V or 2.5 V is to be designated by use of the external pins VO1LV1, VO1LV0. *2: Selection of 2.5 V or 2.0 V or 1.8 V is to be designated by use of the external pins VO2LV1, VO2LV0. The VOUT1 output voltage is being generated by stabilizing the potential difference occurring between "VDD* ­ VSS*" using the V SS* potential as the reference voltage. While the VOUT2 voltage is being generated after selection of the optimum voltage dropping ratio among different voltage dropping ratios for the voltage dropping type charge pump to let it work on the potential difference occurring between "VDD* ­ VSS*" using the VSS* potential as the reference voltage and stabilizing the voltage by fine adjustments of the switching frequencies. Since an extra voltage stabilizing circuit is not being used for the output, high conversion efficiencies can be acquired. Indicated below is the system configuration diagram for the power circuit. VDD PG XVDET S1F78520 S1F78520 LSI, CPU, RAM, etc. VOUT1 VOUT2 VSS Fig. 2 System configuration diagram q Oscillation circuit The S1F78520 S1F78520 incorporates an oscillation circuit for the voltage dropping clock. This circuit is to be used connecting the oscillation current adjusting external resistor ROSC between the ROSC1 pin and the VSS. The oscillation circuit will stop operation under shut down state (XPOFF = VSS* level). Also, the oscillation will be interrupted by setting the ROSC1 pin to the VDD* level or by making the pin into open state. As the oscillation current adjusting external resistance, we recommend use of ROSC = (TBD) . Rev. 1.0 7 S1F78520 S1F78520 q Standby mode By setting the standby mode signal XSTBY externally, current consumption of this IC can be suppressed drastically. The time required after the mode change is made with the standby pin until the internal mode of the IC is stabilized should be (TBS) max. 10ms to min. 0s. Complete timing design should be effected when using the standby mode. XSTBY pin Mode name Max. output current VDD* level Normal mode VOUT1:(100 mA) (TBD) (Under heavy load state) VOUT2:(80 mA) (TBD) VSS* level Standby mode VOUT1:(1 mA) (TBD) (Under light load state) VOUT2:(100 µA) (TBD) Output current from the IC (Actual load) Normal mode Self-consumption current (Under no load state) (TBD) 100 µA (TBD) 20 µA Standby mode (TBD) Min. 0s XSTBY Normal mode (TBD) Max. 10ms Internal operations of the IC Standby mode (TBD) Min. 0s Normal mode Standby mode Fig. 3 below indicates a mode changing timing example. 8 Rev. 1.0 S1F78520 S1F78520 q Low voltage detection circuit This circuit makes low voltage detections by monitoring the input voltage through the VDD pin. For setting of the detecting voltages, use of either of the internal voltage setting fixed to the IC or the external voltage setting pin VSENS is selectable through the external input pin VSEL. VSEL pin Detecting voltage selection VSS* level External pin VSENS VDD* level Internal voltage setting fixed or to the IC Open Detecting voltage value ­VDET: (According to the formula 7.4.2) +VDET: (According to the formula 7.4.4) ­VDET: 3.30 V (TBD) +VDET: 3.39 V (TBD) The detecting voltage (­VDET) in case of external voltage setting will be the VDD voltage value satisfying the following formulae. VREF1 VDD · (Rb)/(Ra + Rb) = VSENS . (Formula 7.4.1) Consequently, VDD VREF1 · (Ra + Rb)/(Rb) [V] . (Formula 7.4.2) can be established. Also, the cancelling voltage (+VDET) in case of external voltage setting will be the VDD voltage value satisfying the following formulae. VREF2 VDD · (Rb)/(Ra + Rb) = VSENS . (Formula 7.4.3) Consequently, VDD VREF2 · (Ra + Rb)/(Rb) [V] . (Formula 7.4.4) can be established. Fig. 4 below shows the block diagram for the external setting. VDD XVDET Ra VSENS + ­ Rb VREF1 VREF2 VREF1 = (TBD) 1.00V VREF2 = (TBD) 1.025V Fig. 4 Block diagram for the external setting Rev. 1.0 9 S1F78520 S1F78520 q Power good detection circuit Power good signals are detected when both of the output pins VOUT1 and VOUT2 are satisfying the specified voltage. As for the power good detection range, provision of a hysteresis width for the lower limit value of detection according to Fig. 5 indicated below is effective to prevent occurrences of unstable power good signal outputs in the neighborhood of the detection limit value range. Also, delay setting can be made for the power good signals by use of the capacitor CDPG and the resistor RDPG. When the output voltage rises beyond the cancelling voltage, charge to the external capacitor will begin. When the capacitor voltage rises beyond the delaying threshold valve voltage, the power good signal changes from the VSS* level to open state. The delaying time can be calculated by (TBD). Fig. 6 is an outline drawing for delay settings and Fig. 7 is the connection diagram in the neighborhood of the power good detection circuit. Lower limit of detection (Power good) Power good detection voltage setting Hysteresis width: 1% Cancellation (No good) Fig. 5 Power good detecting range 10 Rev. 1.0 S1F78520 S1F78520 Graph indicating the correlation between the formula or the capacitor setting and the delay time (TBD) Power good detection voltage Output voltage VOUT1, VOUT2 Delay pin threshold value voltage (VTCPG) Capacitor voltage VSS Power good signal PG VSS Delay time (TDPG) Fig. 6 Outline drawing for delay settings Rev. 1.0 11 S1F78520 S1F78520 [Internal structure of the S1F78520 S1F78520] VOUT1 LDO VOUT2 Voltage dropping type charge pump VDD + RDPG ­ CPG Reference voltage CDPG + ­ Reference voltage PG Fig. 7 Connection diagram in the neighborhood of the power good detection circuit 12 Rev. 1.0 S1F78520 S1F78520 s ABSOLUTE MAXIMUM RATINGS Item Symbol Rating Min. Max. ­0.3 ­0.3 ­0.3 ­0.3 7.0 7.0 7.0 V DD+0.3 (TBD) 120 Input supply voltage Output voltage 1 Output voltage 2 Input pin voltage VDD VOUT1 VOUT2 VIN Input current IVDD - Output current 1 IVOUT1 - Output current 2 IVOUT2 - Allowable dissipation PD Operating temperature Storage temperature Soldering temperature and time Unit Applicable pin Remarks V V V V V DD VOUT1 VOUT2 - - - - mA V DD - mA VOUT1 - mA VOUT2 - - (TBD) 60 (TBD) 60 (TBD) mW - Ta 55 °C Topr Tstg ­30 ­55 85 150 °C °C - - - - Tsol - 260 · 10 °C · s - At leads The applicable pins are VO1LV1, VO1LV0, VO2LV1, VO2LV0, XSTBY, VSENS, VSEL, XPOFF and OSCIN. Do not apply external voltage to the output pins and the pin connecting to the capacitor. Use of the IC under any conditions exceeding the above absolute maximum ratings may cause malfunctioning or permanent breakdown. Or, even if the IC may operate normally temporarily, the reliability may greatly drop. Rev. 1.0 13 S1F78520 S1F78520 s ELECTRICAL CHARACTERISTICS q DC characteristics rLDO (series regulator), voltage dropping type charge pump In case particular designations are not made (Note 1): Ta = 25 °C Item Input supply voltage Symbol VDD High level input voltage VIH Low level input voltage VIL Input leak current ILKI Output voltage 11 VOUT11 VOUT11 Output voltage 12 VOUT12 VOUT12 Output voltage 13 VOUT13 VOUT13 Output voltage 21 VOUT21 VOUT21 Output voltage 22 VOUT22 VOUT22 Output voltage 23 VOUT23 VOUT23 Output voltage 11 IVOUT11 IVOUT11 Output voltage 12 IVOUT12 IVOUT12 Output voltage 13 IVOUT13 IVOUT13 14 Conditions Applicable pin: VDD - - VSS VI VDD VDD = (TBD) 3.6 V Applicable pin: VOUT1 Output voltage setting: 3.3 V VDD = (TBD) 3.6 V IVOUT1 = (TBD) 10 mA Applicable pin: VOUT1 Output voltage setting: 2.9 V VDD = (TBD) 3.6 V IVOUT1 = (TBD)10 mA Applicable pin: VOUT1 Output voltage setting: 2.5 V VDD = (TBD) 3.6 V IVOUT1 = (TBD)10 mA Applicable pin: VOUT2 Output voltage setting: 2.5 V VDD = (TBD) 3.6 V IVOUT2 = (TBD)10 mA Applicable pin: VOUT2 Output voltage setting: 2.0 V VDD = (TBD) 3.6 V IVOUT2 = (TBD)10 mA Applicable pin: VOUT2 Output voltage setting: 1.8 V VDD = (TBD) 3.6 V IVOUT2 = (TBD)10 mA Applicable pin: VOUT1 Output voltage setting: 3.3 V VDD = (TBD) 3.6 V Applicable pin: VOUT1 Output voltage setting: 2.9 V VDD = (TBD) 3.6 V Applicable pin: VOUT1 Output voltage setting: 2.5 V VDD = (TBD) 3.6 V Min. - Rating Typ. 3.6 Max. 5.5 0.7*VDD 0 - - ­0.5 Unit Remarks V - VDD 0.3 *VDD V V 2 2 - 0.5 µA 2 3.20 3.30 3.40 V - 2.81 2.90 2.99 V - 2.42 2.50 2.58 V - 2.40 2.50 2.60 V - 1.92 2.00 2.08 V - 1.72 1.80 1.88 V - - - mA - - - (TBD) 100 mA - - - (TBD) 100 mA - (TBD) 100 Rev. 1.0 S1F78520 S1F78520 Min. Rating Typ. - - - Output voltage setting: 1.8 V VDD = (TBD) 3.6 V - (TBD) IOUT2 I/O voltage difference Output impedance Item Output voltage 21 Symbol Unit Remarks (TBD) 80 mA - - (TBD) 80 mA - - (TBD) 80 mA - - (TBD) (TBD) mV - (TBD) - (TBD) (TBD) mV - VDIF (TBD) - V - RVOUT2 (TBD) VDD = 3.6 V, no load Normal mode - µA - µA - - - IVOUT21 IVOUT21 Output voltage 22 IVOUT22 IVOUT22 Output voltage 23 IVOUT23 IVOUT23 Load stability 1 Load stability 2 V OUT1 IOUT1 V OUT2 Current consumption 1 IOPR1 Current consumption 2 IOPR2 Resting current Input stability 1 Input stability 2 IQ V OUT1 V DD V OUT2 V DD Power conversion Peff efficiency (Charge pump) Output voltage / temperature coefficient 1 Output voltage / temperature coefficient 2 V OUT1 Topr V OUT2 Topr Conditions Applicable pin: VOUT2 Output voltage setting: 2.5 V VDD = (TBD) 3.6 V Applicable pin: VOUT2 Output voltage setting: 2.0 V VDD = (TBD) 3.6 V Applicable pin: VOUT2 VDD = 3.6 V, no load Standby mode VDD = 3.6 V Shut down mode (TBD) - - - Max. (TBD) (TBD) 0.2 0.3 (TBD) (TBD) (TBD) (TBD) 100 (TBD) (TBD) 20 (TBD) µA 1.0 (TBD) - (TBD) (TBD) %/ V - (TBD) - (TBD) (TBD) %/ V - (TBD) - (TBD) (TBD) 85 - % 3 VDD = 3.6 V Normal mode IVOUT2 = (TBD) mA IVOUT2 = (TBD) mA ­30 °C Topr 85°C IVOUT2 = (TBD) mA ­30 °C Topr 85°C - (TBD) - ppm/°C - - (TBD) - ppm/°C - Conditions on the operation mode, external parts constant, pins, etc. in case particular designations are not made are as follows: Connection and parts constant : Standard connection 1, 10.1 XPOFF pin : XPOFF = HIGH (Normal mode) XSTBY pin : XSTBY = HIGH (Normal mode) The applicable pins are V01LV1 V01LV1, V01LV0 V01LV0, V02LV1 V02LV1, V02LV0 V02LV0, XSTBY, VSENS, VSEL, XPOFF and OSCIN. The power conversion efficiency of the voltage dropping type charge pump only. Rev. 1.0 15 S1F78520 S1F78520 rLow voltage detection In case particular designations are not made (Note 1): Ta = 25 °C Item Symbol Detection voltage ­VDET Hysteresis width VHYS Reference detection voltage 1 Reference detection voltage 2 Min. operating voltage Output current (Driver output pin) Off leak current (Driver output pin) Transfer delay time V REF1 V REF2 VVDDL Conditions VSEL pin = VDD * level (Internal voltage setting fixed to the IC) VSEL pin = VDD * level Rating Min. Typ. Max. (TBD) (TBD) (TBD) 3.20 3.30 3.40 (TBD) (TBD) (TBD) (Internal voltage setting fixed to the IC) VSEL pin = VSS * level (TBD) (External voltage setting to the VSENS pin) VSEL pin = VSS * level (TBD) (External voltage setting to the VSENS pin) Topr = 25 °C ­30 °C Topr 85 °C 0.09 (TBD) 1.00 (TBD) 1.025 V - V - V - V - - - (TBD) (TBD) V 2 - mA - µA - µs 3 ppm/°C - (TBD) (TBD) - IVDOFF (TBD) - - - - - - (TBD) Detection voltage / -VDET temperature coefficient Topr (TBD) Remarks - - IVDET TPLH (TBD) Unit (TBD) 1.0 (TBD) 100 VSEL pin = VDD * level (Internal voltage setting fixed to the IC) ­30 °C Topr 85 °C - Conditions on the operation mode, external parts constant, pins, etc. in case particular designations are not made are as follows: Connection and parts constant : Standard connection 1, 10.1 XPOFF pin : XPOFF = HIGH (Normal mode) XSTBY pin : XSTBY = HIGH (Normal mode) The supply voltage value where the output voltage becomes 0.1V or less. (TBD) (TBD) 16 Rev. 1.0 S1F78520 S1F78520 rPower good detection In case particular designations are not made (Note 1): Ta = 25 °C Item Symbol Lower limit detection voltage 11 VDLPG11 VDLPG11 Lower limit detection voltage 12 VDLPG12 VDLPG12 Lower limit detection voltage 13 VDLPG13 VDLPG13 Lower limit detection voltage 21 VDLPG21 VDLPG21 Lower limit detection voltage 22 VDLPG22 VDLPG22 Lower limit detection voltage 23 VDLPG23 VDLPG23 PG output current IPG (Driver output pin) PG off leak current IPGOFF (Driver output pin) Delay pin VTCPG Threshold value voltage CPG output current ICPG (Delay pin) Lower limit detection voltage/ VDLPG1 temperature coefficient 1 Topr Lower limit detection voltage/ VDLPG21 VDLPG21 temperature coefficient 2 Topr Conditions Applicable pin = VOUT1 Output voltage setting: 3.3 V Hysteresis width: 1% Applicable pin = VOUT1 Output voltage setting: 2.9 V Hysteresis width: 1% Applicable pin = VOUT1 Output voltage setting: 2.5 V Hysteresis width: 1% Applicable pin = VOUT2 Output voltage setting: 2.5 V Hysteresis width: 1% Applicable pin = VOUT2 Output voltage setting: 2.0 V Hysteresis width: 1% Min. Rating Typ. Max. Unit Remarks (TBD) 2.82 (TBD) (TBD) 2.91 3.00 V - (TBD) 2.54 (TBD) (TBD) 2.62 2.70 V - (TBD) 2.16 (TBD) (TBD) 2.23 2.30 V - (TBD) (TBD) (TBD) V - 2.16 2.23 2.30 (TBD) 1.68 (TBD) (TBD) 1.74 1.80 V - (TBD) 1.55 (TBD) (TBD) 1.60 1.65 V - (TBD) (TBD) (TBD) - mA - (TBD) - - (TBD) 1.0 µA - (TBD) (TBD) (TBD) V - (TBD) (TBD) - mA - - (TBD) - ppm/°C - - (TBD) - ppm/°C - Applicable pin = VOUT2 Output voltage setting: 1.8 V Hysteresis width: 1% V DD = (TBD) (TBD) Applicable pin: VOUT1 ­30 °C Topr 85 °C Applicable pin: VOUT2 Output voltage setting: 2.0 V ­30 °C Topr 85 °C Conditions on the operation mode, external parts constant, pins, etc. in case particular designations are not made are as follows: Connection and parts constant : Standard connection 1, 10.1 XPOFF pin : XPOFF = HIGH (Normal mode) XSTBY pin : XSTBY = HIGH (Normal mode) Rev. 1.0 17 S1F78520 S1F78520 s REFERENCE EXTERNAL CONNECTION (AN EXAMPLE) q Standard connection 1 VDD + CDD VDD VSS3 2 VO1LV1, VO1LV0 VO1LV1, VO1LV0 2 VO2LV1, VO2LV0 VOUT1 VOUT1 + CVO1 VO2LV1, VO2LV0 ROSC1 VDD2 RS ROSC OSCIN OSCIN C1P + C1 XSTBY XSTBY C1N VSS2 Ra VSENS C2P RP + C2 Rb VSEL VSEL XPOFF XPOFF C2N VOUT2 VOUT2 + CVO2 RVD RDPG CPG XVDET XVDET + CDPG RPG VSS PG PG VSS Recommended values for the external parts ROSC = (TBD) Ra = (Make the detection voltage setting according to the formulae 7.4.2 and 7.4.4.) Rb = (Make the detection voltage setting according to the formulae 7.4.2 and 7.4.4.) RS = RP = RVD = RPG =(TBD) 470 k CDD = (TBD) µF CDPG = (TBD) µF [(TBD) In case a delay time setting of 100ms is made.] RDPG = (TBD) M [(TBD) In case a delay time setting of 100ms is made.] CV01 = CV02 = 47 (TBD) µF C1 = C2 = 0.47 (TBD) µF 18 Rev. 1.0 S1F78520 S1F78520 s DIMENSIONAL OUTLINE DRAWING 7.6±0.2 5.6±0.2 SSOP3­24pin 0 ~ 10° 0.375 Typ. 0.65 0.5±0.2 0.22 +0.1 ­0.05 0.12 0.15 +0.1 ­0.05 0.10±0.05 1.15±0.1 7.9±0.2 M 0.10 Unit : mm Rev. 1.0 19 S1F78520 S1F78520 NOTICE: No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such as, medical products. Moreover, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party. This material or portions thereof may contain technology or the subject relating to strategic products under the control of the Foreign Exchange and Foreign Trade Law of Japan and may require an export license from the Ministry of International Trade and Industry or other approval from another government agency. © Seiko Epson Corporation 2001, All rights reserved. All other product names mentioned herein are trademarks and/or registered trademarks of their respective companies. ELECTRONIC DEVICES MARKETING DIVISION IC Marketing & Engineering Group s EPSON Electronic Devices Website http://www.epson.co.jp/device/ ED International Marketing Department Europe & U.S.A 421-8 Hino, Hino-shi, Tokyo 191-8501, JAPAN Phone: 042­587­5812 FAX: 042­587­5564 ED International Marketing Department Asia 421-8 Hino, Hino-shi, Tokyo 191-8501, JAPAN Phone: 042­587­5814 FAX: 042­587­5110 First issue July, 2001 Printed in Japan H 20 Rev. 1.0