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HS1-82C85RH-Q Intersil Corporation 15MHz, PROC SPECIFIC CLOCK GENERATOR, CDIP24 visit Intersil
HS9-82C85RH-8 Intersil Corporation 15MHz, PROC SPECIFIC CLOCK GENERATOR, CDFP24, CERAMIC, DFP-24 visit Intersil
HS9-82C85RH-Q Intersil Corporation 15MHz, PROC SPECIFIC CLOCK GENERATOR, CDFP24, CERAMIC, DFP-24 visit Intersil
CP82C84AZ Intersil Corporation 8MHz, PROC SPECIFIC CLOCK GENERATOR, PDIP18, ROHS COMPLIANT, PLASTIC, DIP-18 visit Intersil
CS82C84AZ96 Intersil Corporation 8MHz, PROC SPECIFIC CLOCK GENERATOR, PQCC20, ROHS COMPLIANT, PLASTIC, LCC-20 visit Intersil
HS1-82C85RH-8 Intersil Corporation 15MHz, PROC SPECIFIC CLOCK GENERATOR, CDIP24, SIDE BRAZED, CERAMIC, DIP-24 visit Intersil

PECI 2.0 specification

Catalog Datasheet MFG & Type PDF Document Tags

W83795G

Abstract: w83795adg CPU temperature PECI (PLATFORM ENVIRONMENT CONTROL INTERFACE) Support PECI 2.0 Specification , PECI (PLATFORM ENVIRONMENT CONTROL INTERFACE) Support PECI 2.0 Specification Support 8 CPU Address , .105 PECI CONTROL AND SB-TSI FUNCTION . 122 11.1 PECI Control Registers , ) . 128 12.3 PECI Control Register (PCR
nuvoTon
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1c 78 adg

Abstract: SB-TSI CONTROL INTERFACE) z Support PECI 2.0 Specification z Support 8 CPU Address and 2 domains per CPU , . (Including PECI_REQ# mechanism). PECI (PLATFORM ENVIRONMENT CONTROL INTERFACE) z Support PECI 2.0 , .102 11. 12. 13. PECI CONTROL AND SB-TSI FUNCTION . 118 11.1 PECI Control Registers , ) . 124 12.3 PECI Control Register (PCR
nuvoTon
Original
Abstract: ¬ Support PECI 2.0 Specification  Support 8 CPU Address and 2 domains per CPU address AMDTM SB-TSI , PECI 2.0 Specification  Support 8 CPU Address and 2 domains per CPU address FAN Up to 2 Fan , . 100 PECI CONTROL AND SB-TSI FUNCTION . 116 - ii â'" Mar/3/2011 Revision 1.43 W83795G/ADG 12. 13. 11.1 PECI Control , ) . 122 12.3 PECI Control Register (PCR nuvoTon
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W83795G W83795ADG

socket lga 1156 pinout

Abstract: intel i5 MOTHERBOARD pcb CIRCUIT diagram 2.1.6 Processor Mass Specification . , Specifications and Design Guidelines 3 6.2 6.3 Processor Specification for Operation Where Digital , .52 Platform Environment Control Interface (PECI , .52 6.3.2 PECI Client Capabilities , .53 6.1.3 7 Sensor-Based Thermal Specification Design Guidance
Intel
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socket lga 1156 pinout intel i5 MOTHERBOARD pcb CIRCUIT diagram i3 desktop MOTHERBOARD CIRCUIT diagram 115XLM LGA 1156 PIN OUT diagram LGA 1150 Socket PIN diagram LGA1156 E20847 E21320 E58389

vr 0511 mb

Abstract: bg37 Control Interface (PECI) DC Specifications. 40 2.6.1 DC Characteristics , 3.1.6 Processor Mass Specification . , . 121 Platform Environment Control Interface (PECI) . 121 6.3.1 PECI Client Capabilities , . 50 Differential Clock Crosspoint Specification
Intel
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vr 0511 mb bg37 intel G41 MOTHERBOARD pcb CIRCUIT diagram schematic intel g41 LGA1567 peci specification E78800/4800/2800 E7-8800/4800/2800 E7-8800/4800/

peci specification

Abstract: PECI 2.0 specification ) . 18 1.2.5 Platform Environment Control Interface (PECI , ) . 28 2.5 Platform Environment Control Interface (PECI) . 29 2.5.1 PECI Client Capabilities , Retry and Timeout Policy . 72 2.5.3.10 Enumerating PECI , . 118 6.5 PECI Signal
Intel
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PECI 2.0 specification intel PC MOTHERBOARD CIRCUIT diagram x86 family 6 model 7 stepping 3 E5-2400 STS100A

A16HR

Abstract: MMBT3904 Preliminary Specification ­ Subject to change without notice GPIO1 GPIO2 GPIO3 PECI INTERFACE , aSC7621 HARDWARE MONITOR WITH INTEGRATED FAN CONTROL PRODUCT SPECIFICATION Preliminary Specification Measurement System The aSC7621 has a two wire digital interface compatible with SMBus 2.0 , as well as its own die. Support for Platform Environmental Control Interface (PECI) is included , 2's complement coding. Supports PECI interface and monitors internal and remote thermal diodes
Andigilog
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A16HR MMBT3904 amd athlon 64 x2 voltage pins circuit diagram laptop motherboard AMD Athlon 64 X2 AMD Athlon 64 X2 thermal SC7621 70A06010

PECI 2.0 specification

Abstract: ) . 17 1.2.5 Platform Environment Control Interface (PECI , . 28 2.5 Platform Environment Control Interface (PECI) . 31 2.5.1 PECI Client Capabilities , Retry and Timeout Policy .74 2.5.3.10 Enumerating PECI , Specification . 115 5.1.2.5 50W 8-Core Thermal
Intel
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STS100P STS100C

peci specification

Abstract: peci Refer to Intel PECI specification. PECI transaction failed for more than the configured number of , VREF Input Refers Logic Levels to the PECI Supply Voltage Automatic I2C Bus Lockup Timeout Reset , AD0 GND SCL SDA SCL VREF CPU INTERNAL TEMP SENSOR MAX6621 PECI , PECI .-0.3V to (VREF + 0.3V) DC Current through , Voltage High-Level Input Voltage Leakage Current Input Capacitance PECI Supply Voltage to PECI Cell Input
Maxim Integrated Products
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peci 8103H MAX6621AUB 21-0061I

F640

Abstract: MAX6621 Refer to Intel PECI specification. 8100h Polling disabled for requested socket/domain. 8102h , Operating Temperature Range VREF Input Refers Logic Levels to the PECI Supply Voltage Automatic I2C Bus , VCPU VTT VCC SDA I2 C SCL VREF SDA SCL MASTER RESET MAX6621 PECI CPU , PECI .-0.3V to (VREF + 0.3V) DC Current , pF PECI Supply Voltage to PECI Cell VREF 0.95 1.26 V Input Voltage Range VIN
Maxim Integrated Products
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F640 10LUMAX
Abstract: 8000h­ 80FFh 8100h 8101h 8102h DESCRIPTION Refer to Intel PECI specification. PECI transaction failed , Operating Temperature Range VREF Input Refers Logic Levels to the PECI Supply Voltage Automatic I2C Bus , AD2 AD1 AD0 GND SCL SDA SCL VREF CPU INTERNAL TEMP SENSOR MAX6621 PECI , PECI .-0.3V to (VREF + 0.3V) DC Current through , Leakage Current Input Capacitance PECI Supply Voltage to PECI Cell Input Voltage Range Low-Level Input Maxim Integrated Products
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MAX6618 MAX6618AUB

f640

Abstract: 8000h­ 80FFh 8100h 8101h 8102h DESCRIPTION Refer to Intel PECI specification. PECI transaction failed , Operating Temperature Range VREF Input Refers Logic Levels to the PECI Supply Voltage Automatic I2C Bus , AD2 AD1 AD0 GND SCL SDA SCL VREF CPU INTERNAL TEMP SENSOR MAX6621 PECI , PECI .-0.3V to (VREF + 0.3V) DC Current through , Leakage Current Input Capacitance PECI Supply Voltage to PECI Cell Input Voltage Range Low-Level Input
Maxim Integrated Products
Original

peci specification

Abstract: MAX6621 8000h­ 80FFh 8100h 8101h 8102h DESCRIPTION Refer to Intel PECI specification. PECI transaction failed , Operating Temperature Range VREF Input Refers Logic Levels to the PECI Supply Voltage Automatic I2C Bus , AD2 AD1 AD0 GND SCL SDA SCL VREF CPU INTERNAL TEMP SENSOR MAX6621 PECI , PECI .-0.3V to (VREF + 0.3V) DC Current through , Leakage Current Input Capacitance PECI Supply Voltage to PECI Cell Input Voltage Range Low-Level Input
Maxim Integrated Products
Original

STS200C

Abstract: CSR BC57 18 1.2.5 Platform Environment Control Interface (PECI) . 18 , . 28 2.5 Platform Environment Control Interface (PECI) . 30 2.5.1 PECI Client Capabilities , . 144 6.5 PECI Signal , 151 7.1.5 Platform Environmental Control Interface (PECI) . 152
Intel
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STS200C STS200PNRW CSR BC57 MRC 08 mainboard g41 LGA2011 G41 MOTHERBOARD SERVICE MANUAL E5-1600 E5-2600 STS200P

peci specification

Abstract: PECI specification. PECI transaction failed for more than the configured number of consecutive retries , MAX6618 PECI-to-I2C Translator General Description The MAX6618 PECI(1.0)-to-I2C translator provides an efficient, low-cost solution for PECI(1.0)-to-SMBus/I2C protocol conversion. The PECI(1.0)-compliant host reads temperature data directly from up to four PECI(1.0)-enabled CPUs. This translator will only communicate with CPUs that support PECI 1.0. The I2C interface provides an independent serial
Maxim Integrated Products
Original

F640

Abstract: MAX6621 Refer to Intel PECI specification. 8100h Polling disabled for requested socket/domain. 8102h , Operating Temperature Range VREF Input Refers Logic Levels to the PECI Supply Voltage Automatic I2C Bus , VCPU VTT VCC SDA I2C SCL SDA VREF SCL PECI MASTER RESET MAX6621 CPU , PECI .-0.3V to (VREF + 0.3V) DC Current , pF PECI Supply Voltage to PECI Cell VREF 0.95 1.26 V Input Voltage Range VIN
Maxim Integrated Products
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07HREAD I2C BUS address translator

peci specification

Abstract: Refer to Intel PECI specification. PECI transaction failed for more than the configured number of , VREF Input Refers Logic Levels to the PECI Supply Voltage Automatic I2C Bus Lockup Timeout Reset , AD0 GND SCL SDA SCL VREF CPU INTERNAL TEMP SENSOR MAX6621 PECI , PECI .-0.3V to (VREF + 0.3V) DC Current through , Voltage High-Level Input Voltage Leakage Current Input Capacitance PECI Supply Voltage to PECI Cell Input
Maxim Integrated Products
Original

peci specification

Abstract: peci Refer to Intel PECI specification. 8100h Polling disabled for requested socket/domain. 8102h , Operating Temperature Range VREF Input Refers Logic Levels to the PECI Supply Voltage Automatic I2C Bus , VCPU VTT VCC SDA I2C SCL VREF SDA SCL MASTER RESET MAX6621 PECI CPU , PECI .-0.3V to (VREF + 0.3V) DC Current , pF PECI Supply Voltage to PECI Cell VREF 0.95 1.26 V Input Voltage Range VIN
Maxim Integrated Products
Original

peci

Abstract: alternate SDA COMMAND 09h ERROR CODES DESCRIPTION 8000h­ 80FFh Refer to Intel PECI specification , +120°C Operating Temperature Range VREF Input Refers Logic Levels to the PECI Supply Voltage , Circuit +3.3V VCPU VTT VCC SDA I2C SCL VREF SDA SCL MASTER AD2 MAX6618 PECI , PECI .-0.3V to (VREF + 0.3V) DC Current , VIL V +2 10 µA pF PECI Supply Voltage to PECI Cell VREF 0.95 1.26 V
Maxim Integrated Products
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alternate SDA
Abstract: PECI specification. PECI transaction failed for more than the configured number of consecutive retries , Input Refers Logic Levels to the PECI Supply Voltage o Automatic I2C Bus Lockup Timeout Reset o , MAX6618 SCL PECI CPU INTERNAL TEMP SENSOR For pricing, delivery, and ordering information, please , PECI .-0.3V to (VREF + 0.3V) DC Current through , ADDRESS INPUT AD0 Low-Level Input Voltage High-Level Input Voltage Leakage Current Input Capacitance PECI Maxim Integrated Products
Original
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