PDSP16116A PDSP16112/A PDSP16116/A PDSP16116 PSDP16116 2097K AR15-13 PDSP1601 - Datasheet Archive

 

A High Resolution FFT Processor Application Note AN59 ISSUE 2.0 July 1993 The PDSP16116A has been designed with an integral Block

 

AN59 A High Resolution FFT Processor Application Note AN59 ISSUE 2.0 July 1993 The PDSP16116A PDSP16116A has been designed with an integral Block Floating Point system which can be used, in conjunction with other Zarlink Semiconductor PDSP parts, to process FFTs with a combination of speed and accuracy previously unobtainable. All the functionality of this BFP system is contained within the PDSP parts, which are designed to interface easily to achieve a powerful FFT solution. A butterfly processor based on the 20MHz PDSP16116A PDSP16116A will allow the following FFT benchmarks: 1024 point complex radix-2 transform in 259us 512 point complex radix-2 transform in 118us 256 point complex radix-2 transform in 53us This compares favourably with the current industry standard benchmark of around 2ms for a 1024 point complex FFT, but if speed is all important for a particular application, then the Zarlink Semiconductor's PDSP16112/A PDSP16112/A 16x12 Complex Mulitplier can double the PDSP16116/A PDSP16116/A performance with up to 70dB of dynamic range. The FFT Algorithm The Fast Fourier Transform is essentially a computationally efficient algorithm for extracting spectral information from signal waveforms, which may be in real time or recorded form (i.e. a transformation from the time domain to the frequency domain). It is often used to dramatic effect in a growing range of applications including radar and sonar processing, speech recognition and image processing. It is no less accurate than the related Discrete Fourier Transform (DFT), but it enjoys a vastly improved performance due to the `divide and conquer' approach of its algorithm. There are several variations of the FFT algorithm, each with their own merits. For high throughput, hardware implemented solutions, a variant of the Radix-2 Decimation-in-Time algorithm is most suitable. The `Constant Geometry' algorithm (Fig. 1) is easier to implement whereas the `In-Place' algorithm (Fig. 2) halves the amount of memory required. 0 0 1 4 2 2 3 6 4 1 5 5 6 3 7 First Pass Second Pass Final Pass 7 Fig.1 8 point constant geometry DIT radix 2 algorithm with normally ordered inputs and bit-reversed outputs AN59 0 0 1 4 2 2 3 6 4 1 5 5 6 3 7 First Pass Second Pass Final Pass 7 Fig.2 8 point in-place DIT radix 2 algorithm with normally ordered inputs and bit-reversed outputs Both these variations are split vertically into a number of `passes' (log2N passes for an N-point transform), each pass consisting of N/2 `butterfly' operations: A A' A' = A + B. W B' = A - B. W W B B' W is the complex coefficient and A and B are, for the first pass, the sampled data and then, in the second and subsequent passes, the values of A' and B' from the previous pass. The results of the FFT are the values of A' and B' from the butterflies of the final pass. In order to be compatible with previous FFT results, all points must be normalised to a universal format. These final complex number values (cartesian co-ordinates) may then be converted into magnitude and phase components (polar co-ordinates). Defeating the Wordgrowth Problem One of the most difficult problems to overcome when implementing an FFT algorithm in fixed point arithmetic is that of wordgrowth. The power of the PDSP16116s BFP system lies in its flexible and effective response to this problem. Before looking into the operation of this BFP system, the wordgrowth problem and some of the other solutions available are explained. FFTs are implemented by means of successive multiplications and additions. Each time data is processed by an ALU (i.e. twice in each butterfly) there is the possibility of wordgrowth occurring: i.e. when two 16 bit words are added, they may produce a sum of 17 bits. The safe way to deal with this is to always pick the 16MSBs of the result. However, this will cause sign extension, i.e. repetition of the sign bit in the MSBs of the data. These two cases are illustrated in the examples below. Wordgrowth occurs: 0101110101110100 +0110100110101001 01100011100011101 Wordgrowth does not occur: 0101010111011010 +0010100010101110 00111111010001000 sign extension 2 AN59 Sign extension can cause severe problems when the next multiplication occurs, as it is likely to lead to a product with a further extended sign bit. For example: 1 bit sign extension 0011010001010110 *0010001101000101 00000111001101011101110100101110 4 bit sign extension After a few passes of the FFT, there is a danger that the data could become all sign bits and no information - not much use to anyone. The common alternative to this approach is to pick the 16 LSBs from the ALUs and hope that no wordgrowth occurs, as this will then lead to overflow. If overflow is flagged during the course of an FFT, then the calculation must be aborted. The input data is then scaled down and the calculation repeated. The hit and miss nature of this approach can be avoided by automatically scaling down the inputs and accepting the resulting penalty in accuracy. A `conditional shift' system offers some degree of flexibility. Here, the 16 LSBs are selected from the second ALU in the butterfly hardware if no overflow occurs in any butterfly during that pass. The PDSP16116 PDSP16116 offers a superior solution to the problem by employing an intelligent control system which can monitor data magnitudes during the course of the FFT and adjust them as necessary so as to keep extended sign bits to a minimum, whilst eliminating the possibility of overflow. In fact, this system can not only deal with wordgrowth problems as they occur, but can also adjust underscaled input data in anticipation of these problems to ensure that a valid result is obtained at the end of the calculation. A comparison of the data formats provided by each of the methods detailed above will clarify their differences. Given input data of the format: X.XXX. (note the position of the binary point) The UNCONDITIONAL SHIFT implementation will output all data at the end of a pass in the format: XXX.X. regardless of whether the data has increased in magnitude or not. The CONDITIONAL SHIFT implementation will either output ALL data in the format: XX.XX. if the maximum wordgrowth was one bit in any butterfly; or, if two bits of wordgrowth occurred in any butterfly, then ALL data will be output in the format: XXX.X. The BFP implementation can output EACH butterfly result in ANY of the following formats, according to the data magnitude: If data is underscaled If no wordgrowth occurs If wordgrowth occurs once If wordgrowth occurs twice .XXXX. X.XXX. XX.XX. XXX.X. The adaptability of the BFP system is clearly illustrated and it is this adaptability which allows the BFP system to defeat the wordgrowth problem. 3 AN59 How the BFP System Operates A block floating point system is essentially an ordinary integer arithmetic system with some additional logic, the object of which is to lend the system some of the enormous dynamic range afforded by a true floating point system without suffering the corresponding loss in performance. The initial data used by the FFT should all have the same binary weighting, i.e. the binary point should occupy the same position in every data word. This is normal in integer arithmetic. However, during the course of the FFT, a variety of weightings are used in the data words to increase the dynamic range available. This situation is similar to that within a true floating point system, though the range of numbers representable is more limited. In the BFP system used in the PSDP16116 PSDP16116, there are, within any one pass of the FFT, four possible positions of the binary point within the integer words. To record the position of its binary point, each word has a 2-bit word tag associated with it. By way of example, in a particular pass we may have the following four positions of binary point available, each denoted by a certain value of word tag: XX.XXXXXXXXXXXXXX XXX.XXXXXXXXXXXXX XXXX.XXXXXXXXXXXX XXXXX.XXXXXXXXXXX word tag = 00 word tag = 01 word tag = 10 word tag = 11 At the end of each constituent pass of the FFT, the positions of the binary point supported may change to reflect the trend of data increases or decreases in magnitude. Hence, in the pass following that of the above example, the four positions of binary point supported may change to: XXXX.XXXXXXXXXXXX XXXXX.XXXXXXXXXXX XXXXXX.XXXXXXXXXX XXXXXXX.XXXXXXXXX word tag = 00 word tag = 01 word tag = 10 word tag = 11 This variation in the range of binary points supported from pass to pass (i.e. the movement of the binary point relative to its position in the original data) is recorded in the Global Weighting Register (GWR). At the end of the final pass, the distance that the binary point has moved since the start of the FFT can be obtained by modifying the GWR according to the value of WTOUT of a particular word, as shown below: WTOUT1:0 ADJUSTMENT TO GWR 00 01 10 11 SUBTRACT 1 NO ADJUSTMENT ADD 1 ADD 2 For example, if the original data format was: X.XXXXXXXXXXXXXXX then, if the GWR = 01001 and with WTOUT = 10 for a particular word, the binary point has moved 10 places to the right of its original position and will be situated as shown below: XXXXXXXXXXX.XXXXX 4 AN59 Using the GWR with Large FFTs The Global Weighting Register represents the movement of the binary point in two's complement notation in a 5-bit field. An examination of FFT theory and the operation of the BFP system shows that, for an N-point transform, GWR will not exceed (2 = log2N). This means that GWR can handle transforms as large as 8K by representing the movement of the binary point as a two's complement number. However, GWR can be used for much larger transforms by noting that GWR will never drop below -8, since with this degree of left shift, the rounding noise is amplified to fill the whole 16-bit data word. This fact allows GWR to be extended and represented as a six bit value simply by ANDing the two most significant bits to produce a new sign bit (Fig 3). This 6-bit field allows GWR to handle up to a 2097K 2097K transform. Value of GWR Decimal Equiv. 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000* 10001* 10010* 10011* 10100* 10101* 10110* 10111* 11000 11001 11010 11011 11100 11101 11110 11111 0 +1 +2 +3 +4 +5 +6 +7 +8 +9 +10 +11 +12 +13 +14 +15 +16 +17 +18 +19 +20 +21 +22 +23 -8 -7 -6 -5 -4 -3 -2 -1 * not in two's complement format Meaning Binary point as not moved Binary point has moved Binary point has moved 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 8 7 6 5 4 3 2 1 place to the right places to the left Table.1 GWR values and meanings GWR5 GWR4 GWR4 GWR3 GWR2 GWR3 GWR2 GWR1 GWR1 GWR0 GWR0 Fig.3 Extending GWR to 6 bits 5 AN59 SOBFP AR EOPSS BR BI WR WTA WTB WI 3 3 AR15-13 AR15-13 AI 15-13 2 A XR PDSP1601 PDSP1601 IC2 XI YR YI PDSP16116 PDSP16116 IC1 SFTA 2 SFTA C PR AI A PDSP1601 PDSP1601 IC3 C PI 2 2 DAR DAI 3 A B PDSP16318 PDSP16318 IC4 C A'R B SFTR SFTR 3 D 3 2 A'I WTOUT 5 GWR A PDSP16318 PDSP16318 IC5 C D B'R B'I Fig.4 Block Floating Point FFT butterfly Construction of an FFT Butterfly Processor As described earlier, the calculations A' = A + BW and B' = A - BW, forming a `butterfly operation' must be carried out repeatedly in the course of an FFT. Fig. 4 shows how a butterfly processor may be constructed using a single PDSP16116 PDSP16116 in combination with two Zarlink Semiconductor's PDSP16318s and two Zarlink Semiconductor's PSDP1601s. The PDSP1601s are used to match the pipeline delay and shifting operations of the PDSP16116 PDSP16116 to the datapath of the A word. The PDSP16318s are used to perform the complex addition and subtraction of the butterfly operation. Fig. 5 details the underlying architecture of the processor. A detailed list of the various connections required to combine these five chips into a butterfly processor appears in the Appendix. I/O connections are not specified as there are a number of I/O options that allow the butterfly processor to be interfaced with the rest of an FFT system. A point to note is the hard-wired 1-bit right shift in the A-word data paths between the PDSP16116 PDSP16116 outputs and the PDSP16318 PDSP16318 inputs. This is to keep the A-word data format the same as the PDSP16116 PDSP16116 output data format so that the two words may be added within the PDSP16318 PDSP16318. The PDSP1601 PDSP1601 applies a shift of 0 to 3 places to the right whereas data is output from the PDSP16116 PDSP16116 with the binary point shifted from 1 to 4 places to the right. Hence an extra right shift of one place needs to be inserted in the PDSP1601 PDSP1601 data path to keep the data formats compatible at the inputs to the PDSP16318 PDSP16318 (data words must have their binary points in the same places before being added). 6 AN59 S O B F P E O P W W S T T S A B AR P D S P 1 6 0 1 LOGIC BR BI MULTIPLY SFTA MULTIPLY WR WI MULTIPLY MULTIPLY SUBTRACT SHIFT LOGIC PDSP16116 PDSP16116 (Data Path) SHIFT ADD LOGIC SHIFT SFTR WTOUT P D S P 1 6 0 1 ADD SHIFT LOGIC AI SHIFT P D S P 1 6 3 1 8 SUB ADD SHIFT SHIFT A'I B'R P D S P 1 6 3 1 8 SUB SHIFT GWR PDSP16116 PDSP16116 (control logic) A'R B'I Fig.5 BFP Butterfly Detail 7 AN59 CLK Present Br, Bi, Wr, Wi to inputs Present WTA, WTB to inputs Present Ar, Ai to inputs Output SFTA Output SFTR Output Pr, Pi Output DAr, DAi Output WTOUT Output A'r, A'i, B'r, B'i ; ; ; ; ; ; ; ; ; ; ; ; ; n n+1 n+2 n+3 n+4 n+5 n n+1 n+2 n+3 n+4 n+5 n n+1 n+2 n+3 n+4 n+5 n-2 n-1 n n+1 n+2 n+3 n-3 n-2 n-1 n n+1 n+2 n-3 n-2 n-1 n n+1 n+2 n-3 n-2 n-1 n n+1 n+2 n-5 n-4 n-3 n-2 n-1 n n-5 n-4 n-3 n-2 n-1 n Fig.6 Data and Control Timing in the Butterfly The Butterfly Operation A new butterfly operation is commenced each cycle, requiring a new set of data for A, B, W, WTA and WTB. Five cycles later, the corresponding results A' and B' are produced along with their associated WTOUT. In between, the signals SFTA and SFTR are produced and acted upon by the shifters in the PDSP1601 PDSP1601 and PDSP16318 PDSP16318. The timing of the data and control signals is shown in Fig. 6. The results (A' and B') of each butterfly calculation in a pass must be stored away to be used later as the input data (A and B) in the next pass. In every pass, each result must be stored together with its associated word tag, WTOUT. Although WTOUT is common to both A' and B', it must be stored separately with each word as the words are used on different cycles during the next pass. At the inputs, the word tag associated with the A word is known as WTA and the word tag associated with the B word is known as WTB. Hence the WTOUTs from one pass with become the WTAs and the WTBs for the following pass. It should be noted that the first pass is unique in that word tags need not be input into the butterfly as all data must initially have the same weighting. Therefore, during the first pass alone, the inputs WTA and WTB are ignored. Control of the FFT To enable the block floating point hardware to keep track of the data, the following signals are provided: SOBFP - start of the FFT EOPSS - end of current pass These inform the PDSP16116 PDSP16116 when an FFT is starting and when each pass is complete. Fig. 7 shows the timing of these signals and an explanation of their use follows. 8 AN59 CLK SOBFP EOPSS A, B, W, WTA, WTB 1 2 3 4 5 A', B', WTOUT 6 1 7 2 n-1 3 n n-5 1 n-4 n-3 n-2 n-1 2 3 n GWR start of first pass end of first (or subsequent) pass / start of next pass (minimum number of lay cycles shown) Fig.7 Use of BFP Control Signals To commence the FFT, the signal EOPSS should be set high (where it will remain for the duration of the pass). SOBFP should be pulled low during the initial cycle, when the first data words A and B are presented to the inputs of the butterfly processor. The following cycle, SOBFP must be pulled high where it should remain for the duration of the FFT. New data is presented to the processor each successive cycle until the end of the first pass of the FFT. On the last cycle of the pass, the signal EOPSS should be pulled low and remain low for a minimum of five cycles, the time required to clear the pipeline of the butterfly processor so that all the results from one pass are obtained before commencing the following pass (should a longer pause be required between passes - to arrange the data for the next pass, for example - then EOPSS may be kept low for as long as necessary, the next pass cannot commence until it is brought high again). On the initial cycle of each new pass, the signal EOPSS should be pulled high and it should remain high until the final cycle of that pass, when it is pulled low again. Building an FFT System The Butterfly Processor is only one element of a complete FFT system. Also required are fast A/D converters at the front end of the system; a complex heterodyne filter to zoom-in on the frequencies of interest; fast memory and addressing circuits to store the data; additional fast memory and addressing circuits for the coefficients; an output normalisation circuit to make all data consistent; a Pythagoras Processor to extract magnitude and phase information from the results; finally , a D/A converter to allow the magnitude and phase information to be displayed on a video screen or oscilloscope. Fig. 8 shows how these blocks are connected. Zarlink Semiconductor makes a range of high performance DSP devices which solve the more difficult problems outlined above. The complex heterodyne filter may be constructed from a combination of either a PDSP16116 PDSP16116 or PDSP16112 PDSP16112 complex multiplier and either a PDSP16318 PDSP16318 complex accumulator or two PDSP1601 PDSP1601 augmented arithmetic logic units. Output normalisation is a simple matter with the PDSP1601 PDSP1601's adaptable barrel shifter and the PDSP16330 PDSP16330 Pythagoras processor to convert Cartesian to polar coordinates. Memory Requirements Memory requirements differ according to whether the `In-Place' or `Constant Geometry' algorithms are used. In either case, two reads from memory (A and B) and two writes to memory (A' and B') have to be made each 100ns cycle. For the In-Place algorithm, the results (A', B') of a butterfly are written to the same locations from which the inputs (A & B) were read. Hence, the memory must have an access time of 25ns to cope with the two reads and two writes. 9 ANALOG INPUT A/D 10 FFT Control Heterodyne Filter Addr Gen Address Generator Address Generator Data Buffer EOPSS SOBFP B Fig.8 Typical FFT System Coefficent Memory W Butterfly Processor A FFT Data Memory GWR FFT Normalisation Pythagoras Processor D/A PHASE OUTPUT MAGNITUDE OUTPUT AN59 AN59 The Constant Geometry algorithm requires a memory access time of only 50ns, but the memory size must be double that of the In-Place algorithm. This is because the addresses written to after each butterfly are different from those from which the input data was read. This is possible due to the order in which data points are addressed. The memory must be 32 bits wide to accommodate the real and imaginary parts of each word. Also, the 2 bit word tag must be stored with each word. This could be achieved by widening the memory to 34 bits or, alternatively, it could be stored in the LSB of the real and imaginary parts of the word, keeping the memory width at 32 bits. This would not affect the accuracy of the FFT, as the LSB is a rounded value in any case. There would be no problem in the initial pass when no word tags have been written to the memory as the PDSP16116 PDSP16116 ignores the word tag inputs during the initial pass. FFT Output Normalisation In order to preserve the dynamic range of the data during the FFT calculation, the PDSP16116 PDSP16116 employs a range of different weightings, however, at the end of the FFT, the data must be re-formatted to a pre-determined common weighting. This can be done by comparing the exponent of a given data word with the required universal exponent and then shifting the data word by the difference. The PDSP1601 PDSP1601 ALU, with its multifunction 16-bit barrel shifter, is ideally suited to this task. What value should the universal exponent take ? Theoretically, the largest possible data result from an FFT is 1.27N times the largest input data, where N is the size of the FFT. This means that the binary point can move a maximum of (1 + log2N) places to the right. Hence, if the universal exponent is chosen to be (1 + log2N), this should give a sufficient range to represent all data points faithfully. In practice, the FFT output data may never approach the theoretical maximum, therefore it may be worthwhile trying various universal exponents and choosing the one best suited to the particular application. Data is output from the butterfly processor with a two part exponent: the 5-bit GWR applicable to all data words from a given FFT and a 2-bit WTOUT associated with each individual data word. To find the complete exponent for a given word, the GWR for that FFT must be modified by the WTOUT value, the result being the number of places that the binary point has been shifted to the right during the course of the FFT. This value must be subtracted from the universal exponent, the difference being the shift required for that data word, which is input to the SV port of the PDSP1601 PDSP1601. As FFT data consists of real and imaginary parts, either two PDSP1601s must be used or a single PDSP1601 PDSP1601 handling real and imaginary data on alternate cycles, the same shift being applied to both parts. An example of an output normalisation circuit is shown in Fig. 9. Only 4-bit arithmetic is used in calculating the shift which means that very small (negative) values of GWR must be trapped and a forced 16-bit right shift applied. (NB. It is easier to simply add the word tag value to the GWR to determine the shift rather than modifying it exactly. To compensate for this, the universal exponent should be increased by one.) 16-BIT 16-BIT DATA sign bit GWR 4 '1111' B I T B-PORT 4 B I T PDSP1601 PDSP1601 SV-PORT IS ASRSV 4 WTOUT A D D UNIVERSAL EXPONENT B I T M U X C-PORT S U B NORMALISED OUTPUT DATA Fig.9 Output Normalisation Circuitry 11 AN59 Appendix A - Block Floating Point FFT Butterfly Net List The following net lists give all the connections required for implementing the Block Floating Point FFT butterfly shown in Fig.4 : IC1: PDSP16116 PDSP16116 Complex Multiplier Pin No. Net Name D3 C2 B1 D2 E3 C1 E2 D1 F3 F2 E1 G2 G3 F1 G1 H2 H1 H3 J3 J1 K1 J2 K2 K3 L1 L2 M1 N1 M2 L3 N2 P1 M3 N3 P2 R1 N4 P3 R2 P4 N5 R3 P5 R4 N6 P6 R5 P7 N7 R6 R7 12 Pin desc. PI14 PI15 WTOUT1 WTOUT0 SFTR0 SFTR1 SFTR2 OEI CONX CONY ROUND AI13 AI14 AI15 AR13 AR14 AR15 YI15 YI14 YI13 YI12 YI11 YI10 YI9 YI8 YI7 YI6 YI5 YI4 YI3 YI2 YI1 YI0 XI0 GND VDD XI1 XI2 XI3 XI4 XI5 XI6 XI7 XI8 XI9 XI10 XI11 XI12 XI13 XI14 XI15 PI14 PI15 WTOUT1 WTOUT0 SFTR0 SFTR1 SFTR2 AI13 AI14 AI15 AR13 AR14 AR15 WI15 WI14 WI13 WI12 WI11 WI10 WI9 WI8 WI7 WI6 WI5 WI4 WI3 WI2 WI1 WI0 BI0 GND VDD BI1 BI2 BI3 BI4 BI5 BI6 BI7 BI8 BI9 BI10 BI11 BI12 BI13 BI14 BI15 Connections IC5-C11 IC5-C11 IC5-D10 IC5-D10 external o/p external o/p IC4-L7; IC5-L7 IC4-J7; IC5-J7 IC4-J6; IC5-J6 tie low tie low tie low tie high external i/p; IC3-H1 external i/p; IC3-F1 exteral i/p; IC3-G2 external i/p; IC2-H1 external i/p; IC2-F1 external i/p; IC2-G2 external i/p external i/p external i/p external i/p external i/p external i/p external i/p external i/p external i/p external i/p external i/p external i/p external i/p external i/p external i/p external i/p external i/p 0V supply rail +5V supply rail external i/p external i/p external i/p external i/p external i/p external i/p external i/p external i/p external i/p external i/p external i/p external i/p external i/p external i/p external i/p AN59 IC1: PDSP16116 PDSP16116 Complex Multiplier (Continued) Pin No. Pin desc. P8 R8 N8 N9 R9 R10 P9 P10 N10 R11 P11 R12 R13 P12 N11 P13 R14 N12 N13 P14 R15 M13 N14 P15 M14 L13 N15 L14 M15 K13 K14 L15 J14 J13 K15 J15 H14 H15 H13 G13 G15 F15 G14 F14 F13 E15 E14 D15 C15 D14 E13 C14 B15 D13 C13 B14 A15 CEY CEX XR15 XR14 XR13 XR12 XR11 XR10 XR9 XR8 XR7 XR6 XR5 XR4 XR3 XR2 XR1 XR0 YR15 YR14 YR13 GND VDD YR12 YR11 YR10 YR9 YR8 YR7 YR6 YR5 YR4 YR3 YR2 YR1 YR0 EOPSS VDD SOBFP WTB1 WTB0 WTA1 WTA0 MBFP CLK OSEL1 OSEL0 OER SFTA0 SFTA1 GWR0 GWR1 GWR2 GWR3 GWR4 PR15 PR14 Net Name BR15 BR14 BR13 BR12 BR11 BR10 BR9 BR8 BR7 BR6 BR5 BR4 BR3 BR2 BR1 BR0 WR15 WR14 WR13 GND VDD WR12 WR11 WR10 WR9 WR8 WR7 WR6 WR5 WR4 WR3 WR2 WR1 WR0 EOPSS VDD SOBFP WTB1 WTB0 WTA1 WTA0 CLK SFTA0 SFTA1 GWR0 GWR1 GWR2 GWR3 GWR4 PR15 PR14 Connections tie low tie low external i/p external i/p external i/p external i/p external i/p external i/p external i/p external i/p external i/p external i/p external i/p external i/p external i/p external i/p external i/p external i/p external i/p external i/p external i/p 0V supply rail +5V supply rail external i/p external i/p external i/p external i/p external i/p external i/p external i/p external i/p external i/p external i/p external i/p external i/p external i/p external i/p +5V supply rail external i/p external i/p external i/p external i/p external i/p tie high external i/p - common to all ICs tie low tie low tie low IC2-L6; IC3-L6 IC2-L8; IC3-L8 external o/p external o/p external o/p external o/p external io/p IC4-D10 IC4-D10 IC4-C11 IC4-C11 13 AN59 IC1: PDSP16116 PDSP16116 Complex Multiplier (Continued) Pin No. Net Name C12 B13 A14 B12 C11 A13 B11 A12 C10 B10 A11 B9 C9 A10 A9 B8 A8 C8 C7 A7 A6 B7 B6 C6 A5 B5 A4 A3 B4 C5 B3 A2 C4 C3 B2 A1 14 Pin desc. VDD GND PR13 PR12 PR11 PR10 PR9 PR8 PR7 PR6 PR5 GND VDD PR4 PR3 PR2 PR1 PR0 PI0 PI1 PI2 PI3 PI4 VDD PI5 GND PI6 PI7 PI8 PI9 PI10 PI11 PI12 PI13 GND VDD VDD GND PR13 PR12 PR11 PR10 PR9 PR8 PR7 PR6 PR5 GND VDD PR4 PR3 PR2 PR1 PR0 PI0 PI1 PI2 PI3 PI4 VDD PI5 GND PI6 PI7 PI8 PI9 PI10 PI11 PI12 PI13 GND VDD Connections +5V supply rail 0V supply rail IC4-B11 IC4-B11 IC4-C10 IC4-C10 IC4-A11 IC4-A11 IC4-B10 IC4-B10 IC4-B9 IC4-A10 IC4-A10 IC4-A9 IC4-B8 IC4-A8 0V supply rail +5V supply rail IC4-B6 IC4-B7 IC4-A7 IC4-C7 IC4-C6 IC5-C6 IC5-C7 IC5-A7 IC5-B7 IC5-B6 +5V supply rail IC5-A8 0V supply rail IC5-B8 IC5-A9 IC5-A10 IC5-A10 IC5-B9 IC5-B10 IC5-B10 IC5-A11 IC5-A11 IC5-C10 IC5-C10 IC5-B11 IC5-B11 0V supply rail +5V supply rail AN59 IC2: PDSP1601 PDSP1601 - Real Path Pin No. Pin desc. Net Name B10 A6 A5 B5 C5 A4 B4 A3 A2 B3 A1 B2 C2 B1 C1 D2 D1 E3 E2 E1 F2 F3 G3 G1 G2 F1 H1 H2 J1 K1 J2 L1 K2 K3 L2 L3 K4 L4 J5 K5 L5 K6 K10 J6 J7 L7 K7 L6 L8 K8 L9 L10 K9 L11 J10 VCC MSB MSS B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 CEB CLK GND MSA0 MSA1 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 CEA MSC VCC IS0 IS1 IS2 IS3 SV0 SV1 SV2 SV3 SVOE RS0 RS1 RS2 VDD CLK GND AR15 AR14 AR13 AR12 AR11 AR10 AR9 AR8 AR7 AR6 AR5 AR4 AR3 AR2 AR1 AR0 VDD SFTA0 SFTA1 Connections +5V supply rail tie low tie high tie low tie low tie low tie low tie low tie low tie low tie low tie low tie low tie low tie low tie low tie low tie low tie low tie high external i/p - common to all ICs 0V supply rail tie high tie low external i/p ; IC1-H1 external i/p ; IC1 - H2 external i/p ; IC1-G1 external i/p external i/p external i/p external i/p external i/p external i/p external i/p external i/p external i/p external i/p external i/p external i/p external i/p tie low tie high +5V supply rail tie low tie high tie low tie high IC1-C15 IC1-C15 IC1-D14 IC1-D14 tie low tie low tie high tie high tie high tie high 15 AN59 IC2: PDSP1601 PDSP1601 - Real Path (continued) Pin No. K11 J11 H10 H11 F10 G10 G11 G9 F9 F11 E11 E10 E9 D11 D10 C11 B11 C10 A11 B9 A10 A9 B8 A8 B6 B7 A7 C7 C6 16 Pin desc. C0 C1 C2 C3 C4 C5 C6 C7 GND C8 C9 C10 C11 C12 C13 C14 C15 OE BFP CO RA0 RA1 RA2 CI IA0 IA1 IA2 IA3 IA4 Net Name DAR0 DAR1 DAR2 DAR3 DAR4 DAR5 DAR6 GND DAR7 DAR8 DAR9 DAR10 DAR10 DAR11 DAR11 DAR12 DAR12 DAR13 DAR13 DAR14 DAR14:15 Connections N/C IC4-L11 IC4-L11 IC4-K10 IC4-K10 IC4-J10 IC4-J10 IC4-K11 IC4-K11 IC4-J11 IC4-J11 IC4-H10 IC4-H10 IC4-H11 IC4-H11 0V supply rail IC4-F10 IC4-F10 IC4-G10 IC4-G10 IC4-G11 IC4-G11 IC4-G9 IC4-F9 IC4-F11 IC4-F11 IC4-E11 IC4-E11 IC4-E9, E10 tie low N/C N/C L on even cycles, H on odd cycles tie high tie low tie low tie low tie high tie high tie low tie high AN59 IC3: PDSP1601 PDSP1601 - Imaginary Path Pin No. Pin desc. Net Name B10 A6 A5 B5 C5 A4 B4 A3 A2 B3 A1 B2 C2 B1 C1 D2 D1 E3 E2 E1 F2 F3 G3 G1 G2 F1 H1 H2 J1 K1 J2 L1 K2 K3 L2 L3 K4 L4 J5 K5 L5 K6 K10 J6 J7 L7 K7 L6 L8 K8 L9 L10 K9 L11 J10 VCC MSB MSS B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 CEB CLK GND MSA0 MSA1 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 CEA MSC VCC IS0 IS1 IS2 IS3 SV0 SV1 SV2 SV3 SVOE RS0 RS1 RS2 VDD CLK GND AI15 AI14 AI13 AI12 AI11 AI10 AI9 AI8 AI7 AI6 AI5 AI4 AI3 AI2 AI1 AI0 VDD SFTA0 SFTA1 Connections +5V supply rail tie low tie high tie low tie low tie low tie low tie low tie low tie low tie low tie low tie low tie low tie low tie low tie low tie low tie low tie high external i/p - common to all ICs 0V supply rail tie high tie low external i/p ; IC1-F1 external i/p ; IC1 - G3 external i/p ; IC1-G2 external i/p external i/p external i/p external i/p external i/p external i/p external i/p external i/p external i/p external i/p external i/p external i/p external i/p tie low tie high +5V supply rail tie low tie high tie low tie high IC1-C15 IC1-C15 IC1-D14 IC1-D14 tie low tie low tie high tie high tie high tie high 17 AN59 IC3: PDSP1601 PDSP1601 - Imaginary Path (continued) Pin No. K11 J11 H10 H11 F10 G10 G11 G9 F9 F11 E11 E10 E9 D11 D10 C11 B11 C10 A11 B9 A10 A9 B8 A8 B6 B7 A7 C7 C6 18 Pin desc. C0 C1 C2 C3 C4 C5 C6 C7 GND C8 C9 C10 C11 C12 C13 C14 C15 OE BFP CO RA0 RA1 RA2 CI IA0 IA1 IA2 IA3 IA4 Net Name DAI0 DAI1 DAI2 DAI3 DAI4 DAI5 DAI6 GND DAI7 DAI8 DAI9 DAI10 DAI10 DAI11 DAI11 DAI12 DAI12 DAI13 DAI13 DAI14 DAI14:15 Connections N/C IC5-L11 IC5-L11 IC5-K10 IC5-K10 IC5-J10 IC5-J10 IC5-K11 IC5-K11 IC5-J11 IC5-J11 IC5-H10 IC5-H10 IC5-H11 IC5-H11 0V supply rail IC5-F10 IC5-F10 IC5-G10 IC5-G10 IC5-G11 IC5-G11 IC5-G9 IC5-F9 IC5-F11 IC5-F11 IC5-E11 IC5-E11 IC5-E9, E10 tie low N/C N/C L on even cycles, H on odd cycles tie high tie low tie low tie low tie high tie high tie low tie high AN59 IC4: PDSP16318 PDSP16318 - Real Path Pin No. Pin desc. B2 C2 B1 C1 D2 D1 E3 E2 E1 F2 F3 G3 G1 G2 F1 H1 H2 J1 K1 J2 L1 K2 K3 L2 L3 K4 L4 J5 K5 L5 K6 J6 J7 L7 K7 L6 L8 K8 L9 L10 K9 L11 K10 J10 K11 J11 H10 H11 F10 G10 G11 G9 F9 F11 E11 E10 E9 D7 D8 D9 D10 GND VDD D11 D12 D13 D14 D15 C15 C14 C13 C12 VDD GND C11 C10 C9 C8 C7 C6 C5 C4 C3 C2 C1 C0 OED OEC SD2 SD1 SD0 MS ASI1 ASI0 DEL CLR ASR1 ASR0 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 B'R7 B'R8 B'R9 B'R10 GND VDD B'R11 B'R12 B'R13 B'R14 B'R15 A'R15 A'R14 A'R13 A'R12 VDD GND A'R11 A'R10 A'R9 A'R8 A'R7 A'R6 A'R5 A'R4 A'R3 A'R2 A'R1 A'R0 Connections Net Name SFTR2 SFTR1 SFTR0 DAR0 DAR1 DAR2 DAR3 DAR4 DAR5 DAR6 DAR7 DAR8 DAR9 DAR10 DAR10 DAR11 DAR11 DAR12 DAR12 DAR13 DAR13 DAR14 DAR14 DAR15 DAR15 external o/p external o/p external o/p external o/p 0V supply rail +5V supply rail external o/p external o/p external o/p external o/p external o/p external o/p external o/p external o/p external o/p +5V supply rail 0V supply rail external o/p external o/p external o/p external o/p external o/p external o/p external o/p external o/p external o/p external o/p external o/p external o/p tie low tie low IC1-E2 ; IC5-J6 IC1-C1 ; IC5-J7 IC1-E3 ; IC5-L7 tie low tie high tie low tie low tie low tie low tie low IC2-J11 IC2-J11 IC2-H10 IC2-H10 IC2-H11 IC2-H11 IC2-F10 IC2-F10 IC2-G10 IC2-G10 IC2-G11 IC2-G11 IC2-G9 IC2-F11 IC2-F11 IC2-E11 IC2-E11 IC2-E10 IC2-E10 IC2-E9 IC2-D11 IC2-D11 IC2-D10 IC2-D10 IC2-C11 IC2-C11 IC2-B11 IC2-B11 IC2-B11 IC2-B11 19 AN59 IC4: PDSP16318 PDSP16318 - Real Path (continued) Pin No. D11 D10 C11 B11 C10 A11 B10 B9 A10 A9 B8 A8 B6 B7 A7 C7 C6 A6 A5 B5 C5 A4 B4 A3 A2 B3 A1 20 Pin desc. CEA B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 CLK CEB OVR D0 D1 D2 D3 D4 D5 D6 Connections Net Name PR15 PR14 PR13 PR12 PR11 PR10 PR9 PR8 PR7 PR6 PR5 RP4 PR3 PR2 PR1 PR0 CLK B'R0 B'R1 B'R2 B'R3 B'R4 B'R5 B'R6 tie low IC1-B14 IC1-B14 IC1-A15 IC1-A15 IC1-A14 IC1-A14 IC1-B12 IC1-B12 IC1-C11 IC1-C11 IC1-A13 IC1-A13 IC1-B11 IC1-B11 IC1-A12 IC1-A12 IC1-C10 IC1-C10 IC1-B10 IC1-B10 IC1-A11 IC1-A11 IC1-A10 IC1-A10 IC1-A9 IC1-B8 IC1-A8 IC1-C8 external i/p - common to all ICs tie low N/C external o/p external o/p external o/p external o/p external o/p external o/p external o/p AN59 IC5: PDSP16318 PDSP16318 - Imaginary Path Pin No. Pin desc. B2 C2 B1 C1 D2 D1 E3 E2 E1 F2 F3 G3 G1 G2 F1 H1 H2 J1 K1 J2 L1 K2 K3 L2 L3 K4 L4 J5 K5 L5 K6 J6 J7 L7 K7 L6 L8 K8 L9 L10 K9 L11 K10 J10 K11 J11 H10 H11 F10 G10 G11 G9 F9 F11 E11 E10 E9 D7 D8 D9 D10 GND VDD D11 D12 D13 D14 D15 C15 C14 C13 C12 VDD GND C11 C10 C9 C8 C7 C6 C5 C4 C3 C2 C1 C0 OED OEC SD2 SD1 SD0 MS ASI1 ASI0 DEL CLR ASR1 ASR0 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 B'I7 B'I8 B'I9 B'I10 GND VDD B'I11 B'I12 B'I13 B'I14 B'I15 A'I15 A'I14 A'I13 A'I12 VDD GND A'I11 A'I10 A'I9 A'I8 A'I7 A'I6 A'I5 A'I4 A'I3 A'I2 A'I1 A'I0 Connections Net Name SFTR2 SFTR1 SFTR0 DAI0 DAI1 DAI2 DAI3 DAI4 DAI5 DAI6 DAI7 DAI8 DAI9 DAI10 DAI10 DAI11 DAI11 DAI12 DAI12 DAI13 DAI13 DAI14 DAI14 DAI15 DAI15 external o/p external o/p external o/p external o/p 0V supply rail +5V supply rail external o/p external o/p external o/p external o/p external o/p external o/p external o/p external o/p external o/p +5V supply rail 0V supply rail external o/p external o/p external o/p external o/p external o/p external o/p external o/p external o/p external o/p external o/p external o/p external o/p tie low tie low IC1-E2 ; IC4-J6 IC1-C1 ; IC4-J7 IC1-E3 ; IC4-L7 tie low tie high tie low tie low tie low tie low tie low IC3-J11 IC3-J11 IC3-H10 IC3-H10 IC3-H11 IC3-H11 IC3-F10 IC3-F10 IC3-G10 IC3-G10 IC3-G11 IC3-G11 IC3-G9 IC3-F11 IC3-F11 IC3-E11 IC3-E11 IC3-E10 IC3-E10 IC3-E9 IC3-D11 IC3-D11 IC3-D10 IC3-D10 IC3-C11 IC3-C11 IC3-B11 IC3-B11 IC3-B11 IC3-B11 21 AN59 IC5: PDSP16318 PDSP16318 - Imaginary Path (continued) Pin No. D11 D10 C11 B11 C10 A11 B10 B9 A10 A9 B8 A8 B6 B7 A7 C7 C6 A6 A5 B5 C5 A4 B4 A3 A2 B3 A1 22 Pin desc. CEA B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 CLK CEB OVR D0 D1 D2 D3 D4 D5 D6 Connections Net Name PI15 PI14 PI13 PI12 PI11 PI10 PI9 PI8 PI7 PI6 PI5 PI4 PI3 PI2 PI1 PI0 CLK B'I0 B'I1 B'I2 B'I3 B'I4 B'I5 B'I6 tie low IC1-C2 IC1-D3 IC1-C3 IC1-C4 IC1-A2 IC1-B3 IC1-C5 IC1-B4 IC1-A3 IC1-A4 IC1-A5 IC1-B6 IC1-B7 IC1-A6 IC1-A7 IC1-C7 external i/p - common to all ICs tie low N/C external o/p external o/p external o/p external o/p external o/p external o/p external o/p AN59 23 AN59 References For a general introduction to FFTs the following texts are recommended: 1. Rabiner and Gold, `Theory and Application of Digital Signal Processing', Prentice - Hall 1975 2. Oppenhiem and Shafer, `Digital Signal Processing' , Prentice - Hall 1975 Other Zarlink Semiconductor applications notes and briefs of interest include: AN47 `A Radix 2 Butterfly Processor' AN49 `Complex Signal Processing with the PSDP16000 PSDP16000 Family' AN50 `A Fast FFT Processor using the PDSP16000 PDSP16000 Family' AB01 `A 50ns Butterfly Processor' AB10 `FIR Filtering with the PDSP16112 PDSP16112 and PDSP16318 PDSP16318' In addition, many PDSP devices and applications are modelled on the `PDSP Demonstrator' software, intended to be run on IBMPC or compatibles. 24 For more information about all Zarlink products visit our Web Site at www.zarlink.com Information relating to products and services furnished herein by Zarlink Semiconductor Inc. trading as Zarlink Semiconductor or its subsidiaries (collectively "Zarlink") is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual property rights owned by Zarlink or licensed from third parties by Zarlink, whatsoever. Purchasers of products are also hereby notified that the use of product in certain ways or in combination with Zarlink, or non-Zarlink furnished goods or services may infringe patents or other intellectual property rights owned by Zarlink. This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other information appearing in this publication are subject to change by Zarlink without notice. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user's responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to Zarlink's conditions of sale which are available on request. Purchase of Zarlink s I2C components conveys a licence under the Philips I2C Patent rights to use these components in and I2C System, provided that the system conforms to the I2C Standard Specification as defined by Philips. Zarlink and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2001, Zarlink Semiconductor Inc. All Rights Reserved. TECHNICAL DOCUMENTATION - NOT FOR RESALE For more information about all Zarlink products visit our Web Site at www.zarlink.com Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively "Zarlink") is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual property rights owned by Zarlink or licensed from third parties by Zarlink, whatsoever. Purchasers of products are also hereby notified that the use of product in certain ways or in combination with Zarlink, or non-Zarlink furnished goods or services may infringe patents or other intellectual property rights owned by Zarlink. This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other information appearing in this publication are subject to change by Zarlink without notice. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user's responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to Zarlink's conditions of sale which are available on request. Purchase of Zarlink's I2C components conveys a licence under the Philips I2C Patent rights to use these components in and I2C System, provided that the system conforms to the I2C Standard Specification as defined by Philips. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright Zarlink Semiconductor Inc. All Rights Reserved. TECHNICAL DOCUMENTATION - NOT FOR RESALE