PD703002 V852TM 32-/16-BIT PD70P3002 U10038E U10243E U11826EJ3V0DS00 P65/A21 - Datasheet Archive

 

MOS INTEGRATED CIRCUIT µ PD703002 V852TM 32-/16-BIT SINGLE-CHIP MICROCONTROLLER The µ PD703002 is a product in the

 

DATA SHEET MOS INTEGRATED CIRCUIT µ PD703002 PD703002 V852TM V852TM 32-/16-BIT 32-/16-BIT SINGLE-CHIP MICROCONTROLLER The µ PD703002 PD703002 is a product in the V850 Family TM of 32-bit single-chip microcontrollers for real-time control applications. It integrates a 32-bit CPU, ROM, RAM, interrupt controller, real-time pulse unit, and serial interface on a single chip. The µ PD70P3002 PD70P3002 is available as an on-chip PROM version. The details of functions are described in the following user's manuals. Be sure to read them before designing. V852 User's Manual Hardware : U10038E U10038E V850 Family User's Manual Architecture : U10243E U10243E FEATURES · · · · · Number of instructions: 74 · · · · · High-performance interrupt controller Minimum instruction execution time: 40 ns (@ 25-MHz operation) General-purpose register: 32 bits x 32 Instruction set ideal for control application Internal memory ROM : 90 Kbytes RAM : 3 Kbytes Real-time pulse unit ideal for control Powerful serial interface (on-chip dedicated baud rate generator) On-chip clock generator Power save function APPLICATIONS · · · · Audiovisual: Camcorders, VCRs, etc. Office equipment: PPCs, LBPs, printers, etc. Industry: Motor control, numerical control type machine tools, etc. Communication: Cellular phones, etc. The information in this document is subject to change without notice. Document No. U11826EJ3V0DS00 U11826EJ3V0DS00 (3rd edition) Date Published July 1997 N Printed in Japan The mark shows major revised points. © 1996 µPD703002 PD703002 ORDERING INFORMATION Part Number Package µ PD703002GC-25-xxx-7EA 100-pin plastic QFP (fine pitch) (14 × 14 mm) (Resin thickness : 1.45 mm) µ PD703002GC-25-xxx-8EU 100-pin plastic LQFP (fine pitch) (14 × 14 mm) (Resin thickness : 1.40 mm) Remark xxx indicates the ROM code suffix. 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 P65/A21 P65/A21 P66/A22 P66/A22 P67/A23 P67/A23 VSS VDD P30/SO0 P30/SO0 P31/SI0 P31/SI0 P32/SCK0 P32/SCK0 P33/TXD P33/TXD P34/RXD P34/RXD P35/SO1 P35/SO1 P36/SI1 P36/SI1 P37/SCK1 P37/SCK1 VDD VSS P20/NMI P20/NMI P21/INTP00 P21/INTP00 P22/INTP01 P22/INTP01 P23/INTP02 P23/INTP02 P24/INTP03 P24/INTP03 P25/SO2 P25/SO2 P26/SI2 P26/SI2 P27/SCK2 P27/SCK2 VSS VDD PIN CONFIGURATION 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 P07/INTP13 P07/INTP13 P06/INTP12 P06/INTP12 P05/INTP11 P05/INTP11 P04/INTP10 P04/INTP10 P03/TI1 P03/TI1 P02/TCLR1 P02/TCLR1 P01/TO11 P01/TO11 P00/TO10 P00/TO10 VDD VSS P17 P16 P15 P14 P13 P12 P11 P10 VSS VDD MODE0 MODE1 IC0 (G) PLLSEL RESET VSS VDD P90/LBEN P90/LBEN P91/UBEN P91/UBEN P92/R/W P92/R/W P93/DSTB P93/DSTB P94/ASTB P94/ASTB P95/ST0 P95/ST0 P96/ST1 P96/ST1 P97 WAIT VDD VSS X2 X1 CKSEL CVDD CVSS CLKOUT VSS VDD P103 P102 P101/HLDRQ P101/HLDRQ P100/HLDAK P100/HLDAK 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 P64/A20 P64/A20 P63/A19 P63/A19 P62/A18 P62/A18 P61/A17 P61/A17 P60/A16 P60/A16 VSS VDD P57/AD15 P57/AD15 P56/AD14 P56/AD14 P55/AD13 P55/AD13 P54/AD12 P54/AD12 P53/AD11 P53/AD11 P52/AD10 P52/AD10 P51/AD9 P51/AD9 P50/AD8 P50/AD8 VDD VSS P47/AD7 P47/AD7 P46/AD6 P46/AD6 P45/AD5 P45/AD5 P44/AD4 P44/AD4 P43/AD3 P43/AD3 P42/AD2 P42/AD2 P41/AD1 P41/AD1 P40/AD0 P40/AD0 Caution 2 ( ) indicates the processing of the pins not used in the normal operation mode. G : Directly connect this pin to VSS. µPD703002 PD703002 P00 to P07 : Port0 A16 to A23 : Address Bus P10 to P17 : Port1 LBEN : Lower Byte Enable P20 to P27 : Port2 UBEN : Upper Byte Enable P30 to P37 : Port3 R/W : Read/Write Status P40 to P47 : Port4 DSTB : Data Strobe P50 to P57 : Port5 ASTB : Address Strobe P60 to P67 : Port6 ST0, ST1 : Status P90 to P97 : Port9 HLDAK : Hold Acknowledge P100 to P103 : Port10 HLDRQ : Hold Request TO10, TO11 : Timer Output CLKOUT : Clock Output TCLR1 : Timer Clear CKSEL : Clock Select TI1 : Timer Input PLLSEL : PLL Select INTP00 INTP00 to INTP03 INTP03, : Interrupt Request From Peripherals WAIT : Wait INTP10 INTP10 to INTP13 INTP13 MODE0, MODE1 : Mode NMI : Non-maskable Interrupt Request RESET SO0 to SO2 : Serial Output X1, X2 : Crystal SI0 to SI2 : Serial Input CV DD : Power Supply for Clock Generator SCK0 to SCK2 : Serial Clock CV SS : Ground for Clock Generator TXD V DD : Power Supply : Transmit Data : Reset RXD : Receive Data V SS : Ground AD0 to AD15 : Address/Data Bus IC0 : Internally Connected 3 µPD703002 PD703002 FUNCTION BLOCK DIAGRAM ROM BCU CPU NMI INTP00 INTP00 to INTP03 INTP03 Instruction Queue PC INTC INTP10 INTP10 to INTP13 INTP13 90 Kbytes RPU TCLR1 TI1 UBEN Multiplier 16 x 16 32 LBEN WAIT RAM A16 to A23 General-Purpose Register 32 bits x 32 ALU AD0 to AD15 3 Kbytes ST0, ST1 SIO TXD RXD DSTB R/W 32-Bit Barrel Shifter System Register TO10, TO11 ASTB HLDRQ HLDAK UART BRG0 SO1 SI1 SCK1 CSI0 CSI1 BRG1 SO2 SI2 SCK2 4 CSI2 Ports P100 to P103 P90 to P97 P60 to P67 P50 to P57 P40 to P47 P30 to P37 P21 to P27 P20 P10 to P17 P00 to P07 SO0 SI0 SCK0 CG CKSEL PLLSEL CLKOUT X1 X2 MODE0, MODE1 RESET VDD VSS CVDD CVSS µPD703002 PD703002 CONTENTS 1. PIN FUNCTION LIST . 7 1.1 Port Pins . 7 1.2 Non-Port Pins . 9 1.3 Pin I/O Circuits and Recommended Connections of Unused Pins . 11 2. FUNCTION BLOCKS . 13 2.1 Internal Units . 13 2.1.1 CPU . 13 2.1.2 Bus control unit (BCU) . 13 2.1.3 ROM . 13 2.1.4 RAM . 13 2.1.5 Port . 13 2.1.6 Interrupt controller (INTC) . 13 2.1.7 Clock generator (CG) . 13 2.1.8 Real-time pulse unit (RPU) . 13 2.1.9 Serial interface (SIO) . 14 3. CPU FUNCTION . 15 3.1 Features . 15 4. BUS CONTROL FUNCTION . 16 4.1 Features . 16 5. INTERRUPT/EXCEPTION HANDLING . 17 5.1 Features . 17 5.2 Configuration . 17 6. CLOCK GENERATOR . 19 6.1 Features . 19 6.2 Configuration . 19 7. TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) . 20 7.1 Features . 20 7.2 Configuration . 21 8. SERIAL INTERFACE FUNCTION (SIO) . 22 8.1 Features . 22 8.2 Asynchronous Serial Interface (UART) . 22 8.2.1 Features . 22 8.2.2 Configuration . 23 5 µPD703002 PD703002 8.3 Clocked Serial Interface 0 to 2 (CSI0 to CSI2) . 24 8.3.1 Features . 24 8.3.2 Configuration . 24 8.4 Baud Rate Generator 0, 1 (BRG0, BRG1) . 25 8.4.1 Features . 25 8.4.2 Configuration . 25 9. PORT FUNCTION . 26 9.1 Features . 26 9.2 Configuration . 26 10. RESET FUNCTION . 38 10.1 Features . 38 11. INSTRUCTION SET . 39 11.1 Instruction Set List . 39 12. ELECTRICAL SPECIFICATIONS . 46 13. CHARACTERISTIC CURVES (REFERENCE) . 65 14. PACKAGE DRAWINGS . 66 15. RECOMMENDED SOLDERING CONDITIONS . 68 6 µPD703002 PD703002 1. PIN FUNCTION LIST 1.1 Port Pins (1/2) Pin Name P00 I/O I/O Function Alternate Function P01 P02 Port 0 TO10 8-bit input/output port Input/output can be specified bit-wise. TO11 TCLR1 P03 TI1 P04 INTP10 INTP10 P05 INTP11 INTP11 P06 INTP12 INTP12 P07 INTP13 INTP13 P10 to P17 I/O Port 1 8-bit input/output port Input/output can be specified bit-wise. P20 Input P21 I/O Port 2 P20 is the port for input only Operates as an NMI input when a valid edge is input. And shows NMI input status at bit 0 of P2 register. P21 to P27 are 7-bit input/output ports. Input/output can be specified bit-wise. P22 P23 P24 - NMI INTP00 INTP00 INTP01 INTP01 INTP02 INTP02 INTP03 INTP03 P25 SO2 P26 SI2 P27 P30 SCK2 I/O P31 P32 Port 3 8-bit input/output port Input/output can be specified bit-wise. SO0 SI0 SCK0 P33 TXD P34 RXD P35 SO1 P36 SI1 P37 SCK1 P40 to P47 I/O Port 4 8-bit input/output port Input/output can be specified bit-wise. AD0 to AD7 P50 to P57 I/O Port 5 8-bit input/output port Input/output can be specified bit-wise. AD8 to AD15 P60 to P67 I/O Port 6 8-bit input/output port Input/output can be specified bit-wise. A16 to A23 7 µPD703002 PD703002 (2/2) Pin Name P90 I/O I/O Function Alternate Function P92 Port 9 LBEN 8-bit input/output port Input/output can be specified bit-wise. P91 UBEN R/W P93 DSTB P94 ASTB P95 ST0 P96 ST1 P97 P100 P101 P102 P103 8 - I/O Port 10 4-bit input/output port Input/output can be specified bit-wise. HLDAK HLDRQ - - µPD703002 PD703002 1.2 Non-Port Pins (1/2) Pin Name TO10 I/O Output Function Pulse signal output of timer 1 TO11 TCLR1 P00 P01 Input Input INTP11 INTP11 Timer 1 external clear signal input P02 Timer 1 external count clock input TI1 INTP10 INTP10 Alternate Function P03 External maskable interrupt request input, or timer 1 external capture trigger input (in common use) P04 P05 INTP12 INTP12 P06 INTP13 INTP13 P07 NMI Input Non-maskable interrupt request input INTP00 INTP00 Input External maskable interrupt request input P20 P21 INTP01 INTP01 P22 INTP02 INTP02 P23 INTP03 INTP03 P24 SO0 Output CSI0 serial data transmission output P30 SI0 Input CSI0 serial data reception input P31 SCK0 I/O CSI0 serial clock I/O P32 SO1 Output CSI1 serial data transmission output P35 SI1 Input CSI1 serial data reception input P36 SCK1 I/O CSI1 serial clock I/O P37 SO2 Output CSI2 serial data transmission output P25 SI2 Input CSI2 serial data reception input P26 SCK2 I/O CSI2 serial clock I/O P27 TXD Output UART serial data transmission output P33 RXD Input UART serial data reception input P34 AD0 to AD7 I/O 16-bit multiplexed address/data bus when expanding memory externally P40 to P47 AD8 to AD15 P50 to P57 A16 to A23 Output Higher address bus when expanding memory externally P60 to P67 LBEN Output External data bus lower byte enable signal output P90 UBEN External data bus higher byte enable signal output P91 R/W External read/write status output P92 DSTB External data strobe signal output P93 ASTB External address strobe signal output P94 ST0 External bus cycle status output P95 ST1 P96 HLDAK Output Bus hold acknowledge output P100 HLDRQ Input Bus hold request input P101 CLKOUT Output System clock output - CKSEL Input Clock generator operation mode specification - PLLSEL Input Input specifying PLL multiplication coefficient input - 9 µPD703002 PD703002 (2/2) Pin Name I/O Function Alternate Function WAIT Input Bus cycle wait insertion control signal input - MODE0, MODE1 Input Operation mode specification - RESET Input System reset input - X1 Input Connect resonator for system clock. Input external clock to X1. - X2 - CVDD - Positive power for internal clock generator - CVSS - Ground potential for internal clock generator - VDD - Positive power supply - VSS - Ground potential - IC0 - Internally connected - 10 - µPD703002 PD703002 1.3 Pin I/O Circuits and Recommended Connections of Unused Pins Table 1-1 shows the I/O circuit types of the respective pins in the normal operation mode and recommended connections of unused pins. Figure 1-1 shows the respective circuit types partially simplified. When connecting a pin to VDD or VSS via resistor, use of a resistor of 3 to 10 k is recommended. Table 1-1. Types of Pin I/O Circuits and Recommended Connections of Unused Pins I/O Circuit Type Recommended Connections P00/TO10 P00/TO10, P01/TO11 P01/TO11 Pin Name 5 P02/TCLR1 P02/TCLR1, P03/TI1 P03/TI1, P04/INTP10 P04/INTP10 to P07/INTP13 P07/INTP13 8 Input: Individually connect to V DD or V SS via resistor Output: Open P10 to P17 5 P20/NMI P20/NMI 2 Directly connect to VSS P21/INTP00 P21/INTP00 to P24/INTP03 P24/INTP03 8 Input: Individually connect to V DD or V SS via resistor P25/SO2 P25/SO2 5 Output: Open P26/SI2 P26/SI2, P27/SCK2 P27/SCK2 8 P30/SO0 P30/SO0 5 P31/SI0 P31/SI0, P32/SCK0 P32/SCK0 8 P33/TXD P33/TXD, P34/RXD P34/RXD, P35/SO1 P35/SO1 5 P36/SI1 P36/SI1, P37/SCK1 P37/SCK1 8 P40/AD0 P40/AD0 to P47/AD7 P47/AD7 5 P50/AD8 P50/AD8 to P57/AD15 P57/AD15 P60/A16 P60/A16 to P67/A23 P67/A23 P90/LBEN P90/LBEN P91/UBEN P91/UBEN P92/R/W P92/R/W P93/DSTB P93/DSTB P94/ASTB P94/ASTB P95/ST0 P95/ST0, P96/ST1 P96/ST1 P97 P100/HLDAK P100/HLDAK P101/HLDRQ P101/HLDRQ P102, P103 CLKOUT 3 CKSEL 2 - PLLSEL 2 - WAIT 1 MODE0, MODE1 Open 2 Directly connect to VDD - RESET IC0 - Directly connect to VSS CVDD - Directly connect to VDD CVSS - Directly connect to VSS 11 µPD703002 PD703002 Figure 1-1. Pin I/O Circuits Type 1 Type 5 VDD VDD data P-ch IN/OUT P-ch IN output disable N-ch N-ch input enable Type 2 Type 8 VDD data P-ch IN/OUT output disable IN Schmitt trigger input with hysteresis characteristics Type 3 VDD P-ch OUT N-ch 12 N-ch µPD703002 PD703002 2. FUNCTION BLOCKS 2.1 Internal Units 2.1.1 CPU Most instructions, such as address calculation, arithmetic and logic operation, and data transfer, are executed in one clock cycle under control of 5-stage pipeline. The CPU also includes dedicated hardware such as a multiplier (16 by 16) and a 32-bit barrel shifter, aiming at processing complex instructions at high speeds. In addition, the CPU can access internal ROM (90 Kbytes) and RAM (3 Kbytes) in one clock cycle. 2.1.2 Bus control unit (BCU) The BCU initiates necessary external bus cycles based on the physical address given by the CPU. When an instruction fetch of external memory is executed, if no bus cycle initiation is requested by the CPU, the BCU creates a prefetch address to prefetch an instruction code. The prefetched instruction code is taken into the internal instruction queue. 2.1.3 ROM The ROM has a capacity of 90 Kbytes and is mapped from the address 00000000H 00000000H. Access to the ROM is enabled/disabled by setting the MODE0 and MODE1 pins. The CPU can access any address of the ROM in one clock cycle (to fetch an instruction). 2.1.4 RAM This RAM has a capacity of 3 Kbytes and is mapped from address FFFFE000H FFFFE000H. The CPU can access any address of the RAM in one clock cycle (to access data). 2.1.5 Port The µPD703000 PD703000 is provided with a total of 68 input/output port pins (of which one is an input port pin), or ports 0 through 10. These port pins can be used as the control pins. 2.1.6 Interrupt controller (INTC) The interrupt controller controls various interrupt requests (NMI, INTP00-INTP03 INTP00-INTP03, and INTP10-INTP13 INTP10-INTP13) issued by peripheral hardware or external devices. Up to eight levels of interrupt priority can be individually specified for each interrupt request. In addition, multiplexed processing control can be performed. 2.1.7 Clock generator (CG) The clock generator generates a CPU operating clock whose frequency is 1 or 5 times as high as (with the internal PLL) or half (without the internal PLL) the frequency of the resonator connected across the X1 and X2 pins. Instead of connecting a resonator, a clock signal can be input from off-chip. 2.1.8 Real-time pulse unit (RPU) The RPU which includes a 16-bit timer/event counter and a 16-bit interval timer, measures pulse intervals and pulse frequency, and outputs programmable pulses. 13 µPD703002 PD703002 2.1.9 Serial interface (SIO) The serial interface includes one UART channel (asynchronous serial interface) and three CSI channels (clocked serial interface). The UART transfers data with the TXD and RXD pins. The baud rate is generated by an on-chip dedicated baud rate generator. The CSI transfers data with the SO0 to SO2, SI0 to SI2, and SCK0 to SCK2 pins. The baud rate can be generated from an on-chip dedicated baud rate generator, or supplied from off-chip. 14 µPD703002 PD703002 3. CPU FUNCTION The CPU of the µPD703002 PD703002 is based on the RISC architecture and executes almost all the instructions in one clock cycle, using a 5-stage pipeline. 3.1 Features · · · · · · · · · · Minimum instruction execution time: 40 ns (@ internal 25-MHz operation) Address space: 16-Mbyte linear General registers: 32 bits × 32 Internal 32-bit architecture Five-stage pipeline control Multiply/divide instruction Saturated operation instruction 32-bit shift instruction: 1 clock Long/short format Internal memory · ROM: 90 Kbytes · RAM: 3 Kbytes · Bit manipulate instructions: 4 types · Set · Clear · Not · Test 15 µPD703002 PD703002 4. BUS CONTROL FUNCTION 4.1 Features · · External device connectable with port pins (using alternate function) Wait function · Programmable wait function inserting up to 3 states per 2 blocks · External wait function effected by WAIT pin · · · 16 Idle state inserting function Bus arbitration function Bus hold function µPD703002 PD703002 5. INTERRUPT/EXCEPTION HANDLING 5.1 Features · Interrupts · Non-maskable : 1 source · Maskable : 16 sources · 8-level programmable priority control · Multiplexed processing control according to priority · Masking each maskable interrupt request · Valid edge specification for external interrupt request · Exceptions · Software exception : 32 sources · Exception trap : 1 source (illegal instruction code exception) 5.2 Configuration Internal Bus 7 0 ISPR XXMKn (Interrupt Mask Flag) 3 0 1 2 INTP12/INTCC12 INTP12/INTCC12 INTP13/INTCC13 INTP13/INTCC13 INTCM4 INTCSI0 INTSER0 INTSR0 INTST0 INTCSI1 INTCSI2 INTP00 INTP00 INTP01 INTP01 INTP02 INTP02 INTP03 INTP03 INTM1 Edge Detection SIO Edge Detection INTM2 INTP10 INTP10 INTP11 INTP11 INTP12 INTP12 INTP13 INTP13 INTP11/INTCC11 INTP11/INTCC11 Selector 3 2 1 0 3 2 1 0 INTOV1 INTP10/INTCC10 INTP10/INTCC10 OVIF1 P1IF0 P1IF1 P1IF2 P1IF3 CMIF4 CSIF0 SEIF0 SRIF0 STIF0 P0IF0 P0IF1 P0IF2 P0IF3 CSIF1 CSIF2 Handler Address Generator Priority Controller XXPRn RPU CPU Interrupt Request Interrupt Request Acknowledge HALT Mode Release Signal PSW ID XX: Identification name for each peripheral unit (OV, P1, CM, CS, SE, SR, ST, P0, CS) n : Peripheral unit number (0 to 4) 17 µPD703002 PD703002 Table 5-1. Interrupts Interrupt/Exception Causes Type Class Name Control Register Generation Cause Default Exception Generating Priority Code Unit Handler Restore Address PC Reset Interrupt RESET - Reset input - - 0000H 0000H 00000000H 00000000H Undefined Non-maskable Interrupt NMI - NMI input - - 0010H 0010H 00000010H 00000010H next PC Software exception Exception TRAP0nNote - TRAP instruction - - 004nNoteH 00000040H 00000040H next PC Note - TRAP instruction - - 005nNoteH 00000050H 00000050H next PC - Illegal instruction code Exception TRAP1n Exception trap Exception ILGOP Maskable Interrupt INTOV1 OVIC1 Timer 1 overflow - - 0060H 0060H 00000060H 00000060H next PC RPU 0 0080H 0080H 00000080H 00000080H next PC Interrupt INTP10/INTCC10 INTP10/INTCC10 P1IC0 Match of INTP10 INTP10 & CC10 Pin/RPU 1 0090H 0090H 00000090H 00000090H next PC Interrupt INTP11/INTCC11 INTP11/INTCC11 Interrupt INTP12/INTCC12 INTP12/INTCC12 P1IC1 Match of INTP11 INTP11 & CC11 Pin/RPU 2 00A0H 00A0H 000000A0H 000000A0H next PC P1IC2 Match of INTP12 INTP12 & CC12 Pin/RPU 3 00B0H 00B0H 000000B0H 000000B0H next PC Interrupt INTP13/INTCC13 INTP13/INTCC13 P1IC3 Match of INTP13 INTP13 & CC13 Pin/RPU 4 00C0H 00C0H 000000C0H 000000C0H next PC Interrupt INTCM4 CMIC4 Match of CM4 RPU 5 00D0H 00D0H 000000D0H 000000D0H next PC Interrupt INTCSI0 CSIC0 SIO 6 00E0H 00E0H 000000E0H 000000E0H next PC CSI0 transmit/receive completion Interrupt INTSER0 SEIC0 UART0 receive error SIO 7 00F0H 00F0H 000000F0H 000000F0H next PC Interrupt INTSR0 SRIC0 UART0 receive completion SIO 8 0100H 0100H 00000100H 00000100H next PC Interrupt INTST0 STIC0 UART0 transmit completion SIO 9 0110H 0110H 00000110H 00000110H next PC Interrupt INTP00 INTP00 P0IC0 INTP00 INTP00 pin Pin 10 0120H 0120H 00000120H 00000120H next PC Interrupt INTP01 INTP01 P0IC1 INTP01 INTP01 pin Pin 11 0130H 0130H 00000130H 00000130H next PC Interrupt INTP02 INTP02 P0IC2 INTP02 INTP02 pin Pin 12 0140H 0140H 00000140H 00000140H next PC Interrupt INTP03 INTP03 P0IC3 INTP03 INTP03 pin Pin 13 0150H 0150H 00000150H 00000150H next PC Interrupt INTCSI1 CSIC1 CSI1 transmit/receive completion SIO 14 0160H 0160H 00000160H 00000160H next PC Interrupt INTCSI2 CSIC2 CSI2 transmit/receive completion SIO 15 0170H 0170H 00000170H 00000170H next PC Note The "n" in the "Software exception" rows is a value from 0 to FH. Remarks 1. 2. 18 Default priority: Priority used when two or more maskable interrupt requests having the same priority are simultaneously generated. 0 indicates the highest priority. Restore PC: PC value saved to EIPC or FEPC when interrupt/exception processing is started. However, the restore PC value saved if an interrupt is accepted while the DIVH (division) instruction is being executed is the PC value of the current instruction (DIVH). The execution address of an illegal instruction when an illegal instruction code exception occurs can be calculated as (restore PC­4). µPD703002 PD703002 6. CLOCK GENERATOR 6.1 Features · · · Multiply function by PLL clock synthesizer (f XX = or fXX = /5) Direct mode directly to input external clock Power save mode · HALT mode · IDLE mode · Software STOP mode · Clock output inhibit function 6.2 Configuration CKSEL In direct mode (fXX) X1 (fXX) X2 OSC 1 2 PFC SCF 1 2 VCO In PLL mode (fVCO) Divider PLLSEL PLL Synthesizer fVCO : VCO oscillation frequency ( = 2 · fXX when PLLSEL = 0), (= 10 · fXX when PLLSEL = 1) : Internal system clock frequency ( = 1/2 · fVCO : in PLL mode) Internal system clock frequency ( = 1/2 · f×× : in direct mode) OSC : Oscillator (supported in PLL mode only) PFC : Phase Frequency Comparator SCF : Switched Capacitor Filter VCO : Voltage Controlled Oscillator Divide ratio of the divider (= 1/4 when PLLSEL = 0), (= 1/20 when PLLSEL = 1) 19 µPD703002 PD703002 7. TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) 7.1 Features · Pulse interval and frequency measurement and output of programmable pulse · 16-bit measurement possible · Pulse can be generated in various shapes (interval pulse, one-shot pulse) · Timer 1 · 16-bit timer/event counter · Sources of count clock: 2 types (divided system clock or external pulse input) · Capture/compare registers: 4 · Count clear pin: TCLR1 · Interrupt sources: 5 · External pulse output: 2 · Timer 4 · 16-bit interval timer · Count clock selected from divided system clock · Compare register: 1 · Interrupt source: 1 20 µPD703002 PD703002 7.2 Configuration (1) Timer 1 (16-bit timer/event counter) Edge Detection TCLR1 /2 m /4 m m/4 m/8 m/16 TI1 Note2 Clear & start Clear and start Note1 INTOV1 TM1 (16 bits) Edge Detection INTCC10 INTCC10 INTCC11 INTCC11 INTP10 INTP10 Edge Detection CC10 S INTP11 INTP11 Edge Detection CC11 RNote3 Q INTP12 INTP12 Edge Detection CC12 S INTP13 INTP13 Edge Detection CC13 RNote3 Q Q TO10 Q TO11 INTCC12 INTCC12 INTCC13 INTCC13 Notes 1. Internal count clock 2. External count clock 3. Gives priority to reset Remark indicates the system clock. (2) Timer 4 (16-bit interval timer) /2 m /4 /8 m/16 Note m/32 TM4 (16 bits) Clear & start CM4 INTCM4 Note Internal count clock Remark indicates the system clock. 21 µPD703002 PD703002 8. SERIAL INTERFACE FUNCTION (SIO) 8.1 Features The µPD703002 PD703002 is provided with four independent serial interface channels. (1) Asynchronous serial interface (UART): 1 channel (2) Clocked synchronous serial interface (CSI0 to CSI2): 3 channels 8.2 Asynchronous Serial Interface (UART) 8.2.1 Features · · · Transfer rate: 110 to 38400 bps (with BRG, when = 25 MHz) Up to 781 Kbps (with /2, when = 25 MHz) Full-duplex communication 2-pin configuration TXD: Transmit data output pin RXD: Receive data input pin · Receive error detection function · Parity error · Framing error · Overrun error · Three interrupt sources · Receive error interrupt (INTSER0) · Reception completion interrupt (INTSR0) · Transmission completion interrupt (INTST0) · · Character length of transmission/reception data is specified by setting ASIM00 ASIM00, ASIM01 ASIM01 register. · · · Parity function Character length : 7, 8 bits 9 bits (with extended bit appended) Transmission stop bit: 1 or 2 bits Baud rate generator Remark 22 : odd, even, 0, none indicates the system clock µPD703002 PD703002 8.2.2 Configuration Internal Bus 8 16/8 Receive Buffer 8 ASIM00 ASIM00 16/8 RXB0 RXB0L 8 ASIM01 ASIM01 EBS0 RXE0 PS01 PS00 CL0 SL0 SCLS0 ASIS0 RXD Receive Shift Register PE0 FE0 OVE0 SOT0 Transmit Shift TXS0 Register TXS0L TXD 1 16 INTSR0 Transmit INTSER0 Control Parity Append INTST0 1 16 1 2 Selector Receive Control Parity Check Baud Rate Generator 23 µPD703002 PD703002 8.3 Clocked Serial Interface 0 to 2 (CSI0 to CSI2) 8.3.1 Features · · Number of channels: 3 (CSIn) · · · · · Half-duplex communication High-speed transfer rate 6.25 Mbps MAX. (with /2, = 25 MHz) Data length of 8 bits MSB first/LSB first can be switched for data Selection of external serial clock input/internal serial clock output Three pins used SOn : Serial data output pin SIn : Serial data input pin SCKn : Serial clock I/O pin · Three interrupt sources · Interrupt request signal (INTCSIn) Remark 1. indicates the system clock. 2. n = 0 to 2 8.3.2 Configuration CSI0 CSIM0 CTXE0 CRXE0 CSOT0 MOD0 CLS01 CLS01 CLS00 CLS00 SO Latch Serial I/O Shift Register (SIO0) SI0 D Q Serial Clock Counter Baud Rate Generator /2 Interrupt Controller SI1 SO1 SCK1 CSI1 SI2 SO2 SCK2 24 1 2 CSI2 INTCSI0 Internal Bus Serial Clock Controller Circuit Selector SCK0 Selector SO0 µPD703002 PD703002 8.4 Baud Rate Generator 0, 1 (BRG0, BRG1) 8.4.1 Features · · Serial clock selectable from baud rate generator output and (system clock) Same baud rate for transmission/reception 8.4.2 Configuration Baud Rate Generator 0 BPR00 BPR00 BPR01 BPR01 BPR02 BPR02 BRG0 BRCE0 BPRM0 Match UART CSI0 TMBRG0 Prescaler Baud Rate Generator 1 1 2 Internal Bus Clear BPR10 BPR10 BPR11 BPR11 BPR12 BPR12 BRG1 BRCE1 BPRM1 Match CSI1 Clear CSI2 TMBRG1 Prescaler 25 µPD703002 PD703002 9. PORT FUNCTION 9.1 Features The ports of the µPD703002 PD703002 have the following features: · Number of port pins Input port: 1 I/O port: 67 · · · · Shared with I/O pins of other peripheral functions Input/output specifiable bitwise Noise elimination Edge detection 9.2 Configuration Figure 9-1. Block Diagram of P00, P01 (Port 0) WRPMC PMC0n WRPM TO1n Selector P0n RDIN Remark n = 0, 1 26 Address P0n Selector WRPORT Selector Internal Bus PM0n µPD703002 PD703002 Figure 9-2. Block Diagram of P02 to P07 (Port 0) WRPMC PMC0n WRPM Internal Bus PM0n WRPORT P0n Address RDIN INTP10 INTP10 to INTP13 INTP13, TCLR1, TI1 Selector Selector P0n Noise Elimination Edge Detection Remark n = 2 to 7 Figure 9-3. Block Diagram of P10 to P17 (Port 1) WRPM WRPORT P1n RDIN Selector P1n Selector Internal Bus PM1n Address Remark n = 0 to 7 27 µPD703002 PD703002 Selector Internal Bus Figure 9-4. Block Diagram of P20 (Port 2) 1 Noise Elimination P20 Address RDIN NMI Edge Detection Figure 9-5. Block Diagram of P21 to P24 (Port 2) WRPMC PMC2n WRPM WRPORT P2n RDIN INTP00 INTP00 to INTP03 INTP03 Remark n = 1 to 4 28 Address Noise Elimination Edge Detection Selector P2n Selector Internal Bus PM2n µPD703002 PD703002 Figure 9-6. Block Diagram of P25 (Port 2) WRPMC PMC25 PMC25 WRPM WRPORT Selector Internal Bus PM25 SO2 P25 RDIN Selector Selector P25 Address Figure 9-7. Block Diagram of P26 (Port 2) WRPMC PMC26 PMC26 WRPM WRPORT P26 Selector P26 Selector Internal Bus PM26 Address RDIN SI2 29 µPD703002 PD703002 Figure 9-8. Block Diagram of P27 (Port 2) WRPMC PMC27 PMC27 WRPM SCK2 Output Selector P27 Address RDIN SCK2 Input 30 P27 Selector WRPORT Selector Internal Bus PM27 µPD703002 PD703002 Figure 9-9. Block Diagram of P30, P33, P35 (Port 3) WRPMC PMC3n WRPM SO0, SO1, TXD Selector P3n RDIN P3n Selector WRPORT Selector Internal Bus PM3n Address Remark n = 0, 3, 5 Figure 9-10. Block Diagram of P31, P36 (Port 3) WRPMC PMC3n WRPM WRPORT P3n Address RDIN Remark n = 1, 6 Selector P3n Selector Internal Bus PM3n S0, SI1 31 µPD703002 PD703002 Figure 9-11. Block Diagram of P32, P37 (Port 3) WRPMC PMC3n WRPM WRPORT Selector Internal Bus PM3n SCKm Output P3n Selector Selector P3n Address RDIN Remark n = 2, 7 m = 0, 1 SCKm Input Figure 9-12. Block Diagram of P34 (Port 3) WRPMC PMC34 PMC34 WRPM WRPORT P34 RDIN Address RXD 32 Selector P34 Selector Internal Bus PM34 µPD703002 PD703002 Figure 9-13. Block Diagram of P40 to P47 (Port 4) MODE0, MODE1 MM0 to MM2 WRPM WRPORT P4n RDIN I/O Control Circuit Internal Bus PM4n P4n AD0 to AD7 Remark n = 0 to 7 33 µPD703002 PD703002 Figure 9-14. Block Diagram of P50 to P57 (Port 5) MODE0, MODE1 MM0 to MM2 WRPM WRPORT P5n RDIN AD8 to AD15 Remark n = 0 to 7 34 I/O Control Circuit Internal Bus PM5n P5n µPD703002 PD703002 Figure 9-15. Block Diagram of P60 to P67 (Port 6) MODE0, MODE1 MM0 to MM2 WRPM WRPORT P6n RDIN I/O Control Circuit Internal Bus PM6n P6n A16 to A23 Remark n = 0 to 7 35 µPD703002 PD703002 Figure 9-16. Block Diagram of P90 to P97 (Port 9) MODE0, MODE1 MM0 to MM3 WRPM Internal Bus PM9n I/O Control Circuit WRPORT P9n RDIN P9n LBEN, UBEN, R/W, DSTB, ASTB, ST0, ST1 Remark n = 0 to 7 Figure 9-17. Block Diagram of P100, P103 (Port 10) WRPMC PMC10n WRPM HLDAK, RFU Selector P10n Note RDIN Note RFU is undefined value. Remark n = 0, 3 36 Address P10n Selector WRPORT Selector Internal Bus PM10n µPD703002 PD703002 Figure 9-18. Block Diagram of P101 (Port 10) WRPMC PMC101 PMC101 WRPM WRPORT P101 Selector P101 Selector Internal Bus PM101 PM101 Address RDIN HLDRQ Figure 9-19. Block Diagram of P102 (Port 10) WRPM WRPORT P102 RDIN Selector P102 Selector Internal Bus PM102 PM102 Address 37 µPD703002 PD703002 10. RESET FUNCTION When the RESET signal is made low, the system is reset, and the on-chip hardware units are initialized. The reset status is cleared when the RESET signal is made high, and the CPU starts executing the program. Initialize the contents of each register in the program as necessary. 10.1 Features · 38 Noise elimination circuit of analog delay (60 to 220 ns) provided to the reset pin µPD703002 PD703002 11. INSTRUCTION SET 11.1 Instruction Set List · How to read instruction set list This column indicates an instruction group. This instruction set list classifies instructions by group. This column indicates the mnemonic of the instruction. This column indicates the operand of the instruction (refer to Table 11-1). This column indicates the instruction code in binary number . The instruction code of a 32-bit instruction is shown in two columns (refer to Table 11-2). This column indicates the operation of the instruction (refer to Table 11-3). Instruction Group These columns indicate the operation of the flags (refer to Table 11-4). Flag Mnemonic Operand Operation Code Operation CY OV S Z SAT Table 11-1. Symbols Shown in "Operand" Column Symbol Description reg1 General register (used as source register) reg2 General register (mainly used as destination register. Some are also used as source registers) ep Element pointer bit#3 3-bit data for bit number specification immX X-bit immediate dispX X-bit displacement regID System register number vector 5-bit data specifying trap vector (00H through 1FH) cccc 4-bit data indicating condition code 39 µPD703002 PD703002 Table 11-2. Symbols Shown in "Operation Code" Column Symbol Meaning R 1-bit-wise data of code specifing reg1 or regID r 1-bit-wise data of code specifing reg2 d 1-bit-wise data of displacement i 1-bit-wise data of immediate cccc 4-bit data indicating condition code bbb 3-bit data specifing bit number Table 11-3. Symbols Shown in "Operation" Column Symbol Meaning Assignment GR [ ] General register SR [ ] System register zero-extend (n) Zero-extends "n" to word length sign-extend (n) Sign-extends "n" to word length load-memory (a, b) Reads data of size "b" from address "a" store-memory (a, b, c) Writes data "b" of size "c" to address "a" load-memomy-bit (a, b) Reads bit "b" of address "a" store-memory-bit (a, b, c) Writes "c" to bit "b" of address "a" saturated (n) Performs saturated processing of n (n is 2's complement) "n" indicates result of operation. If "n" 7FFFFFFFH, 7FFFFFFFH If "n" 80000000H 80000000H, 80000000H 80000000H result Reflects result on flag Byte Byte (8 bits) Halfword Halfword (16 bits) Word Word (32 bits) + Add ­ Subtract || Bit concatenation × Multiply ÷ Divide AND Logical product OR Logical sum XOR Exclusive logical sum NOT Logical left shift logically shift right by Logical right shift arithmetically shift right by 40 Logical negation logically shift left by Arithmetic right shift µPD703002 PD703002 Table 11-4. Symbols Shown in "Flag" Column Identifier Meaning (blank) Not affected 0 Cleared to 0 × Set or cleared according to result R Value once saved is restored Table 11-5. Condition Codes Condition Name (cond) V Condition Code (cccc) 0000 Conditional Expression Meaning OV = 1 Overflow NV 1000 OV = 0 No overflow C/L 0001 CY = 1 Carry Lower (Less than) NC/NL 1001 CY = 0 No carry Not lower (Greater than or equal) Z/E 0010 Z=1 Zero Equal NZ/NE 1010 Z=0 Not zero Not equal NH 0011 (CY OR Z) = 1 Not higher (Less than or equal) H 1011 (CY OR Z) = 0 Higher (Greater than) N 0100 S=1 Negative P 1100 S=0 Positive T 0101 ­ Always (unconditional) SA 1101 SAT = 1 Saturated LT 0110 (S XOR OV) = 1 Less than signed GE 1110 (S XOR OV) = 0 Greater than or equal signed LE 0111 (S XOR OV) OR Z) = 1 Less than or equal signed GT 1111 (S XOR OV) OR Z) = 0 Greater than signed 41 µPD703002 PD703002 Instruction Group Instruction Set List Flag Mnemonic Operand Operation Code Operation CY disp7[ep], reg2 rrrrr0110ddddddd SLD.H disp8[ep], reg2 rrrrr1000ddddddd rrrrr1010dddddd0 LD.B disp16[reg1], reg2 Z × × × × × × × × × × × × × × × × × × × × GR[reg2]sign-extend(Load-memory(adr, Byte) adrep+zero-extend(disp8) disp8[ep], reg2 S adrep+zero-extend(disp7) SLD.W Load/store SLD.B OV Note 2 GR[reg2]Load-memory(adr, Word) rrrrr111000RRRRR adrGR[reg1]+sign-extend(disp16) Note 1 GR[reg2]sign-extend(Load-memory(adr, Halfword) adrep+zero-extend(disp8) ddddddddddddddd GR[reg2]sign-extend(Load-memory(adr, Byte) LD.H disp16[reg1], reg2 LD.W disp16[reg1], reg2 rrrrr111001RRRRR adrGR[reg1]+sign-extend(disp16) ddddddddddddddd0 Note 3 GR[reg2]sign-extend(Load-memory(adr, Halfword) rrrrr111001RRRRR adrGR[reg1]+sign-extend(disp16) ddddddddddddddd1 Note 3 GR[reg2]Load-memory(adr, Word) SST.B reg2, disp7[ep] rrrrr0111ddddddd adrep+zero-extend(disp7) SST.H reg2, disp8[ep] rrrrr1001ddddddd Store-memory(adr, GR[reg2], Byte) adrep+zero-extend(disp8) SST.W reg2, disp8[ep] rrrrr1010dddddd1 ST.B reg2, disp16[reg1] Note 2 Store-memory(adr, GR[reg2], Word) rrrrr111010RRRRR adrGR[reg1]+sign-extend(disp16) Note 1 Store-memory(adr, GR[reg2], Halfword) adrep+zero-extend(disp8) dddddddddddddddd Store-memory(adr, GR[reg2], Byte) ST.H reg2, disp16[reg1] ST.W reg2, disp16[reg1] rrrrr111011RRRRR adrGR[reg1]+sign-extend(disp16) ddddddddddddddd0 Note 3 Store-memory(adr, GR[reg2], Halfword) rrrrr111011RRRRR adrGR[reg1]+sign-extend(disp16) ddddddddddddddd1 Note 3 Store-memory(adr, GR[reg2], Word) reg1, reg2 imm5, reg2 rrrrr000000RRRRR GR[reg2]GR[reg1] r r r r r 0 1 0 0 0 0 i i i i i GR[reg2]sign-extend(imm5) MOVHI imm16, reg1, reg2 rrrrr110010RRRRR GR[reg2]GR[reg1]+(imm16 || 0 ) iiiiiiiiiiiiiiii MOVEA Arithmetic MOV MOV imm16, reg1, reg2 rrrrr110001RRRRR GR[reg2]GR[reg1]+sign-extend(imm16) 16 iiiiiiiiiiiiiiii ADD ADD reg1, reg2 imm5, reg2 rrrrr001110RRRRR GR[reg2]GR[reg2]+GR[reg1] rrrrr010010RRRRR GR[reg2]GR[reg2]+sign-extend(imm5) ADDI imm16, reg1, reg2 rrrrr110000RRRRR GR[reg2]GR[reg1]+sign-extend(imm16) iiiiiiiiiiiiiii SUB reg1, reg2 rrrrr001101RRRRR GR[reg2]GR[reg2]­GR[reg1] SUBR reg1, reg2 rrrrr001100RRRRR GR[reg2]GR[reg1]­GR[reg2] Notes 1. ddddddd = the higher 7 bits of disp8 2. dddddd = the higher 6 bits of disp8 3. ddddddddddddddd = the higher 15 bits of disp16 42 SAT Instruction Group µPD703002 PD703002 Flag Mnemonic Operand Operation Code Operation CY OV S Z × × × × × × × × × SAT × × imm16, reg1, reg2 rrrrr110111RRRRR GR[reg2]GR[reg2]Note×imm16 iiiiiiiiiiiiiii reg1, reg2 (signed multiply) rrrrr000010RRRRR GR[reg2]GR[reg2]÷GR[reg1]Note(signed divide) CMP CMP reg1, reg2 imm5, reg2 rrrrr001111RRRRR resultGR[reg2]­GR[reg1] r r r r r 0 1 0 0 1 1 i i i i i resultGR[reg2]­sign-extend(imm5) SETF Arithmetic ×GR[reg1] (signed multiply) rrrrr000111RRRRR GR[reg2]GR[reg2] r r r r r 0 1 0 1 1 1 i i i i i GR[reg2]GR[reg2]Note×sign-extend(imm5) DIVH Saturation operation reg1, reg2 imm5, reg2 MULHI Logical operation MULH MULH cccc, reg2 rrrrr1111110cccc if conditions are satisfied 0000000000000000 then GR[reg2]00000001H 00000001H SATADD reg1, reg2 else GR[reg2]00000000H 00000000H rrrrr000110RRRRR GR[reg2]saturated(GR[reg2]+GR[reg1]) × × × × × SATADD SATSUB imm5, reg2 reg1, reg2 r r r r r 0 1 0 0 0 1 i i i i i GR[reg2]saturated(GR[reg2]+sign-extend(imm5) rrrrr000101RRRRR GR[reg2]saturated(GR[reg2]­GR[reg1]) × × × × × × × × × × SATSUBI imm16, reg1, reg2 rrrrr110011RRRRR GR[reg2]saturated(GR[reg1]­sign-extend(imm16) iiiiiiiiiiiiiiii × × × × × SATSUBR TST reg1, reg2 reg1, reg2 rrrrr000100RRRRR GR[reg2]saturated(GR[reg1]­GR[reg2]) rrrrr001011RRRRR resultGR[reg2]AND GR[reg1] × × 0 × × × × × OR ORI reg1, reg2 imm16, reg1, reg2 rrrrr001000RRRRR GR[reg2]GR[reg2]OR GR[reg1] rrrrr110100RRRRR GR[reg2]GR[reg1]OR zero-extend(imm16) 0 0 × × × × 0 0 × 0 × × 0 × × 0 × × Note Note (signed multiply) iiiiiiiiiiiiiiii AND ANDI reg1, reg2 imm16, reg1, reg2 rrrrr001010RRRRR GR[reg2]GR[reg2]AND GR[reg1] rrrrr110110RRRRR GR[reg2]GR[reg1]AND zero-extend(imm16) iiiiiiiiiiiiiiii XOR XORI reg1, reg2 imm16, reg1, reg2 rrrrr001001RRRRR GR[reg2]GR[reg2]XOR GR(reg1) rrrrr110101RRRRR GR[reg2]GR[reg1]XOR zero-extend(imm16) iiiiiiiiiiiiiiii NOT SHL reg1, reg2 reg1, reg2 rrrrr000001RRRRR GR[reg2]NOT(GR[reg1]) rrrrr111111RRRRR GR[reg2]GR[reg2]logically shift left by GR[reg1] 0 × × × 0 × × 0000000011000000 SHL imm5, reg2 r r r r r 0 1 0 1 1 0 i i i i i GR[reg2]GR[reg2]logically shift left by × 0 × × SHR reg1, reg2 zero-extend(imm5) rrrrr111111RRRRR GR[reg2]GR[reg2]logically shift right by GR[reg1] × 0 × × 0000000010000000 SHR imm5, reg2 r r r r r 0 1 0 1 0 0 i i i i i GR[reg2]GR[reg2]logically shift right by × 0 × × SAR reg1, reg2 zero-extend(imm5) rrrrr111111RRRRR GR[reg2]GR[reg2]arithmetically shift right by × 0 × × × 0 × × 0000000010100000 GR[reg1] SAR imm5, reg2 r r r r r 0 1 0 1 0 1 i i i i i GR[reg2]GR[reg2]arithmetically shift right by zero-extend(imm5) Note Only the lower halfword data is valid. 43 Branch Instruction Group µPD703002 PD703002 Flag Mnemonic Operand Operation Code Operation CY JMP JR [reg1] disp22 OV S Z 00000000011RRRRR 00000000011RRRRR PCGR[reg1] 0000011110dddddd PCPC+sign-extend(disp22) ddddddddddddddd0 Note 1 JARL disp22, reg2 Bcond disp9 SET1 bit#3, disp16[reg1] CLR1 bit#3, disp16[reg1] rrrrr11110dddddd GR[reg2]PC+4 ddddddddddddddd0 Note 1 PCPC+sign-extend(disp22) ddddd1011dddcccc if conditions are satisfied Bit manipulate Note 2 then PCPC+sign-extend(disp9) 00bbb111110RRRRR adrGR[reg1]+sign-extend(disp16) ddddddddddddddd Z flagNot(Load-memory-bit(adr, bit#3) Store-memory-bit(adr, bit#3, 1) 10bbb111110RRRRR adrGR[reg1]+sign-extend(disp16) × ddddddddddddddd Z flagNot(Load-memory-bit(adr, bit#3) Store-memory-bit(adr, bit#3, 0) NOT1 bit#3, disp16[reg1] TST1 bit#3, disp16[reg1] 01bbb111110RRRRR adrGR[reg1]+sign-extend(disp16) ddddddddddddddd Z flagNot(Load-memory-bit(adr, bit#3) Store-memory-bit(adr, bit#3, Z flag) 11bbb111110RRRRR adrGR[reg1]+sign-extend(disp16) ddddddddddddddd Z flagNot(Load-memory-bit(adr, bit#3) Notes 1. ddddddddddddddddddddd = the higher 21 bits of disp22 2. dddddddd = the higher 8 bits of disp9 44 × × × SAT Instruction Group µPD703002 PD703002 Flag Mnemonic Operand Operation CY LDSR reg2, regID STSR Special Operation Code regID, reg2 rrrrr111111RRRRR SR[regID]GR[reg2] 0000000000100000 regID = PSW S Z SAT × × × × × R R R R R reg ID = EIPC, FEPC reg ID = EIPSW, FEPSW Note rrrrr111111RRRRR GR[reg2]SR[regID] OV 0000000001000000 TRAP vector 0 0 0 0 0 1 1 1 1 1 1 i i i i i EIPCPC+4 (restore PC) 0000000100000000 EIPSWPSW ECR.EICCInterrupt code PSW.EP1 PSW.ID1 PC00000040H PC00000040H(vector=00H-0FH 00H-0FH) 00000050H 00000050H(vector=10H-1FH 10H-1FH) 0000011111100000 if PSW.EP=1 RETI 0000000101000000 then PCEIPC PSWEIPSW else if PSW.NP=1 then PCFEPC PSWFEPSW else PCEIPC PSWEIPSW HALT 0000011111100000 Stops 0000000100100000 DI 0000011111100000 PSW.ID1 0000000101100000 (disables maskable interrupt) 1000011111100000 PSW.ID0 EI 0000000101100000 (enables maskable interrupt) NOP 0000000000000000 Dissipates 1 clock cycle without doing anything Note This instruction uses source register reg2, but its op code actually uses the field of reg1. Therefore, the meanings of the mnemonic description and op code of this instruction are different from those of the others. rrrrr = regID specification, RRRRR = reg2 specification 45 µPD703002 PD703002 12. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (TA = 25°C) Parameter Supply voltage Symbol Condition Ratings Unit VDD VDD pin ­0.5 to +7.0 V CVDD CVDD pin ­0.5 to +7.0 V CVSS CVSS pin ­0.5 to +0.5 V VI1 Except X1 pin, VDD = 5.0 V ±10% ­0.5 to VDD + 0.3 V Clock input voltage VX X1 pin, VDD = 5.0 ±10% ­0.5 to VDD + 1.0 V Output current, low IOL 1 pin 4.0 mA Total of all pins 100 mA 1 pin ­4.0 mA Total of all pins ­100 mA ­0.5 to VDD + 0.3 V Input voltage Output current, high IOH VDD = 5.0 V ±10% Output voltage VO Operating ambient temperature TA ­40 to +85 °C Storage temperature Tstg ­65 to +150 °C Cautions 1. Do not directly connect the output (or I/O) pins of IC products, and do not directly connect them to VDD, VCC or GND pin. Open-drain pins and open-collector pins may be directly connected to one another however. Moreover, an external circuit that is designed to prevent contention of output can be connected to pins that go into a high-impedance state. 2. Should the absolute maximum rating of even one of the above parameters be exceeded even momentarily, the quality of the product may be degraded. The absolute maximum ratings are, therefore, the values exceeding which the product may be physically damaged. Never exceed or approximate these values when using the product. The normal operating ranges of ratings and conditions in which the quality of the product is guaranteed are specified in the following DC Characteristics and AC Characteristics. Capacitance (TA = 25°C, VDD = VSS = 0 V) Parameter Symbol Condition MIN. TYP. MAX. Unit Input capacitance CI fC = 1 MHz 15 pF I/O capacitance CIO Unmeasured pins returned to 0 V. 15 pF Output capacitance CO 15 pF Operating Conditions Operation Mode Direct mode PLL mode 46 Internal Operating Clock Frequency () Operating Ambient Temperature (TA) 0 to 25 MHz Freerunning oscillation frequency to 25 MHz Supply Voltage (VDD) ­40 to +85°C 5.0 V ±10% ­40 to +85°C 5.0 V ±10% µPD703002 PD703002 Recommended Oscillation Circuit (a) Connecting ceramic resonator (T A = ­20 to +70 °C) (i) Manufacturer: Kyocera, TDK X1 X2 Rd C1 C2 Oscillation Frequency fXX (MHz) C1 (pF) C2 (pF) Rd () Through-hole KBR-2.0MS type KBR-2.7MS 2.0 100 100 820 4.5 5.5 0.80 2.7 100 100 820 4.5 5.5 0.60 KBR-3.2MS Manufacturer Kyocera Corp. Part Number Recommended Circuit Constant Oscillation Voltage Oscillation Range Stabilization Time MIN. (V) MAX. (V) (MAX.) TOST (ms) TDK Corp. 3.2 82 82 0 4.5 5.5 0.40 Surface-mount PBRC5.0A type PBRC5.0B 5.0 33 33 680 4.5 5.5 0.20 5.0 Incorporated Incorporated 680 4.5 5.5 0.20 CCR2.0MC33 0MC33 2.0 Incorporated Incorporated 10K 4.5 5.5 0.56 CCR3.2MC3 3.2 Incorporated Incorporated 3.3K 4.5 5.5 0.40 CCR5.0MC3 5.0 Incorporated Incorporated 680 4.5 5.5 0.38 FCR5.0MC5 5.0 Incorporated Incorporated 0 4.5 5.5 0.28 CCR10 CCR10.0MC5 10.0 Incorporated Incorporated 0 4.5 5.5 0.12 CCR16 CCR16.0MC6 16.0 Incorporated Incorporated 2.2K 4.5 5.5 0.34 FCR25 FCR25.0MCG 25.0 Incorporated Incorporated 0 4.5 5.5 0.24 Cautions 1. 2. Connect the oscillation circuit as closely to the X1 and X2 pins as possible. Do not wire any other signal lines in the area indicated by the broken line in the above figure. 3. Thoroughly evaluate the matching between the µPD703002 PD703002 and oscillator. 47 µPD703002 PD703002 (ii) Manufacturer: Murata Mfg. X1 X2 C1 Manufacturer Part Number Murata Mfg. CST2.00MG040 00MG040 Oscillation Frequency fXX (MHz) C2 Recommended Circuit Constant Oscillation Voltage Oscillation Stabilization Range Time (MAX.) MIN. (V) MAX. (V) TOST (ms) C2 (pF) Incorporated 2.0 C1 (pF) Incorporated 4.5 5.5 0.48 CSA2.00MG040 00MG040 2.0 100 100 4.5 5.5 0.48 CST2.70MGW040 70MGW040 2.7 Incorporated Incorporated 4.5 5.5 0.47 CSA2.70MG040 70MG040 2.7 100 100 4.5 5.5 0.47 CST3.20MGW040 20MGW040 3.2 Incorporated Incorporated 4.5 5.5 0.44 CSA2.20MG040 20MG040 3.2 100 100 4.5 5.5 0.44 CST5.00MGW040 00MGW040 5.0 Incorporated Incorporated 4.5 5.5 0.41 CSA5.00MG040 00MG040 5.0 100 100 4.5 5.5 0.41 Cautions 1. 2. Connect the oscillation circuit as closely to the X1 and X2 pins as possible. Do not wire any other signal lines in the area indicated by the broken line in the above figure. 3. Thoroughly evaluate the matching between the µPD703002 PD703002 and oscillator. (b) External clock input X1 X2 Open External clock Caution Input the voltage at the CMOS level to the X1 pin. 48 µPD703002 PD703002 DC Characteristics (TA = ­40 to +85°C, VDD = 5.0 V ±10%, VSS = 0 V) Parameter Input voltage, high Symbol VIH Condition X1, except Note 1 MIN. TYP. MAX. Unit 2.2 VDD V 0.8VDD VDD V X1, except Note 1 0 0.8 V Note 1 0 0.2VDD V Direct mode 0.8VDD VDD V PLL mode 0.8VDD VDD V Direct mode 0 0.6 V PLL mode 0 0.6 V Note 1 Input voltage, low VIL X1 clock input voltage, high VXH X1 clock input voltage, low VXL Schmitt trigger input threshold voltage VT+ Schmitt trigger input VT Note 1 Rising + VT ­VT ­ V Note 1 Falling ­ 3.0 2.0 V Note 1 0.5 V IOH = ­2.5 mA 0.7VDD V IOH = ­100 µA VDD ­ 0.4 V hysteresis width Output voltage, high VOH Output voltage, low VOL IOL = 2.5 mA 0.45 V Input leakage current, high ILIH Input leakage current, low ILIL VI = VDD 10 µA VI = 0 V ­10 µA Output leakage current, high ILOH VO = VDD 10 µA Output leakage current, low ILOL VO = 0V Supply current IDD1 Direct mode 1.5 × +6 2.2 × +10 mA PLL mode (fXX = /5) 1.6 × +7 2.4 × +11 mA PLL mode (fXX = ) 1.9 × +9 3.0 × +15 mA Direct mode 0.5 × +4 0.8 × +10 mA PLL mode (fXX = /5) 0.6 × +5 1.0 × +11 mA PLL mode (fXX = ) 0.9 × +7 1.6 × +15 mA Direct mode 15 × +200 26 × +200 µA PLL mode (fXX = /5) 0.1 × +0.2 0.2 × +0.2 mA Operating HALT IDLE IDD2 IDD3 ­10 µA PLL mode (fXX = ) STOP IDD4 0.4 × +3 0.8 × +5 mA ­40°C T A +50°C 1 50 µA 200 µA 50°C < TA 85°C Note RESET, P02/TCLR1 P02/TCLR1, P03/TI1 P03/TI1, P04/INTP10 P04/INTP10 through P07/INTP13 P07/INTP13, P20/NMI P20/NMI, P21/INTP00 P21/INTP00 through P24/ INTP03 INTP03, P26/SI2 P26/SI2, P27/SCK2 P27/SCK2, P31/SI0 P31/SI0, P32/SCK0 P32/SCK0, P36/SI1 P36/SI1, P37/SCK1 P37/SCK1, MODE0, MODE1, CKSEL Remarks 1. 2. TYP. value is a value for reference at TA = 25°C, VDD = 5.0 V. : internal operating clock frequency 49 µPD703002 PD703002 Data Retention Characteristics (TA = ­40 to +85°C) Parameter Symbol Condition MIN. TYP. MAX. Data hold voltage VDDDR STOP mode 5.5 V Data hold current IDDDR VDD = VDDDR, ­40°C T A +50°C 0.2VDDDR 50 µA VDD = VDDDR, 50°C < T A +85°C 0.2VDDDR 200 µA Supply voltage rise time 1.5 Unit tRVD µs 200 Supply voltage fall time tFVD 200 µs Supply voltage hold time (from STOP mode setting) tHVD 0 ms STOP mode releasing signal input time tDREL 0 ns Data hold input voltage, high VIHDR Note 0.9VDDDR V DDDR V Data hold input voltage, low VILDR Note 0 0.1VDDDR V Note RESET, P02/TCLR1 P02/TCLR1, P03/TI1 P03/TI1, P04/INTP10 P04/INTP10 through P07/INTP13 P07/INTP13, P20/NMI P20/NMI, P21/INTP00 P21/INTP00 through P24/ INTP03 INTP03, P26/SI2 P26/SI2, P27/SCK2 P27/SCK2, P31/SI0 P31/SI0, P32/SCK0 P32/SCK0, P36/SI1 P36/SI1, P37/SCK1 P37/SCK1, MODE0, MODE1, CKSEL, X1 Remark TYP. value is a value for reference at TA = 25°C, VDD = 5.0 V. STOP mode set VDD VDD VDD VDDDR tHVD RESET (input) NMI (input) (released by falling edge) tFVD tRVD VIHDR VIHDR NMI (input) (released by rising edge) VILDR 50 tDREL µPD703002 PD703002 AC Characteristics (TA = ­40 to +85°C, VDD = 5.0 V ±10%, VSS = 0 V, CL (output pin load capacitance) = 50 pF) AC test input wave (a) RESET, P02/TCLR1 P02/TCLR1, P03/TI1 P03/TI1, P04/INTP10 P04/INTP10 through P07/INTP13 P07/INTP13, P20/NMI P20/NMI, P21/INTP00 P21/INTP00 through P24/INTP03 P24/INTP03, P26/SI2 P26/SI2, P27/SCK2 P27/SCK2, P31/SI0 P31/SI0, P32/SCK0 P32/SCK0, P36/SI1 P36/SI1, P37/SCK1 P37/SCK1, MODE0, MODE1, CKSEL, X1 VDD 0.8VDD 0.8VDD Test points 0V 0.2VDD 0.2VDD (b) Other than (a) above 2.4 V 2.2 V 2.2 V Test points 0.4 V 0.8 V 0.8 V AC test output test point 2.2 V 2.2 V Test points 0.8 V 0.8 V Load condition DUT (tested device) CL = 50 pF Caution If the load capacitance exceeds 50 pF due to the configuration of the circuit, keep the load capacitance of this device to within 50 pF by using a buffer. 51 µPD703002 PD703002 (1) Clock timing Parameter Symbol X1 input cycle MIN. Unit tWXH 20 DC ns 200 285 ns PLL mode (fXX = ) Direct mode MAX. PLL mode (fXX = /5) X1 input high-level width tCYX Conditions 40 100 ns Direct mode 7 ns PLL mode (fXX = /5) X1 input low-level width tWXL 80 ns PLL mode (fXX = ) 10 ns Direct mode 7 ns PLL mode (fXX = /5) X1 input rise time ns 10 ns ns 15 ns 7 ns Direct mode 7 ns PLL mode (fXX = /5) tXF 7 PLL mode (fXX = ) Direct mode PLL mode (fXX = /5) X1 input fall time tXR 80 PLL mode (fXX = ) 15 ns PLL mode (fXX = ) CPU operating frequency 7 ns ­ 0 25 MHz DC ns CLKOUT output cycle tCYK 40 CLKOUT high-level width tWKH 0.5T­10 ns CLKOUT low-level width tWKL 0.5T­10 ns CLKOUT rise time tKR 5 ns CLKOUT fall time tKF 5 ns 17 ns X1 CLKOUT delay time tDXK Direct mode 3 Remark T = tCYK Parameter Symbol Freerunning oscillation ­ P Condition TYP. 0.6 PLL mode frequency X1 (input) (PLL mode) X1 (input) (direct mode) CLKOUT (output) 52 Unit MHz µPD703002 PD703002 (2) Input wave (a) RESET, P02/TCLR1 P02/TCLR1, P03/TI1 P03/TI1, P04/INTP10 P04/INTP10 through P07/INTP13 P07/INTP13, P20/NMI P20/NMI, P21/INTP00 P21/INTP00 through P24/INTP03 P24/INTP03, P26/SI2 P26/SI2, P27/SCK2 P27/SCK2, P31/SI0 P31/SI0, P32/SCK0 P32/SCK0, P36/SI1 P36/SI1, P37/SCK1 P37/SCK1, MODE0, MODE1, CKSEL, X1 Parameter Symbol Condition MIN. MAX. Unit Input rise time tIR2 20 ns Input fall time tIF2 20 ns VDD 0.8VDD 0.8VDD Input signal 0.2VDD 0V 0.2VDD (b) Other than (a) above Parameter Symbol Condition MIN. MAX. Unit Input rise time tIR1 10 ns Input fall time tIF1 10 ns 2.4 V 2.2 V 2.2 V Input signal 0.4 V 0.8 V 0.8 V 53 µPD703002 PD703002 (3) Output waveform (other than CLKOUT) Parameter Symbol Condition MIN. MAX. Unit Output rise time tOR 10 ns Output fall time tOF 10 ns MAX. Unit 2.2 V 2.2 V Output signal 0.8 V 0.8 V (4) Reset timing Parameter Symbol RESET high-level width tWRSL MIN. tWRSH RESET low-level width Condition 500 ns On power application and on releasing STOP mode 500+TOST ns Except on power application and on releasing STOP mode 500 ns Remark TOST: Oscillation Stabilization Time RESET (input) 54 µPD703002 PD703002 [MEMO] 55 µPD703002 PD703002 (5) Read timing (1/2) Parameter Symbol Condition MIN. MAX. Unit CLKOUT Address delay time t DKA 3 20 ns CLKOUT Address float time t FKA 3 15 ns CLKOUT ASTB delay time t DKST 3 15 ns CLKOUT DSTB delay time t DKD 3 15 ns CLKOUT Status delay time t DKS 3 15 ns Data input setup time (to CLKOUT ) t SIDK 5 ns Data input hold time (from CLKOUT ) t HKID 5 ns WAIT setup time (to CLKOUT ) t SWTK 5 ns WAIT hold time (from CLKOUT ) t HKWT 5 ns Address hold time (from CLKOUT ) t HKA 0 ns Address setup time (to ASTB ) t SAST 0.5T­10 ns Address hold time (from ASTB ) t HSTA 0.5T­10 ns DSTB Address float delay time t FDA 0 ns Data input setup time (to address) t SAID (2+n)T­20 ns Data input setup time (to DSTB ) t SDID (1+n)T­20 ns ASTB DSTB delay time t DSTD 0.5T­10 ns Data input hold time (from DSTB ) t HDID 0 ns DSTB Address output delay time t DDA (1+i)T ns DSTB ASTB delay time t DDSTH 0.5T­10 ns DSTB ASTB delay time t DDSTL (1.5+i)T­10 ns Status setup time (to ASTB ) t SSST 0.5T­10 ns Status hold time (from ASTB ) t HSTS 0.5T­10 ns DSTB low-level width t WDL (1+n)T­10 ns ASTB high-level width t WSTH T­10 ns WAIT setup time (to address) t SAWT1 WAIT hold time (from address) t HAWT1 t HAWT2 WAIT setup time (to ASTB ) t SSTWT1 t SSTWT2 t HSTWT1 n1 t SAWT2 t HSTWT2 WAIT hold time (from ASTB ) Remarks 1. 2. n1 1.5T­20 ns (0.5+n)T ns (1.5+n)T n1 ns T­15 n1 ns (1+n)T­15 ns nT ns (1+n)T ns T = tCYK n indicates the number of wait clocks inserted in a bus cycle. The sampling timing varies when programmable wait states are inserted. 3. i indicates the number of idle states (0 or 1) inserted in the read cycle. 4. 56 ns (1.5+n)T­20 Satisfy at least one of the data input hold times tHKID () and tHDID (). µPD703002 PD703002 (5) Read timing (2/2): 1 wait T1 T2 TW T3 CLKOUT (output) A16 to A23 (output) Note AD0 to AD15 (I/O) A0 to A15 (output) D0 to D15 (input) ASTB (output) DSTB (output) ST0, ST1 (output) WAIT (input) Note R/W (output), UBEN (output), LBEN (output) Remark The broken line indicates the high-impedance state. 57 µPD703002 PD703002 (6) Write timing (1/2) Parameter Symbol Condition MIN. MAX. Unit CLKOUT Address delay time t DKA 3 20 ns CLKOUT ASTB delay time t DKST 3 15 ns CLKOUT DSTB delay time t DKD 3 15 ns CLKOUT Status delay time t DKS 3 15 ns WAIT setup time (to CLKOUT ) t SWTK 5 ns WAIT hold time (from CLKOUT ) t HKWT 5 ns Address hold time (from CLKOUT ) t HKA 0 ns Address setup time (to ASTB ) t SAST 0.5T­10 ns Address hold time (from ASTB ) t HSTA 0.5T­10 ns ASTB DSTB delay time t DSTD 0.5T­10 ns DSTB ASTB delay time t DDSTH 0.5T­10 ns Status setup time (to ASTB ) t SSST 0.5T­10 ns Status hold time (from ASTB ) t HSTS 0.5T­10 ns DSTB low-level width t WDL (1+n)T­10 ns ASTB high-level width t WSTH WAIT setup time (to address) t SAWT1 t SAWT2 WAIT hold time (from address) T­10 n1 ns ns (1.5+n)T­20 n1 1.5T­20 ns t HAWT1 t HAWT2 t SSTWT1 t SSTWT2 t HSTWT1 t HSTWT2 CLKOUT Data output delay time t DKOD 20 ns DSTB Data output delay time t DDOD 10 ns WAIT setup time (to ASTB ) WAIT hold time (from ASTB ) (0.5+n)T ns (1.5+n)T ns n1 ns (1+n)T­15 n1 T­15 ns nT ns (1+n)T ns Data output hold time (from CLKOUT ) t HKOD 0 ns Data output setup time (to DSTB ) t SODD (1+n)T­15 ns Data output hold time (from DSTB ) t HDOD T­10 ns Remarks 1. 2. T = tCYK n indicates the number of wait clocks inserted in a bus cycle. The sampling timing varies when programmable wait states are inserted. 58 µPD703002 PD703002 (6) Write timing (2/2): 1 wait T1 T2 TW T3 CLKOUT (output)