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Part : PCI9060-3A Supplier : PLX Technology Manufacturer : Bristol Electronics Stock : 4 Best Price : - Price Each : -
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PCI9060 Datasheet

Part Manufacturer Description PDF Type
PCI9060 N/A 12O COMPATIBLE PCI BUS MASTER INTERFACE CHIP FOR ADAPTERS AND EMBEDDED SYSTEMS Original
PCI9060 PLX Technology PCI Bus Master Interface Chip for Adapters and Embedded Systems Original
PCI9060 PLX Technology PCI Bus Master Interface Chip for Adapters and Embedded Systems Original
PCI9060ES N/A 12O COMPATIBLE PCI BUS MASTER INTERFACE CHIP FOR ADAPTERS AND EMBEDDED SYSTEMS Original
PCI9060ES PLX Technology PCI Bus Master Interface Chip for Adapters and Embedded Systems Original
PCI9060ES PLX Technology PCI Bus Master Interface Chip for Adapters and Embedded Systems Original
PCI9060ES PLX Technology PCI Bus Master Interface Chip for Adapters and Embedded Systems Scan
PCI9060SD N/A 12O COMPATIBLE PCI BUS MASTER INTERFACE CHIP FOR ADAPTERS AND EMBEDDED SYSTEMS Original
PCI9060SD PLX Technology PCI bus master interface chip Original
PCI9060SD PLX Technology PCI Bus Master Interface Chip Original
PCI9060SD PLX Technology PCI Bus Master Interface Chip for Master and Slave Adapters Scan
PCI9060SD PLX Technology PCI Bus Master Interface Chip for Master and Slave Adapters Scan

PCI9060

Catalog Datasheet MFG & Type PDF Document Tags

93CS56

Abstract: I960CX to PCI bus transfers. 2.1.2.1 DMA Master Command Codes The PCI9060's DMA controllers can generate , PCI bus master or the PCI9060's DMA controller are written. An access to an 8 or 16 bit bus results , the data parity pins do not effect operation of the PCI9060. PCI bus parity checking and generation , the base address specified in the PCI9060's PCI Base Address for Memory Mapped Runtime Register or an I/O cycle with the PCI bus address matching the base address specified in the PCI9060's PCI Base
PLX Technology
Original
93CS56 I960CX NM93CS06 NM93CS46 I960JX 10B5 A31-29

93CS46

Abstract: 10B5 returned to the PCI9060. The first word of data is read from the static ram and returned to the PCI9060. , devices on the PCI bus using the direct master feature of the PCI9060. First the 68040 must arbitrate for , transitions to state C0 where ADS~ is asserted to the PCI9060. If the 68040 is accessing the PCI9060 local , bits 0-31 of the 68040 are connected directly to data bits 0-31 of the local bus, SRAM, and PCI9060. , PCI9060/68040 AN July 1995 PCI9060/68040 Application Note VERSION 1.0
PLX Technology
Original
93CS46 0x00000018 E 32.0000 C c code for pci master PCI9060/68040

i486 DX2

Abstract: SiS chipset cards were tried behind DEC 2.1 P2P bridge. PCI9060 (EB) and PCI9060ES (EB) passed the PCI SIG discard , ) PCI9060 (EB) was configured. DS, DM, and DMA transactions were performed. 2) PCI9060ES (EB) was , -AB bridge. PCI9060 (EB) and PCI9060ES (EB) passed the card test and performed DS, DM, and DMA (Rev3 only , . PCI9060 (EB) and PCI9060ES (EB) passed the card test and performed DS, DM, DMA (Rev3 only , Compatibility Test Report April 1996 Two evaluation boards with an I960 and PCI9060 Rev. 3, and another
PLX Technology
Original
9060ES 21052-AB 440FX 430HX i486 DX2 SiS chipset 430FX intel pentium p5 micro i486 dx2 133MH 100MH 200MH

16V8H-15

Abstract: 20-2136J PLX TECHNOLOGY PCI9060 Demo Board I/O MAP 06/16/96 PCI Configuration Registers Address , - PLX TECHNOLOGY PCI9060 Demo Board 0x00000010 0-31 0 1 1-2 I/O MAP 06/16/96 3 , Reserved 0x00000038 0-31 Reserved - 2 - PLX TECHNOLOGY PCI9060 Demo Board 0x0000003C , sequentially in the EEPROM. Therefore, a 256-bit device can be used. - 3 - PLX TECHNOLOGY PCI9060 Demo , power of 2 (Default size = 1 Mbyte) - 4 - PLX Technology PCI9060 DEMO List of Materials 06
PLX Technology
Original
16V8H-15 20-2136J U0401 PT3877 R0801 20V8H-7 00000009-B 0000000A 0000000B MCON8-12 MCON13-15

small endian

Abstract: 9060ES of the PCI9060ES. PCI bus parity checking and generation is independent of local bus parity checking , both a PCI bus Master and Target General Description _ The PCI9060ES provides a , . The PCI9060ES allows the i960® processors and other intelligent controllers to perform direct bus master transfers on the PCI bus. The PCI9060ES also enables the local processor to configure other PCI devices in the system, an important feature for embedded systems. The PCI9060ES supports both memory
PLX Technology
Original
small endian AD-1508
Abstract: bus writes, only the bytes specified by a PCI bus master or the PCI9060's DMA controller are written , is optional. The signals on the data parity pins do not effect operation of the PCI9060. PCI bus , SECTION 2 BUS OPERATION 2. SECTION 2 - BUS OPERATION 2.1 PCI BUS CYCLES The PCI9060 is PCI Compliant. 2.1.1 PCI Target Command Codes As a target, the PCI9060 allows access to the PCI9060 internal , the PCI9060 can be byte, word or long word accesses. All memory commands are aliased to the basic -
OCR Scan
80960C
Abstract: SECTION 1 GENERAL DESCRIPTION 1. SECTION 1 - PCI 9060 GENERAL DESCRIPTION The PCI9060 is a , , multiplexed 80960 processor Cx, Hx Jx, Kx Sx The PCI9060 bus interface chip offers substantial performance , transfer large amounts of data to and from the adapter. The PCI9060 provides two independent bi-directional , . Using the PLX PCI9060 bus master chip also reduces total hardware and software development costs for disk controller, communication adapter and embedded system designs. The PCI9060 provides a single chip -
OCR Scan
Abstract: PCI9060. Ground pins. Table 61 EEPROM Interface Pin Description Twal'Tifrtrt Number : ftii* SiMai;-.' , byte lanes on the local bus. Parity is checked for writes to the PCI9060 or reads by the PCI9060. Parity is generated for reads from the PCI9060 or writes by the PCI9060. When a channel is programmed , the bottom. Parity is checked for writes to the PCI9060 or reads by the PCI9060. Parity is checked for , tables describe the PCI9060 pins. The pins in the following tables are common to all three local bus -
OCR Scan
Abstract: bytes specified by a PCI bus master or the PCI9060â'™s DMA controller are written. An access to an 8 or , parity is optional. The signals on the data parity pins do not effect operation of the PCI9060. PCI bus , in the PCI9060â'™s PCI Base Address for Memory Mapped Runtime Register or an I/O cycle with the PCI bus address matching the base address specified in the PCI9060â'™s PCI Base Address for I/O Mapped , /from PCI host bus data transfers The PCI9060 provides a compact high performance PCI bus master -
OCR Scan
00Q07

68040* part numbering

Abstract: 93CS46 , SRRDY~ is asserted in S0, causing READYI~ to be returned to the PCI9060. The first word of data is read from the static ram and returned to the PCI9060. During state S0, SRINC is true which allows the , direct master feature of the PCI9060. First the 68040 must arbitrate for the local bus by asserting BR~. , ~ is asserted to the PCI9060. If the 68040 is accessing the PCI9060 local configuration registers , bits 0-31 of the 68040 are connected directly to data bits 0-31 of the local bus, SRAM, and PCI9060.
PLX Technology
Original
68040* part numbering SR96 L16 eeprom Motorola 68040 Pal programming BCLK-30

10B5

Abstract: 93CS46 returned to the PCI9060. The first word of data is read from the static ram and returned to the PCI9060. , devices on the PCI bus using the direct master feature of the PCI9060. First the 68040 must arbitrate for , transitions to state C0 where ADS~ is asserted to the PCI9060. If the 68040 is accessing the PCI9060 local , bits 0-31 of the 68040 are connected directly to data bits 0-31 of the local bus, SRAM, and PCI9060. , local bus priority to the PCI9060. "If the 68040 wants the bus, it waits until the PCI9060 "negates
PLX Technology
Original

10B5

Abstract: 9060ES of the PCI9060ES. PCI bus parity checking and generation is independent of local bus parity checking , specified in the PCI9060ES's PCI Base Address for Memory Mapped Runtime Register or an I/O cycle with the PCI bus address matching the base address specified in the PCI9060ES's PCI Base Address for I/O , both a PCI bus Master and Target General Description _ The PCI9060ES provides a , . The PCI9060ES allows the i960® processors and other intelligent controllers to perform direct bus
PLX Technology
Original

PC19060

Abstract: EI96 SECTION 8 TIMING DIAGRAMS 8. SECTION 8- TIMING DIAGRAMS The PCI9060 operates in three modes , . 78 Timing Diagram 2. PCI9060 Local bus Arbitration , #.79 Timing Diagram 5. (CX Mode) Local Bus Write to PCI9060 Configuration Register. 80 Timing Diagram 6. (CX Mode) Local Bus Read from PCI9060 Configuration Register , .86 Timing Diagram 13. (CX Mode) PCI9060 DMA or Direct Slave Burst Write, Bterm Enabled
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OCR Scan
PC19060 EI96

I960 hx

Abstract: 10B5 to PCI bus transfers. 2.1.2.1 DMA Master Command Codes The PCI9060's DMA controllers can generate , PCI bus master or the PCI9060's DMA controller are written. An access to an 8 or 16 bit bus results , the data parity pins do not effect operation of the PCI9060. PCI bus parity checking and generation , the base address specified in the PCI9060's PCI Base Address for Memory Mapped Runtime Register or an I/O cycle with the PCI bus address matching the base address specified in the PCI9060's PCI Base
PLX Technology
Original
I960 hx 93C06

LA3101

Abstract: PC19060 specified by a PCI bus master or the PCI9060's DMA controller are written. An access to an 8 or 16 bit bus , parity pins do not effect operation of the PCI9060. PCI bus parity checking and generation is independent , the PCI bus address matching the base address specified in the PCI9060's PCI Base Address for Memory , the PCI9060's PCI Base Address for I/O Mapped Runtime Register. All PCI read or write accesses to the , Package General Description_ The PCI9060 provides a compact high performance PCI bus master interface
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OCR Scan
LA3101 Igus LD-310 LDL8 pci9080 LAJ31 Q0007 0Q007 PCI90S0

I960JX

Abstract: I960 hx to PCI bus transfers. 2.1.2.1 DMA Master Command Codes The PCI9060's DMA controllers can generate , PCI bus master or the PCI9060's DMA controller are written. An access to an 8 or 16 bit bus results , the data parity pins do not effect operation of the PCI9060. PCI bus parity checking and generation , The PCI9060 provides a compact high performance PCI bus master interface for adapter boards and , . The PCI9060 provides two independent bi-directional DMA channels with bi-directional FIFOs supporting
PLX Technology
Original
eeprom 1011

Asus P5

Abstract: 430FX PCI9060 Rev. 3, and another with an I960 and PCI9060ES were checked on different systems. The test , performed. 3) Both cards were tried behind DEC 2.1 P2P bridge. PCI9060 (EB) and PCI9060ES (EB) passed the , Passed 1) PCI9060 (EB) was configured. DS, DM, and DMA transactions were performed. 2) PCI9060ES (EB , 21052-AB bridge. PCI9060 (EB) and PCI9060ES (EB) passed the card test and performed DS, DM, and DMA , Intel P2P Moon Bridge. PCI9060 (EB) and PCI9060ES (EB) passed the card test and performed DS, DM, DMA
PLX Technology
Original
Asus P5 magma pxb-7 X451 HP Vectra INTEL I486 DX2 TRITON HX 166MH
Abstract: DMA Master Command Codes The PCI9060's DMA controllers can generate the following memory cycles , PCI bus master or the PCI9060's DMA controller are written. An access to an 8 or 16 bit bus results in , not effect operation of the PCI9060. PCI bus parity checking and generation is independent of local , PCI9060's PCI Base Address for Memory Mapped Runtime Register or an I/O cycle with the PCI bus address matching the base address specified in the PCI9060's PCI Base Address for I/O Mapped Runtime Register PLX Technology
Original
9060-SIL-ER-P0-1

doorbell application

Abstract: PCI9060's PCI Base Address for Memory Mapped Runtime Register or an I/O cycle with the PCI bus address matching the base address specified in the PCI9060's PCI Base Address for I/O Mapped Runtime Register , the appropriate application specific action. It can then clear the abort bits in the PCI9060's PCI , applies only to direct ("pass through") master and slave accesses through the PCI9060. Deadlock will not , request that the external arbiter not grant the bus to any local bus master except the PCI9060. A status
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OCR Scan
doorbell application

16V8H-15

Abstract: 20-2136J PLX Technology PCI9060 DEMO List of Materials 06/16/96 Description Qty Vendor Vendor Part Reference Designator PCB,PCI9060 DEMO,Rev A IC,PCI9060,PQFP IC,80960CA,33 MHz,PQFP IC,82596CA,33 MHz,PFQP IC,82C503,PLCC IC,16550A,PLCC IC,Static Ram, 32Kx8, 15 nsec, 28 Pin 300 Mil SOJ IC,Flash EPROM,256Kx8,90 nsec,DIP IC,EEPROM,256 Bit Serial,DIP 1 1 1 1 1 1 4 1 1 , J1001 DS0702 DS0301,0601,0701 RP1110,1111 RP1101-1109 -1- PLX Technology PCI9060 DEMO
PLX Technology
Original
U0602 MSL-260-G-H PT3868 res 10k sip 16V8H-15 pc IC 4020 pulse TRANSFORMER valor res 0402 NS16550AV IS61C256AH-15J D28F020-90P1C4 NM93CS06N U0201 U0301

pci9080

Abstract: PQ-32/9060 68040 with the PCI 9060 (Schematics etc.) PCI9060/68040 AN July 1995 PCI9060/68040 Application , Features_ · · · · · · · · PCI9060 bridge between Primary PCI Bus and , application note describes a simple design consisting of a PCI9060, 68040, and static RAM. The PCI9060 can , ram using direct slave cycles. PCI9060 Direct Slave to Static RAM Local Bus Arbiter with back-off capability 93CS46 68040 PCI BUS PCI9060 SRAM LOCAL BUS Figure 1. PCI to 68040 Application
PLX Technology
Original
PQ-32/9060 47k ohm resistor 9060SD 93C46

PQ-32/9060

Abstract: 9060SD 11/01/95 0.9 1/5/96 1.0 Comment Initial draft from PCI9060 Rev 0.9. 1. DEN# is an I/O , , the PCI9060 allows access to the PCI9060 internal registers and PCI bus. In the Cx and Jx modes, local bus slave accesses to the PCI9060 must be for a 32 bit non-pipelined bus. In the Sx mode, local bus slave accesses to the PCI9060 must be for a 16 bit non-pipelined bus. The PCI9060 READYo , enabled, the PCI9060 emulates the i960®Sx, i960®Jx or i960®Cx mode of bursting with the exception of the
PLX Technology
Original

doorbell application

Abstract: doorbell circuit application SECTION 2 BUS OPERATION 2. SECTION 2 - BUS OPERATION 2.1 PCI BUS CYCLES The PCI9060 is PCI Compliant. 2.1.1 PCI Target Command Codes As a target, the PCI9060 allows access to the PCI9060 internal , the PCI9060 can be byte, word or long word accesses. All memory commands are aliased to the basic memory commands. All I/O accesses to the PCI9060 are decoded to a long word boundary. The byte enables , combinations is terminated with a Target Abort. 2.1.2 PCI Master Command Codes The PCI9060 can access
Intel
Original
doorbell circuit application intel i960 series doorbell PCI I/O Intel i960 208-P
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