PCI32 XCS20XL TQ144 XCS30XL PQ208 PQ240 XCS40XL X7954 XCS30 XCS40 X7951 - Datasheet Archive

 

0 0 PCI32 SpartanXL Master & Slave Interface March, 1999 Data Sheet R LogiCORETM Facts Core Specifics Xilinx Inc. 2100 Logic

 

2 0 0 PCI32 PCI32 SpartanXL Master & Slave Interface March, 1999 Data Sheet R LogiCORETM Facts Core Specifics Xilinx Inc. 2100 Logic Drive San Jose, CA 95124 Phone: +1 408-559-7778 Fax: +1 408-377-3259 E-mail: Techsupport: hotline@xilinx.com Feedback: logicore@xilinx.com URL: http://www.xilinx.com/pci Introduction With Xilinx LogiCORE PCI32 PCI32 SpartanXL Master & Slave Interface, a designer can build a cost-efficient, customizable, zero wait-state, 32-bit, 33MHz fully PCI compliant system in a SpartanXL family FPGA. Features · · · · · · · · Fully PCI V 2.2 compliant 32-bit, 33MHz Interface - Master (Initiator/Target) Incorporates Xilinx Smart-IP Technology with predefined implementation for predictable timing in Xilinx SpartanXL FPGAs (see LogiCORE Facts for listing of supported devices) 3.3V and 5V operation with SpartanXL devices Zero wait-state burst operation Fully verified design - Tested with Xilinx internal testbench and in hardware (silicon proven) Configurable on-chip dual-port FIFOs can be added for maximum burst speed (see Xilinx Documents section) Programmable single-chip solution with customizable back-end functionality Supported Master functions - Memory Read, Memory Write, Memory Read Multiple, Memory Read Line commands - I/O Read and I/O Write commands - Configuration Read and Configuration Write commands - Special Cycles, Interrupt Acknowledge - Basic Host Bridging - Bus Parking March, 1999 Device Family CLBs Used1 IOBs Used System Clock fmax Device Features Used SpartanXL 152 - 268 53 0 - 33MHz Bi-directional data buses SelectRAMTM (optional user FIFO) Boundary scan (optional) Supported Devices/Resources Remaining I/O CLB1 XCS20XL XCS20XL TQ144 TQ144 60 190 - 2482 XCS30XL XCS30XL PQ208 PQ208 107 308 - 424 XCS30XL XCS30XL PQ240 PQ240 141 308 - 424 XCS40XL XCS40XL PQ208 PQ208 107 516 - 632 XCS40XL XCS40XL PQ240 PQ240 141 516 - 632 Provided with Core3 Documentation PCI Design Guide Implementation Guide Conversion Guide Design File Formats VHDL & Verilog Simulation Models NGO Netlist Constraint Files M1 User Constraint File (UCF) M1 Guide files Verification Tools VHDL and Verilog Testbench Core Symbols VHDL, Verilog Reference designs Synthesizable PCI Bridge Design Design Tool Requirements Xilinx Core Tools M1.5I Entry Tools4 FPGA Express, FPGA Compiler, Synplicity Verification Tools4 Verilog-XL, MTI Support Xilinx provides technical support for this LogiCORE product when used as described in the User's Guide or in the Application Notes. Notes: 1. The exact number of CLBs depends on user configuration of the core and level of resource sharing with adjacent logic. Factors that can affect the size of the design are number and size of the BARs, and use of the latency timer. 2. The XCS20XL XCS20XL device only supports one BAR. 3. Available on Xilinx web site: www.xilinx.com/pci 4. See Xilinx web site for latest list of tested EDA tools and version numbers. 1 PCI32 PCI32 SpartanXL Master & Slave Interface Features (cont.) Applications · · PAR PERRSERR- · · · PCI add-in boards such as graphic cards, video adapters, LAN adapters, and data acquisition boards Embedded applications within networking, telecommunication, and industrial systems CompactPCI boards Other applications that need PCI General Description The LogiCORETM PCI32 PCI32 SpartanXL Master and Slave Interfaces are pre-implemented and fully tested modules for Xilinx SpartanXL FPGAs (see LogiCORE Facts for listing of supported devices). The pin-out and the relative placement of the internal Configurable Logic Blocks (CLBs) are pre-defined. Critical paths are controlled by TimeSpecs and guide files to ensure that timing is always met. This significantly reduces engineering time required to implement the PCI portion of your design. Resources can instead be focused on the unique back-end logic in the FPGA and the system level design. As a result, LogiCORE PCI products can minimize development time. Xilinx SpartanXL family FPGAs enables the design of fully PCI compliant systems. These devices meet all specifications for 3.3 V and 5 V PCI and meet all required electrical and timing parameters including AC output drive characteristics, input capacitance specifications (10pF), 7 ns setup and 0 ns hold to system clock, and 11 ns system clock to output. Base Address Register 0 Base Address Register 1 Command/ Status Register Interrupt Pin and Line Register Parity Generator/ Checker Latency Timer Register Vendor ID, Rev ID, Other User Data PCI I/O INTERFACE AD[3 1 :0 ] ADI O[ 3 1 : 0 ] FRAMEIRDYREQGNT- Initiator State Machine USER APPLICATION · Supported Target functions - Type 0 Configuration Space Header - Up to 2 Base Address Registers (memory or I/O with adjustable block size from 16 Bytes to 2 GBytes, slow decode speed) - Parity Generation (PAR), Parity Error Detection (PERR# and SERR#) - Extended Capabilities Registers (backend module) - Memory Read, Memory Write, Memory Read Multiple (MRM), Memory Real Line (MRL), and Memory Write & Invalidate (MWI) commands - I/O Read and I/O Write commands - Configuration Read and Configuration Write commands - Interrupt Acknowledge - 32-bit data transfers, burst transfers with linear address ordering - Target Abort, Target Retry, Target Disconnect - Full Command/Status Register Available for configuration and download on the web - Web-based configuration tool - Generation of proven design files - Instant access to new releases PC I C o n f ig u r at io n Sp ace TRDYDEVSELSTOP- Target State Machine X7954 X7954 Figure 1: LogiCORE PCI32 PCI32 SpartanXL Interface Block Diagram (one BAR only in XCS20XL XCS20XL) 2 March, 1999 The PCI Compliance Checklists, found in the Xilinx PCI Databook, have additional details. Other features that enable efficient implementation of a complete PCI system in the SpartanXL family includes: · · · · · Select-RAMTM memory: on-chip ultra-fast RAM with synchronous write option and dual-port RAM option. Used in the PCI32 PCI32 SpartanXL Interface to implement the FIFO. Individual output enable for each I/O Internal 3-state bus capability 8 global low-skew clock or signal distribution networks IEEE 1149.1-compatible boundary scan logic support See Spartan FPGA Data Sheet for more details. The module is carefully optimized for best possible performance and utilization in the SpartanXL FPGA architecture. When implemented in the XCS30 XCS30, more than 50% of the FPGA's resources remain for integrating a unique back-end interface and other system functions into a fully programmable one-chip solution. When implemented in the XCS40 XCS40, more than 65% of the FPGA's resources remain for integrating a unique back-end interface and other system functions into a fully programmable one-chip solution. Smart-IP Technology Drawing on the architectural advantages of Xilinx FPGAs, new Xilinx Smart-IP technology ensures optimal performance, predictability, reproducibility, and flexibility in PCI designs. The Smart-IP technology is incorporated in every LogiCORE PCI. Xilinx Smart-IP technology leverages the Xilinx architectural advantages, such as look-up tables (LUTs), distributed RAM, and segmented routing, logic mapping, and relative location constraints. This Smart-IP technology provides the best physical layout, predictability, performance, and significantly reduced compile times in designing a PCI Core. The PCI32 PCI32 SpartanXL Interface can be parameterized, allowing for design flexibility in which users can create the exact PCI interface needed. PCI Cores made with Smart-IP technology are unique by maintaining their performance and predictability regardless of the device size. Functional Description The LogiCORE PCI32 PCI32 SpartanXL Interface is partitioned into five major blocks, plus the user application, shown in Figure 1. Each block is described below. PCI I/O Interface Block The I/O interface block handles the physical connection to the PCI bus including all signaling, input and output synchronization, output three-state controls, and all requestgrant handshaking for bus mastering. March, 1999 Parity Generator/Checker Generates/checks even parity across the AD bus, the CBE lines, and the PAR signal. Reports data parity errors via PERR- and address parity errors via SERR-. Target State Machine This block manages control over the PCI32 PCI32 SpartanXL Interface for Target functions. The states implemented are a subset of equations defined in "Appendix B" of the PCI Local Bus Specification. The controller is a high-performance state machine using state-per-bit (one-hot) encoding for maximum performance. State-per-bit encoding has narrower and shallower next-state logic functions that closely match the Xilinx FPGA architecture. Initiator State Machine This block manages control over the PCI32 PCI32 SpartanXL Interface for Initiator functions. The states implemented are a subset of equations defined in "Appendix B" of the PCI Local Bus Specification. The Initiator Control Logic also uses state-per-bit encoding for maximum performance. PCI Configuration Space This block provides the first 64 bytes of Type 0, version 2.1, Configuration Space Header (CSH) (see Table 1) to support software-driven "Plug-and Play" initialization and configuration. This includes Command, Status, and two Base Address Registers (BARs). These BARs illustrate how to implement memory- or I/O-mapped address spaces. Each BAR sets the base address for the interface and allows the system software to determine the addressable range required by the interface. Using a combination of Configurable Logic Block (CLB) flip-flops for the read/write registers and CLB look-up tables for the read-only registers results in optimized packing density and layout. With this release, the hooks for extending configuration space has been built into the backend interface. Setting the CapPtr and bit 15 of the Status Register allows the user to implement functions such as Advanced Configuration and Power Interface (ACPI) in the backend design. User Application with Optional Burst FIFOs The LogiCORE PCI32 PCI32 SpartanXL Interface provides a simple, general-purpose interface with a 32-bit data path and latched address for de-multiplexing the PCI address/data bus. The general-purpose user interface allows the rest of the device to be used in a wide range of applications. Typically, the user application contains burst FIFOs to increase PCI system performance (An Application Note is available, please see the Xilinx Documents section). An onchip read/write FIFO, built from the on-chip synchronous dual-port RAM (SelectRAMTM) available in SpartanXL devices, supports data transfers in excess of 33 MHz. 3 PCI32 PCI32 SpartanXL Master & Slave Interface Table 1: PCI Configuration Space Header 31 16 15 Table 2: PCI Bus Commands 0 Device ID Vendor ID 00h Status Command 04h Class Code BIST Header Type Rev ID Latency Timer 08h Cache 0Ch Line Size Base Address Register 0 (BAR0) 10h Base Address Register 1 (BAR1) 14h Base Address Register 2 (BAR2) 18h Base Address Register 3 (BAR3) 1Ch Base Address Register 4 (BAR5) 20h Base Address Register 5 (BAR5) 24h Cardbus CIS Pointer 28h Subsystem Vendor ID 2Ch Subsystem ID Expansion ROM Base Address Reserved CapPtr Min_Gnt Interrupt Pin Reserved 34h Interrupt Line 4 Note: 1. The Initiator can present these commands, however, they either require additional user-application logic to support them or have not been thoroughly tested. Table 2 illustrates the PCI bus commands supported by the LogiCORE PCI32 PCI32 SpartanXL Interface. The compliance checklist later in this data book have more details on supported and unsupported commands. 40h-FFh The LogiCORE PCI32 PCI32 SpartanXL Interface can easily be configured to fit unique system requirements using Xilinx web-based PCI Configuration and Download Tool. The following customization is supported by the LogiCORE product and described in accompanying documentation. · · Interrupt Acknowledge Special Cycle I/O Read I/O Write Reserved Reserved Memory Read Memory Write Reserved Reserved Configuration Read Configuration Write Memory Read Multiple Dual Address Cycle Memory Read Line Memory Write Invalidate PCI Slave Yes Ignore Yes Yes Ignore Ignore Yes Yes Ignore Ignore Yes Yes Yes Ignore Yes Yes Supported PCI Commands Interface Configuration · · 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 PCI Master Yes Yes Yes Yes Ignore Ignore Yes Yes Ignore Ignore Yes Yes Yes No1 Yes No1 3Ch Note: Italicized address areas are not implemented in the LogiCORE PCI32 PCI32 SpartanXL Interface default configuration. These locations return zero during configuration read accesses. · · Command 38h Reserved Max_Lat 30h CBE [3:0] Initiator and target functionality Base Address Register configuration (1-2 Registers in XCS30XL XCS30XL and XCS40XL XCS40XL, 1 BAR only in XCS20XL XCS20XL, size and mode of BAR) Configuration Space Header ROM Initiator and target state machine (e.g., termination conditions, transaction types and request/transaction arbitration) Burst functionality User Application including FIFO (back-end design) Burst Transfer The PCI bus derives its performance from its ability to support burst transfers. The performance of any PCI application depends largely on the size of the burst transfer. A FIFO to support PCI burst transfer can efficiently be implemented using the SpartanXL on-chip RAM feature, SelectRAMTM. Each SpartanXL CLB supports two 16x1 RAM blocks. This corresponds to 32 bits of single-ported RAM or 16 bits of dual-ported RAM, with simultaneous read/write capability. Bandwidth The Xilinx PCI32 PCI32 SpartanXL Interface supports a sustained bandwidth of up to 132 MBytes/sec. The design can be configured to take advantage of the ability of the LogiCORE PCI32 PCI32 Interface to do very long bursts. Since the FIFO does not have a fixed size, a burst can go on for as long as the chipset arbiter will allow. Furthermore, since the FIFOs and the DMA are decoupled from the proven core, a designer can modify these functions without affecting the critical PCI timing. March, 1999 The flexible Xilinx backend, combined with support for many different PCI features, gives users a solution that can be used in many high-performance applications. Xilinx is able to support different depths of FIFOs as well as dual port FIFOs, synchronous or asynchronous FIFOs, and multiple FIFOs. The user is not restricted to one DMA engine, hence, a DMA that fits a specific application can be designed. The theoretical maximum bandwidth of a 32-bit, 33 MHz PCI bus is 132 MBytes. How close you get to this maximum bandwidth will depend on several factors, including the PCI design used, PCI chipset, the processor's ability to keep up with your data stream, the maximum capability of your PCI design, and other traffic on the PCI bus. Older chipsets and processors will tend to allow less bandwidth than newer ones. In the Zero wait-state mode, no wait-states are inserted either while sourcing data or receiving data. This allows a 100% burst transfer rate in both directions with full PCI compliance. No additional wait-states are inserted in response to a wait-state from another agent on the bus, as required by the PCI V 2.2 specification. Either IRDY or TRDY is kept asserted until the current data phase ends, as required by PCI V 2.2 Specification. In this version of the PCI Interface, based on the Xilinx V3.0.X PCI Interface, the end of initiator transaction waitstate has been removed. See Table 3 for PCI bus transfer rates for various operations in Zero wait-state mode. Table 3: LogiCORE PCI32 PCI32 SpartanXL Transfer Rates Zero Wait-State Mode Operation Transfer Rate Initiator Write (PCI LogiCORE) 3-1-1-1 Initiator Read (PCI LogiCORE) 4-1-1-1 Target Write (PCI LogiCORE) 5-1-1-1 Target Read (PCI LogiCORE) 6-1-1-1 Note: Initiator Read and Target Write operations have effectively the same bandwidth for burst transfer. Timing Specification The SpartanXL family, together with the LogiCORE PCI32 PCI32 Interface enables design of fully compliant PCI systems. Backend design can affect the maximum speed your design is capable of. Factors in your back-end designs that March, 1999 can affect timing include loading of hot signals coming directly from the PCI bus, gate count and floor planning. Table 4 shows the key timing parameters for the LogiCORE PCI32 PCI32 SpartanXL Interface that must be met for full PCI compliance. Verification Methods Xilinx has developed a testbench with numerous vectors to test the Xilinx PCI design; this is included with the LogiCORE PCI32 PCI32 SpartanXL Master and Slave Interfaces. A version of this testbench is also used internally by the Xilinx PCI team to verify the PCI32 PCI32 Interfaces. Additionally, the PCI32 PCI32 Interfaces have been tested in hardware for electrical, functional and timing compliance. Table 4. Advanced Timing Parameters [ns] Parameter CLK Cycle Time CLK High Time CLK Low Time CLK to Bus Signals Valid3 CLK to REQ# and GNT# Valid3 Tri-state to Active CLK to Tri-state Bus Signal Setup to CLK (IOB) Bus Signal Setup to CLK (CLB) GNT# Setup to CLK Input Hold Time After CLK (IOB) Input Hold Time After CLK (CLB) RST# to Tri-state Ref. TICK- PCI Spec. Min 30 11 11 2 Max 2 LogiCORE PCI32 PCI32, XCSXL-4 Min Max 301 11 11 22 9.6 12 11 OF TICK- 22 9.6 OF 22 2 28 7 281 7 7 71 TPSU 10 5.2 TPH 0 0 0 02 40 402 TPSU Notes: 1. Controlled by TIMESPECs, included in product 2. Verified by analysis and bench-testing 3. IOB configured for Fast slew rate 5 PCI32 PCI32 SpartanXL Master & Slave Interface The testbench shipped with the interface verifies the PCI interface functions according to the test scenarios specified in PCI Compliance Checklist, V 2.1; see Figure 2. This testbench consists of 28 test scenarios, each designed to test a specific PCI bus operation. Refer to the checklists chapter in this databook for a complete list of scenarios. Figure 2. PCI Protocol Testbench faketarg pci_lc_i testbnch Target Functional Mode LogiCORE PCI Interface Initiator Protocol Test User Application Device Utilization The Target-Only and Target/Initiator options require a variable amount of CLB resources for the PCI32 PCI32 Spartan Interface. The core includes a switch to force the entire deletion of unused Base Address Registers. Utilization can vary widely, depending on the configuration choices made by the designer. Options that can affect the size of the core are: · · pcim_tst · Simple Arbiter fakearb Number of Base Address Registers Used. Turning off any unused BARs will save on resources. Size of the BARs. Setting the BAR to a smaller size requires more flip-flops. A smaller address space requires more flip-flops to decode. Latency timer. Disabling the latency timer will save a few resources. It must be enabled for bursting. Recommended Design Experience X7951 X7951 Ping Reference Design The Xilinx LogiCORE PCI "PING" Application Example, delivered in VHDL and Verilog, has been developed to provide an easy-to-understand example which demonstrates many of the principles and techniques required to successfully use a LogiCORE PCI32 PCI32 Spartan Interface in a System-on-a-Chip solution. Synthesizable PCI Bridge Design Example The LogiCORE PCI32 PCI32 Spartan Interface is pre-implemented allowing engineering focus at the unique back-end functions of a PCI design. Regardless, PCI is a high-performance system that is challenging to implement in any technology, ASIC or FPGA. Therefore, we recommend previous experience with building high-performance, pipelined FPGA designs using Xilinx implementation software, TIMESPECs, and guide files. The challenge to implement a complete PCI design including back-end functions varies depending on configuration and functionality of your application. Contact your local Xilinx representative for details on your specific design requirements. Synthesizable PCI bridge design examples, delivered in Verilog and VHDL, are available to demonstrate how to interface with the LogiCORE PCI32 PCI32 Spartan Interface and provide a modular foundation upon which to base other designs. See separate data sheet for details. 6 March, 1999