PC2700 PC1600 VT8233 VT8233A VT8233C VT8235 VT8703 VT8751 VT8753 VT8754 P4M266 - Datasheet Archive

 

for Pentium 4 CPUs with 533 / 400 MHz FSB and 8x / 4x / 2x AGP Bus plus Advanced ECC Memory Controller supporting PC2700 / 2100 /

 

Single-Chip North Bridge for Pentium 4 CPUs with 533 / 400 MHz FSB and 8x / 4x / 2x AGP Bus plus Advanced ECC Memory Controller supporting PC2700 PC2700 / 2100 / PC1600 PC1600 DDR DRAM for Desktop PC Systems Revision 0.91 July 19, 2002 VIA TECHNOLOGIES, INC. Copyright Notice: Copyright © 2001, 2002 VIA Technologies Incorporated. All Rights Reserved. No part of this document may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language, in any form or by any means, electronic, mechanical, magnetic, optical, chemical, manual or otherwise without the prior written permission of VIA Technologies Incorporated. The material in this document is for information only and is subject to change without notice. VIA Technologies Incorporated reserves the right to make changes in the product design without reservation and without notice to its users. Trademark Notices: VT8233 VT8233, VT8233A VT8233A, VT8233C VT8233C, VT8235 VT8235, VT8703 VT8703, VT8751 VT8751, VT8753 VT8753, VT8754 VT8754, P4M266 P4M266, P4N266 P4N266, P4X266 P4X266, P4X266A P4X266A, and P4X400 P4X400 may only be used to identify products of VIA Technologies. IntelTM, PentiumTM and MMXTM are registered trademarks of Intel Corp. VIA C3TM is a registered trademark of VIA Technologies AthlonTM and AMD-K7TM are registered trademarks of Advanced Micro Devices Corp. Windows XPTM. Windows 2000TM 2000TM. Windows METM, Windows 98TM, and Plug and PlayTM are registered trademarks of Microsoft Corp. PCITM is a registered trademark of the PCI Special Interest Group. PS/2TM is a registered trademark of International Business Machines Corp. All trademarks are the properties of their respective owners. Disclaimer Notice: No license is granted, implied or otherwise, under any patent or patent rights of VIA Technologies, Inc. VIA Technologies makes no warranties, implied or otherwise, in regard to this document and to the products described in this document. The information provided by this document is believed to be accurate and reliable to the publication date of this document. However, VIA Technologies assumes no responsibility for any errors in this document. Furthermore, VIA Technologies assumes no responsibility for the use or misuse of the information in this document and for any patent infringements that may arise from the use of this document. The information and product specifications within this document are subject to change at any time, without notice and without obligation to notify any person of such change. Offices: VIA Technologies Incorporated USA Office: 940 Mission Court Fremont, CA 94539 USA Tel: (510) 683-3300 Fax: (510) 683-3301 or (510) 687-4654 Web: http://www.viatech.com VIA Technologies Incorporated Taiwan Office: th 8 Floor, No. 533 Chung-Cheng Road, Hsin-Tien Taipei, Taiwan ROC Tel: (886-2) 2218-5452 Fax: (886-2) 2218-5453 Web: http://www.via.com.tw Technologies, Inc. P4X400 P4X400 Chipset ­ VT8754 VT8754 Pentium 4 DDR V-Link North Bridge We Connect REVISION HISTORY Document Release 0.1 Date 12/18/01 0.2 1/3/02 0.3 2/8/02 0.31 0.4 2/11/02 2/27/02 0.5 2/28/02 0.6 3/11/02 0.7 4/5/02 0.71 4/22/02 0.72 0.8 0.9 5/29/02 6/25/02 7/19/02 0.91 7/19/02 Revision 0.91, July 19, 2002 Revision Initial internal release based on P4X266A P4X266A data sheet rev 1.0 published 12/5/01 Updated cover, block diagram and feature bullets to add AGP 8x and DDR 333 Updated pin diagram per project #3168 engg ballout rev 1.2 dated 12/7/01 Updated pin lists, updated AGP pin descriptions for AGP 8x mode Added CPU pins HA34-35 HA34-35, AP[1-0], HDP[3-0], RSP, VCC/GNDHCK2 Added AGP pins AGP8XDT#, GCKE, GSERR# Added Mem pins MAA15 MAA15, MAB15 MAB15, QDRRD#, QDRWR# Added V-Link pin VPAR and Miscellaneous pin NMI Replaced mechanical spec with HSBGA-859 HSBGA-859 Fixed SDRAM feature bullets; Changed mechanical spec to HSBGA-858 HSBGA-858 Updated pinouts to match engineering ballout 1.5 (removed VCC25 VCC25 ball at AA10) Fixed PC2700 PC2700 notation; fixed various formatting and typographical errors Fixed/updated ball count, AGP 8x, V-Link and DRAM feature bullets & overview Updated block diagram, feature bullets & overview to use VT8235 VT8235 south bridge Updated strap definitions; Removed SDR support Updated Device 0 Rx13-10, 41, 43-44, 47-49, 4B-4C, 4F-52 4F-52, 54-55, 60, 63, 66-67, 6A-6E, 70, 80-83, A4-B0, B2, B4-B6, B8-BA, BC-BE, D0-D6, DA-DB, E0-E3, E6, E8-EF, Device 1 Rx3-2, F, 48 Replaced mech spec with correct 858-ball diagram Regenerated pdf file to fix non-printing mechnical spec diagram Added P4X333 P4X333 "product logo" to cover page and page headers Fixed first main feature bullet to target high performance PC desktop systems Fixed Figure 1 block diagram (bad diagram printout due to MS-Word bug) Changed V-Link to 533 MB/sec in feature bullets and overview Fixed errors and typos (package pin count, # of PCI slots, etc) in Overview text Fixed mistakes in power/ground pin lists at bottom of pin list tables 1 and 2 Fixed part number and product name typos in pin descriptions Fixed register references in memory pin descriptions and electrical specs Fixed voltages in AGPVREF, VCCMEM, and VCCAGP pin descriptions Fixed AGPVREF and AGPVCC pin descriptions Device 0 Fixed Rx3-2 default, 52[5], 53-54, A7-A4 default, 64[6-4], 69[6], B2[7] Device 0 Removed Rx52[4], 67[7-6], B4 (8233 configuration only) Fixed P4X400 P4X400 logo to print in color; changed max memory to 16GB Added feature bullet to include support for both registered and unbuffered DIMMs Changed pins AK7 and AJ16 to NC; Updated AGPVREF pin description Added pin type and pin name to GCKE, HDP[3-0], AP[1-0], RSP#, NMI, GSERR# Updated Table 7 MA Mapping to add 512Mb and 1Gb DRAMs; Updated Rx69[6] Fixed VIA USA address and VIA Taiwan fax # on legal page Fixed VLVREF pin description; Fixed typographical error in mech spec drawing Corrected TW fax number; Corrected typo in pin diagram in VCCVL pin names Updated block diagram to show six PCI slots for VT8235 VT8235 south bridge Fixed feature bullet error (AGP 8x not 4x in first sub-bullet); Updated table 6 Changed chip name from P4X333 P4X333 to P4X400 P4X400 Updated Device 0 Rx0D[2-1], 47[7-6,1], 4D, 51[0], 60[7-6] (default), 69[6], A8[76,3], B0[7] (& register name in sumary tables), B1 (register name), EE, EF[1-0] Replaced Rx80-B3, F0-FF (AGP 2.0/3.0 regs) from KT400 KT400 data sheet rev 0.42 Increased size of figure 1 block diagram; Fixed Rx13-10, 34 -i- Initials DH DH DH DH DH DH DH DH DH DH DH DH DH Revision History Technologies, Inc. We Connect P4X400 P4X400 Chipset ­ VT8754 VT8754 Pentium 4 DDR V-Link North Bridge TABLE OF CONTENTS REVISION HISTORY .I TABLE OF CONTENTS. II LIST OF FIGURES .IV LIST OF TABLES .IV PRODUCT FEATURES. 1 OVERVIEW. 3 PINOUTS. 5 PIN DESCRIPTIONS . 8 REGISTERS. 17 REGISTER OVERVIEW . 17 MISCELLANEOUS I/O . 21 CONFIGURATION SPACE I/O . 21 DEVICE 0 REGISTER DESCRIPTIONS . 22 Device 0 Host Bridge Header Registers . 22 Device 0 Host Bridge Device-Specific Registers. 24 V-Link Control. 24 Host CPU Control . 27 DRAM Control . 29 PCI Bus Control. 35 GART / Graphics Aperture . 37 AGP 2.0 Registers. 38 CPU-to-Memory Access Control . 38 AGP 3.0 Registers. 40 AGP 2.0 / 3.0 Registers. 42 V-Link Compensation / Drive Control. 44 Power Management Control . 45 Extended Power Management Control. 46 Error Control. 46 Host CPU AGTL+ I/O Control . 47 DRAM Above 4G Control . 48 Host CPU P6 Interface DRDY Timing Control . 49 BIOS Scratch . 49 Miscellaneous Registers. 49 DEVICE 1 REGISTER DESCRIPTIONS . 50 Device 1 PCI-to-PCI Bridge Header Registers . 50 Device 1 PCI-to-PCI Bridge Device-Specific Registers . 52 AGP Bus Control . 52 AGP Bus Control (continued) . 54 Power Management. 54 FUNCTIONAL DESCRIPTION . 55 CONFIGURATION STRAPPING . 55 ELECTRICAL SPECIFICATIONS . 56 ABSOLUTE MAXIMUM RATINGS . 56 Revision 0.91, July 19, 2002 -ii- Table of Contents Technologies, Inc. We Connect P4X400 P4X400 Chipset ­ VT8754 VT8754 Pentium 4 DDR V-Link North Bridge DC CHARACTERISTICS . 56 POWER CHARACTERISTICS . 57 AC TIMING SPECIFICATIONS . 58 MECHANICAL SPECIFICATIONS. 59 Revision 0.91, July 19, 2002 -iii- Table of Contents Technologies, Inc. We Connect P4X400 P4X400 Chipset ­ VT8754 VT8754 Pentium 4 DDR V-Link North Bridge LIST OF FIGURES FIGURE 1. P4X400 P4X400 CHIPSET SYSTEM BLOCK DIAGRAM. 3 FIGURE 2. VT8754 VT8754 / P4X400 P4X400 BALL DIAGRAM (TOP VIEW). 5 FIGURE 3. GRAPHICS APERTURE ADDRESS TRANSLATION. 37 FIGURE 4. MECHANICAL SPECIFICATIONS ­ HSBGA-858 HSBGA-858 BALL GRID ARRAY PACKAGE WITH HEAT SPREADER . 59 LIST OF TABLES TABLE 1. VT8754 VT8754 PIN LIST (NUMERICAL ORDER). 6 TABLE 2. VT8754 VT8754 PIN LIST (ALPHABETICAL ORDER). 7 TABLE 3. VT8754 VT8754 / P4X400 P4X400 PIN DESCRIPTIONS. 8 TABLE 4. VT8754 VT8754 / P4X400 P4X400 REGISTERS . 17 TABLE 5. SYSTEM MEMORY MAP. 29 TABLE 6. DEVICE 0 RX58 MA MAP TYPE ENCODING. 30 TABLE 7. DDR DRAM MEMORY ADDRESS MAPPING TABLE . 30 TABLE 8. DIMM MODULE CONFIGURATION. 34 TABLE 9. VGA/MDA MEMORY/IO REDIRECTION . 52 TABLE 10. ABSOLUTE MAXIMUM RATINGS. 56 TABLE 11. DC CHARACTERISTICS. 56 TABLE 12. POWER CHARACTERISTICS ­ INTERNAL AND INTERFACE DIGITAL LOGIC . 57 TABLE 13. POWER CHARACTERISTICS ­ ANALOG AND REFERENCE VOLTAGES. 58 TABLE 14. AC TIMING MIN / MAX CONDITIONS . 58 Revision 0.91, July 19, 2002 -iv- Table of Contents Technologies, Inc. P4X400 P4X400 Chipset ­ VT8754 VT8754 Pentium 4 DDR V-Link North Bridge We Connect P4X400 P4X400 CHIPSET VT8754 VT8754 Single-Chip North Bridge for Pentium 4 CPUs with 533 / 400 MHz Front Side Bus and 8x / 4x / 2x AGP Bus plus Advanced ECC Memory Controller supporting PC2700 PC2700 / 2100 / PC1600 PC1600 DDR SDRAM for Desktop PC Systems PRODUCT FEATURES · Defines Highly Integrated Solutions for Performance PC Desktop Designs ­ ­ ­ ­ ­ · High Performance CPU Interface ­ ­ ­ ­ · High performance North Bridge with 533 MHz Front Side Bus for PentiumTM 4 plus AGP 8x external bus 64-bit Advanced ECC Memory controller supporting PC2700 PC2700 / PC2100 PC2100 / PC1600 PC1600 DDR Synchronous DRAM Combines with VIA VT8235 VT8235 V-Link South Bridge for integrated LAN, Audio, ATA133 ATA133 IDE, and 6 USB 2.0 ports 2.5V Core and AGTL+ I/O 35 x 35mm HSBGA package (Ball Grid Array with Heat Spreader) with 858 balls and 1mm ball pitch Support for IntelTM Pentium 4 processors with 533 MHz (4 x 133 MHz) CPU Front Side Bus (FSB) Built-in Phase Lock Loop circuitry for optimal skew control within and between clocking regions Thirteen outstanding transactions (twelve In-Order Queue (IOQ) plus one output latch) Dynamic deferred transaction support Full Featured Accelerated Graphics Port (AGP) Controller ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ Supports 533 MHz 8x, 266 MHz 4x, and 133 MHz 2x transfer modes for AD and SBA signaling AGP v3.0 compliant with 8x transfer mode Pseudo-synchronous with the host CPU bus with optimal skew control Supports SideBand Addressing (SBA) mode (non-multiplexed address / data) AGP pipelined split-transaction long-burst transfers up to 1GB/sec Eight level read request queue Four level posted-write request queue Thirty-two level (quadwords) read data FIFO (256 bytes) Sixteen level (quadwords) write data FIFO (128 bytes) Intelligent request reordering for maximum AGP bus utilization Supports Flush/Fence commands Graphics Address Relocation Table (GART) ­ ­ ­ ­ ­ One level TLB structure Sixteen entry fully associative page table LRU replacement scheme Independent GART lookup control for host / AGP / PCI master accesses Windows 95 OSR-2 VXD and integrated Windows 98 / Windows 2000 miniport driver support Revision 0.91, July 19, 2002 -1- Product Features Technologies, Inc. We Connect · Advanced High-Performance DDR DRAM Controller ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ · DRAM interface pseudo-synchronous with host CPU (166 / 133 / 100 MHz) for most flexible configuration DRAM interface may be faster than CPU by 33 MHz to allow use of 133 MHz memory with 100 MHz FSB clock or 166 MHz memory with 133 MHz FSB clock Concurrent CPU, AGP, and V-Link access Clock Enable (CKE) control for DRAM power reduction in high speed systems Mixed 1M / 2M / 4M / 8M / 16M / 32M / 64M / 128M x 8/16/32 DRAMs Supports 8 banks up to 16 GB DRAMs Allows use of either unbuffered or registered memory modules Flexible row and column addresses. 64-bit data width only 2.5V SSTL-2 DRAM interface Programmable I/O drive capability for MA, MD, and command signals Dual copies of MA and control signals for improved drive ECC (single-bit error correction and multi-bit error detection) or EC (error checking only) for DRAM integrity Two-bank interleaving for 16Mbit DRAM support Four bank interleaving for 64Mb, 128Mb, 256Mb, 512Mb, and 1Gb DRAM support Supports maximum 16-bank interleave (i.e., 16 pages open simultaneously); banks are allocated based on LRU Seamless DRAM command scheduling for maximum DRAM bus utilization ­ (e.g., precharge other banks while accessing the current bank) Four cache lines (16 quadwords) of CPU to DRAM write buffers Four cache lines of CPU to DRAM read prefetch buffers Read around write capability for non-stalled CPU read Speculative DRAM read before snoop result Burst read and write operation Burst length 4 and 8 Supports CL 2/2.5 and 1T per command 1T and 2T command rate which can be specified bank by bank Decoupled and burst DRAM refresh with staggered RAS timing (CAS before RAS or self refresh) High Bandwidth 533 MB / Sec 8-bit V-Link Host Controller ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ · P4X400 P4X400 Chipset ­ VT8754 VT8754 Pentium 4 DDR V-Link North Bridge Supports 66 MHz V-Link Host interface with peak bandwidth of 533 MB/sec Operates in 2x, 4x, and 8x modes Full duplex commands with separate command / strobe Request / Data split transaction Configurable outstanding transaction queue for Host to V-Link Client accesses Supports Defer / Defer-Reply transactions Transaction assurance for V-Link Host to Client access eliminates V-Link Host-Client Retry cycles Intelligent V-Link transaction protocol to eliminate data wait-state / throttle transfer latency All V-Link transactions for both Host and Client have a consistent view of transaction data depth and buffer size to avoid data overflow Highly efficient V-Link arbitration with minimum overhead All V-Link transactions have predictable cycle length with known command / data duration Advanced System Power Management Support ­ ­ ­ ­ ­ Dynamic power down of DRAM (CKE) VTT suspend power plane preserves memory data Suspend-to-DRAM and self-refresh power down Low-leakage I/O pads ACPI 1.0B and PCI Bus Power Management 1.1 compliant Revision 0.91, July 19, 2002 -2- Product Features Technologies, Inc. P4X400 P4X400 Chipset ­ VT8754 VT8754 Pentium 4 DDR V-Link North Bridge We Connect OVERVIEW The P4X400 P4X400 (VT8754 VT8754 North Bridge plus VT8235 VT8235 South Bridge) is a high performance, cost-effective and energy efficient chip set for the implementation of desktop personal computer systems with 533 MHz (4x133 MHz) or 400 MHz (4x100 MHz) CPU host bus ("Front Side Bus") based on 64-bit Intel Pentium-4 super-scalar processors. Network Interface PHY 10/100 Ethernet VT6103 VT6103 System Management Bus 64-bit Pentium 4 CPU 533 MHz (4x133 MHz) Front Side Bus 8x / 4x / 2x AGP Slot MII 166 / 133 / 100 MHz DDR with ECC UDMA / ATA 133 / 100 / 66 / 33 66MHz 8x/ 4x/ 2x, 8-bit V-Link P4X400 P4X400 Chipset PCI Slots VT8754 VT8754 Pentium 4 DDR North Bridge 33MHz, 32-bit PCI 858-pin HSBGA P4X400 P4X400 Chipset VT8235 VT8235 V-Link South Bridge 487-pin PBGA Direct LPC EPROM Or LPC AC-Link 6X USB 2.0 VT1616 VT1616 AC'97 Audio Codec MC-97 MC-97 Modem Codec Integrated AC'97 Audio VT1211 VT1211 LPC Super I/O Serial / IR Parallel Floppy Disk Keyboard Mouse Figure 1. P4X400 P4X400 Chipset System Block Diagram The P4X400 P4X400 chip set consists of the VT8754 VT8754 North Bridge (858-pin BGA) and the VT8235 VT8235 V-Link South Bridge (487 pin BGA). The VT8754 VT8754 (sometimes also called a "Host System Controller") is an update of VIA's VT8753A VT8753A (P4X266A P4X266A) with a faster DDR memory interface and a new pinout enhanced to add AGP 8x functionality. The VT8754 VT8754 provides superior performance between the CPU, DRAM, V-Link bus and AGP 8x graphics controller bus with pipelined, burst, and concurrent operation. The VT8235 VT8235 (which may also be referred to as a "V-Link Client Controller") is a highly integrated PCI / LPC controller. Its internal bus structure is based on a 66 MHz PCI bus that provides 2x / 4x / 8x bandwidth compared to previous generation PCI bridge chips. The VT8235 VT8235 also provides a 533 MB/sec bandwidth Host / Client V-Link interface with V-Link-PCI and V-Link-LPC controllers. It supports six PCI slots of arbitration and decoding for all integrated functions and LPC bus. The VT8754 VT8754 supports eight banks of DDR Synchronous DRAMs (SDRAMs) up to 16 GB. The DRAM controller supports PC2700 PC2700 / PC2100 PC2100 / PC1600 PC1600 Double-Data-Rate (DDR) SDRAM. The DDR DRAM interface allows zero wait state bursting between the DRAM and the data buffers at 166 / 133 / 100 MHz. The different banks of DRAM can be composed of an arbitrary mixture of 1M / 2M / 4M / 8M / 16M / 32M / 64M / 128M x 8/16/32 DRAMs. Both unbuffered and registered memory modules are supported. The DRAM controller also supports optional ECC (single-bit error correction and multi-bit detection) or EC (error checking) capability. The DRAM controller can run either synchronous or pseudo-synchronous with the host CPU bus. The VT8754 VT8754 supports a high speed 8-bit 8x 66 MHz Quad Data Transfer interconnect (V-Link) to the VT8235 VT8235 South Bridge. The chip also contains a built-in bus-to-bus bridge to allow simultaneous concurrent operations on each bus. Five levels (doublewords) of post write buffers are included to allow for concurrent CPU and V-Link operation. For V-Link Host operation, forty-eight levels (doublewords) of post write buffers and sixteen levels (doublewords) of prefetch buffers are included for concurrent V-Link bus and DRAM/cache accesses. When combined, the V-Link Host / Client controllers realize a complete PCI sub-system and support enhanced PCI bus commands such as "Memory-Read-Line", "Memory-Read-Multiple" and "Memory-Write-Invalid" Revision 0.91, July 19, 2002 -3- Overview Technologies, Inc. We Connect P4X400 P4X400 Chipset ­ VT8754 VT8754 Pentium 4 DDR V-Link North Bridge commands to minimize snoop overhead. In addition, advanced features are supported such as snoop ahead, snoop filtering, L1 write-back forward to PCI master, and L1 write-back merged with PCI post write buffers to minimize PCI master read latency and DRAM utilization. Delay transaction and read caching mechanisms are also implemented for further improvement of overall system performance. The 487-pin Ball Grid Array VT8235 VT8235 Client V-Link PCI / LPC controller supports four levels (doublewords) of line buffers, type F DMA transfers and delay transaction to allow efficient PCI bus utilization and (PCI-2.1 compliant). The VT8235 VT8235 integrated PCI controller and PCI arbitration for up to five PCI slots. One of the PCI REQ / GNT pairs can be configured as high-priority to better support a low latency PCI bus master device. The VT8235 VT8235 integrated networking MAC controller with standard MII interface to an external PHY for 10/100Mb base-T Ethernet or 1/10Mb PNA home networking. The VT8235 VT8235 also includes an integrated keyboard controller with PS2 mouse support, integrated DS12885 DS12885 style real time clock with extended 256 byte CMOS RAM, integrated master mode enhanced IDE controller with full scatter / gather capability and extension to UltraDMA-133/100/66/33 for 133/100/66/33 MB/sec transfer rate, integrated USB 2.0 interface with three root hubs and six functional ports with built-in physical layer transceivers, Distributed DMA support, and OnNow / ACPI compliant advanced configuration and power management interface. For sophisticated power management, the P4X400 P4X400 chipset provides independent clock stop controls for the CPU / SDRAM and AGP bus plus Dynamic CKE control for powerdown of the SDRAM. A separate suspend-well plane is implemented for the SDRAM control signals for Suspend-to-DRAM operation. Coupled with the VT8235 VT8235 south bridge chip, a complete power conscious PC main board can be implemented with no external TTLs. Revision 0.91, July 19, 2002 -4- Overview Technologies, Inc. P4X400 P4X400 Chipset ­ VT8754 VT8754 Pentium 4 DDR V-Link North Bridge We Connect PINOUTS Figure 2. VT8754 VT8754 / P4X400 P4X400 Ball Diagram (Top View) Key 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 A G STOP# G DSEL# G TRDY# GD18 GD17 GD19 G BE3# GD23 GD28 SBA 5 SBA 3 G RBF# G GNT# AGP 8XDT# VCC 25 VCC 25 VCC 25 CPU RST# HD62# HD63# HD55# HD51# HD48# HD43# HDBI 2# HDS 2# HD37# HD P0 HD26# HD28# HD30# HD22# HD19# HD20# B VCC AGP GND GND G BE2# GD16 GND GD21 GD26 GND SBA 7 SBA 1 GND ST1 GND VCC 25 VCC 25 VCC 25 GND HD60# HD56# GND HD54# HD49# GND HD42# HDS 2 GND HD P2 HD31# GND HDS 1# HD16# GND HD21# C VCC AGP VCC AGP GND G IRDY# G FRM# GD25 GD22 GDS1 GDS1F GD29 SBA 6 SBS# SBSS SBA 2 G PIPE# G REQ# VCC 25 VCC 25 VCC 25 GND HD61# HD57# HDS 3 HD53# HD50# HD44# HD41# HD38# HD39# HD35# HD29# HDBI 1# HDS 1 HD23# HD17# HD18# D VCC AGP VCC AGP VCC AGP GND GND GD20 GD27 GDS1# GDS1S GD30 GDBIL SBS SBSF SBA 0 G WBF# ST0 VCC 25 VCC 25 VCC 25 GND HD58# HD59# HDS 3# HD52# HD47# HD45# HD34# HD33# HD32# HD P3 HD25# HD24# HD7# HD14# GND HD15# E VCC AGP VCC AGP VCC AGP VCC AGP GND GND GD24 GD31 GND GDBIH GPIPE# SBA 4 GND ST2 VCC 25 VCC 25 VCC 25 VCC 25 GND GND GND GND HDBI 3# HD46# GND HD40# HD36# GND HD P1 HD27# GND HD10# HDS 0# HD13# HD12# F G SERR# VCC AGP VCC AGP VCC AGP VCC AGP GND GND GND GND AGP VREF GND GND GND VCC 25 VCC 25 VCC 25 VCC 25 GND HD VREF GND GND GND GND HD VREF GND TT GND GND HD VREF GND HD11# GND HDS 0 GND HD9# G GD14 G BE1# VCC AGP VCC AGP VCC AGP VCC AGP F7 G28 GND HDBI 0# HD3# HD8# HD2# HD6# H GD12 GND GND VCC AGP VCC AGP VCC AGP H H GND HCMP VREF HR COMP HD5# HD4# HD1# J GD8 GD10 G PAR GND VCC AGP VCC AGP J HD VREF GND GND GND GND HD0# K G BE0# GD7 GDS0 GDS0F GDS0# GDS0S GND VCC AGP K VTT VTT VTT VTT VTT VTT L GD6 GND GD5 GD11 GD15 GND L VTT VTT VTT VTT VTT VTT 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 AGP Pins J J12 13 J14 J18 19 20 21 J22 K K11 VCC 25 VCC 25 VCC 25 K15 16 K17 VCC 25 VCC 25 VCC 25 VCC 25 VCC 25 K23 L L11 VCC AGP VCC AGP VCC AGP VCC AGP VCC AGP VCC AGP VTT VTT VTT VTT VTT VTT M M10 VCC AGP VCC AGP VCC AGP VCC AGP VCC AGP VCC AGP VCC AGP VTT VTT VTT VTT VTT VTT VTT M25 CPU M VTT VTT VTT VTT VTT VTT N N10 VCC AGP VCC AGP N13 14 15 16 17 18 19 20 21 N22 VTT VTT N Pins N VTT VTT VTT VTT VTT VTT VCC AGP VCC AGP L24 M GD2 GD4 GD0 GND GD13 AGP VREF N GD1 VAD 4 GD3 GD9 G CLK VCC QQ P VAD 5 GND V PAR GND QQ AGP COMP GND P P9 VCC 25 P GND GND GND GND GND GND GND GND P VTT VTT P P VTT VTT VTT VTT VTT NMI R V BE# VAD 1 VAD 0 GND GND GND R R VCC 25 VCC AGP VCC AGP R GND GND GND GND GND GND GND GND R VTT VTT R25 R GND GND GND GND GND BPRI# T UP STB# UP STB DN STB# DN STB DN CMD GND T T9 VCC 25 VCC VL VCC VL T GND GND GND GND GND GND GND GND T VTT VTT VCC 25 T H CLK# VCC HCK1 GND HCK1 DE FER# GND HITM# U VAD 6 GND VAD 7 VAD 3 VAD 2 VL COMP U Link U10 VCC VL VCC VL U GND GND GND GND GND GND GND GND U VTT VTT VCC 25 U U H CLK VCC HCK2 GND HCK2 RS 2# RS 0# HIT# V SUS ST# UP CMD VL VREF GND VSUS 25 GND V Pins V10 VCC VL VCC MEM V GND GND GND GND GND GND GND GND V VTT VTT VCC 25 V V GTL VREF RS1# BNR# D BSY# H LOCK# ADS# W RE SET# GND PWR OK# GND GND VCC VL W VCC 25 VCC MEM VCC MEM W GND GND GND GND GND GND GND GND W VTT VTT VCC 25 W W GND GND HT RDY# B REQ# GND D RDY# Y VCC VL VCC VL VCC VL VCC VL VCC VL VCC VL Y10 VCC MEM VCC MEM HREQ 4# AA VCC VL VCC VL VCC VL VCC VL VCC VL VCC VL AA AA10 VCC MEM VCC MEM HA6 AB VCC MEM VCC MEM VCC MEM VCC MEM VCC MEM VCC MEM AB VCC 25 VCC MEM VCC MEM AB13 14 15 16 17 18 19 20 21 AC VCC MEM VCC MEM VCC MEM VCC MEM VCC MEM VCC MEM AC AC10 VCC MEM VCC MEM VCC MEM VCC MEM VCC MEM VCC MEM VCC MEM VCC MEM VCC MEM VCC MEM VCC MEM AD VCC MEM VCC MEM VCC MEM VCC MEM VCC MEM VCC MEM AD AD11 VCC MEM VCC MEM VCC MEM VCC MEM VCC MEM VCC MEM VCC MEM VCC MEM VCC MEM VCC MEM AE MD63 GND MD59 GND GND GND AE11 VCC 25 VCC 25 VCC 25 VCC 25 VCC 25 VCC 25 VCC 25 VCC 25 VCC 25 VCC 25 SCAS B# SCAS A# MEM VREF AF SWE B# GND AG V- W9 Y AB9 AE AF MD62 MD58 DQS 7# AG MD57 MD61 DQM 7 SWE A# AH MD56 GND MD60 MD51 GND GND AH7 MAA 10 MAB 10 GND GND MAA 1 AF12 8 AJ MD55 MD50 MD54 GND AK DQS 6# DQM 6 MAB 11 SRAS B# MAA 11 MAA 12 NC AL MD53 GND MD52 MD49 GND MAB 12 MD45 MAB 0 CS7# CS6# 13 14 GND GND GND GND GND MAA 3 GND GND MAA 2 MAB 2 MECC 6 MECC 2 MAA 4 MD38 MD34 MAB 3 MD32 MECC 1 MAB 4 MD37 GND MECC 7 DQS 8# MD36 MECC 3 DQM 8 CS0# MD35 GND DQS 4# CS3# MD39 DQM 4 Revision 0.91, July 19, 2002 AA GND MAB 1 GND MD44 GND GND 13 DQS 5# MD41 GND GND GND MDLL DQM 5 CS1# GND GND 12 CS4# GND GND GND VCC MDLL MD40 MD43 GND GND 11 CS2# AN GND GND MEM VREF MD42 MD46 GND GND 10 CS5# MD47 AP 9 MAA 0 MD48 GND 15 16 17 18 VTT AA VTT VTT VCC 25 AB22 GND VCC MEM VCC 25 VCC MEM VCC MEM VCC MEM VCC MEM VCC MEM Y AC25 AE22 AE23 MD33 14 15 20 HA9 HA7 GND TT GND HA5 HREQ 1# GND HA11 GND HA16 HA8 HA14 HA13 HA10 HA VREF HA24 HA20 HA18 HA15 HA12 GND GND HA19 HA21 GND HA17 AF AF21 17 GND NC MEM VREF GND GND GND MAB 6 MAA 5 GND MAB 8 MAA 7 GND MD27 MAA 6 MAA 8 MD24 MAB 7 MAA 13 MAB 13 MD31 MAB 5 DQS 3# MD28 MD22 MAA 9 MAB 9 GND MECC 5 MD26 GND MD29 MD19 GND DQM 2 MECC 0 MECC 4 MD30 DQM 3 MD18 DQS 2# MD25 HREQ 3# 19 MD23 20 21 HA25 HA23 HA22 HA26 HA30 HA33 HA27 HA32 HA29 26 27 AH28 GND GND RSP# HAP 1 GND GND GND VCC MEM VCC MEM VCC MEM VCC MEM VCC MEM HAP 0 HA35 HA31 HA34 MAB 15 GCKE VCC MEM VCC MEM VCC MEM VCC MEM VCC MEM VCC MEM VCC MCK GND MCK MCLK GND VCC MEM VCC MEM VCC MEM VCC MEM VCC MEM VCC MEM VCC MEM VCC MEM MCLK FB MD1 VCC MEM VCC MEM VCC MEM VCC MEM VCC MEM TEST IN# MD6 DQS 0# GND MD4 VCC MEM VCC MEM VCC MEM VCC MEM MD7 DQM 0 MD0 VCC MEM VCC MEM VCC MEM VCC MEM 23 GND GND MEM VREF MAA 14 MAA 15 GND MAB 14 MD20 DQS 1# MD21 MD11 DQM 1 MD8 MD3 MD2 MD17 GND MD15 MD12 GND MD10 HA28 GND 25 22 MD16 GND HAS 1# AG 19 16 -5- 18 HA3 HAS 0# AC AD24 AB26 HA4 HA VREF AB AA GND AA Y HREQ 0# AE VTT HREQ 2# AD Y VCC 25 Mem Pins SRAS A# AM Y T26 24 MD14 MD13 MD9 MD5 Overview Technologies, Inc. P4X400 P4X400 Chipset ­ VT8754 VT8754 Pentium 4 DDR V-Link North Bridge We Connect Table 1. VT8754 VT8754 Pin List (Numerical Order) Pin # A01 A02 A03 A04 A05 A06 A07 A08 A09 A10 A11 A12 A13 A14 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 B04 B05 B07 B08 B10 B11 B13 B19 B20 B22 B23 B25 B26 B28 B29 B31 B32 B34 C04 C05 C06 C07 C08 C09 C10 C11 C12 C13 C14 C19 C20 C21 C22 C23 C24 C25 Pin Name IO IO IO IO IO IO IO IO IO I I I O I O IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO I I O IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO I I I I I IO IO IO IO IO IO IO GSTOP# GDEVSEL# GTRDY# GD18 GD17 GD19 GBE3# GD23 GD28 SBA5 SBA3 GRBF# GGNT# AGP8XDT# CPURST# HD62# HD63# HD55# HD51# HD48# HD43# HDBI2# HDS2# HD37# HDP0 HD26# HD28# HD30# HD22# HD19# HD20# GBE2# GD16 GD21 GD26 SBA7 SBA1 ST1 HD60# HD56# HD54# HD49# HD42# HDS2 HDP2 HD31# HDS1# HD16# HD21# GIRDY# GFRM# GD25 GD22 GDS1 / GDS1F GD29 SBA6 SBS# / SBSS SBA2 GPIPE# GREQ# HD61# HD57# HDS3 HD53# HD50# HD44# HD41# VCC25 VCC25 (50 pins): VCCMEM (86 pins): VCCAGP (43 pins): VCCVL (18 pins): VTT (60 pins): GND (199 pins): Pin # C26 C27 C28 C29 C30 C31 C32 C33 C34 D06 D07 D08 D09 D10 D11 D12 D13 D14 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 D32 D34 E07 E08 E10 E11 E13 E22 E23 E25 E26 E28 E29 E31 E32 E33 E34 F01 F10 F19 F24 F25 F28 F30 F32 F34 G01 G02 G30 G31 G32 G33 G34 H01 H30 H31 Pin Name IO IO IO IO IO IO IO IO IO IO IO IO IO IO I I I O IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO I O IO IO IO IO IO IO IO IO IO IO IO P P P P P IO IO IO IO IO IO IO IO IO IO IO P AI Pin # HD38# HD39# HD35# HD29# HDBI1# HDS1 HD23# HD17# HD18# GD20 GD27 GDS1# / GDS1S GD30 GDBIL SBS / SBSF SBA0 GWBF# ST0 HD58# HD59# HDS3# HD52# HD47# HD45# HD34# HD33# HD32# HDP3 HD25# HD24# HD07# HD14# HD15# GD24 GD31 GDBIH / GPIPE# SBA4 ST2 HDBI3# HD46# HD40# HD36# HDP1 HD27# HD10# HDS0# HD13# HD12# GSERR# AGPVREF HDVREF HDVREF GNDTT HDVREF HD11# HDS0 HD09# GD14 GBE1# HDBI0# HD03# HD08# HD02# HD06# GD12 HCMPVREF HRCOMP H32 H33 H34 J01 J02 J03 J29 J34 K01 K02 K03 K04 L01 L03 L04 L05 M01 M02 M03 M05 M06 N01 N02 N03 N04 N05 N06 P01 P03 P04 P05 P34 R01 R02 R03 R34 T01 T02 T03 T04 T05 T29 T30 T31 T32 T34 U01 U03 U04 U05 U06 U29 U30 U31 U32 U33 U34 V01 V02 V03 V05 V29 V30 V31 V32 V33 V34 Pin Name IO IO IO IO IO IO P IO IO IO IO IO IO IO IO IO IO IO IO IO P IO IO IO IO I P IO IO P AI O IO IO IO IO I I O O O I P P IO I IO IO IO IO AI I P P IO IO IO I I P P P IO IO IO I IO Pin # HD05# HD04# HD01# GD8 GD10 GPAR HDVREF HD00# GBE0# GD7 GDS0 / GDS0F GDS0# / GDS0S GD6 GD5 GD11 GD15 GD2 GD4 GD0 GD13 AGPVREF GD1 VAD4 / strap GD3 GD9 GCLK VCCQQ VAD5 / strap VPAR GNDQQ AGPCOMP NMI VBE# VAD1 / strap VAD0 / strap BPRI# UPSTB# UPSTB DNSTB# DNSTB DNCMD HCLK# VCCHCK1 GNDHCK1 DEFER# HITM# VAD6 / strap VAD7 / strap VAD3 / strap VAD2 / strap VLCOMP HCLK VCCHCK2 GNDHCK2 RS2# RS0# HIT# SUSST# UPCMD VLVREF VSUS25 VSUS25 GTLVREF RS1# BNR# DBSY# HLOCK# ADS# W01 W03 W31 W32 W34 Y30 Y31 Y32 Y33 Y34 AA29 AA30 AA31 AA32 AA33 AA34 AB29 AB31 AB32 AB34 AC30 AC31 AC32 AC33 AC34 AD29 AD30 AD31 AD32 AD33 AD34 AE01 AE03 AE31 AE32 AE34 AF01 AF02 AF03 AF04 AF05 AF06 AF30 AF31 AF32 AF33 AF34 AG01 AG02 AG03 AG04 AG05 AG30 AG31 AG32 AG33 AG34 AH01 AH03 AH04 AH31 AH32 AH34 AJ01 AJ02 AJ03 AJ05 Pin Name I I IO O IO IO IO IO IO IO P IO IO IO IO IO P IO IO IO IO IO IO IO IO P IO IO IO IO IO IO IO IO IO IO IO IO IO O O P IO IO IO IO IO IO IO O O O IO IO IO IO IO IO IO IO O IO IO IO IO IO O Pin # RESET# PWROK HTRDY# BREQ# DRDY# HA04 HREQ2# HA03 HREQ0# HREQ4# HAVREF HAS0# HREQ3# HA09 HA07 HA06 GNDTT HA05 HREQ1# HA11 HA16 HA08 HA14 HA13 HA10 HAVREF HA24 HA20 HA18 HA15 HA12 MD63 MD59 HA19 HA21 HA17 MD62 MD58 DQS7# / CKE7 SCASB# SCASA# MEMVREF HA28 HAS1# HA25 HA23 HA22 MD57 MD61 DQM7 / CKE7 SWEA# SWEB# HA26 HA30 HA33 HA27 HA32 MD56 MD60 MD51 RSP# HAP1 HA29 MD55 MD50 MD54 SRASA# AJ06 AJ07 AJ11 AJ12 AJ13 AJ16 AJ17 AJ23 AJ31 AJ32 AJ33 AJ34 AK01 AK02 AK03 AK04 AK05 AK06 AK07 AK09 AK12 AK15 AK16 AK18 AK19 AK21 AK22 AK24 AK25 AK32 AK33 AK34 AL01 AL03 AL04 AL06 AL07 AL08 AL09 AL10 AL11 AL12 AL13 AL14 AL15 AL16 AL17 AL18 AL19 AL20 AL21 AL22 AL23 AL24 AL34 AM01 AM02 AM03 AM04 AM05 AM06 AM07 AM08 AM09 AM10 AM11 AM12 Pin Names O O P P P P P IO IO IO IO IO O O O O O ­ O O O O O O O O O O P P O IO IO IO O IO O O O O IO IO O IO O O IO O O O O IO IO I IO IO IO O IO O IO O IO IO O IO Pin # MAA10 MAA10 MAB10 MAB10 MEMVREF VCCMDLL GNDMDLL NC MEMVREF MEMVREF HAP0 HA35 HA31 HA34 DQS6# / CKE6 DQM6 / CKE6 MAB11 MAB11 SRASB# MAA11 MAA11 MAA12 MAA12 NC MAB01 MAB01 MAA03 MAA03 MAB06 MAB06 MAA05 MAA05 MAB08 MAB08 MAA07 MAA07 MAA14 MAA14 MAA15 MAA15 MAB15 MAB15 GCKE VCCMCK GNDMCK MCLK MD53 MD52 MD49 MAB12 MAB12 MD45 MAB00 MAB00 MAA01 MAA01 MAA02 MAA02 MAB02 MAB02 MECC6 / CKE6 MECC2 / CKE2 MAA04 MAA04 MD27 MAA06 MAA06 MAA08 MAA08 MD24 MAB07 MAB07 MAA13 MAA13 MAB13 MAB13 MAB14 MAB14 MD20 DQS1# / CKE1 MCLKF MD48 MD47 MD46 CS5# MD42 CS2# MD40 MAA00 MAA00 MD38 MD34 MAB03 MAB03 MD32 AM13 AM14 AM15 AM16 AM17 AM18 AM19 AM21 AM22 AM23 AM24 AM25 AM26 AM27 AM28 AM30 AM34 AN01 AN03 AN04 AN06 AN07 AN09 AN10 AN12 AN13 AN15 AN16 AN18 AN19 AN21 AN22 AN24 AN25 AN27 AN28 AN30 AP01 AP02 AP03 AP04 AP05 AP06 AP07 AP08 AP09 AP10 AP11 AP12 AP13 AP14 AP15 AP16 AP17 AP18 AP19 AP20 AP21 AP22 AP23 AP24 AP25 AP26 AP27 AP28 AP29 AP30 Pin Name IO O IO O IO IO IO O IO IO O IO IO IO IO O I IO O IO O IO IO IO IO IO IO IO IO IO O IO IO IO IO IO IO O O O O O IO IO IO O IO IO IO O IO IO IO O IO IO IO IO IO IO IO IO IO IO O IO IO MECC1 / CKE1 MAB04 MAB04 MD31 MAB05 MAB05 DQS3# / CKE3 MD28 MD22 MAB09 MAB09 MD21 MD11 DQM1 / CKE1 MD08 MD03 MD02 MD01 MAA09 MAA09 TESTIN# MD43 CS4# DQS5# / CKE5 CS0# MD35 DQS4# / CKE4 MD37 MECC7 / CKE7 DQS8# MECC5 / CKE5 MD26 MD29 MD19 DQM2 / CKE2 MD17 MD15 MD12 MD06 DQS0# / CKE0 MD04 CS7# CS6# CS3# DQM5 / CKE5 CS1# MD41 MD44 MD39 DQM4 / CKE4 MD33 MD36 MECC3 / CKE3 DQM8 MECC0 / CKE0 MECC4 / CKE4 MD30 DQM3 / CKE3 MD25 MD23 MD18 DQS2# / CKE2 MD16 MD10 MD14 MD13 MD09 MD07 DQM0 / CKE0 MD05 MD00 A15-17 A15-17, B15-17 B15-17, C15-17 C15-17, D15-17 D15-17, E14-17 E14-17, F14-17 F14-17, K12-14 K12-14,18-22, P10, R10, T10,25, U25, V25, W10,25, Y25, AA25, AB10,25, AE12-21 AE12-21 V12, W11-12 W11-12, Y11-12 Y11-12, AA11-12 AA11-12, AB1-6,11-12,24, AC1-6,11-24, AD1-6,12-23, AJ26-30 AJ26-30, AK26-31 AK26-31, AL26-33 AL26-33, AM29-33 AM29-33, AN31-34 AN31-34, AP31-34 AP31-34 B1, C1-2, D1-3, E1-4, F2-5, G3-6, H4-6, J5-6, K6, L12-17 L12-17, M11-17 M11-17, N11-12 N11-12, P11-12 P11-12, R11-12 R11-12 T11-12 T11-12, U11-12 U11-12, V11, W6, Y1-6, AA1-6 K29-34 K29-34, L18-23 L18-23,29-34, M18-24 M18-24,29-34, N23-24 N23-24,29-34, P23-24 P23-24,29-33, R23-24 R23-24, T23-24 T23-24, U23-24 U23-24, V23-24 V23-24, W23-24 W23-24, Y23-24 Y23-24, AA23-24 AA23-24 B2-3,6,9,12,14,18,21,24,27,30,33, C3,18, D4-5,18,33, E5-6,9,12,18-21,24,27,30, F6-9,11-13,18,20-23,26-27,29,31,33, G29, H2-3,29, J4,30-33, K5, L2,6, M4, P2,6,14-21, R4-6,14-21,29-33, T6,14-21,33, U2,14-21, V4,6,14-21, W2,4-5,14-21,29-30,33, Y14-21 Y14-21,29, AA14-21 AA14-21, AB23,30,33, AC29, AE2,4-6,29-30,33, AF29, AG6,29, AH2,5-6,29-30,33, AJ4,8-10,14-15,18-22,24-25, AK8,10-11,13-14,17,20,23, AL2,5,25, AN2,5,8,11,14,17,20,23,26,29 Revision 0.91, July 19, 2002 -6- Pin Lists Technologies, Inc. P4X400 P4X400 Chipset ­ VT8754 VT8754 Pentium 4 DDR V-Link North Bridge We Connect Table 2. VT8754 VT8754 Pin List (Alphabetical Order) Pin # V34 A14 P05 F10 M06 V31 R34 W32 A18 AN06 AP05 AM06 AP03 AN03 AM04 AP02 AP01 V32 T32 T05 T04 T03 AP28 AM24 AN21 AP17 AP09 AP04 AK02 AG03 AP13 AN28 AL24 AP21 AM17 AN09 AN04 AK01 AF03 AN13 W34 K01 G02 B04 A07 AK25 N05 M03 N01 M01 N03 M02 L03 L01 K02 J01 N04 J02 L04 H01 M05 G01 L05 B05 A05 A04 A06 Pin Name IO I AI P P IO IO O O O O O O O O O O IO IO O O O O O O O O O O O O IO IO IO IO IO IO IO IO IO IO IO IO IO IO O I IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO Pin # ADS# AGP8XDT# AGPCOMP AGPVREF AGPVREF BNR# BPRI# BREQ# CPURST# CS0# CS1# CS2# CS3# CS4# CS5# CS6# CS7# DBSY# DEFER# DNCMD DNSTB DNSTB# DQM0 / CKE0 DQM1 / CKE1 DQM2 / CKE2 DQM3 / CKE3 DQM4 / CKE4 DQM5 / CKE5 DQM6 / CKE6 DQM7 / CKE7 DQM8 DQS0# / CKE0 DQS1# / CKE1 DQS2# / CKE2 DQS3# / CKE3 DQS4# / CKE4 DQS5# / CKE5 DQS6# / CKE6 DQS7# / CKE7 DQS8# DRDY# GBE0# GBE1# GBE2# GBE3# GCKE GCLK GD0 GD1 GD2 GD3 GD4 GD5 GD6 GD7 GD8 GD9 GD10 GD11 GD12 GD13 GD14 GD15 GD16 GD17 GD18 GD19 D06 B07 C07 A08 E07 C06 B08 D07 A09 C09 D09 E08 E10 D10 K03 K04 C08 D08 A02 C05 A13 C04 T31 U31 AK33 AJ13 P04 F25 AB29 J03 C13 A12 C14 F01 A01 V29 A03 D13 Y32 Y30 AB31 AA34 AA33 AC31 AA32 AC34 AB34 AD34 AC33 AC32 AD33 AC30 AE34 AD32 AE31 AD31 AE32 AF34 AF33 AD30 AF32 AG30 AG33 AF30 AH34 AG31 AJ33 VCC25 VCC25 (50 pins): VCCMEM (86 pins): VCCAGP (43 pins): VCCVL (18 pins): VTT (60 pins): GND (199 pins): Pin Name IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO O IO P P P P P P P IO I I I IO IO P IO I IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO Pin # GD20 GD21 GD22 GD23 GD24 GD25 GD26 GD27 GD28 GD29 GD30 GD31 GDBIH / GPIPE# GDBIL GDS0 / GDS0F GDS0# / GDS0S GDS1 / GDS1F GDS1# / GDS1S GDEVSEL# GFRM# GGNT# GIRDY# GNDHCK1 GNDHCK2 GNDMCK GNDMDLL GNDQQ GNDTT GNDTT GPAR GPIPE# GRBF# GREQ# GSERR# GSTOP# GTLVREF GTRDY# GWBF# HA03 HA04 HA05 HA06 HA07 HA08 HA09 HA10 HA11 HA12 HA13 HA14 HA15 HA16 HA17 HA18 HA19 HA20 HA21 HA22 HA23 HA24 HA25 HA26 HA27 HA28 HA29 HA30 HA31 AG34 AG32 AJ34 AJ32 AJ31 AH32 AA30 AF31 AA29 AD29 U29 T29 H30 J34 H34 G33 G31 H33 H32 G34 D31 G32 F34 E31 F30 E34 E33 D32 D34 B32 C33 C34 A33 A34 B34 A32 C32 D30 D29 A29 E29 A30 C29 A31 B29 D27 D26 D25 C28 E26 A27 C26 C27 E25 C25 B25 A24 C24 D24 E23 D23 A23 B23 C23 A22 D22 C22 Pin Name IO IO IO IO IO IO IO IO P P I I P IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO Pin # HA32 HA33 HA34 HA35 HAP0 HAP1 HAS0# HAS1# HAVREF HAVREF HCLK HCLK# HCMPVREF HD00# HD01# HD02# HD03# HD04# HD05# HD06# HD07# HD08# HD09# HD10# HD11# HD12# HD13# HD14# HD15# HD16# HD17# HD18# HD19# HD20# HD21# HD22# HD23# HD24# HD25# HD26# HD27# HD28# HD29# HD30# HD31# HD32# HD33# HD34# HD35# HD36# HD37# HD38# HD39# HD40# HD41# HD42# HD43# HD44# HD45# HD46# HD47# HD48# HD49# HD50# HD51# HD52# HD53# B22 A21 B20 C20 D19 D20 B19 C19 A19 A20 G30 C30 A25 E22 A28 E28 B28 D28 F32 E32 C31 B31 B26 A26 C21 D21 F19 F24 F28 J29 U34 T34 V33 H31 Y33 AB32 Y31 AA31 Y34 W31 AM08 AL09 AL10 AK12 AL14 AK16 AL16 AK19 AL17 AM30 AJ06 AK05 AK06 AL20 AK21 AK22 AL08 AK09 AL11 AM11 AM14 AM16 AK15 AL19 AK18 AM21 AJ07 Pin Name IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO P P P P IO I I AI IO IO IO IO IO IO O O O O O O O O O O O O O O O O O O O O O O O O O O O Pin # HD54# HD55# HD56# HD57# HD58# HD59# HD60# HD61# HD62# HD63# HDBI0# HDBI1# HDBI2# HDBI3# HDP0 HDP1 HDP2 HDP3 HDS0 HDS0# HDS1 HDS1# HDS2 HDS2# HDS3 HDS3# HDVREF HDVREF HDVREF HDVREF HIT# HITM# HLOCK# HRCOMP HREQ0# HREQ1# HREQ2# HREQ3# HREQ4# HTRDY# MAA00 MAA00 MAA01 MAA01 MAA02 MAA02 MAA03 MAA03 MAA04 MAA04 MAA05 MAA05 MAA06 MAA06 MAA07 MAA07 MAA08 MAA08 MAA09 MAA09 MAA10 MAA10 MAA11 MAA11 MAA12 MAA12 MAA13 MAA13 MAA14 MAA14 MAA15 MAA15 MAB00 MAB00 MAB01 MAB01 MAB02 MAB02 MAB03 MAB03 MAB04 MAB04 MAB05 MAB05 MAB06 MAB06 MAB07 MAB07 MAB08 MAB08 MAB09 MAB09 MAB10 MAB10 AK03 AL06 AL21 AL22 AK24 AK34 AL34 AP30 AM28 AM27 AM26 AN30 AP29 AN27 AP27 AM25 AP26 AP23 AM23 AN25 AP25 AP24 AN24 AP22 AN22 AP20 AN19 AL23 AM22 AM19 AP19 AL18 AP18 AN16 AL15 AM18 AN18 AP16 AM15 AM12 AP10 AM10 AN07 AP11 AN10 AM09 AP08 AM07 AP06 AM05 AN01 AP07 AL07 AM03 AM02 AM01 AL04 AJ02 AH04 AL03 AL01 AJ03 AJ01 AH01 AG01 AF02 AE03 Pin Names O O O O O O I IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO Pin # MAB11 MAB11 MAB12 MAB12 MAB13 MAB13 MAB14 MAB14 MAB15 MAB15 MCLK MCLKF MD00 MD01 MD02 MD03 MD04 MD05 MD06 MD07 MD08 MD09 MD10 MD11 MD12 MD13 MD14 MD15 MD16 MD17 MD18 MD19 MD20 MD21 MD22 MD23 MD24 MD25 MD26 MD27 MD28 MD29 MD30 MD31 MD32 MD33 MD34 MD35 MD36 MD37 MD38 MD39 MD40 MD41 MD42 MD43 MD44 MD45 MD46 MD47 MD48 MD49 MD50 MD51 MD52 MD53 MD54 MD55 MD56 MD57 MD58 MD59 AH03 AG02 AF01 AE01 AP14 AM13 AL13 AP12 AP15 AN15 AL12 AN12 AF06 AJ11 AJ17 AJ23 AK07 AJ16 P34 W03 W01 U33 V30 U32 AH31 D12 B11 C12 A11 E11 A10 C10 B10 D11 C11 AF05 AF04 AJ05 AK04 D14 B13 E13 V01 AG04 AG05 AM34 V02 T02 T01 R03 R02 U05 U04 N02 P01 U01 U03 R01 T30 U30 AK32 AJ12 N06 U06 V03 P03 V05 Pin Name IO IO IO IO IO IO IO IO IO IO IO IO P P P P ­ ­ O I I IO IO IO O I I I I I I I I I I O O O O O O O I O O I I I I IO IO IO IO IO IO IO IO IO P P P P P AI P IO P MD60 MD61 MD62 MD63 MECC0 / CKE0 MECC1 / CKE1 MECC2 / CKE2 MECC3 / CKE3 MECC4 / CKE4 MECC5 / CKE5 MECC6 / CKE6 MECC7 / CKE7 MEMVREF MEMVREF MEMVREF MEMVREF NC NC NMI PWROK RESET# RS0# RS1# RS2# RSP# SBA0 SBA1 SBA2 SBA3 SBA4 SBA5 SBA6 SBA7 SBS / SBSF SBS# / SBSS SCASA# SCASB# SRASA# SRASB# ST0 ST1 ST2 SUSST# SWEA# SWEB# TESTIN# UPCMD UPSTB UPSTB# VAD0 / strap VAD1 / strap VAD2 / strap VAD3 / strap VAD4 / strap VAD5 / strap VAD6 / strap VAD7 / strap VBE# VCCHCK1 VCCHCK2 VCCMCK VCCMDLL VCCQQ VLCOMP VLVREF VPAR VSUS25 VSUS25 A15-17 A15-17, B15-17 B15-17, C15-17 C15-17, D15-17 D15-17, E14-17 E14-17, F14-17 F14-17, K12-14 K12-14,18-22, P10, R10, T10,25, U25, V25, W10,25, Y25, AA25, AB10,25, AE12-21 AE12-21 V12, W11-12 W11-12, Y11-12 Y11-12, AA11-12 AA11-12, AB1-6,11-12,24, AC1-6,11-24, AD1-6,12-23, AJ26-30 AJ26-30, AK26-31 AK26-31, AL26-33 AL26-33, AM29-33 AM29-33, AN31-34 AN31-34, AP31-34 AP31-34 B1, C1-2, D1-3, E1-4, F2-5, G3-6, H4-6, J5-6, K6, L12-17 L12-17, M11-17 M11-17, N11-12 N11-12, P11-12 P11-12, R11-12 R11-12 T11-12 T11-12, U11-12 U11-12, V11, W6, Y1-6, AA1-6 K29-34 K29-34, L18-23 L18-23,29-34, M18-24 M18-24,29-34, N23-24 N23-24,29-34, P23-24 P23-24,29-33, R23-24 R23-24, T23-24 T23-24, U23-24 U23-24, V23-24 V23-24, W23-24 W23-24, Y23-24 Y23-24, AA23-24 AA23-24 B2-3,6,9,12,14,18,21,24,27,30,33, C3,18, D4-5,18,33, E5-6,9,12,18-21,24,27,30, F6-9,11-13,18,20-23,26-27,29,31,33, G29, H2-3,29, J4,30-33, K5, L2,6, M4, P2,6,14-21, R4-6,14-21,29-33, T6,14-21,33, U2,14-21, V4,6,14-21, W2,4-5,14-21,29-30,33, Y14-21 Y14-21,29, AA14-21 AA14-21, AB23,30,33, AC29, AE2,4-6,29-30,33, AF29, AG6,29, AH2,5-6,29-30,33, AJ4,8-10,14-15,18-22,24-25, AK8,10-11,13-14,17,20,23, AL2,5,25, AN2,5,8,11,14,17,20,23,26,29 Revision 0.91, July 19, 2002 -7- Pin Lists Technologies, Inc. P4X400 P4X400 Chipset ­ VT8754 VT8754 Pentium 4 DDR V-Link North Bridge We Connect Pin Descriptions Table 3. VT8754 VT8754 / P4X400 P4X400 Pin Descriptions CPU Interface Signal Name Pin # I/O Signal Description HA[35:3]# (see pinout tables) IO HAP[1:0] HAS[1:0]# AH32, AJ31 AF31, AA30 IO IO HD[63:0]# (see pinout tables) D28, B28, E28, A28 E22, A25, C30, G30 IO Host CPU Address Bus. Connect to the address bus of the host CPU. Inputs during CPU cycles and driven by the VT8754 VT8754 during cache snooping operations. Address signals up through HA[35] allow support of a 64 Gbyte memory space. Host CPU Addres Parity. Host CPU Address Strobe. Source synchronous strobes used to transfer HA[31:3]# and HREQ[4:0]# at a 2x transfer rate. HAS1# is the strobe for HA[31:17]# and HAS0# is the strobe for HA[16:3] and HREQ[4:0]#. Host CPU Data. These signals are connected to the CPU data bus. IO Host Data Parity. HDP[3:0] Host CPU Dynamic Bus Inversion. Driven along with HD[63:0]# to indicate if the associated signals are inverted or not. Used to limit the number of simultaneously switching signals to 8 for the associated 16-bit data pin group (HDBI3# for HD[63:48]#, HDBI2# for HD[47:32]#, HDBI1# for HD[31:16]#, and HDBI0# for HD[15:0]#). HDBIn# is asserted such that the number of data bits driven low for the corresponding group does not exceed 8. C21, B26, IO Host CPU Differential Data Strobes. Source synchronous strobes used to transfer HDS[3:0] C31, F32 HD[63:0]# and HDBI[3:0]# at a 4x transfer rate. HDS3 / HDS3# are the strobes for HD[63:48]# and HDBI3#; HDS2 / HDS2# are the strobes for HD[47:32]# and D21, A26, HDBI2#; HDS1 / HDS1# are the strobes for HD[31:16]# and HDBI1#; and HDS0 / HDS[3:0]# B31, E32 HDS0# are the strobes for HD[15:0]# and HDBI0#. V34 IO Address Strobe. The CPU asserts ADS# in T1 of the CPU bus cycle. ADS# V32 IO Data Bus Busy. Used by the data bus owner to hold the data bus for transfers requiring DBSY# more than one cycle. W34 IO Data Ready. Asserted for each cycle that data is transferred. DRDY# U34 IO Hit. Indicates that a caching agent holds an unmodified version of the requested line. HIT# Also driven in conjunction with HITM# by the target to extend the snoop window. T34 I Hit Modified. Asserted by the CPU to indicate that the address is modified in the L1 HITM# cache and needs to be written back. V33 I Host Lock. All CPU cycles sampled with the assertion of HLOCK# and ADS# until HLOCK# the negation of HLOCK# must be atomic. Y34, AA31, IO Request Command. Asserted during both clocks of the request phase. In the first HREQ[4:0]# Y31, AB32, clock, the signals define the transaction type to a level of detail that is sufficient to Y33 begin a snoop request. In the second clock, the signals carry additional information to define the complete transaction type. W31 IO Host Target Ready. Indicates that the target of the processor transaction is able to HTRDY# enter the data transfer phase. Note: Clocking of the CPU interface is performed with HCLK and HCLK# (see clock pin description group). Note: Internal pullup resistors are provided on all AGTL+ interface pins. If the CPU does not have internal pullups, these north bridge internal pullups may be enabled to allow the interface to meet AGTL+ bus interface specifications (see VAD3 strap). HDBI[3:0]# Revision 0.91, July 19, 2002 IO -8- Pin Descriptions Technologies, Inc. P4X400 P4X400 Chipset ­ VT8754 VT8754 Pentium 4 DDR V-Link North Bridge We Connect CPU Interface (continued) Signal Name Pin # I/O Signal Description RS[2:0]# U32, V30, U33 IO RSP# BREQ# BPRI# AH31 W32 R34 O O IO BNR# V31 IO DEFER# T32 IO CPURST# A18 O Response Signals. Indicates the type of response per the table below: RS[2:0]# Response type RS[2:0]# Response type 000 Idle State 100 Hard Failure 001 Retry Response 101 Normal Without Data 010 Defer Response 110 Implicit Writeback 011 Reserved 111 Normal With Data Response Parity. Bus Request. Bus request output to CPU. Priority Agent Bus Request. The owner of this signal will always be the next bus owner. This signal has priority over symmetric bus requests and causes the current symmetric owner to stop issuing new transactions unless the HLOCK# signal is asserted. The VT8754 VT8754 drives this signal to gain control of the processor bus. Block Next Request. Used to block the current request bus owner from issuing new requests. This signal is used to dynamically control the processor bus pipeline depth. Defer. The VT8754 VT8754 uses a dynamic deferring policy to optimize system performance. The VT8754 VT8754 also uses the DEFER# signal to indicate a processor retry response. CPU Reset. Reset output to CPU. External pullup and filter capacitor to ground should be provided per CPU manufacturer's recommendations. The pinouts were defined assuming the ATX PCB layout model shown below (and general pin layout shown) as a guide for PCB component placement. Other PCB layouts (AT, LPX, and NLX) were also considered and can typically follow the same general component placement. Power Supply Pentium 4 CPU PCI Slots AGP Slot 1 34 A AGP VT8235 VT8235 V-Link South Bridge IDE Connectors Revision 0.91, July 19, 2002 CPU VT 8754 VL DRAM . AP DRAM Modules -9- Pin Descriptions Technologies, Inc. P4X400 P4X400 Chipset ­ VT8754 VT8754 Pentium 4 DDR V-Link North Bridge We Connect DRAM Interface Signal Name Pin # I/O Signal Description (see pin lists) IO AN12, AL12, AN15, AP15, AP12, AL13, AM13, AP14 IO MAA[15:0] (see pin lists) O MAB[15:0] (see pin lists) O SRASA#, SCASA#, SWEA# AJ5, AF5, AG4 O SRASB#, SCASB#, SWEB# AK4, AF4, AG5 O AP1, AP2, AM4, AN3, AP3, AM6, AP5, AN6 AP13, AG3, AK2, AP4, AP9, AP17, AN21, AM24, AP28 AN13, AF3, AK1, AN4, AN9, AM17, AP21, AL24, AN28 (see above) O Memory Data. These signals are connected to the DRAM data bus. Output drive strength may be set by Device 0 RxE8. DRAM ECC or EC Data: when ECC is enabled. Clock Enables: For each DRAM bank for powering down the SDRAMs in notebook applications. Also used in desktop systems for clock control to reduce power usage and for reducing heat/temperature in high-speed memory systems. Memory Address A. DRAM address lines (two sets for better drive). Output drive strength may be set by Device 0 RxEA. Memory Address B. DRAM address lines (two sets for better drive). Output drive strength may be set by Device 0 RxEB. Row Address, Column Address and Write Enable Command Indicator Set A. (two sets for better drive). Output drive strength may be set by Device 0 RxEA. Row Address, Column Address and Write Enable Command Indicator Set B. (two sets for better drive). Output drive strength may be set by Device 0 RxEB. Chip Select. Chip select of each bank. Output drive strength may be set by Device 0 RxE9. Data Mask. Data mask of each byte lane plus DQM8 for ECC byte. Output drive strength may be set by Device 0 RxE8. DDR Data Strobe. Data strobe of each byte lane plus DQS8# for ECC byte. Output drive strength may be set by Device 0 RxE8. Clock Enables. Clock enables for each DRAM bank for powering down the SDRAM or clock control for reducing power usage and for reducing heat / temperature in highspeed memory systems. See Device 0 RxBD[6] for CKE function enable. Global Clock Enable. No Connect. Reserved for future use. MD[63:0] MECC[7:0] / CKE[7:0] CS[7:0]# DQM[8], DQM[7:0] / CKE[7:0] DQS[8], DQS[7:0]# / CKE[7:0] CKE[7:0] / MECC[7:0] -orCKE[7:0] / DQM[7:0] -orCKE[7:0] / DQS[7:0]# GCKE NC Revision 0.91, July 19, 2002 AK25 AJ16, AK7 O IO O O ­ -10- Pin Descriptions Technologies, Inc. P4X400 P4X400 Chipset ­ VT8754 VT8754 Pentium 4 DDR V-Link North Bridge We Connect AGP Bus Interface Signal Name Pin # I/O Signal Description GD[31:0] IO (GBE[3:0] for 8x mode) (see pinlist) A7, B4, G2, K1 GPAR GDBIH / GPIPE#, GDBIL J3 E10 D10 IO IO GDS0 (GDS0F for 8x), GDS0# (GDS0S for 8x) GDS1 (GDS1F for 8x), GDS1# (GDS1S for 8x) GFRM# (GFRM for 8x) GIRDY# (GIRDY for 8x) K3 IO Address / Data Bus. Address is driven with GDS assertion for AGP-style transfers and with GFRM# assertion for PCI-style transfers. Command / Byte Enable. (Interpreted as C/BE# for AGP 2x/4x and C#/BE for 8x) AGP: These pins provide command information (different commands than for PCI) driven by the master (graphics controller) when requests are being enqueued using GPIPE# (2x/4x only as GPIPE# isn't used in 8x mode). These pins provide valid byte information during AGP write transactions and are driven by the master. The target (this chip) drives these lines to "0000" during the return of AGP read data. PCI: Commands are driven with GFRM# assertion. Byte enables corresponding to supplied or requested data are driven on following clocks. AGP Parity. A single parity bit is provided over GD[31:0] and GBE[3:0]. Dynamic Bus Inversion High / Low. AGP 8x transfer mode only. Driven by the source to indicate whether the corresponding data bit group (GDBIH for GD[31:16] and GDBIL for GD[15:0]) needs to be inverted on the receiving end (1 on GDBIx indicates that the corresponding data bit group should be inverted). Used to limit the number of simultaneously switching outputs to 8 for each 16-pin group. Bus Strobe 0. Source synchronous strobes for GD[15:0] (the agent that is providing the data drives these signals). GDS0 provides timing for 2x data transfer mode; GDS0 and GDS0# provide timing for 4x transfer mode. For 8x transfer mode, GDS0 is interpreted as GDS0F ("First" strobe) and GDS0# as GDS0S ("Second" strobe). Bus Strobe 1. Source synchronous strobes for GD[31:16] (i.e., the agent that is providing the data drives these signals). GDS1 provides timing for 2x data transfer mode; GDS1 and GDS1# provide timing for 4x transfer mode. For 8x transfer mode, GDS1 is interpreted as GDS1F ("First" strobe) and GDS1# as GDS1S ("Second" strobe). Frame. Assertion indicates the address phase of a PCI transfer. Negation indicates that one more data transfer is desired by the cycle initiator. Interpreted as active high for 8x. Initiator Ready. (Interpreted as active low for PCI/AGP2x/4x and high for AGP 8x) AGP: For write operations, the assertion of this pin indicates that the master is ready to provide all write data for the current transaction. Once this pin is asserted, the master is not allowed to insert wait states. For read operations, the assertion of this pin indicates that the master is ready to transfer a subsequent block of read data. The master is never allowed to insert a wait state during the initial block of a read transaction. However, it may insert wait states after each block transfers. PCI: Asserted when the initiator is ready for data transfer. Target Ready. (Interpreted as active low for PCI/AGP2x/4x and high for AGP 8x) AGP: Indicates that the target is ready to provide read data for the entire transaction (when the transaction can complete within four clocks) or is ready to transfer a (initial or subsequent) block of data when the transfer requires more than four clocks to complete. The target is allowed to insert wait states after each block transfer for both read and write transactions. PCI: Asserted when the target is ready for data transfer. Stop (PCI transactions only). Asserted by the target to request the master to stop the current transaction. Interpreted as active high for AGP 8x. Device Select (PCI transactions only). This signal is driven by the VT8754 VT8754 when a PCI initiator is attempting to access main memory. It is an input when the VT8754 VT8754 is acting as PCI initiator. Not used for AGP cycles. Interpreted as active high for AGP 8x. Pipelined Request. Asserted by the master (the external graphics controller) to indicate that a full-width request is to be enqueued by the target VT8754 VT8754. The master enqueues one request each rising edge of GCLK while GPIPE# is asserted. When GPIPE# is deasserted no new requests are enqueued across the AD bus. Not used by AGP 8x. GBE[3:0]# IO K4 C8 IO D8 C5 IO C4 IO GTRDY# (GTRDY for 8x) A3 IO GSTOP# (GSTOP for 8x) GDEVSEL# (GDEVSEL for 8x mode) GPIPE# (GPIPE for 8x) A1 IO A2 IO C13 I Revision 0.91, July 19, 2002 -11- Pin Descriptions Technologies, Inc. P4X400 P4X400 Chipset ­ VT8754 VT8754 Pentium 4 DDR V-Link North Bridge We Connect AGP Bus Interface (continued) Signal Name Pin # I/O AGP8DT# A14 I GRBF# (GRBF for 8x) A12 I GWBF# (GWBF for 8x) SBA[7:0] (SBA[7:0]# for 8x) D13 I B10, C10, A10, E11, A11, C12, B11, D12 D11 C11 I SideBand Address. Provides an additional bus to pass address and command information from the master (graphics controller) to the target (VT8754 VT8754 north bridge logic). These pins are ignored until enabled. I E13, B13, D14 O C14 I Sideband Strobe. Driven by the master to provide timing for SBA[7:0]. SBS is used for AGP 2x while SBS and SBS# are used together for AGP 4x. For 8x mode, the strobe mechanism works differently with SBS interpreted as SBSF ("First" strobe) and SBS# as SBSS ("Second" strobe). Status (AGP only). Provides information from the arbiter to a master to indicate what it may do. Only valid while GGNT# is asserted. 000 Indicates that previously requested low priority read or flush data is being returned to the master (graphics controller). 001 Indicates that previously requested high priority read data is being returned to the master. 010 Indicates that the master is to provide low priority write data for a previously enqueued write command. 011 Indicates that the master is to provide high priority write data for a previously enqueued write command. 100 Reserved. (arbiter must not issue, may be defined in the future). 101 Reserved. (arbiter must not issue, may be defined in the future). 110 Reserved. (arbiter must not issue, may be defined in the future). 111 Indicates that the master (graphics controller) has been given permission to start a bus transaction. The master may enqueue AGP requests by asserting PIPE# or start a PCI transaction by asserting GFRM#. ST[2:0] are always outputs from the target (north bridge logic) and inputs to the master (graphics controller). Request. Master (graphics controller) request for use of the AGP bus. A13 O Grant. Permission is given to the master (graphics controller) to use the AGP bus. F1 IO AGP System Error. SBS (SBSF for 8x), SBS# (SBSS for 8x) ST[2:0] GREQ# (GREQ for 8x) GGNT# (GGNT for 8x) GSERR# Note: Note: Note: Note: Note: Note: Signal Description AGP 8x Transfer Mode Detect. Low indicates that the external graphics card can support 8x transfer mode Read Buffer Full. Indicates if the master (graphics controller) is ready to accept previously requested low priority read data. When GRBF# is asserted, the VT8754 VT8754 will not return low priority read data to the graphics controller. Write Buffer Full. For PCI operation on the AGP bus, the following pins are not required: - PERR# (parity and error reporting not required on transient data devices such as graphics controllers) - LOCK# (no lock requirement on AGP) - IDSEL (internally connected to AD16 on AGP-compliant masters) Separate system interrupts are not provided for AGP. The AGP connector provides interrupts via PCI bus INTA-B#. The AGP bus supports only one master directly (REQ[3:0]# and GNT[3:0]# are not provided). External logic is required to implement additional master capability. Note that the arbitration mechanism on the AGP bus is different from the PCI bus. A separate reset is not required for the AGP bus (RESET# resets both PCI and AGP buses) Two mechanisms are provided by the AGP bus to enqueue master requests: GPIPE# (to send addresses multiplexed on the AD lines) and the SBA port (to send addresses unmultiplexed). AGP masters implement one or the other or select one at initialization time (they are not allowed to change during runtime). Only one of the two will be used; the signals associated with the other will not be used. GRBF# has an internal pullup to maintain it in the deasserted state in case it is not implemented on the master device. AGP 8x mode allows only SBA (GPIPE# isn't used in 8x mode). AGP 8x signal levels are 0V and 0.8V. AGP 8x mode maintains most signals at a low level when inactive resulting in no current flow. Revision 0.91, July 19, 2002 -12- Pin Descriptions Technologies, Inc. P4X400 P4X400 Chipset ­ VT8754 VT8754 Pentium 4 DDR V-Link North Bridge We Connect V-Link Interface Signal Name Pin # I/O Signal Description VAD7 / strap, VAD6 / strap, VAD5 / strap, VAD4 / strap, VAD3 / strap, VAD2 / strap, VAD1 / strap, VAD0 / strap VPAR VBE# UPCMD UPSTB UPSTB# DNCMD DNSTB DNSTB# U3 U1 P1 N2 U4 U5 R2 R3 P3 R1 V2 T2 T1 T5 T4 T3 IO IO IO IO IO IO IO IO IO IO I I I O O O Address / Data Bus. Connection VAD7 strap ­ Dual CPU L=Single, H=Dual VAD6 strap ­ Auto-Configure L=Disable, H=Enable VAD5 strap ­ AGTL+ Drive Strength 4x L=1x, H=4x VAD4 strap ­ AGTL+ Drive Strength 2x L=1x, H=2x VAD3 strap ­ Internal AGTL+ Pullups L=Enable, H=Disable VAD2 strap ­ IOQ Depth L=1-level, H=12-level VAD1 strap ­ -reservedVAD0 strap ­ CPU FSB Frequency L=100 MHz, H=133 MHz Parity. Byte Enable. Command from Client (South Bridge) to Host (North Bridge). Strobe from Client to Host. Complement Strobe from Client to Host. Command from Host (North Bridge) to Client (South Bridge). Strobe from Host to Client. Complement Strobe from Host to Client. Revision 0.91, July 19, 2002 -13- Register Rx50[6] Rx54[5] Rx52[5] Rx50[7] Rx54[6] SB Pin SDCS3# SDA2 SDA1 SDA0 SA19 SA18 SA17 SA16 Pin Descriptions Technologies, Inc. P4X400 P4X400 Chipset ­ VT8754 VT8754 Pentium 4 DDR V-Link North Bridge We Connect Clocks, Resets, Power Control, General Purpose I/O, Interrupts and Test Signal Name Pin # I/O HCLK U29 I HCLK# MCLK T29 AK34 I O MCLKF GCLK RESET# AL34 N5 W1 I I I PWROK SUSST# W3 V1 I I NMI TESTIN# P34 AM34 O I Revision 0.91, July 19, 2002 Signal Description Host Clock. This pin receives the host CPU clock (100 / 133 MHz). This clock is used by all P4X400 P4X400 logic that is in the host CPU domain. Host Clock Complement. Used for Quad Data Transfer on host CPU bus. Memory (SDRAM) Clock. Output from internal clock generator to the external clock buffer. Memory (SDRAM) Clock Feedback. Input from the external clock buffer. AGP Clock. Clock for AGP logic. Reset. Input from the South Bridge chip. When asserted, this signal resets P4X400 P4X400 and sets all register bits to the default value. The rising edge of this signal is used to sample all power-up strap options Power OK. Connect to South Bridge and Power Good circuitry. Suspend Status. For implementation of the Suspend-to-DRAM feature. Connect to an external pull-up to disable. Non Maskable Interrupt. Connect to South Bridge NMI input. Test In. This pin is used for testing and must be left unconnected or tied high on all board designs. -14- Pin Descriptions Technologies, Inc. P4X400 P4X400 Chipset ­ VT8754 VT8754 Pentium 4 DDR V-Link North Bridge We Connect Reference Voltages Signal Name Pin # I/O GTLVREF V29 P F19, F24, F28, J29 AA29, AD29 P HCMPVREF H30 P MEMVREF AF6, AJ11, AJ17, AJ23 V3 P F10, M6 P HDVREF HAVREF VLVREF AGPVREF P P Signal Description Host CPU Interface AGTL+ Voltage Reference. 2/3 VTT ±2% typically derived using a resistive voltage divider. See P4X400 P4X400 Design Guide. Host CPU Data Voltage Reference. 2/3 VTT ±2% typically derived using a resistive voltage divider. See P4X400 P4X400 Design Guide. Host CPU Address Voltage Reference. 2/3 VTT ±2% typically derived using a resistive voltage divider. See P4X400 P4X400 Design Guide. Host CPU Compensation Voltage Reference. 1/3 VTT ±2% typically derived using a resistive voltage divider. See P4X400 P4X400 Design Guide. Memory Voltage Reference. 1/2 VCC25 VCC25 ±2% typically derived using a resistive voltage divider. See P4X400 P4X400 Design Guide. V-Link Voltage Reference. 0.625V ±2% derived using a resistive voltage divider. See P4X400 P4X400 Design Guide. AGP Voltage Reference. 0.5 VCCQQ (0.75V) for AGP 2.0 (4x transfer mode) and 0.23 VCCQQ (0.35V) for AGP 3.0 (8x transfer mode). See the P4X400 P4X400 Design Guide for additional information and circuit implementation details. Compensation Signal Name Pin # I/O Signal Description HRCOMP H31 AI VLCOMP AGPCOMP U6 P5 AI AI Host CPU Compensation. Connect 20.5 1% resistor to ground. Used for Host CPU interface I/O buffer calibration. Vlink Compensation. Connect 70 1% resistor to ground. AGP Compensation. Analog Power / Ground Signal Name Pin # I/O VCCHCK1 GNDHCK1 T30 T31 P P VCCHCK2 GNDHCK2 U30 U31 P P VCCMCK GNDMCK AK32 AK33 P P VCCMDLL GNDMDLL AJ12 AJ13 P P Revision 0.91, July 19, 2002 Signal Description Power for Host CPU Clock PLL 1 (2.5V ±5%) Ground for Host CPU Clock 1 Circuitry. Connect to main ground plane through a ferrite bead. Power for Host CPU Clock PLL 2 (2.5V ±5%) Ground for Host CPU Clock 2 Circuitry. Connect to main ground plane through a ferrite bead. Power for Memory Clock PLL (2.5V ±5%) Ground for Memory Clock Circuitry. Connect to main ground plane through a ferrite bead. Power for Memory Strobe DLL (2.5V ±5%) Ground for Memory Strobe DLL Circuitry. Connect to main ground plane through a ferrite bead. -15- Pin Descriptions Technologies, Inc. P4X400 P4X400 Chipset ­ VT8754 VT8754 Pentium 4 DDR V-Link North Bridge We Connect Digital Power / Ground Signal Name VTT GNDTT VCCMEM VCCVL VCCAGP VCCQQ GNDQQ VCC25 VCC25 VSUS25 VSUS25 GND Pin # I/O (see pin lists) F25, AB29 (see pin lists) (see pin lists) (see pin lists) N6 P4 (see pin lists) V5 (see pin lists) P P P P P P P P P P Revision 0.91, July 19, 2002 Signal Description Power for CPU I/O Interface Logic (60 Pins). Voltage is CPU dependent. Ground for CPU I/O Interface Logic (2 Pins). Power for Memory I/O Interface Logic (86 Pins). 2.5V ±5%. Power for V-Link I/O Interface Logic (18 Pins). 2.5V ±5% Power for AGP Bus I/O Interface Logic (43 Pins). 1.5V ±5% AGP Quiet Power. Connect to main AGP power (VCCAGP) through a ferrite bead. Ground for AGP Quiet Power. Connect to main ground plane. Power for Internal Logic (50 Pins). 2.5V ±5% Suspend Power. 2.5V ±5% Digital Ground (199 Pins). Connect to main ground plane. -16- Pin Descriptions Technologies, Inc. P4X400 P4X400 Chipset ­ VT8754 VT8754 Pentium 4 DDR V-Link North Bridge We Connect REGISTERS Register Overview The following tables summarize the configuration and I/O registers of the P4X400 P4X400. These tables also document the power-on default value ("Default") and access type ("Acc") for each register. Access type definitions used are RW (Read/Write), RO (Read/Only), "-" for reserved / used (essentially the same as RO), RWC (or just WC) (Read / Write 1's to Clear individual bits), and W1 (Write Once then Read / Only after that). Registers indicated as RW may have some read/only bits that always read back a fixed value (usually 0 if unused); registers designated as RWC or WC may have some read-only or read write bits (see individual register descriptions following these tables for details). All offset and default values are shown in hexadecimal unless otherwise indicated. The graphics registers are described in a separate document. Table 4. VT8754 VT8754 / P4X400 P4X400 Registers P4X400 P4X400 I/O Ports Port # 22 CFB-8 CFF-C I/O Port PCI / AGP Arbiter Disable Configuration Address Configuration Data Revision 0.91, July 19, 2002 Default 00 0000 0000 0000 0000 Acc RW RW RW -17- Register Overview Technologies, Inc. We Connect P4X400 P4X400 Chipset ­ VT8754 VT8754 Pentium 4 DDR V-Link North Bridge P4X400 P4X400 Device 0 Registers - Host Bridge Header Registers Device-Specific Registers (continued) Configuration Space Header Default Acc Vendor ID RO 1106 Device ID RO 3168 Command 0006 RW Status 0210 WC Revision ID RO 0n Program Interface 00 RO Sub Class Code 00 RO Base Class Code RO 06 -reserved00 - Latency Timer 00 RW Header Type 00 RO Built In Self Test (BIST) 00 RO Graphics Aperture Base 0000 0008 RW -reserved00 - Subsystem Vendor ID 0000 W1 Subsystem ID 0000 W1 -reserved00 - Capability Pointer AGP 2.0: RO A0 (CAPPTR) AGP 3.0: RO 80 35-3F 35-3F -reserved00 - Offset 1-0 3-2 5-4 7-6 8 9 A B C D E F 13-10 14-2B 14-2B 2D-2C 2F-2E 30-33 34 Device-Specific Registers Offset 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F V-Link Control V-Link Revision ID V-Link NB Capability V-Link NB Downlink Command V-Link NB Uplink Max Req Depth V-Link NB Uplink Buffer Size V-Link NB Bus Timer V-Link NB Misc Control V-Link Control V-Link NB/SB Configuration V-Link SB Capability V-Link SB Downlink Status V-Link SB Uplink Max Req Depth V-Link SB Uplink Buffer Size V-Link SB Bus Timer CCA Master High Priority V-Link SB Miscellaneous Control Default Acc 00 RO 19 WC RW 88 RW 80 RW 82 RW 44 00 RW 00 RW RW 18 19 WC 88 RO RW 80 RW 82 RW 44 00 RW 00 RW Offset 50 51 52 53 54 Host CPU Protocol Control CPU Interface Request Phase Control CPU Interface Basic Control CPU Interface Advanced Control CPU Interface Arbitration Control CPU Frequency Default 00 00 00 00 00 Revision 0.91, July 19, 2002 Offset 55 56-57 59-58 5F-5A 5A 5B 5C 5D 5E 5F 56 57 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F DRAM Control Default Acc DRAM Control 00 RW (see below) MA Map Type RW 2222 DRAM Row Ending Address: Bank 0 Ending (HA[31:24]) RW 01 Bank 1 Ending (HA[31:24]) RW 01 Bank 2 Ending (HA[31:24]) RW 01 Bank 3 Ending (HA[31:24]) RW 01 Bank 4 Ending (HA[31:24]) RW 01 Bank 5 Ending (HA[31:24]) RW 01 Bank 6 Ending (HA[31:24]) RW 01 Bank 7 Ending (HA[31:24]) RW 01 DRAM Type RW 80 ROM Shadow Control C0000-CFFFF C0000-CFFFF 00 RW ROM Shadow Control D0000-DFFFF D0000-DFFFF 00 RW ROM Shadow Control E0000-FFFFF E0000-FFFFF 00 RW DRAM Timing for All Banks RW E4 DRAM Arbitration Timer 00 RW DRAM Arbitration Control 00 RW DRAM Strobe Input Delay 00 RW DRAM Strobe Output Delay 00 RW DRAM Clock Select 00 RW DRAM Refresh Counter 00 RW DRAM Arbitration Control RW 10 DRAM Clock Control 00 RW -reserved00 - ECC Control 00 RW ECC Status 00 WC Offset 70 71 72 73 74 75 76 77-7F 77-7F PCI Bus Control PCI Buffer Control CPU to PCI Flow Control -reservedPCI Master Control -reservedPCI Arbitration 1 PCI Arbitration 2 -reserved- Default Acc 00 RW 48 WC 00 - 00 RW 00 - 00 RW 00 RW 00 - Acc RW RW RW RW RW -18- Register Summary Tables Technologies, Inc. We Connect P4X400 P4X400 Chipset ­ VT8754 VT8754 Pentium 4 DDR V-Link North Bridge Device 0 Device-Specific Registers (continued) Device 0 Device-Specific Registers (continued) Default Acc Offset AGP 2.0 Control (RxFD[1]=1) 83-80 AGP 2.0 GART/TLB Control 0000 0000 RW 84 AGP 2.0 Graphics Aperture Size 00 RW 85 AGP 2.0 Write Policy 00 RW 86 CPU / DRAM Bandwidth Timer Ctrl 00 RW 87 CPU / DRAM Bandwidth Limit 00 RW 8B-88 8B-88 AGP 2.0 GART Table Base 0000 0000 RW 8C-9F -reserved00 - A3-A0 AGP 2.0 Capabilities 0020 C002 RO A7-A4 AGP 2.0 Status 1F00 0201 RO AB-A8 AGP 2.0 Command 0000 0000 RW Registers A0-AB in the AGP 2.0 register group in the table above are actually offsets from CAPPTR (Rx34) which (with Rx34 = A0h for AGP 2.0) result in the offsets listed above. Offset AGP 3.0 Control (RxFD[1]=0) Default Acc 83-80 AGP 3.0 Capabilities 0030 C002 RO 87-84 AGP 3.0 Status 1F00 0A03 RO 8B-88 8B-88 AGP 3.0 Command 1F00 0000 RW 8F-8C -reserved0000 0000 - 93-90 AGP 3.0 GART / TLB Control 0000 0000 RW 97-94 AGP 3.0 Graphics Aperture Size 0001 0F00 RW 9B-98 9B-98 AGP 3.0 GART Table Base 0000 0000 RW 9C-AB -reserved00 - Registers 80-AB 80-AB in the AGP 3.0 register group in the table above are actually offsets from CAPPTR (Rx34) which (with Rx34 = 80h for AGP 3.0) result in the offsets listed above. Offset AGP 2.0 / 3.0 Control Default Acc AC AGP Control 00 RW AD AGP Latency Timer RW 02 AE AGP Miscellaneous Control 00 RW AF AGP 3.0 Control 00 RW B0 AGP Pad Control / Status RW 8x B1 AGP Drive Strength RW 63 B2 AGP Pad Drive / Delay Control RW 08 B3 AGP Strobe Output Drive Control 00 RW Offset C0 C1 C2 C3 C4 C5 C6 C7 C8-CF Extended Power Management Ctrl Power Management Capability Power Management Next Pointer Power Management Capabilities I Power Management Capabilities II Power Management Control/Status Power Management Status PCI-to-PCI Bridge Support Extension Power Management Data -reserved- Default 01 00 02 00 00 00 00 00 00 Offset D3-D0 D4 D5 D6 D7 Error Control DRAM ECC Error Address DRAM ECC Error Syndrome Bit Host CPU Parity Status Host CPU Parity Enable -reserved- Default Acc xx RO xx RO 00 WC 00 RW 00 - Offset D8 D9 DA DB DC DD DE DF Host CPU AGTL+ I/O Control Host Address (2x) Pullup Drive Host Address (2x) Pulldown Drive Host Data (4x) Pullup Drive Host Data (4x) Pulldown Drive AGTL+ Output Delay / Stagger Ctrl AGTL+ I/O Control AGTL+ Compensation Status AGTL+ AutoCompensation Offset Default 00 00 00 00 00 00 00 00 Acc RW RW RW RW RW RW RW RW Offset E0-E3 E4 E5 E6 E7 E8 E9 EA EB EC-ED DRAM Control -reservedLow Top Address Low Low Top Address High SMM / APIC Decoding -reservedDRAM DQ Drive DRAM CS Drive DRAM MAA Drive DRAM MAB Drive -reserved- Default 00 00 FF 01 00 00 00 00 00 00 Acc - RW RW RW - RW RW RW RW - Offset P6 Interface DRDY Timing Control Default EE DRDY Timing 1 00 EF DRDY Timing 2 00 Acc RW RW Offset F0-FC FD FE-FF Acc - RW - Offset B4 B5 B6 B7 B8 B9 BA BB V-Link Compenation / Drive Ctrl V-Link NB Compensation Control V-Link NB Strobe Drive Control V-Link NB Data Drive Control -reservedV-Link SB Compensation Control V-Link SB Strobe Drive Control V-Link SB Data Drive Control -reserved- Default 00 00 00 00 00 00 00 00 Acc RW RW RW - RW RW RW - Offset BC BD BE BF Power Management Control Power Management Mode DRAM Power Management Dynamic Clock Stop MA / SCMD Pad Toggle Reduction Default 00 00 00 00 Acc RW RW RW RW Revision 0.91, July 19, 2002 -19- Miscellaneous -reserved- (Do Not Program) AGP 2.0 / 3.0 Select -reserved- (Do Not Program) Default 00 00 00 Acc RO RO RO RO RW RO RO RO - Register Summary Tables Technologies, Inc. We Connect P4X400 P4X400 Chipset ­ VT8754 VT8754 Pentium 4 DDR V-Link North Bridge P4X400 P4X400 Device 1 Registers - PCI-to-PCI Bridge Header Registers Offset 1-0 3-2 5-4 7-6 8 9 A B C D E F 10-17 18 19 1A 1B 1C 1D 1F-1E 21-20 23-22 25-24 27-26 28-33 34 35-3D 35-3D 3F-3E Configuration Space Header Vendor ID Device ID Command Status Revision ID Program Interface Sub Class Code Base Class Code -reservedLatency Timer Header Type -reserved- (Built In Self Test) -reservedPrimary Bus Number Secondary Bus Number Subordinate Bus Number Secondary Latency Timer I/O Base I/O Limit Secondary Status Memory Base Memory Limit (Inclusive) Prefetchable Memory Base Prefetchable Memory Limit -reservedCapability Pointer -reservedPCI-to-PCI Bridge Control Revision 0.91, July 19, 2002 Device-Specific Registers Default 1106 B168 0007 0230 nn 00 04 06 00 00 01 00 00 00 00 00 00 F0 00 0000 FFF0 0000 FFF0 0000 00 80 00 00 Acc RO RO RW WC RO RO RO RO - RO RO - - RW RW RW RO RW RW RO RW RW RW RW - RO - RW -20- Offset 40 41 42 43 44 45 47-46 48 49-7F 49-7F AGP Bus Control CPU-to-AGP Flow Control 1 CPU-to-AGP Flow Control 2 AGP Master Control AGP Master Latency Timer Reserved (Do Not Program) Fast Write Control PCI-to-PCI Bridge Device ID AGP / PCI2 Error Reporting -reserved- Default Acc 00 RW RW 08 00 RW RW 22 00 RW RW 72 0000 RW 00 WC 00 - Offset 80 81 82 83 84 85 86 87 88-FF 88-FF Power Management Capability ID Next Pointer Power Management Capabilities 1 Power Management Capabilities 2 Power Management Control / Status Power Management Status PCI-PCI Bridge Support Extensions Power Management Data -reserved- Default 01 00 02 00 00 00 00 00 00 Acc RO RO RO RO RW RO RO RO - Register Summary Tables Technologies, Inc. We Connect P4X400 P4X400 Chipset ­ VT8754 VT8754 Pentium 4 DDR V-Link North Bridge Miscellaneous I/O Configuration Space I/O One I/O port is defined in the P4X400 P4X400: Port 22. All registers in the P4X400 P4X400 (listed above) are addressed via the following configuration mechanism: Port 22 ­ PCI / AGP Arbiter Disable .RW 7-2 Reserved . always reads 0 1 AGP Arbiter Disable 0 Respond to GREQ# signal .default 1 Do not respond to GREQ# signal 0 PCI Arbiter Disable 0 Respond to all REQ# signals .default 1 Do not respond to any REQ# signals, including PREQ# This port can be enabled for read/write access by setting bit-7 of Device 0 Configuration Register 78. Mechanism #1 These ports respond only to double-word accesses. Byte or word accesses will be passed on unchanged. Port CFB-CF8 - Configuration Address. RW 31 Configuration Space Enable 0 Disabled. default 1 Convert configuration data port writes to configuration cycles on the PCI bus 30-24 Reserved .always reads 0 23-16 PCI Bus Number Used to choose a specific PCI bus in the system 15-11 Device Number Used to choose a specific device in the system (devices 0 and 1 are defined for the P4X400 P4X400) 10-8 Function Number Used to choose a specific function if the selected device supports multiple functions (only function 0 is defined for the P4X400 P4X400). 7-2 Register Number (also called the "Offset") Used to select a specific DWORD in the P4X400 P4X400 configuration space 1-0 Fixed .always reads 0 Port CFF-CFC - Configuration Data. RW Refer to PCI Bus Specification Version 2.2 for further details on operation of the above configuration registers. Revision 0.91, July 19, 2002 -21- Miscellaneous and Configuration Space I/O Technologies, Inc. We Connect P4X400 P4X400 Chipset ­ VT8754 VT8754 Pentium 4 DDR V-Link North Bridge Device 0 Register Descriptions Device 0 Offset 7-6 ­ Status (0210h).RWC 15 Detected Parity Error 0 No parity error detected. default 1 Error detected in either address or data phase. This bit is set even if error response is disabled (command register bit-6). .write one to clear 14 Signaled System Error (SERR# Asserted) .always reads 0 13 Signaled Master Abort 0 No abort received . default 1 Transaction aborted by the master . .write one to clear 12 Received Target Abort 0 No abort received . default 1 Transaction aborted by the target . .write one to clear 11 Signaled Target Abort .always reads 0 0 Target Abort never signaled 10-9 DEVSEL# Timing 00 Fast 01 Medium .always reads 01 10 Slow 11 Reserved 8 Data Parity Error Detected 0 No data parity error detected . default 1 Error detected in data phase. Set only if error response enabled via command bit-6 = 1 and P4X400 P4X400 was initiator of the operation in which the error occurred. .write one to clear 7 Fast Back-to-Back Capable .always reads 0 6 User Definable Features .always reads 0 5 66MHz Capable.always reads 0 4 Supports New Capability list.always reads 1 3-0 Reserved .always reads 0 Device 0 Host Bridge Header Registers All registers are located in PCI configuration space. They should be programmed using PCI configuration mechanism 1 through CF8 / CFC with bus number, function number, and device number equal to zero. Device 0 Offset 1-0 - Vendor ID (1106h) .RO 15-0 ID Code (reads 1106h to identify VIA Technologies) Device 0 Offset 3-2 - Device ID (3168h).RO 15-0 ID Code (reads 3168h to identify the P4X400 P4X400) Device 0 Offset 5-4 ­Command (0006h).RW 15-10 Reserved . always reads 0 9 Fast Back-to-Back Cycle Enable . RO 0 Fast back-to-back transactions only allowed to the same agent.default 1 Fast back-to-back transactions allowed to different agents 8 SERR# Enable. RO 0 SERR# driver disabled.default 1 SERR# driver enabled (SERR# is used to report ECC errors). 7 Address / Data Stepping . RO 0 Device never does stepping.default 1 Device always does stepping 6 Parity Error Response.RW 0 Ignore parity errors & continue.default 1 Take normal action on detected parity errors 5 VGA Palette Snoop . RO 0 Treat palette accesses normally.default 1 Don't respond to palette accesses on PCI bus 4 Memory Write and Invalidate Command . RO 0 Bus masters must use Mem Write.default 1 Bus masters may generate Mem Write & Inval 3 Special Cycle Monitoring . RO 0 Does not monitor special cycles.default 1 Monitors special cycles 2 PCI Bus Master. RO 0 Never behaves as a bus master 1 Can behave as a bus master.default 1 Memory Space. RO 0 Does not respond to memory space 1 Responds to memory space.default 0 I/O Space . RO 0 Does not respond to I/O space .default 1 Responds to I/O space Revision 0.91, July 19, 2002 Device 0 Offset 8 - Revision ID (0nh). RO 7-0 Chip Revision Code.always reads 0nh Device 0 Offset 9 - Programming Interface (00h). RO 7-0 Interface Identifier .always reads 00h Device 0 Offset A - Sub Class Code (00h). RO 7-0 Sub Class Code .reads 00 to indicate Host Bridge Device 0 Offset B - Base Class Code (06h). RO 7-0 Base Class Code. reads 06 to indicate Bridge Device Device 0 Offset D - Latency Timer (00h) . RW Specifies the latency timer value in PCI bus clocks. 7-3 Guaranteed Time Slice for CPU . default=0 2-0 Reserved (fixed granularity of 8 clks) . always read 0 Bits 2-1 are writeable but read 0 for PCI specification compatibility. The programmed value may be read back in Rx75[6-4] (PCI Arbitration 1). -22- Device 0 Register Descriptions Technologies, Inc. We Connect P4X400 P4X400 Chipset ­ VT8754 VT8754 Pentium 4 DDR V-Link North Bridge Device 0 Host Bridge Header Registers (continued) Device 0 Offset 13-10 - Graphics Aperture Base (AGP 3.0) (00000008h) . RW This register is interpreted per the following definition if RxFD[1]=0 (AGP 3.0 registers enabled). This register may only be read if AGP 3.0 register Rx90[8] = 1. Device 0 Offset E - Header Type (00h).RO 7-0 Header Type Code . reads 00: single function Device 0 Offset F - Built In Self Test (BIST) (00h).RO 7 BIST Supported .reads 0: no supported functions 6-0 Reserved . always reads 0 31-22 Programmable Base Address Bits . def=0 These bits behave as if hardwired to 0 if the corresponding AGP 3.0 Graphics Aperture Size register bit (Device 0 Offset 94h) is 0. Device 0 Offset 13-10 - Graphics Aperture Base (AGP 2.0) (00000008h) .RW This register is interpreted per the following definition if RxFD[1]=1 (AGP 2.0 registers enabled). 31 11 RW RW RW RW RW RW RW RW RW RW 0 31-28 Upper Programmable Base Address Bits . def=0 27-20 Lower Programmable Base Address Bits . def=0 These bits behave as if hardwired to 0 if the corresponding AGP 2.0 Graphics Aperture Size register bit (Device 0 Offset 84h) is 0. 27 26 25 24 23 22 21 20 7 6 5 4 3 2 1 0 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW 0 RW RW RW RW RW RW 0 0 RW RW RW RW RW 0 0 0 RW RW RW RW 0 0 0 0 RW RW RW 0 0 0 0 0 RW RW 0 0 0 0 0 0 RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (Base) (Size) 1M 2M 4M 8M 16M 32M 64M 128M 256M 30 10 RW RW RW RW RW RW RW RW RW 0 0 29 9 RW RW RW RW RW RW RW RW 0 0 0 28 8 RW RW RW RW RW RW RW 0 0 0 0 7 0 0 0 0 0 0 0 0 0 0 0 6 0 0 0 0 0 0 0 0 0 0 0 27 5 RW RW RW RW RW RW 0 0 0 0 0 26 4 RW RW RW RW RW 0 0 0 0 0 0 25 3 RW RW RW RW 0 0 0 0 0 0 0 24 2 RW RW RW 0 0 0 0 0 0 0 0 23 1 RW RW 0 0 0 0 0 0 0 0 0 22 (Base) 0 (Size) RW 4M 0 8M 0 16M 0 32M 0 64M 0 128M 0 256M 0 512M 0 1G 0 2G-max 0 4G 21-4 Reserved .always reads 0 3 Prefetchablealways reads 1 Indicates that the locations in the address range defined by this register are prefetchable. 2-1 Type .always reads 0 Indicates the address range in the 32-bit address space. 0 Memory Space .always reads 0 Indicates the address range in the memory address space. 19-4 Reserved . always reads 0 3 Prefetchablealways reads 1 Indicates that the locations in the address range defined by this register are prefetchable. 2-1 Type . always reads 0 Indicates the address range in the 32-bit address space. 0 Memory Space. always reads 0 Indicates the address range in the memory address space. Device 0 Offset 2D-2C ­ Subsystem Vendor ID (0000h)R/W1 15-0 Subsystem Vendor ID . default = 0 This register may be written once and is then read only. Device 0 Offset 2F-2E ­ Subsystem ID (0000h). R/W1 15-0 Subsystem ID . default = 0 This register may be written once and is then read only. Device 0 Offset 34 - Capability Pointer (CAPPTR). RO Contains an offset from the start of configuration space. 7-0 Revision 0.91, July 19, 2002 -23- AGP Capabili