128MB 256MB 512MB 184-PIN MT8VDDT1664A MT8VDDT3264A MT8VDDT6464A MO-206 PC1600 - Datasheet Archive

 

184-PIN DDR SDRAM DIMM DDR SDRAM DIMM MT8VDDT1664A ­ 128MB MT8VDDT3264A ­ 256MB MT8VDDT6464A ­ 512MB For the latest

 

128MB 128MB, 256MB 256MB, 512MB 512MB (x64) 184-PIN 184-PIN DDR SDRAM DIMM DDR SDRAM DIMM MT8VDDT1664A MT8VDDT1664A ­ 128MB 128MB MT8VDDT3264A MT8VDDT3264A ­ 256MB 256MB MT8VDDT6464A MT8VDDT6464A ­ 512MB 512MB For the latest data sheet, please refer to the Micronâ Web site: www.micron.com/moduleds Features Figure 1: 184-Pin DIMM (MO-206 MO-206) · 184-pin dual in-line memory module (DIMM) · Fast data transfer rates: PC1600 PC1600, PC2100 PC2100, or PC2700 PC2700 · Utilizes 200 MT/s, 266 MT/s, and 333 MT/s DDR SDRAM components · 128MB 128MB (16 Meg x 64), 256MB 256MB (32 Meg x 64), and 512MB 512MB (64 Meg x 64) · VDD = VDDQ = +2.5V · VDDSPD = +2.3V to +3.6V · 2.5V I/O (SSTL_2 compatible) · Commands entered on each positive CK edge · DQS edge-aligned with data for READs; centeraligned with data for WRITEs · Internal, pipelined double data rate (DDR) architecture; two data accesses per clock cycle · Bidirectional data strobe (DQS) transmitted/ received with data-i.e., source-synchronous data capture · Differential clock inputs (CK and CK#) · Four internal device banks for concurrent operation · Programmable burst lengths: 2, 4, or 8 · Auto precharge option · Auto Refresh and Self Refresh Modes · 15.625µs (128MB 128MB), 7.8125µs (256MB 256MB, 512MB 512MB) maximum average periodic refresh interval · Serial Presence Detect (SPD) with EEPROM · Programmable READ CAS latency · Gold edge contacts Table 1: 1.25in. (31.75mm) OPTIONS MARKING · Package 184-pin DIMM (standard) G 1 Y 184-pin DIMM (lead-free) 2 · Memory Clock/Speed, CAS Latency 6ns (167 MHz), 333 MT/s, CL = 2.5 -335 7.5ns (133 MHz), 266 MT/s, CL = 2 -262 7.5ns (133 MHz), 266 MT/s, CL = 2 -26A 7.5ns (133 MHz), 266 MT/s, CL = 2.5 -265 10ns (100 MHz), 200 MT/s, CL = 2 -202 · PCB 1.25in. (31.75mm) See page 2 note NOTE: 1. Consult Micron for availability of Lead-free products. 2. CL = CAS (READ) Latency Address Table 128MB 128MB Refresh Count Row Addressing Device Bank Addressing Device Configuration Column Addressing Module Rank Addressing 09005aef80867a99 DD8C16 DD8C16_32_64x64AG_A.fm - Rev. A 8/03 EN 256MB 256MB 512MB 512MB 4K 4K (A0­A11) 4 (BA0, BA1) 16 Meg x 8 1K (A0­A9) 1 (S0#) 8K 8K (A0­A12) 4 (BA0, BA1) 32 Meg x 8 1K (A0­A9) 1 (S0#) 8K 8K (A0­A12) 4 (BA0, BA1) 64 Meg x 8 2K (A0­A9, A11) 1 (S0#) 1 ©2003 Micron Technology, Inc. PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. 128MB 128MB, 256MB 256MB, 512MB 512MB (x64) 184-PIN 184-PIN DDR SDRAM DIMM Table 2: Part Numbers and Timing Parameters PARTNUMBER MT8VDDT1664AG-335 MT8VDDT1664AG-335_ MT8VDDT1664AY-335 MT8VDDT1664AY-335_ MT8VDDT1664AG-262 MT8VDDT1664AG-262_ MT8VDDT1664AY-262 MT8VDDT1664AY-262_ MT8VDDT1664AG-26A MT8VDDT1664AG-26A_ MT8VDDT1664AY-26A MT8VDDT1664AY-26A_ MT8VDDT1664AG-265 MT8VDDT1664AG-265_ MT8VDDT1664AY-265 MT8VDDT1664AY-265_ MT8VDDT1664AG-202 MT8VDDT1664AG-202_ MT8VDDT1664AY-202 MT8VDDT1664AY-202_ MT8VDDT3264AG-335 MT8VDDT3264AG-335_ MT8VDDT3264AY-335 MT8VDDT3264AY-335_ MT8VDDT3264AG-262 MT8VDDT3264AG-262_ MT8VDDT3264AY-262 MT8VDDT3264AY-262_ MT8VDDT3264AG-26A MT8VDDT3264AG-26A_ MT8VDDT3264AY-26A MT8VDDT3264AY-26A_ MT8VDDT3264AG-265 MT8VDDT3264AG-265_ MT8VDDT3264AY-265 MT8VDDT3264AY-265_ MT8VDDT3264AG-202 MT8VDDT3264AG-202_ MT8VDDT3264AY-202 MT8VDDT3264AY-202_ MT8VDDT6464AG-335 MT8VDDT6464AG-335_ MT8VDDT6464AY-335 MT8VDDT6464AY-335_ MT8VDDT6464AG-262 MT8VDDT6464AG-262_ MT8VDDT6464AY-262 MT8VDDT6464AY-262_ MT8VDDT6464AG-26A MT8VDDT6464AG-26A_ MT8VDDT6464AY-26A MT8VDDT6464AY-26A_ MT8VDDT6464AG-265 MT8VDDT6464AG-265_ MT8VDDT6464AY-265 MT8VDDT6464AY-265_ MT8VDDT6464AG-202 MT8VDDT6464AG-202_ MT8VDDT6464AY-202 MT8VDDT6464AY-202_ MODULE DENSITY CONFIGURATION MODULE BANDWITH MEMORYCLOCK/ DATA RATE LATENCY (CL - TRCD - TRP) 128MB 128MB 128MB 128MB 128MB 128MB 128MB 128MB 128MB 128MB 128MB 128MB 128MB 128MB 128MB 128MB 128MB 128MB 128MB 128MB 256MB 256MB 256MB 256MB 256MB 256MB 256MB 256MB 256MB 256MB 256MB 256MB 256MB 256MB 256MB 256MB 256MB 256MB 256MB 256MB 512MB 512MB 512MB 512MB 512MB 512MB 512MB 512MB 512MB 512MB 512MB 512MB 512MB 512MB 512MB 512MB 512MB 512MB 512MB 512MB 16 Meg x 64 16 Meg x 64 16 Meg x 64 16 Meg x 64 16 Meg x 64 16 Meg x 64 16 Meg x 64 16 Meg x 64 16 Meg x 64 16 Meg x 64 32 Meg x 64 32 Meg x 64 32 Meg x 64 32 Meg x 64 32 Meg x 64 32 Meg x 64 32 Meg x 64 32 Meg x 64 32 Meg x 64 32 Meg x 64 64 Meg x 64 64 Meg x 64 64 Meg x 64 64 Meg x 64 64 Meg x 64 64 Meg x 64 64 Meg x 64 64 Meg x 64 64 Meg x 64 64 Meg x 64 2.7GB/s 2.7GB/s 2.1GB/s 2.1GB/s 2.1GB/s 2.1GB/s 2.1GB/s 2.1GB/s 1.6GB/s 1.6GB/s 2.7GB/s 2.7GB/s 2.1GB/s 2.1GB/s 2.1GB/s 2.1GB/s 2.1GB/s 2.1GB/s 1.6GB/s 1.6GB/s 2.7GB/s 2.7GB/s 2.1GB/s 2.1GB/s 2.1GB/s 2.1GB/s 2.1GB/s 2.1GB/s 1.6GB/s 1.6GB/s 6ns/333MT/s 6ns/333MT/s 7.5ns/266MT/s 7.5ns/266MT/s 7.5ns/266MT/s 7.5ns/266MT/s 7.5ns/266MT/s 7.5ns/266MT/s 10ns/200MT/s 10ns/200MT/s 6ns/333MT/s 6ns/333MT/s 7.5ns/266MT/s 7.5ns/266MT/s 7.5ns/266MT/s 7.5ns/266MT/s 7.5ns/266MT/s 7.5ns/266MT/s 10ns/200MT/s 10ns/200MT/s 6ns/333MT/s 6ns/333MT/s 7.5ns/266MT/s 7.5ns/266MT/s 7.5ns/266MT/s 7.5ns/266MT/s 7.5ns/266MT/s 7.5ns/266MT/s 10ns/200MT/s 10ns/200MT/s 2.5-3-3 2.5-3-3 2-2-2 2-2-2 2-3-3 2-3-3 2.5-3-3 2.5-3-3 2-2-2 2-2-2 2.5-3-3 2.5-3-3 2-2-2 2-2-2 2-3-3 2-3-3 2.5-3-3 2.5-3-3 2-2-2 2-2-2 2.5-3-3 2.5-3-3 2-2-2 2-2-2 2-3-3 2-3-3 2.5-3-3 2.5-3-3 2-2-2 2-2-2 NOTE: All part numbers end with a two-place code (not shown), designating component and PCB revisions. Consult factory for current revision codes. Example: MT8VDDT3264AG-265A1 MT8VDDT3264AG-265A1. 09005aef80867a99 DD8C16 DD8C16_32_64x64AG_A.fm - Rev. A 8/03 EN 2 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology. Inc. 128MB 128MB, 256MB 256MB, 512MB 512MB (x64) 184-PIN 184-PIN DDR SDRAM DIMM Table 3: Pin Assignment (184-Pin DIMM Front) Table 4: Pin Assignment (184-Pin DIMM Back) PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 93 VSS 116 VSS 139 VSS 162 DQ47 94 DQ4 117 DQ21 140 DNU 163 NC 95 DQ5 118 A11 141 A10 164 VDDQ 96 VDDQ 119 DQS11/DM2 DQS11/DM2 142 DNU 165 DQ52 97 DQS9/DM0 120 VDD 143 VDDQ 166 DQ53 98 DQ6 121 DQ22 144 DNU 167 NC 99 DQ7 122 A8 145 VSS 168 VDD 100 VSS 123 DQ23 146 DQ36 169 DQS15/DM6 DQS15/DM6 101 NC 124 VSS 147 DQ37 170 DQ54 102 NC 125 A6 148 VDD 171 DQ55 DQS13/DM4 DQS13/DM4 172 103 NC 126 DQ28 149 VDD 104 VDDQ 127 DQ29 150 DQ38 173 NC 105 DQ12 128 VDDQ 151 DQ39 174 DQ60 106 DQ13 129 DQS12/DM3 DQS12/DM3 152 VSS 175 DQ61 DQS10/DM1 DQS10/DM1 130 107 A3 153 DQ44 176 VSS 108 VDD 131 DQ30 154 RAS# 177 DQS16/DM7 DQS16/DM7 109 DQ14 132 VSS 155 DQ45 178 DQ62 110 DQ15 133 DQ31 156 VDDQ 179 DQ63 111 DNU 134 DNU 157 S0# 180 VDDQ 112 VDDQ 135 DNU 158 DNU 181 SA0 113 NC 136 VDDQ 159 DQS14/DM5 DQS14/DM5 182 SA1 114 DQ20 137 CK0 160 VSS 183 SA2 115 NC/A12 NC/A12 138 CK0# 161 DQ46 184 VDDSPD VREF DQ0 VSS DQ1 DQS0 DQ2 VDD DQ3 NC NC VSS DQ8 DQ9 DQS1 VDDQ CK1 CK1# VSS DQ10 DQ11 CKE0 VDDQ DQ16 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 DQ17 DQS2 VSS A9 DQ18 A7 VDDQ DQ19 A5 DQ24 VSS DQ25 DQS3 A4 VDD DQ26 DQ27 A2 VSS A1 DNU DNU VDD 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 DNU A0 DNU VSS DNU BA1 DQ32 VDDQ DQ33 DQS4 DQ34 VSS BA0 DQ35 DQ40 VDDQ WE# DQ41 CAS# VSS DQS5 DQ42 DQ43 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 VDD NC DQ48 DQ49 VSS CK2# CK2 VDDQ DQS6 DQ50 DQ51 VSS NC DQ56 DQ57 VDD DQS7 DQ58 DQ59 VSS NC SDA SCL NOTE: Pin 115 is "No Connect" for 128MB 128MB, "A12" for 256MB 256MB and 512MB 512MB. Figure 2: 184-Pin DIMM Pin Locations Front View U10 U1 U2 U3 U4 PIN 1 U6 PIN 52 U7 PIN 53 U8 U9 PIN 92 Back View No Components This Side of Module PIN 184 PIN 145 Indicates a VDD or VDDQ pin 09005aef80867a99 DD8C16 DD8C16_32_64x64AG_A.fm - Rev. A 8/03 EN PIN 93 PIN 144 3 Indicates a VSS pin Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology. Inc. 128MB 128MB, 256MB 256MB, 512MB 512MB (x64) 184-PIN 184-PIN DDR SDRAM DIMM Table 5: Pin Descriptions Pin numbers may not correlate with symbols. Refer to Pin Assignment tables on page 3 for more information PIN NUMBERS SYMBOL TYPE DESCRIPTION 63, 65, 154 WE#, CAS#, RAS# Input 16, 17, 75, 76, 137, 138 CK0, CK0#, CK1, CK1#, CK2, CK2# Input 21, 111 CKE0, CKE1 Input 157, 158 S0#, S1# Input 52, 59 BA0, BA1 Input 27, 29, 32, 37, 41, 43, 48, 115 (256MB 256MB, 512MB 512MB), 118, 122, 125, 130, 141 A0-A11 A0-A11 (128MB 128MB) A0-A12 A0-A12 (256MB 256MB, 512MB 512MB) Input 5, 14, 25, 36, 56, 67, 78, 86 DQS0-DQS7 Input/ Output 5, 14, 25, 36, 56, 67, 78, 86, 97, 107, 119, 129, 149, 159, 169, 177 DQS9/DM0­ DQS16/DM7 DQS16/DM7 Input Command Inputs: RAS#, CAS#, and WE# (along with S#) define the command being entered. Clock: CK, CK# are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK,and negative edge of CK#. Output data (DQs and DQS) is referenced to the crossings of CK and CK#. Clock Enable: CKE HIGH activates and CKE LOW deactivates the internal clock, input buffers and output drivers. Taking CKE LOW provides PRECHARGE POWER-DOWN and SELF REFRESH operations (all device banks idle), or ACTIVE POWERDOWN (row ACTIVE in any device bank). CKE is synchronous for POWER-DOWN entry and exit, and for SELF REFRESH entry. CKE is asynchronous for SELF REFRESH exit and for disabling the outputs. CKE must be maintained HIGH throughout read and write accesses. Input buffers (excluding CK, CK# and CKE) are disabled during POWER-DOWN. Input buffers (excluding CKE) are disabled during SELF REFRESH. CKE is an SSTL_2 input but will detect an LVCMOS LOW level after VDD is applied and until CKE is first brought HIGH. After CKE is brought HIGH, it becomes an SSTL_2 input only. Chip Selects: S# enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when S# is registered HIGH. S# is considered part of the command code. Bank Address: BA0 and BA1 define to which device bank an ACTIVE, READ, WRITE, or PRECHARGE command is being applied. Address Inputs: Provide the row address for ACTIVE commands, and the column address and auto precharge bit (A10) for READ/WRITE commands, to select one location out of the memory array in the respective device bank. A10 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one device bank (A10 LOW, device bank selected by BA0, BA1) or all device banks (A10 HIGH). The address inputs also provide the op-code during a MODE REGISTER SET command. BA0 and BA1 define which mode register (mode register or extended mode register) is loaded during the LOAD MODE REGISTER command. Data Strobe: Output with READ data, input with WRITE data. DQS is edge-aligned with READ data, centered in WRITE data. Used to capture data. Data Write Mask: DQS9­DQS16 DQS16 function as DM0­DM7. DM LOW allows WRITE operation. DM HIGH blocks WRITE operation. DM lines do not affect READ operation. 09005aef80867a99 DD8C16 DD8C16_32_64x64AG_A.fm - Rev. A 8/03 EN 4 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology. Inc. 128MB 128MB, 256MB 256MB, 512MB 512MB (x64) 184-PIN 184-PIN DDR SDRAM DIMM Table 5: Pin Descriptions (Continued) Pin numbers may not correlate with symbols. Refer to Pin Assignment tables on page 3 for more information PIN NUMBERS SYMBOL TYPE 2, 4, 6, 8, 12, 13, 19, 20, 23, 24, 28, 31, 33, 35, 39, 40, 53, 55, 57, 60, 61, 64, 68, 69, 72, 73, 79, 80, 83, 84, 87, 88, 94, 95, 98, 99, 105, 106, 109, 110, 114, 117, 121, 123, 126, 127, 131, 133, 146, 147, 150, 151, 153, 155, 161, 162, 165, 166, 170, 171, 174, 175, 178, 179 92 DQ0-DQ63 DQ0-DQ63 Input/ Output SCL Input 181,182, 183 SA0-SA2 Input 91 SDA Input/ Output 1 15, 22, 30, 54, 62, 77, 96, 104, 112, 128, 136, 143, 156, 164, 172, 180 7, 38, 46, 70, 85, 108, 120, 148, 168 3, 11, 18, 26, 34, 42, 50, 58, 66, 74, 81, 89, 93, 100, 116, 124, 132, 139, 145, 152, 160, 176 184 44, 45, 47, 49, 51, 134, 135, 140, 142, 144 9, 10, 71, 82, 90, 101, 102, 103, 113, 115 (128MB 128MB), 163, 167, 173 VREF VDDQ Input Supply Serial Clock for Presence-Detect: SCL is used to synchronize the presence-detect data transfer to and from the module. Presence-Detect Address Inputs: These pins are used to configure the presence-detect device. Serial Presence-Detect Data: SDA is a bidirectional pin used to transfer addresses and data into and out of the presencedetect device. SSTL_2 reference voltage. DQ Power Supply: +2.5V ±0.2V. VDD Supply Power Supply: +2.5V ±0.2V. VSS Supply Ground. VDDSPD DNU Supply - NC - Serial EEPROM positive power supply: +2.3V to +3.6V. Do Not Use: These pins are not connected on these modules, but are assigned pins on other modules in this product family. No Connect: These pins should be left unconnected. 09005aef80867a99 DD8C16 DD8C16_32_64x64AG_A.fm - Rev. A 8/03 EN DESCRIPTION Data I/Os: Data bus. 5 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology. Inc. 128MB 128MB, 256MB 256MB, 512MB 512MB (x64) 184-PIN 184-PIN DDR SDRAM DIMM Figure 3: Functional Block Diagram S0# DQS0 DQS4 DQS9/DM0 DQS13/DM4 DQS13/DM4 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DM CS# DQS DQ U2 DQ DQ DQ DQ DQ DQ DQ DQS2 DQS6 DQS11/DM2 DQS11/DM2 DQS15/DM6 DQS15/DM6 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DM CS# DQS DQ U3 DQ DQ DQ DQ DQ DQ DQ DQS3 DQS7 DQS12/DM3 DQS12/DM3 DQS16/DM7 DQS16/DM7 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 5.1 5.1 5.1 A0-A12 A0-A12 (256MB 256MB, 512MB 512MB) 5.1 RAS# CAS# 5.1 5.1 WE# CKE0 DM CS# DQS DQ U9 DQ DQ DQ DQ DQ DQ DQ DQS14/DM5 DQS14/DM5 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 A0-A11 A0-A11 (128MB 128MB) DM CS# DQS DQ U8 DQ DQ DQ DQ DQ DQ DQ DQS5 DQS10/DM1 DQS10/DM1 BA0, BA1 DM CS# DQS DQ U7 DQ DQ DQ DQ DQ DQ DQ DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQS1 DM CS# DQS DQ U6 DQ DQ DQ DQ DQ DQ DQ DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DM CS# DQS DQ U1 DQ DQ DQ DQ DQ DQ DQ DM CS# DQS DQ U4 DQ DQ DQ DQ DQ DQ DQ 120 BA0, BA1: DDR SDRAMS A0-A11 A0-A11: DDR SDRAMS 120 DDR SDRAM x2 CK0 CK0# A0-A12 A0-A12: DDR SDRAMS 6pF RAS#: DDR SDRAMS CAS#: DDR SDRAMS 4.5pF 120 DDR SDRAM x3 CK2 CK2# WE#: DDR SDRAMS DDR SDRAM x3 CK1 CK1# 4.5pF CKE0: DDR SDRAMS VDDSPD SPD VDDQ DDR SDRAMS VSS SDA DDR SDRAMS VREF U10 A0 A1 A2 DDR SDRAMS VDD SERIAL PD SCL WP DDR SDRAMS SA0 SA1 SA2 NOTE: 1. All resistor values are 22W unless otherwise specified. 2. Per industry standard, Micron utilizes various component speed grades as referenced in the Module Part Numbering Guide at www.micron.com/numberguide. 3. To optimize system and loading and signal integrity for -335 speed grade, 3W stub resistors may be placed on command/address and control lines. Contact Micron CCG Applications for additional information. 09005aef80867a99 DD8C16 DD8C16_32_64x64AG_A.fm - Rev. A 8/03 EN 6 MT46V16M8TG MT46V16M8TG = DDR SDRAMs, 128MB 128MB Module MT46V32M8TG MT46V32M8TG = DDR SDRAMs, 256MB 256MB Module MT46V64M8TG MT46V64M8TG = DDR SDRAMs, 512MB 512MB Module Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology. Inc. 128MB 128MB, 256MB 256MB, 512MB 512MB (x64) 184-PIN 184-PIN DDR SDRAM DIMM General Description The pipelined, multibank architecture of DDR SDRAM modules allows for concurrent operation, thereby providing high effective bandwidth by hiding row precharge and activation time. An auto refresh mode is provided, along with a power-saving power-down mode. All inputs are compatible with the JEDEC Standard for SSTL_2. All outputs are SSTL_2, Class II compatible. For more information regarding DDR SDRAM operation, refer to the 128Mb, 256Mb, and 512Mb DDR SDRAM component data sheets. The MT8VDDT1664A MT8VDDT1664A, MT8VDDT3264A MT8VDDT3264A, and MT8VDDT6464A MT8VDDT6464A are high-speed CMOS, dynamic random-access, 128MB 128MB, 256MB 256MB, and 512MB 512MB memory modules organized in a x64 configuration. DDR SDRAM modules use internally configured quad-bank DDR SDRAM devices. DDR SDRAM modules use a double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the DDR SDRAM module effectively consists of a single 2n-bit wide, one-clock-cycle data transfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O pins. A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in data capture at the receiver. DQS is an intermittent strobe transmitted by the DDR SDRAM during READs and by the memory controller during WRITEs. DQS is edge-aligned with data for READs and center-aligned with data for WRITEs. DDR SDRAM modules operate from multiple differential clocks (CK and CK#); the crossing of CK going HIGH and CK# going LOW will be referred to as the positive edge of CK. Commands (address and control signals) are registered at every positive edge of CK. Input data is registered on both edges of DQS, and output data is referenced to both edges of DQS, as well as to both edges of CK. Read and write accesses to DDR SDRAM modules are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the device bank and row to be accessed (BA0, BA1 select device bank; A0­A11 select device row for the 128MB 128MB module, A0­A12 select device row for the 256MB 256MB and 512MB 512MB modules). The address bits registered coincident with the READ or WRITE command are used to select the device bank and the starting device column location for the burst access. DDR SDRAM modules provide for programmable read or write burst lengths of 2, 4, or 8 locations. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. 09005aef80867a99 DD8C16 DD8C16_32_64x64AG_A.fm - Rev. A 8/03 EN Serial Presence-Detect Operation These DDR SDRAM modules incorporate serial presence-detect (SPD). The SPD function is implemented using a 2,048-bit EEPROM. This nonvolatile storage device contains 256 bytes. The first 128 bytes can be programmed by Micron to identify the module type and various SDRAM organizations and timing parameters. The remaining 128 bytes of storage are available for use by the customer. System READ/ WRITE operations between the master (system logic) and the slave EEPROM device (DIMM) occur via a standard I2C bus using the DIMM's SCL (clock) and SDA (data) signals, together with SA (2:0), which provide eight unique DIMM/EEPROM addresses. Write protect (WP) is tied to ground on the module, permanently disabling hardware write protect. Mode Register Definition The mode register is used to define the specific mode of operation of the DDR SDRAM device. This definition includes the selection of a burst length, a burst type, a CAS latency and an operating mode, as shown in Figure 4, Mode Register Definition Diagram, on page 8. The mode register is programmed via the MODE REGISTER SET command (with BA0 = 0 and BA1 = 0) and will retain the stored information until it is programmed again or the device loses power (except for bit A8, which is self-clearing). Reprogramming the mode register will not alter the contents of the memory, provided it is performed correctly. The mode register must be loaded (reloaded) when all device banks are idle and no bursts are in progress, and the controller must wait the specified time before initiating the subsequent operation. Violating either of these requirements will result in unspecified operation. Mode register bits A0­A2 specify the burst length, A3 specifies the type of burst (sequential or interleaved), A4­A6 specify the CAS latency, and A7­A11 (128MB 128MB) or A7­A12 (256MB 256MB, 512MB 512MB) specify the operating mode. 7 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology. Inc. 128MB 128MB, 256MB 256MB, 512MB 512MB (x64) 184-PIN 184-PIN DDR SDRAM DIMM Burst Type Figure 4: Mode Register Definition Diagram Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit M3. The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in Table 6, Burst Definition Table, on page 9. 128MB 128MB Module BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 13 12 0* 0* 11 10 9 8 7 6 5 4 3 2 1 0 Operating Mode CAS Latency BT Burst Length Mode Register (Mx) * M13 and M12 (BA1 and BA0) must be "0, 0" to select the base mode register (vs. the extended mode register). Burst Length Read and write accesses to the DDR SDRAM are burst oriented, with the burst length being programmable, as shown in Figure 4, Mode Register Definition Diagram. The burst length determines the maximum number of column locations that can be accessed for a given READ or WRITE command. Burst lengths of 2, 4, or 8 locations are available for both the sequential and the interleaved burst types. Reserved states should not be used, as unknown operation or incompatibility with future versions may result. When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached. The block is uniquely selected by A1­Ai when the burst length is set to two, by A2­Ai when the burst length is set to four, and by A3­Ai when the burst length is set to eight (where Ai is the most significant column address bit for a given configuration. See Note 5 of Figure 6, Burst Definition Table, on page 9). The remaining (least significant) address bit(s) is (are) used to select the starting location within the block. The programmed burst length applies to both read and write bursts. 256MB 256MB and 512MB 512MB Modules BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 14 13 12 11 10 9 8 Operating Mode 0* 0* 7 6 5 4 3 2 1 0 CAS Latency BT Burst Length * M14 and M13 (BA1 and BA0) must be "0, 0" to select the base mode register (vs. the extended mode register). Address Bus Mode Register (Mx) Burst Length M2 M1 M0 M3 = 0 M3 = 1 0 0 0 Reserved Reserved 0 0 1 2 2 0 1 0 4 4 0 1 1 8 8 1 0 0 Reserved Reserved 1 0 1 Reserved Reserved 1 1 0 Reserved Reserved 1 1 1 Reserved Reserved Burst Type M3 0 Sequential 1 Interleaved CAS Latency M6 M5 M4 0 0 Reserved 0 1 Reserved 0 1 0 2 0 1 1 Reserved 1 0 0 Reserved 1 0 1 Reserved 1 1 0 2.5 1 The READ latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first bit of output data. The latency can be set to 2 or 2.5 clocks, as shown in Figure 5, CAS Latency Diagram, on page 9. If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available nominally coincident with clock edge n + m. Table 7, CAS Latency (CL) Table, on page 9, indicates the operating frequencies at which each CAS latency setting can be used. Reserved states should not be used as unknown operation or incompatibility with future versions may result. 0 0 Read Latency 09005aef80867a99 DD8C16 DD8C16_32_64x64AG_A.fm - Rev. A 8/03 EN Address Bus 1 1 Reserved M12 M11 M10 M9 M8 M7 M6-M0 Operating Mode 0 0 0 0 0 Valid Normal Operation 0 0 0 0 1 0 Valid Normal Operation/Reset DLL - 8 0 - - - - - - All other states reserved Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology. Inc. 128MB 128MB, 256MB 256MB, 512MB 512MB (x64) 184-PIN 184-PIN DDR SDRAM DIMM Table 6: BURST LENGTH 2 4 8 Figure 5: CAS Latency Diagram Burst Definition Table T0 ORDER OF ACCESSES WITHIN A BURST STARTING COLUMN ADDRESS TYPE = SEQUENTIAL A0 0 1 A1 A0 0 0 0 1 1 0 1 1 A2 A1 A0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 COMMAND READ NOP T2n NOP T3 T3n NOP CL = 2 0-1 1-0 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 DQS 0-1 1-0 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 DQ CK# T0 T1 T2 READ NOP T2n T3 NOP T3n CK COMMAND NOP CL = 2.5 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 DQS 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0 DQ Burst Length = 4 in the cases shown Shown with nominal tAC, tDQSCK, and tDQSQ TRANSITIONING DATA The normal operating mode is selected by issuing a MODE REGISTER SET command with bits A7­A11 (128MB 128MB), or A7­A12 (256MB 256MB, 512MB 512MB) each set to zero, and bits A0­A6 set to the desired values. A DLL reset is initiated by issuing a MODE REGISTER SET command with bits A7 and A9­A11 (128MB 128MB), or A7 and A9­A12 (256MB 256MB, 512MB 512MB) each set to zero, bit A8 set to one, and bits A0­A6 set to the desired values. Although not required by the Micron device, JEDEC specifications recommend when a LOAD MODE REGISTER command is issued to reset the DLL, it should always be followed by a LOAD MODE REGISTER command to select normal operating mode. All other combinations of values for A7­A11, or A7­ A12, are reserved for future use and/or test modes. Test modes and reserved states should not be used because unknown operation or incompatibility with future versions may result. CAS Latency (CL) Table ALLOWABLE OPERATING CLOCK FREQUENCY (MHZ) SPEED CL = 2 CL = 2.5 -335 -262 -26A -265 -202 75 £ f £ 133 75 £ f £ 133 75 £ f £ 133 75 £ f £ 100 75 £ f £ 100 DON'T CARE Operating Mode 1. For a burst length of two, A1­Ai select the twodata-element block; A0 selects the first access within the block. 2. For a burst length of four, A2­Ai select the fourdata-element block; A0­A1 select the first access within the block. 3. For a burst length of eight, A3­Ai select the eightdata-element block; A0­A2 select the first access within the block. 4. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block. 5. i = 9 (128MB 128MB, 256MB 256MB) i = 9, 11 (512MB 512MB) 75 £ f £ 167 75 £ f £ 133 75 £ f £ 133 75 £ f £ 133 N/A 09005aef80867a99 DD8C16 DD8C16_32_64x64AG_A.fm - Rev. A 8/03 EN T2 CK TYPE = INTERLEAVED NOTE: Table 7: T1 CK# Extended Mode Register The extended mode register controls functions beyond those controlled by the mode register; these additional functions are DLL enable/disable and output drive strength. These functions are controlled via the bits shown in Figure 6, Extended Mode Register Definition Diagram, on page 10. The extended mode register is programmed via the LOAD MODE REGIS- 9 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology. Inc. 128MB 128MB, 256MB 256MB, 512MB 512MB (x64) 184-PIN 184-PIN DDR SDRAM DIMM Figure 6: Extended Mode Register Definition Diagram TER command to the mode register (with BA0 = 1 and BA1 = 0) and will retain the stored information until it is programmed again or the device loses power. The enabling of the DLL should always be followed by a LOAD MODE REGISTER command to the mode register (BA0/BA1 both low) to reset the DLL. The extended mode register must be loaded when all device banks are idle and no bursts are in progress, and the controller must wait the specified time before initiating any subsequent operation. Violating either of these requirements could result in unspecified operation. 128MB 128MB Module BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 13 12 11 10 9 8 7 6 5 Operating Mode 01 11 4 3 2 1 Address Bus 0 Extended Mode Register (Ex) DS DLL 256MB 256MB and 512MB 512MB Modules BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus DLL Enable/Disable 14 13 12 11 10 9 8 7 6 5 Operating Mode 01 11 The DLL must be enabled for normal operation. DLL enable is required during power-up initialization and upon returning to normal operation after having disabled the DLL for the purpose of debug or evaluation. (When the device exits self refresh mode, the DLL is enabled automatically.) Any time the DLL is enabled, 200 clock cycles must occur before a READ command can be issued. 4 3 2 1 0 Extended Mode Register (Ex) DS DLL E0 DLL 0 Enable 1 Disable E1 E12 E11 E10 E9 E8 E7 E6 E5 E4 E3 E22 Drive Strength 0 Normal E1, E0 Operating Mode 0 0 0 0 0 0 0 0 0 0 0 Valid Reserved ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ Reserved NOTE: 1. BA1 and BA0 (E13 and E12 for 128MB 128MB, E14 and E13 for 256MB 256MB and 512MB 512MB) must be "0, 1" to select the Extended Mode Register (vs. the base Mode Register). 2. The QFC# option is not supported. 09005aef80867a99 DD8C16 DD8C16_32_64x64AG_A.fm - Rev. A 8/03 EN 10 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology. Inc. 128MB 128MB, 256MB 256MB, 512MB 512MB (x64) 184-PIN 184-PIN DDR SDRAM DIMM Commands Table 8, Commands Truth Table, and Table 9, DM Operation Truth Table, provide a general reference of available commands. For a more detailed description Table 8: of commands and operations, refer to the 128Mb , 256Mb, and 512Mb DDR SDRAM component data sheets. Commands Truth Table CKE is HIGH for all commands shown except SELF REFRESH NAME (FUNCTION) CS# CAS# WE# ADDR NOTES H L L L L L L L L DESELECT (NOP) NO OPERATION (NOP) ACTIVE (Select bank and activate row) READ (Select bank and column, and start READ burst) WRITE (Select bank and column, and start WRITE burst) BURST TERMINATE PRECHARGE (Deactivate row in bank or banks) AUTO REFRESH or SELF REFRESH (Enter self refresh mode) LOAD MODE REGISTER RAS# X H L H H H L L L X H H L L H H L L X H H H L L L H L X X Bank/Row Bank/Col Bank/Col X Code X Op-Code 1 1 2 3 3 4 5 6, 7 8 NOTE: 1. DESELECT and NOP are functionally interchangeable. 2. BA0­BA1 provide device bank address and A0­A11 (128MB 128MB) or A0­A12 (256MB 256MB, 512MB 512MB) provide device row address. 3. BA0­BA1 provide device bank address; A0­A9 (128MB 128MB, 256MB 256MB) or A0­A9 , A11( 512MB 512MB) provide device column address; A10 HIGH enables the auto precharge feature (non-persistent), and A10 LOW disables the auto precharge feature. 4. Applies only to read bursts with auto precharge disabled; this command is undefined (and should not be used) for read bursts with auto precharge enabled and for write bursts. 5. A10 LOW: BA0­BA1 determine which device bank is precharged. A10 HIGH: all device banks are precharged and BA0­BA1 are "Don't Care." 6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW. 7. Internal refresh counter controls device row addressing; all inputs and I/Os are "Don't Care" except for CKE. 8. BA0­BA1 select either the mode register or the extended mode register (BA0 = 0, BA1 = 0 select the mode register; BA0 = 1, BA1 = 0 select extended mode register; other combinations of BA0­BA1 are reserved). A0­A11 (128MB 128MB) or A0­A12 (256MB 256MB, 512MB 512MB) provide the op-code to be written to the selected mode register. Table 9: DM Operation Truth Table Used to mask write data; provided coincident with the corresponding data NAME (FUNCTION) DM L H WRITE Enable WRITE Inhibit 09005aef80867a99 DD8C16 DD8C16_32_64x64AG_A.fm - Rev. A 8/03 EN 11 DQS Valid X Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology. Inc. 128MB 128MB, 256MB 256MB, 512MB 512MB (x64) 184-PIN 184-PIN DDR SDRAM DIMM Absolute Maximum Ratings Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the opera- tional sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Voltage on VDD Supply Relative to VSS . . . . . . . . . . . . . . . . . . . . -1V to +3.6V Voltage on VDDQ Supply Relative to VSS . . . . . . . . . . . . . . . . . . . . -1V to +3.6V Voltage on VREF and Inputs Relative to VSS . . . . . . . . . . . . . . . . . . . . -1V to +3.6V Voltage on I/O Pins Relative to VSS . . . . . . . . . . . . -0.5V to VDDQ +0.5V Operating Temperature TA (ambient) . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C Storage Temperature (plastic) . . . . . .-55°C to +150°C Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . 8W Short Circuit Output Current. . . . . . . . . . . . . . . . 50mA Table 10: DC Electrical Characteristics and Operating Conditions Notes: 1­5, 14; notes appear on pages 20­23; 0°C £ TA £ +70°C PARAMETER/CONDITION SYMBOL Supply Voltage I/O Supply Voltage I/O Reference Voltage I/O Termination Voltage (system) Input High (Logic 1) Voltage Input Low (Logic 0) Voltage Command/ INPUT LEAKAGE CURRENT ANY INPUT 0V £ VIN £ VDD, VREF PIN 0V £ VIN £ 1.35V Address, RAS#, (All other pins not under test = 0V) CAS#, WE#, S#, CKE CK0, CK0# CK1, CK1#, CK2, CK2# DM DQ, DQS OUTPUT LEAKAGE CURRENT (DQs are disabled; 0V £ VOUT £ VDDQ) OUTPUT LEVELS: High Current (VOUT = VDDQ-0.373V, minimum VREF, minimum VTT) Low Current (VOUT = 0.373V, maximum VREF, maximum VTT) VDD VDDQ VREF VTT VIH(DC) VIL(DC) II MIN MAX UNITS NOTES V V V V V V µA 32, 36 32, 36, 39 6, 39 7, 39 25 25 47 2.3 2.7 2.3 2.7 0.49 x VDDQ 0.51 x VDDQ VREF - 0.04 VREF + 0.04 VREF + 0.15 VDD + 0.3 -0.3 VREF - 0.15 -16 16 -4 4 -6 6 IOZ -5 -5 5 5 µA 47 IOH IOL -16.8 16.8 ­ ­ mA mA 33, 34 Table 11: AC Input Operating Conditions Notes: 1­5, 14; notes appear on pages 20­23; 0°C £ TA £ +70°C; VDD = VDDQ = +2.5V ±0.2V PARAMETER/CONDITION Input High (Logic 1) Voltage Input Low (Logic 0) Voltage I/O Reference Voltage 09005aef80867a99 DD8C16 DD8C16_32_64x64AG_A.fm - Rev. A 8/03 EN SYMBOL MIN MAX UNITS NOTES VIH(AC) VIL(AC) VREF(AC) VREF + 0.310 ­ 0.49 x VDDQ ­ VREF - 0.310 0.51 x VDDQ V V V 12, 25, 35 12, 25, 35 6 12 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology. Inc. 128MB 128MB, 256MB 256MB, 512MB 512MB (x64) 184-PIN 184-PIN DDR SDRAM DIMM Table 12: IDD Specifications and Conditions ­ 128MB 128MB DDR SDRAM components only Notes: 1­5, 8, 10, 12, 48; notes appear on pages 20­23; 0°C £ TA £ +70°C; VDD = VDDQ = +2.5V ±0.2V MAX PARAMETER/CONDITION SYM -335 -262 -26A/ -26A/ -265 -202 UNITS NOTES OPERATING CURRENT: One device bank; Active-Precharge; RC = tRC (MIN); tCK = tCK (MIN); DQ, DM, and DQS inputs changing once per clock cycle; Address and control inputs changing once every two clock cycles OPERATING CURRENT: One device bank; Active-Read-Precharge; Burst = 2; tRC = tRC (MIN); tCK = tCK (MIN); IOUT = 0mA; Address and control inputs changing once per clock cycle PRECHARGE POWER-DOWN STANDBY CURRENT: All device banks idle; Power-down mode; tCK = tCK (MIN); CKE = LOW IDLE STANDBY CURRENT: CS# = HIGH; All device banks idle; t CK = tCK (MIN); CKE = HIGH; Address and other control inputs changing once per clock cycle. VIN = VREF for DQ, DQS, and DM ACTIVE POWER-DOWN STANDBY CURRENT: One device bank active; Power-down mode; tCK = tCK (MIN); CKE = LOW ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One device bank; Active-Precharge; tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); IOUT = 0mA OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle t AUTO REFRESH CURRENT RC = tREFC (MIN) IDD0 960 880 840 800 mA 20, 42 IDD1 1,080 960 960 880 mA 20, 42 IDD2P 24 24 24 24 mA 21, 28, 44 IDD2F 360 360 360 280 mA 45 IDD3P 200 200 160 160 mA 21, 28, 44 IDD3N 360 360 360 280 mA 20, 41 IDD4R 1,040 1,040 1,000 840 mA 20, 42 IDD4W 1,080 1,000 920 840 mA 20 IDD5 1,880 1,720 1,680 1,640 mA 20, 44 IDD5A 40 40 40 40 mA 24, 44 IDD6 IDD7 24 2,840 24 2,640 16 2,600 16 2,200 mA mA 9 20, 43 t t REFC = 15.625µs SELF REFRESH CURRENT: CKE £ 0.2V OPERATING CURRENT: Four device bank interleaving READs (BL= 4) with auto precharge,tRC = minimum tRC allowed; t CK = tCK (MIN); Address and control inputs change only during Active, READ, or WRITE commands 09005aef80867a99 DD8C16 DD8C16_32_64x64AG_A.fm - Rev. A 8/03 EN 13 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology. Inc. 128MB 128MB, 256MB 256MB, 512MB 512MB (x64) 184-PIN 184-PIN DDR SDRAM DIMM Table 13: IDD Specifications and Conditions ­ 256MB 256MB DDR SDRAM components only Notes: 1­5, 8, 10, 12, 48; notes appear on pages 20­23; 0°C £ TA £ +70°C; VDD = VDDQ = +2.5V ±0.2V MAX SYM -335 -262 -26A/ -26A/ -265 -202 IDD0 OPERATING CURRENT: One device bank; Active-Precharge; tRC = t t t RC (MIN); CK = CK (MIN); DQ, DM, and DQS inputs changing once per clock cycle; Address and control inputs changing once every two clock cycles IDD1 OPERATING CURRENT: One device bank; Active-Read-Pre-charge; Burst = 4; tRC = tRC (MIN); tCK = tCK (MIN); IOUT = 0mA; Address and control inputs changing once per clock cycle PRECHARGE POWER-DOWN STANDBY CURRENT: All device banks IDD2P idle; Power-down mode; tCK = tCK (MIN); CKE = LOW IDD2F IDLE STANDBY CURRENT: CS# = HIGH; All device banks idle; t CK = tCK (MIN); CKE = HIGH; Address and other control inputs changing once per clock cycle. VIN = VREF for DQ, DQS, and DM IDD3P ACTIVE POWER-DOWN STANDBY CURRENT: One device bank t t active; Power-down mode; CK = CK (MIN); CKE = LOW IDD3N ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One device bank; Active-Precharge; tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle IDD4R OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); IOUT = 0mA IDD4W OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle t IDD5 AUTO REFRESH CURRENT RC = tREFC (MIN) 1,000 1,000 840 960 mA 20, 42 1,360 1,280 1,160 1,240 mA 20, 42 32 32 32 32 mA 21, 28, 44 400 360 360 360 mA 45 240 200 200 240 mA 21, 28, 44 480 400 400 400 mA 20, 41 1,400 1,200 1,200 1,400 mA 20, 42 1,240 1,080 1,080 1,520 mA 20 2,040 1,880 1,880 1,960 mA 20, 44 IDD5A REFC = 7.8125µs IDD6 SELF REFRESH CURRENT: CKE £ 0.2V IDD7 OPERATING CURRENT: Four device bank interleaving READs (BL= 4) with auto precharge,tRC = minimum tRC allowed; tCK = tCK (MIN); Address and control inputs change only during Active, READ, or WRITE commands 48 48 48 48 mA 24, 44 32 3,240 32 2,800 32 2,800 32 2,920 mA mA 9 20, 43 PARAMETER/CONDITION t 09005aef80867a99 DD8C16 DD8C16_32_64x64AG_A.fm - Rev. A 8/03 EN 14 UNITS NOTES Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology. Inc. 128MB 128MB, 256MB 256MB, 512MB 512MB (x64) 184-PIN 184-PIN DDR SDRAM DIMM Table 14: IDD Specifications and Conditions ­ 512MB 512MB DDR SDRAM components only Notes: 1­5, 8, 10, 12, 48; notes appear on pages 20­23; 0°C £ TA £ +70°C; VDD = VDDQ = +2.5V ±0.2V MAX SYM t t OPERATING CURRENT: One device bank; Active-Precharge; RC = RC (MIN); tCK = tCK (MIN); DQ, DM, and DQS inputs changing once per clock cycle; Address and control inputs changing once every two clock cycles OPERATING CURRENT: One device bank; Active-Read-Pre-charge; Burst = 4; tRC = tRC (MIN); tCK = tCK (MIN); IOUT = 0mA; Address and control inputs changing once per clock cycle PRECHARGE POWER-DOWN STANDBY CURRENT: All device banks idle; Power-down mode; tCK = tCK (MIN); CKE = LOW IDLE STANDBY CURRENT: CS# = HIGH; All device banks idle; t CK = tCK (MIN); CKE = HIGH; Address and other control inputs changing once per clock cycle. VIN = VREF for DQ, DQS, and DM ACTIVE POWER-DOWN STANDBY CURRENT: One device bank active; Power-down mode; tCK = tCK (MIN); CKE = LOW ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One device bank; Active-Precharge; tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; t CK = tCK (MIN); IOUT = 0mA OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; t CK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle t AUTO REFRESH CURRENT RC = tREFC (MIN) t REFC = 7.8125µs SELF REFRESH CURRENT: CKE £ 0.2V OPERATING CURRENT: Four device bank interleaving READs (BL = 4) with auto precharge,tRC = minimum tRC allowed; tCK = tCK (MIN); Address and control inputs change only during Active, READ, or WRITE commands -335 -262 UNITS NOTES IDD0 1,040 1,040 920 mA 20, 42 IDD1 1,480 1,480 1,160 mA 20, 42 IDD2P 40 40 40 mA 21, 28, 44 IDD2F 360 360 320 mA 45 IDD3P 280 280 240 mA 21, 28, 44 IDD3N 360 360 320 mA 41 IDD4R 1,320 1,320 1,160 mA 20, 42 IDD4W 1,240 1,240 1,080 mA 20 IDD5 2,320 2,320 2,240 mA 20, 44 IDD5A PARAMETER/CONDITION -26A/ -26A/ -265 -202 80 80 80 mA 24, 44 IDD6 IDD7 40 3,240 40 3,200 40 2,800 mA mA 9 20, 43 Table 15: Capacitance Note: 11; notes appear on pages 20­23 PARAMETER SYMBOL 09005aef80867a99 DD8C16 DD8C16_32_64x64AG_A.fm - Rev. A 8/03 EN 15 MAX UNITS CIO CI 1 CI 2 CI 3 CI3 CI4 Input/Output Capacitance: DQ, DQS Input Capacitance: Command and Address, S#, CKE Input Capacitance: CK0, CK0# Input Capacitance: CK1, CK1#; CK2, CK2# Input Capacitance: SDA Input Capacitance: SCL, SA0, SA2 MIN 4.0 16.0 10.0 9.0 ­ ­ 5.0 24.0 12.0 12.0 8.0 6.0 pF pF pF pF pF pF Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology. Inc. 128MB 128MB, 256MB 256MB, 512MB 512MB (x64) 184-PIN 184-PIN DDR SDRAM DIMM Table 16: DDR SDRAM Component Electrical Characteristics and Recommended AC Operating Conditions (-335, -262) Notes: 1­5, 12­15, 29; notes appear on pages 20­23; 0°C £ TA £ +70°C; VDD = VDDQ = +2.5V ±0.2V AC CHARACTERISTICS -335 PARAMETER MIN MAX MIN MAX Access window of DQs from CK/CK# t -0.70 +0.70 -0.75 +0.75 CK high-level width t CH 0.45 0.55 0.45 0.55 t 26 CK low-level width t CL 0.45 0.55 0.45 0.55 t 26 CK (2.5) 6 12 7.5 7.5 12 7.5/10 Clock cycle time SYM -262 AC CL = 2.5 CL = 2 t t CK (2) UNITS NOTES ns CK 13 CK ns 40, 46 13 ns 40, 46 DQ and DM input hold time relative to DQS t DH 0.45 0.5 ns 23, 27 DQ and DM input setup time relative to DQS t 0.45 0.5 ns 23, 27 ns 27 DS DQ and DM input pulse width (for each input) t DIPW 1.75 Access window of DQS from CK/CK# t DQSCK -0.60 DQS input high pulse width t DQSH 0.35 0.35 t DQS input low pulse width t 0.35 0.35 t DQS-DQ skew, DQS to last DQ valid, per group, per access t Write command to first DQS latching transition t DQSL 1.75 +0.60 +0.75 0.75 1.25 ns CK 0.45 DQSQ DQSS -0.75 0.5 0.75 1.25 CK ns 22, 23 t CK DQS falling edge to CK rising - setup time t DSS 0.2 0.2 t DQS falling edge from CK rising - hold time t DSH 0.2 0.2 t CK CK ns 30 ns 16, 37 -0.75 ns 16, 38 0.75 0.90 ns 12 ISF 0.75 0.90 ns 12 IHS 0.80 1 ns 12 t ISS 0.80 1 ns 12 IPW 2.2 2.2 ns 15 ns HP QHS ns Half clock period t t Data-outhigh-impedancewindowfromCK/CK# t Data-outlow-impedancewindowfromCK/CK# t LZ -0.70 Address and control input hold time (fast slew rate) t IHF Address and control input setup time (fast slew rate) t Address and control input hold time (slow slew rate) t Address and control input setup time (slow slew rate) HP HZ Address and Control input pulse width (for each input) t LOAD MODE REGISTER command cycle time t t CH, CL +0.70 12 MRD t t QH CH, CL +0.75 t t DQ-DQS hold, DQS to first DQ to go non-valid, per access t t 22, 23 t HP QHS 0.55 0.75 ns 120,000 ns Data hold skew factor t ACTIVE to PRECHARGE command t RAS 42 ACTIVE to READ with auto precharge command t RAP 18 15 ns t RC 60 60 ns QHS ACTIVEto ACTIVE/AUTO REFRESH command period 70,000 40 AUTO REFRESH command period t RFC 72 75 ns ACTIVE to READ or WRITE delay t RCD 18 15 ns t 15 31 RP 18 DQS read preamble t RPRE 0.9 1.1 0.9 1.1 t DQS read postamble t 0.4 0.6 0.4 0.6 44 t PRECHARGE command period 09005aef80867a99 DD8C16 DD8C16_32_64x64AG_A.fm - Rev. A 8/03 EN RPST 16 ns CK 37 CK Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology. Inc. 128MB 128MB, 256MB 256MB, 512MB 512MB (x64) 184-PIN 184-PIN DDR SDRAM DIMM Table 16: DDR SDRAM Component Electrical Characteristics and Recommended AC Operating Conditions (-335, -262) (Continued) Notes: 1­5, 12­15, 29; notes appear on pages 20­23; 0°C £ TA £ +70°C; VDD = VDDQ = +2.5V ±0.2V AC CHARACTERISTICS -335 PARAMETER SYM MIN MIN 12 WPRE 0.25 WPRES 0 0 t DQS write preamble setup time t DQS write postamble t WPST 0.4 t 15 Write recovery time WR t Data valid output window WTR na t REFC t REFI t VTD 0.6 QH - DQSQ 140.6 70.3 15.6 7.8 0 t 75 75 Exit SELF REFRESH to READ command t 200 200 XSRD 17 0.6 t CK ns 18, 19 17 t t QH - DQSQ 140.6 70.3 15.6 7.8 0 Exit SELF REFRESH to non-READ command XSNR CK ns 1 t NOTES ns 15 1 t UNITS t 0.4 t 09005aef80867a99 DD8C16 DD8C16_32_64x64AG_A.fm - Rev. A 8/03 EN MAX 15 0.25 ACTIVE bank a to ACTIVE bank b command REFRESH to REFRESH command interval 128MB 128MB 256MB 256MB, 512MB 512MB Average periodic refresh interval 128MB 128MB 256MB 256MB, 512MB 512MB Terminating voltage delay to VDD MAX RRD t DQS write preamble Internal WRITE to READ command delay -262 CK ns µs µs µs µs ns 22 21 21 21 21 ns t CK Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology. Inc. 128MB 128MB, 256MB 256MB, 512MB 512MB (x64) 184-PIN 184-PIN DDR SDRAM DIMM Table 17: DDR SDRAM Component Electrical Characteristics and Recommended AC Operating Conditions (-26A, -265, -202) Notes: 1­5, 12­15, 29, 48.; notes appear on pages 20­23; 0°C £ TA £ +70°C; VDD = VDDQ = +2.5V ±0.2V AC CHARACTERISTICS -26A/-265 -26A/-265 PARAMETER MIN MAX Access window of DQs from CK/CK# t -0.75 CK high-level width t CH 0.45 CK low-level width t CL CK (2.5) Clock cycle time SYM AC CL = 2.5 CL = 2 t t CK (2) -202 MIN MAX UNITS NOTES +0.75 -0.8 +0.8 0.55 0.45 0.55 t 26 0.45 0.55 0.45 0.55 t 26 7.5 13 8 7.5/10 13 10 ns CK 13 CK ns 40, 46 13 ns 40, 46 DQ and DM input hold time relative to DQS t DH 0.5 0.6 ns 23, 27 DQ and DM input setup time relative to DQS t 0.5 0.6 ns 23, 27 ns 27 DS DQ and DM input pulse width (for each input) t DIPW 1.75 Access window of DQS from CK/CK# t DQSCK -0.75 DQS input high pulse width t DQSH 0.35 0.35 t DQS input low pulse width t 0.35 0.35 t DQS-DQ skew, DQS to last DQ valid, per group, per access t Write command to first DQS latching transition t DQSL -0.8 0.5 DQSQ DQSS 2 +0.75 0.75 1.25 +0.8 CK 0.6 0.75 ns 1.25 CK ns 22, 23 t CK DQS falling edge to CK rising - setup time t DSS 0.2 0.2 t DQS falling edge from CK rising - hold time t DSH 0.2 0.2 t tCH, tCL tCH, tCL CK CK ns 30 ns 16, 37 -0.8 ns 16, 38 0.90 1.1 ns 12 t ISF 0.90 1.1 ns 12 Address and control input hold time (slow slew rate) t IHS 1 1.1 ns 12 Address and control input setup time (slow slew rate) t ISS 1 1.1 ns 12 IPW 2.2 2.2 ns 16 ns HP QHS ns Half clock period t Data-out high-impedance window from CK/CK# t Data-out low-impedance window from CK/CK# t LZ -0.75 Address and control input hold time (fast slew rate) t IHF Address and control input setup time (fast slew rate) HP +0.75 HZ Address and Control input pulse width (for each input) t LOAD MODE REGISTER command cycle time t 15 MRD t +0.8 Data hold skew factor t ACTIVE to READ with auto precharge command t 0.75 QHS RAS 40 120,000 1 40 ns 120,000 ns RAP 20 20 RC 65 70 31 ns t ACTIVEto ACTIVE/AUTO REFRESH command period 22, 23 t HP QHS t ACTIVE to PRECHARGE command QH t t DQ-DQS hold, DQS to first DQ to go non-valid, per access t ns AUTO REFRESH command period t RFC 75 80 ns ACTIVE to READ or WRITE delay t RCD 20 20 ns t RP 20 20 RPRE 0.9 1.1 0.9 1.1 t 0.4 0.6 0.4 0.6 t PRECHARGE command period DQS read preamble t DQS read postamble t 09005aef80867a99 DD8C16 DD8C16_32_64x64AG_A.fm - Rev. A 8/03 EN RPST 18 44 ns CK 37 CK Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology. Inc. 128MB 128MB, 256MB 256MB, 512MB 512MB (x64) 184-PIN 184-PIN DDR SDRAM DIMM Table 17: DDR SDRAM Component Electrical Characteristics and Recommended AC Operating Conditions (-26A, -265, -202) (Continued) Notes: 1­5, 12­15, 29, 48.; notes appear on pages 20­23; 0°C £ TA £ +70°C; VDD = VDDQ = +2.5V ±0.2V AC CHARACTERISTICS -26A/-265 -26A/-265 PARAMETER SYM MIN MAX -202 MIN RRD 15 t WPRE 0.25 0.25 DQS write preamble setup time t WPRES 0 0 DQS write postamble t MAX 15 DQS write preamble t ACTIVE bank a to ACTIVE bank b command WPST 0.4 t 15 Write recovery time Internal WRITE to READ command delay t Data valid output window REFRESH to REFRESH command interval 128MB 128MB 256MB 256MB, 512MB 512MB Average periodic refresh interval 128MB 128MB 256MB 256MB, 512MB 512MB Terminating voltage delay to VDD t WR WTR na REFC t REFI t VTD 0.6 QH - DQSQ 140.6 70.3 15.6 7.8 0 75 80 Exit SELF REFRESH to READ command t 200 200 09005aef80867a99 DD8C16 DD8C16_32_64x64AG_A.fm - Rev. A 8/03 EN 19 0.6 t CK ns 18, 19 17 t t QH - DQSQ 140.6 70.3 15.6 7.8 0 Exit SELF REFRESH to non-READ command XSRD CK ns 1 t t XSNR ns 15 t NOTES t 0.4 1 t UNITS CK ns µs µs µs µs ns 22 21 21 21 21 ns t CK Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology. Inc. 128MB 128MB, 256MB 256MB, 512MB 512MB (x64) 184-PIN 184-PIN DDR SDRAM DIMM Notes 1. All voltages referenced to VSS. 2. Tests for AC timing, Idd, and electrical AC and DC characteristics may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. 3. Outputs measured with equivalent load: 12. VTT Output (VOUT) 13. 50 Reference Point 30pF 14. 4. AC timing and IDD tests may use a VIL-to-VIH swing of up to 1.5V in the test environment, but input timing is still referenced to VREF (or to the crossing point for CK/CK#), and parameter specifications are guaranteed for the specified AC input levels under normal use conditions. The minimum slew rate for the input signals used to test the device is 1V/ns in the range between VIL(AC) and VIH(AC). 5. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e., the receiver will effectively switch as a result of the signal crossing the AC input level, and will remain in that state as long as the signal does not ring back above [below] the DC input LOW [HIGH] level). 6. VREF is expected to equal VddQ/2 of the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise (non-common mode) on VREF may not exceed ±2 percent of the DC value. From VDDQ/2, VREF is allowed ±25mV for DC error and an additional ±25mV for AC noise, measured at the nearest VREF bypass capacitor. 7. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in the DC level of VREF. 8. IDD is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle time at CL = 2 for -26A and -202, CL = 2.5 for -335 and -265 with the outputs open. 9. Enables on-chip refresh and address counters. 10. IDD specifications are tested after the device is properly initialized, and is averaged at the defined cycle rate. 11. This parameter is sampled. VDD = +2.5V ±0.2V, VDDQ = +2.5V ±0.2V, VREF = Vss, f = 100 MHz, TA = 25°C, VOUT(DC) = VDDQ/2, VOUT (peak to peak) = 09005aef80867a99 DD8C16 DD8C16_32_64x64AG_A.fm - Rev. A 8/03 EN 15. 16. 17. 18. 19. 20. 21. 20 0.2V. DM input is grouped with I/O pins, reflecting the fact that they are matched in loading. For slew rates < 1 V/ns and ³ 0.5 Vns. If slew rate is less than 0.5 V/ns, timing must be derated: tIS has an additional 50ps per each 100 mV/ns reduction in slew rate from 500 mV/ns, while tIH is unaffected. If slew rate exceeds 4.5V/ns, functionality is uncertain. The CK/CK# input reference level (for timing referenced to CK/CK#) is the point at which CK and CK# cross; the input reference level for signals other than CK/CK# is VREF. Inputs are not recognized as valid until VREF stabilizes. Exception: during the period before Vref stabilizes, CKE £ 0.3 x VDDQ is recognized as LOW. The output timing reference level, as measured at the timing reference point indicated in Note 3, is VTT. Transitions occur in the same access time windows as data valid transitions. These parameters are not referenced to a specific voltage level, but specify when the device output is no longer driving (tRPST, tHZ) or begins driving (LZ). The intent of the Don't Care state after completion of the postamble is the DQS-driven signal should either be high, low, or high-Z and that any signal transition within the input switching region must follow valid input requirements. That is, if DQS transitions high (above VIHDC (MIN) then it must not transition low (below VIHDC) prior to tDQSH (MIN). This is not a device limit. The device will operate with a negative value, but system performance could be degraded due to bus turnaround. It is recommended that DQS be valid (HIGH or LOW) on or before the WRITE command. The case shown (DQS going from High-Z to logic LOW) applies when no WRITEs were previously in progress on the bus. If a previous WRITE was in progress, DQS could be HIGH during this time, depending on tDQSS. MIN (tRC or tRFC) for IDD measurements is the smallest multiple of tCK that meets the minimum absolute value for the respective parameter. tRAS (MAX) for IDD measurements is the largest multiple of tCK that meets the maximum absolute value for tRAS. The refresh period 64ms. This equates to an average refresh rate of 15.625µs (128MB 128MB), or 7.8125µs (256MB 256MB, 512MB 512MB). However, an AUTO REFRESH Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology. Inc. 128MB 128MB, 256MB 256MB, 512MB 512MB (x64) 184-PIN 184-PIN DDR SDRAM DIMM 22. 23. 24. 25. command must be asserted at least once every 140.6µs (128MB 128MB) or 70.3µs (256MB 256MB, 512MB 512MB); burst refreshing or posting by the DRAM controller greater than eight refresh cycles is not allowed. The valid data window is derived by achieving other specifications: tHP (tCK/2), tDQSQ, and tQH (tQH = tHP - tQHS). The data valid window derates directly porportional with the clock duty cycle and a practical data valid window can be derived. The clock is allowed a maximum duty cycle variation of 45/55, beyond which functionality is uncertain. Figure 7, Derating Data Valid Window, shows derating curves for duty cycles ranging between 50/50 and 45/55. Each byte lane has a corresponding DQS. This limit is actually a nominal value and does not result in a fail value. CKE is HIGH during REFRESH command period (tRFC [MIN]) else CKE is LOW (i.e., during standby). To maintain a valid level, the transitioning edge of the input must: a. Sustain a constant slew rate from the current AC level through to the target AC level, VIL(AC) or VIH(AC). 26. 27. 28. 29. 30. b. Reach at least the target AC level. c. After the AC target level is reached, continue to maintain at least the target DC level, VIL(DC) or VIH(DC). CK and CK# input slew rate must be ³ 1V/ns (£2V/ ns differentially). DQ and DM input slew rates must not deviate from DQS by more than 10 percent. If the DQ/ DM/DQS slew rate is less than 0.5V/ns, timing must be derated: 50ps must be added to tDS and t DH for each 100mv/ns reduction in slew rate. For -335 speed grade, slow rate must be ³ 0.5 V/ns. If slew rate exceeds 4V/ns, functionality is uncertain. VDD must not vary more than 4 percent if CKE is not active while any bank is active. The clock is allowed up to ±150ps of jitter. Each timing parameter is allowed to vary by the same amount. t HP min is the lesser of tCL minimum and tCH minimum actually applied to the device CK and CK# inputs, collectively during bank active. Figure 7: Derating Data Valid Window (tQH - tDQSQ) 3.8 3.750 3.700 3.6 3.400 3.4 3.350 3.650 3.600 3.550 3.500 3.450 3.300 3.400 3.250 3.200 3.150 3.2 -26A/-265 -26A/-265 @ tCK = 10ns -202 @ tCK = 10ns -26A/-265 -26A/-265 @ tCK = 7.5ns -202 @ tCK = 8ns N/A -335 @ tCK = 6ns ns 3.0 2.8 2.6 3.100 2.500 2.463 2.425 3.350 2.388 2.350 2.313 2.275 3.250 3.050 3.000 2.4 3.300 2.238 2.200 2.950 2.163 2.2 2.900 2.125 2.0 1.8 50/50 49.5/50.5 49/51 48.5/52.5 48/52 47.5/53.5 47/53 46.5/54.5 46/54 45.5/55.5 45/55 Clock Duty Cycle 09005aef80867a99 DD8C16 DD8C16_32_64x64AG_A.fm - Rev. A 8/03 EN 21 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology. Inc. 128MB 128MB, 256MB 256MB, 512MB 512MB (x64) 184-PIN 184-PIN DDR SDRAM DIMM 31. READs and WRITEs with auto precharge are not allowed to be issued until tRAS(min) can be satisfied prior to the internal precharge command being issued. 32. Any positive glitch in the nominal voltage must be less than 1/3 of the clock and not more than +400mV or 2.9V, whichever is less. Any negative glitch must be less than 1/3 of the clock cycle and not exceed either -300mV or 2.2V, whichever is more positive. 33. Normal Output Drive Curves: a. The full variation in driver pull-down current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the V-I curve of Figure 8, Pull-Down Characteristics. b. The variation in driver pull-down current within nominal limits of voltage and temperature is expected, but not guaranteed, to lie within the inner bounding lines of the V-I curve of Figure 8, Pull-Down Characteristics. c. The full variation in driver pull-up current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the V-I curve of Figure 9, Pull-Up Characteristics. d. The variation in driver pull-up current within nominal limits of voltage and temperature is expected, but not guaranteed, to lie within the inner bounding lines of the V-I curve of Figure 9, Pull-Up Characteristics. e. The full variation in the ratio of the maximum to minimum pull-up and pull-down current should be between 0.71 and 1.4, for device drain-to-source voltages from 0.1V to 1.0V, and at the same voltage and temperature. f. The full variation in the ratio of the nominal pull-up to pull-down current should be unity ±10 percent, for device drain-to-source voltages from 0.1V to 1.0V. The voltage levels used are derived from a minimum VDD level and the referenced test load. In practice, the voltage levels obtained from a properly terminated bus will provide significantly different voltage values. VIH overshoot: VIH(MAX) = VDDQ + 1.5V for a pulse width £ 3ns and the pulse width cannot be greater than 1/3 of the cycle rate. VIL undershoot: VIL (MIN) = -1.5V for a pulse width £ 3ns and the pulse width cannot be greater than 1/3 of the cycle rate. VDD and VDDQ must track each other. This maximum value is derived from the referenced test load. In practice, the values obtained in a typical terminated design may reflect up to 310ps less for tHZ (MAX) and the last DVW. tHZ (MAX) will prevail over tDQSCK (MAX) + tRPST (MAX) condition. tLZ (MIN) will prevail over t DQSCK (MIN) + tRPRE (MAX) condition. For slew rates greater than 1V/ns the (LZ) transition will start about 310ps earlier. During initialization, VDDQ, VTT, and VREF must be equal to or less than VDD + 0.3V. Alternatively, VTT may be 1.35V maximum during power up, even if VDD/VDDQ are 0V, provided a minimum of 42W of series resistance is used between the VTT supply and the input pin. The current Micron part operates below the slowest JEDEC operating frequency of 83 MHz. As such, future die may not reflect this option. 34. 35. 36. 37. 38. 39. 40. Figure 8: Pull-Down Characteristics Figure 9: Pull-Up Characteristics 0 160 -20 um 140 Maxim Maximum -40 120 IOUT (mA) Nominal high -60 high IOUT (mA) Nominal 100 80 Nominal low -80 -100 Nom -120 inal 60 -140 Minimum 40 Min imu -160 20 low m -180 -200 0 0.0 0.5 1.0 1.5 2.0 0.0 2.5 09005aef80867a99 DD8C16 DD8C16_32_64x64AG_A.fm - Rev. A 8/03 EN 0.5 1.0 1.5 2.0 2.5 VDDQ - VOUT (V) VOUT (V) 22 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology. Inc. 128MB 128MB, 256MB 256MB, 512MB 512MB (x64) 184-PIN 184-PIN DDR SDRAM DIMM 41. For the -335, -262, -26A and -265 modules, IDD3N is specified to be 35mA per DDR SDRAM device at 100 MHz. 42. Random addressing changing and 50 percent of data changing at every transfer. 43. Random addressing changing and 100 percent of data changing at every transfer. 44. CKE must be active (high) during the entire time a refresh command is executed. That is, from the time the AUTO REFRESH command is registered, CKE must be active at each rising clock edge, until t RFC has been satisfied. 45. IDD2N specifies the DQ, DQS, and DM to be driven to a valid high or low logic level. IDD2Q is 09005aef80867a99 DD8C16 DD8C16_32_64x64AG_A.fm - Rev. A 8/03 EN similar to IDD2F except IDD2Q specifies the address and control inputs to remain stable. Although IDD2F, IDD2N, and IDD2Q are similar, IDD2F is "worst case." 46. Whenever the operating frequency is altered, not including jitter, the DLL is required to be reset, followed by 200 clock cycles before any READ command. 47. Leakage number reflects the worst case leakage possible through the module pin, not what each memory device contributes. 48. When an input signal is HIGH or LOW, it is defined as a steady state logic HIGH or LOW. 23 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology. Inc. 128MB 128MB, 256MB 256MB, 512MB 512MB (x64) 184-PIN 184-PIN DDR SDRAM DIMM SPD Clock and Data Conventions SPD Acknowledge Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions (as shown in Figure 10, Data Validity, and Figure 11, Definition of Start and Stop). Acknowledge is a software convention used to indicate successful data transfers. The transmitting device, either master or slave, will release the bus after transmitting eight bits. During the ninth clock cycle, the receiver will pull the SDA line LOW to acknowledge that it received the eight bits of data (as shown in Figure 12, Acknowledge Response From Receiver). The SPD device will always respond with an acknowledge after recognition of a start condition and its slave address. If both the device and a WRITE operation have been selected, the SPD device will respond with an acknowledge after the receipt of each subsequent eight-bit word. In the read mode the SPD device will transmit eight bits of data, release the SDA line and monitor the line for an acknowledge. If an acknowledge is detected and no stop condition is generated by the master, the slave will continue to transmit data. If an acknowledge is not detected, the slave will terminate further data transmissions and await the stop condition to return to standby power mode. SPD Start Condition All commands are preceded by the start condition, which is a HIGH-to-LOW transition of SDA when SCL is HIGH. The SPD device continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition has been met. SPD Stop Condition All communications are terminated by a stop condition, which is a LOW-to-HIGH transition of SDA when SCL is HIGH. The stop condition is also used to place the SPD device into standby power mode. Figure 10: Data Validity Figure 11: Definition of Start and Stop SCL SCL SDA SDA DATA STABLE DATA CHANGE DATA STABLE START BIT STOP BIT Figure 12: Acknowledge Response From Receiver SCL from Master 8 9 Data Output from Transmitter Data Output from Receiver Acknowledge 09005aef80867a99 DD8C16 DD8C16_32_64x64AG_A.fm - Rev. A 8/03 EN 24 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology. Inc. 128MB 128MB, 256MB 256MB, 512MB 512MB (x64) 184-PIN 184-PIN DDR SDRAM DIMM Table 18: EEPROM Device Select Code Most significant bit (b7) is sent first DEVICE TYPE IDENTIFIER SELECT CODE CHIP ENABLE RW b7 Memory Area Select Code (two arrays) Protection Register Select Code b6 b5 b4 b3 b2 b1 b0 1 0 0 1 1 1 0 0 SA2 SA2 SA1 SA1 SA0 SA0 RW RW Table 19: EEPROM Operating Modes MODE RW BIT Current Address Read Random Address Read Sequential Read Byte Write Page Write WC BYTES 1 0 1 1 0 0 VIH or VIL VIH or VIL VIH or VIL VIH or VIL VIL VIL 1 1 1 ³1 1 £ 16 INITIAL SEQUENCE START, Device Select, RW = "1" START, Device Select, RW = "0", Address reSTART, Device Select, RW = "1" Similar to Current or Random Address Read START, Device Select, RW = "0" START, Device Select, RW = "0" Figure 13: SPD EEPROM Timing Diagram tF t HIGH tR t LOW SCL t SU:STA t HD:STA t SU:DAT t HD:DAT t SU:STO SDA IN t DH t AA t BUF SDA OUT UNDEFINED 09005aef80867a99 DD8C16 DD8C16_32_64x64AG_A.fm - Rev. A 8/03 EN 25 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology. Inc. 128MB 128MB, 256MB 256MB, 512MB 512MB (x64) 184-PIN 184-PIN DDR SDRAM DIMM Table 20: Serial Presence-Detect EEPROM DC Operating Conditions All voltages referenced to VSS; VDDSPD = +2.3V to +3.6V PARAMETER/CONDITION SYMBOL VDDSPD Vih VIL VOL ILI ILO ISB ICC SUPPLY VOLTAGE INPUT HIGH VOLTAGE: Logic 1; All inputs INPUT LOW VOLTAGE: Logic 0; All inputs OUTPUT LOW VOLTAGE: IOUT = 3mA INPUT LEAKAGE CURRENT: VIN = GND to VDD OUTPUT LEAKAGE CURRENT: VOUT = GND to VDD STANDBY CURRENT: SCL = SDA = VDD - 0.3V; All other inputs = VDD or VSS POWER SUPPLY CURRENT: SCL clock frequency = 100 KHz MIN MAX UNITS 2.3 3.6 VDDSPD ´ 0.7 VDDSPD + 0.5 -1 VDDSPD ´ 0.3 ­ 0.4 ­ 10 ­ 10 ­ 30 ­ 2 V V V V µA µA µA mA Table 21: Serial Presence-Detect EEPROM AC Operating Conditions All voltages referenced to VSS; VDDSPD = +2.3V to +3.6V PARAMETER/CONDITION SYMBOL t AA BUF t DH t F t HD:DAT t HD:STA t HIGH t I t LOW t R f SCL t SU:DAT t SU:STA t SU:STO t WRC SCL LOW to SDA data-out valid Time the bus must be free before a new transition can start Data-out hold time SDA and SCL fall time Data-in hold time Start condition hold time Clock HIGH period Noise suppression time constant at SCL, SDA inputs Clock LOW period SDA and SCL rise time SCL clock frequency Data-in setup time Start condition setup time Stop condition setup time WRITE cycle time t MIN MAX UNITS NOTES 0.2 1.3 200 0.9 µs µs ns ns µs µs µs ns µs µs KHz ns µs µs ms 1 300 0 0.6 0.6 50 1.3 0.3 400 100 0.6 0.6 10 2 2 3 4 NOTE: 1. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL = 1 and the falling or rising edge of SDA. 2. This parameter is sampled. 3. For a reSTART condition, or following a WRITE cycle. 4. The SPD EEPROM WRITE cycle time (tWRC) is the time from a valid stop condition of a write sequence to the end of the EEPROM internal erase/program cycle. During the WRITE cycle, the EEPROM bus interface circuit is disabled, SDA remains HIGH due to pull-up resistor, and the EEPROM does not respond to its slave address. 09005aef80867a99 DD8C16 DD8C16_32_64x64AG_A.fm - Rev. A 8/03 EN 26 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology. Inc. 128MB 128MB, 256MB 256MB, 512MB 512MB (x64) 184-PIN 184-PIN DDR SDRAM DIMM Table 22: Serial Presence-Detect Matrix "1"/"0": Serial Data, "driven to HIGH"/"driven to LOW"; notes appear on page 29 BYTE DESCRIPTION ENTRY(VERSION) 0 1 2 3 Number of SPD Bytes Used by Micron Total Number of Bytes in SPD Device Fundamental Memory Type Number of Row Addresses on Assembly Number of Column Addresses on Assembly Number of Physical Ranks on DIMM Module Data Width Module Data Width (Continued) Module Voltage Interface Levels 128 256 SDRAM DDR 12 or 13 80 08 07 0C 80 08 07 0D 80 08 07 0D 10 or 11 0A 0A 0B 01 40 00 04 60 70 75 80 70 75 80 00 80 08 01 40 00 04 60 70 75 80 70 75 80 00 82 08 01 40 00 04 60 70 75 80 70 75 80 00 82 08 00 01 00 01 00 01 0E 04 0C 01 02 20 C0 0E 04 0C 01 02 20 C0 0E 04 0C 01 02 20 C0 75 A0 75 A0 75 A0 70 75 80 00 70 75 80 00 70 75 80 00 00 00 00 48 3C 50 30 3C 48 3C 50 30 3C 48 3C 50 30 3C 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 1 64 0 SSTL 2.5V 6ns (-335) SDRAM Cycle Time, tCK, (CAS Latency 7ns (-262/-26A -262/-26A) = 2.5) (See note 1) 7.5ns (-265) 8ns (-202) t 0.70ns (-335) SDRAM Access From Clock, AC, 0.75ns(-262/ -26A/-265 -26A/-265) (CAS Latency = 2.5) (See note 1) 0.8ns (-202) None Module Configuration Type 15.6 or 7.81µs/SELF Refrsh Rate/Type 8 SDRAM Device Width (Primary SDRAM) None Error-checking SDRAM Data Width 1 Minimum Clock Delay, Back-to-Back Random Column Access 2, 4, 8 Burst Lengths Supported 4 Number of Banks on SDRAM Device 2, 2.5 CAS Latencies Supported 0 CS Latency 1 WE Latency SDRAM Module Attributes Fast / Concurrent SDRAM Device Attributes: General AutoPrecharge t 7.5ns (-335/-262/-26A -335/-262/-26A) SDRAM Cycle Time, CK (CAS Latency 10ns (-265/-202) = 2) (See note 1) 7ns (-335) 7.5ns (-262/-26A/-265 -262/-26A/-265) 8ns (-202) t ­ SDRAM Cycle Time, CK, (CAS Latency = 1.5) ­ SDRAM Access From CK, tAC, (CAS SDRAM Access From CK, tAC (CAS Latency = 2) (See note 1) MT8VDDT1664A MT8VDDT1664A MT8VDDT3264A MT8VDDT3264A MT8VDDT6464A MT8VDDT6464A Latency = 1.5) 27 28 18ns (-335) 15ns (-262) 20ns (-26A/-265/-202 -26A/-265/-202) 12ns (-335) MInimum Row Active To Row Active, t 15ns (-262/-26A/-265/-202 -262/-26A/-265/-202) RRD Minimum Row Precharge Time, tRP 09005aef80867a99 DD8C16 DD8C16_32_64x64AG_A.fm - Rev. A 8/03 EN 27 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology. Inc. 128MB 128MB, 256MB 256MB, 512MB 512MB (x64) 184-PIN 184-PIN DDR SDRAM DIMM Table 22: Serial Presence-Detect Matrix "1"/"0": Serial Data, "driven to HIGH"/"driven to LOW"; notes appear on page 29 BYTE 29 30 31 32 33 34 35 36-40 41 42 43 44 45 46 47 48­61 62 63 64 65-71 72 73-90 91 92 DESCRIPTION ENTRY(VERSION) 18ns (-335) 20ns (-26A/-265/-202 -26A/-265/-202) 42ns (-335) Minimum RAS# Pulse Width, tRAS 45ns (-262/-26A/-265 -262/-26A/-265) (See note 2) 40ns (-202) 128MB 128MB or 256MB 256MB Module Rank Density 0.8ns (-335) Address And Command Setup Time, t 1.0ns (-262/-26A/-265 -262/-26A/-265) IS (See note 3) 1.1ns (-202) 0.8ns (-335) Address And Command Hold Time, t 1.0ns (-262/-26A/-265 -262/-26A/-265) IH (See note 3) 1.1ns (-202) 0.45ns (-335) Data/data Mask Input Setup Time, t 0.5ns (-262/-26A/-265 -262/-26A/-265) DS 0.6ns (-202) 0.45ns (-335) Data/Data Mask Input Hold Time, t 0.5ns (-262/-26A/-265 -262/-26A/-265) DH 0.6ns (-202) Reserved 60ns (-335/-262) Minimum Active/ Auto Refresh Time, t 65ns (-26A/-265 -26A/-265) RC 70ns (-202) 72ns (-335) Minimum Auto Refresh To Active/ Auto Refresh Command Period, tRFC 75ns (-262/-26A/-265 -262/-26A/-265) 80ns (-202) t 12ns (-335) Maximum Cycle Time, CK (MAX) 13ns (-262/-26A/-265/-202 -262/-26A/-265/-202) 0.45ns (-335) Maximum DQS-DQ Skew Time, t 0.5ns (-262/-26A/-265 -262/-26A/-265) DQSQ 0.6ns (-202) 0.55ns (-335) Maximum Read Data Hold Skew 0.75ns (-262/-26A/-265 -262/-26A/-265) Factor, tQHS 1ns (-202) Reserved Standard DIMM Height Reserved Release 1.0 SPD Revision -335 Checksum For Bytes 0-62 -262 -26A -265 -202 MICRON Manufacturer's JEDEC ID Code (continued) Manufacturer's JEDEC ID Code (continued) 1 - 12 Manufacturing Location Module Part Number (ASCII) 1-9 PCB Identification Code 0 Identification Code (continued) Minimum RAS# to CAS# Delay, tRCD 09005aef80867a99 DD8C16 DD8C16_32_64x64AG_A.fm - Rev. A 8/03 EN 28 MT8VDDT1664A MT8VDDT1664A MT8VDDT3264A MT8VDDT3264A MT8VDDT6464A MT8VDDT6464A 48 50 2A 2D 28 20 80 A0 B0 80 A0 B0 45 50 60 45 50 60 00 3C 41 46 48 4B 50 30 34 2D 32 3C 55 75 A0 00 01 00 10 04 97 C4 F4 8F 2C FF 48 50 2A 2D 28 40 80 A0 B0 80 A0 B0 45 50 60 45 50 60 00 3C 41 46 48 4B 50 30 34 2D 32 3C 55 75 A0 00 01 00 10 27 BA E7 17 B2 2C FF 48 50 2A 2D 28 40 80 A0 B0 80 A0 B0 45 50 60 45 50 60 00 3C 41 46 48 4B 50 30 34 2D 32 3C 55 75 A0 00 01 00 10 68 FB 28 58 F3 2C FF 01 - 0C Variable Data 01 - 09 00 01 - 0C Variable Data 01 - 09 00 01 - 0C Variable Data 01 - 09 00 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology. Inc. 128MB 128MB, 256MB 256MB, 512MB 512MB (x64) 184-PIN 184-PIN DDR SDRAM DIMM Table 22: Serial Presence-Detect Matrix "1"/"0": Serial Data, "driven to HIGH"/"driven to LOW"; notes appear on page 29 BYTE 93 94 95-98 99-127 DESCRIPTION ENTRY(VERSION) MT8VDDT1664A MT8VDDT1664A MT8VDDT3264A MT8VDDT3264A MT8VDDT6464A MT8VDDT6464A Variable Data Variable Data Variable Data ­ Year of Manufacture In BCD Week of Manufacture In BCD Module Serial Number Manufacturer-Specific Data (RSVD) Variable Data Variable Data Variable Data ­ Variable Data Variable Data Variable Data ­ NOTE: 1. Value for -26A tCK set to 7ns (0x70) for optimum BIOS compatibility. Actual device spec. value is 7.5ns. 2. The value of tRAS for -26A and -265 modules is calculated from tRC - tRP. Actual device spec. value is 40ns. 3. The JEDEC SPD specification allows fast or slow slew rate values for these bytes. The worst-case (slow slew rate) value is represented here. Systems requiring the fast slew rate setup and hold values are supported, provided the faster minimum slew rate is met. 09005aef80867a99 DD8C16 DD8C16_32_64x64AG_A.fm - Rev. A 8/03 EN 29 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology. Inc. 128MB 128MB, 256MB 256MB, 512MB 512MB (x64) 184-PIN 184-PIN DDR SDRAM DIMM Figure 14: 184-Pin DIMM Dimensions 0.125 (3.18) MAX FRONT VIEW 5.256 (133.50) 5.244 (133.20) 0.079 (2.00) R (4X) U10 U1 U2 U3 U4 U6 U7 U8 U9 1.255 (31.88) 1.245 (31.62) 0.700 (17.78) TYP. 0.098 (2.50) D (2X) 0.091 (2.30) TYP. 0.035 (0.90) R PIN 1 0.091 (2.30) TYP. PIN 92 0.250 (6.35) TYP. 0.050 (1.27) TYP. 0.054 (1.37) 0.046 (1.17) 0.040 (1.02) TYP. 4.750 (120.65) BACK VIEW No Components This Side of Module PIN 184 PIN 93 0.150 (3.80) 1.95 (49.53) 2.55 (64.77) 0.150 (3.80) 0.394 (10.00) TYP. TYP. NOTE: All dimensions are in inches (millimeters), with MAX MIN or typical where noted Data Sheet Designation Released: This data sheet contains minimum and maximum limits specified over the complete power supply and temperature range for production devices. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. ® 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992 Micron, the M logo, and the Micron logo are trademarks and/or service marks of Micron Technology, Inc. 09005aef80867a99 DD8C16 DD8C16_32_64x64AG_A.fm - Rev. A 8/03 EN 30 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc