128MB 184-PIN MT5VDDT872A MT5VDDT1672A MO-206 PC1600 PC2100 PC2700 16X72AG - Datasheet Archive

 

184-PIN DDR SDRAM DIMM DDR SDRAM DIMM MT5VDDT872A ­ 64MB MT5VDDT1672A ­ 128MB For the latest data sheet, please refer to

 

64MB, 128MB 128MB (x72, ECC) 184-PIN 184-PIN DDR SDRAM DIMM DDR SDRAM DIMM MT5VDDT872A MT5VDDT872A ­ 64MB MT5VDDT1672A MT5VDDT1672A ­ 128MB 128MB For the latest data sheet, please refer to the Micronâ Web site: www.micron.com/moduleds Features Figure 1: 184-Pin DIMM (MO-206 MO-206) · JEDEC-standard 184-pin, dual in-line memory module (DDR DIMM) · Utilizes 200 MT/s, 266 MT/s, and 333MT/s DDR SDRAM components · Fast data transfer rates PC1600 PC1600, PC2100 PC2100, or PC2700 PC2700 · 64MB (8 Meg x 72) and 128MB 128MB (16 Meg x 72) · ECC, 1-bit error detection and correction · VDD= VDDQ= +2.5V · VDDSPD = +2.3V to +3.6V · 2.5V I/O (SSTL_2 compatible) · Commands entered on each positive CK edge · DQS edge-aligned with data for READs; centeraligned with data for WRITEs · Internal, pipelined double data rate (DDR) architecture; two data accesses per clock cycle · Bidirectional data strobe (DQS) transmitted/ received with data-i.e., source-synchronous data capture · Differential clock inputs (CK and CK#) · Four internal device banks for concurrent operation · Selectable burst lengths: 2, 4, or 8 · Auto precharge option · Auto Refresh and Self Refresh Modes · 15.625µs (64MB); 7.8125µs (128MB 128MB) maximum average periodic refresh interval · Serial Presence Detect (SPD) with EEPROM · Selectable READ CAS latency for maximum compatibility 09005aef806e1c40 DD5C8_16X72AG 16X72AG_C.fm - Rev. C 8/03 EN OPTIONS MARKING · Package 184-pin DIMM (Gold) G 184-pin DIMM (Lead-Free) Y · Memory Clock, Speed, CAS Latency (CL) 6ns, 333 MT/s (167 MHz), CL = 2.5 -335 7.5ns, 266 MT/s (133 MHz), CL = 2 -262 7.5ns, 266 MT/s (133 MHz), CL = 2 -26A 7.5ns, 266 (133 MHz), CL = 2.5 -265 10ns, 200 MT/s (100 MHz), CL = 2 -202 · Self Refresh Standard None Low Power L Table 1: Address Table 64MB 128MB 128MB 4K Refresh Count 4K (A0 ­A11) Row Addressing 4 (BA0, BA1) Device Bank Addressing 8 Meg x 16 Device Configuration 512 (A0 ­A8) Column Addressing 1 (S0#) Module Rank Addressing 1 8K 8K (A0 ­A12) 4 (BA0, BA1) 16 Meg x 16 512 (A0 ­A8) 1 (S0#) ©2003 Micron Technology, Inc. PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. 64MB, 128MB 128MB (x72, ECC) 184-PIN 184-PIN DDR SDRAM DIMM Table 2: Part Numbers and Timing Parameters PART NUMBER MT5VDDT872 MT5VDDT872(L)AG-335 AG-335_ MT5VDDT872 MT5VDDT872(L)AY-335 AY-335_ MT5VDDT872 MT5VDDT872(L)AG-262 AG-262_ MT5VDDT872 MT5VDDT872(L)AY-262 AY-262_ MT5VDDT872 MT5VDDT872(L)AG-26A AG-26A_ MT5VDDT872 MT5VDDT872(L)AY-26A AY-26A_ MT5VDDT872 MT5VDDT872(L)AG-265 AG-265_ MT5VDDT872 MT5VDDT872(L)AY-265 AY-265_ MT5VDDT872 MT5VDDT872(L)AG-202 AG-202_ MT5VDDT872 MT5VDDT872(L)AY-202 AY-202_ MT5VDDT1672 MT5VDDT1672(L)AG-335 AG-335_ MT5VDDT1672 MT5VDDT1672(L)AY-335 AY-335_ MT5VDDT1672 MT5VDDT1672(L)AG-262 AG-262_ MT5VDDT1672 MT5VDDT1672(L)AY-262 AY-262_ MT5VDDT1672 MT5VDDT1672(L)AG-26A AG-26A_ MT5VDDT1672 MT5VDDT1672(L)AY-26A AY-26A_ MT5VDDT1672 MT5VDDT1672(L)AG-265 AG-265_ MT5VDDT1672 MT5VDDT1672(L)AY-265 AY-265_ MT5VDDT1672 MT5VDDT1672(L)AG-202 AG-202_ MT5VDDT1672 MT5VDDT1672(L)AY-202 AY-202_ MODULE DENSITY CONFIGURATION MODULE BANDWITH MEMORY CLOCK, DATA RATE CLOCK LATENCY (CL - tRCD - tRP) 64MB 64MB 64MB 64MB 64MB 64MB 64MB 64MB 64MB 64MB 128MB 128MB 128MB 128MB 128MB 128MB 128MB 128MB 128MB 128MB 128MB 128MB 128MB 128MB 128MB 128MB 128MB 128MB 128MB 128MB 8 Meg x 72 8 Meg x 72 8 Meg x 72 8 Meg x 72 8 Meg x 72 8 Meg x 72 8 Meg x 72 8 Meg x 72 8 Meg x 72 8 Meg x 72 16 Meg x 72 16 Meg x 72 16 Meg x 72 16 Meg x 72 16 Meg x 72 16 Meg x 72 16 Meg x 72 16 Meg x 72 16 Meg x 72 16 Meg x 72 2.7GB/s 2.7GB/s 2.1GB/s 2.1GB/s 2.1GB/s 2.1GB/s 2.1GB/s 2.1GB/s 1.6 GB/s 1.6 GB/s 2.7 GB/s 2.7 GB/s 2.1 GB/s 2.1 GB/s 2.1 GB/s 2.1 GB/s 2.1GB/s 2.1GB/s 1.6 GB/s 1.6 GB/s 6ns, 333 MT/s 6ns, 333 MT/s 7.5ns, 266 MT/s 7.5ns, 266 MT/s 7.5ns, 266 MT/s 7.5ns, 266 MT/s 7.5ns, 266 MT/s 7.5ns, 266 MT/s 10ns, 200 MT/s 10ns, 200 MT/s 6ns, 333 MT/s 6ns, 333 MT/s 7.5ns, 266 MT/s 7.5ns, 266 MT/s 7.5ns, 266 MT/s 7.5ns, 266 MT/s 7.5ns, 266 MT/s 7.5ns, 266 MT/s 10ns, 200 MT/s 10ns, 200 MT/s 2.5-3-3 2.5-3-3 2-2-2 2-2-2 2-3-3 2-3-3 2.5-3-3 2.5-3-3 2-2-2 2-2-2 2.5-3-3 2.5-3-3 2-2-2 2-2-2 2-3-3 2-3-3 2.5-3-3 2.5-3-3 2-2-2 2-2-2 NOTE: All part numbers end with a two-place code (not shown), designating component and PCB revisions. Consult factory for current revision codes. Example: MT5VDDT1672AG-265A1 MT5VDDT1672AG-265A1. 09005aef806e1c40 DD5C8_16X72AG 16X72AG_C.fm - Rev. C 8/03 EN 2 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology. Inc. 64MB, 128MB 128MB (x72, ECC) 184-PIN 184-PIN DDR SDRAM DIMM Table 3: Pin Assignment (184-Pin DIMM Front) Table 4: Pin Assignment (184-Pin DIMM Back) PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 93 VSS 116 VSS 94 DQ4 117 DQ21 95 DQ5 118 A11 96 VDDQ 119 DQS11/ DQS11/ DM2 VDD 97 DQS9/DM0 120 98 DQ6 121 DQ22 99 DQ7 122 A8 100 VSS 123 DQ23 101 NC 124 VSS 102 NC 125 A6 103 NC 126 DQ28 104 VDDQ 127 DQ29 105 DQ12 128 VDDQ 106 DQ13 129 DQS12/ DQS12/ DM3 A3 107 DQS10/DM1 DQS10/DM1 130 108 VDD 131 DQ30 109 DQ14 132 VSS 110 DQ15 133 DQ31 111 DNU 134 CB4 CB5 112 VDDQ 135 113 NC 136 VDDQ 114 DQ20 137 CK0 115 NC/A12 NC/A12 138 CK0# VREF DQ0 VSS DQ1 DQS0 DQ2 VDD DQ3 NC DNU VSS DQ8 DQ9 DQS1 VDDQ CK1 CK1# VSS DQ10 DQ11 CKE0 VDDQ DQ16 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 DQ17 DQS2 VSS A9 DQ18 A7 VDDQ DQ19 A5 DQ24 VSS DQ25 DQS3 A4 VDD DQ26 DQ27 A2 VSS A1 CB0 CB1 VDD 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 DQS8 A0 CB2 VSS CB3 BA1 DQ32 VDDQ DQ33 DQS4 DQ34 VSS BA0 DQ35 DQ40 VDDQ WE# DQ41 CAS# VSS DQS5 DQ42 DQ43 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 VDD NC DQ48 DQ49 VSS CK2# CK2 VDDQ DQS6 DQ50 DQ51 VSS NC DQ56 DQ57 VDD DQS7 DQ58 DQ59 VSS NC SDA SCL 139 VSS 162 DQ47 NC 140 DQS17/DM8 DQS17/DM8 163 141 A10 164 VDDQ 142 CB6 165 DQ52 143 VDDQ 166 DQ53 144 CB7 167 NC 168 VDD 145 VSS 146 DQ36 169 DQS15/DM6 DQS15/DM6 147 DQ37 170 DQ54 148 VDD 171 DQ55 149 DQS13/DM4 DQS13/DM4 172 VDDQ 150 DQ38 173 NC 151 DQ39 174 DQ60 152 VSS 175 DQ61 153 DQ44 176 VSS 154 RAS# 177 DQS16/DM7 DQS16/DM7 155 DQ45 178 DQ62 156 VDDQ 179 DQ63 157 S0# 180 VDDQ 158 NC 181 SA0 159 DQS14/DM5 DQS14/DM5 182 SA1 160 VSS 183 SA2 161 DQ46 184 VDDSPD NOTE: Pin 115 is no connect (NC) for 64MB modules or is address input A12 for 128MB 128MB modules. Figure 2: 184-Pin DIMM Pin Illustration Front View U1 U3 U2 U4 U5 U6 PIN 1 PIN 52 PIN 53 PIN 92 Back View No Components This Side of Module PIN 184 Indicates a VDD or VDDQ pin 09005aef806e1c40 DD5C8_16X72AG 16X72AG_C.fm - Rev. C 8/03 EN PIN 93 PIN 144 PIN 145 3 Indicates a VSS pin Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology. Inc. 64MB, 128MB 128MB (x72, ECC) 184-PIN 184-PIN DDR SDRAM DIMM Table 5: Pin Descriptions Refer to Pin Assignment tables on page 3 for pin number and symbol correlation PIN NUMBERS SYMBOL TYPE DESCRIPTION 1 63, 65, 154 VREF WE#, CAS#, RAS# Input Input 16, 17, 75, 76, 137, 138 CK0, CK0#, CK1, CK1#, CK2, CK2# Input 21 CKE0 Input 157 S0# Input 52, 59 BA0, BA1 Input 27, 29, 32, 37, 41, 43, 48, 115 (128MB 128MB), 118, 122, 125, 130, 141 A0-A11 A0-A11(64MB), A0-A12 A0-A12 (128MB 128MB) Input 91 SDA Input/ Output 92 SCL Input 181, 182, 183 SA0-SA2 Input SSTL_2 reference voltage. Command Inputs: RAS#, CAS#, and WE# (along with S0#) define the command being entered. Clock: CK and CK# are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK#. Output data (DQs and DQS) is refer- enced to the crossings of CK and CK#. Clock Enable: CKE HIGH activates and CKE LOW deactivates the internal clock, input buffers, and output drivers. Taking CKE LOW provides PRECHARGE POWER-DOWN and SELF REFRESH operations (all device banks idle), or ACTIVE POWER-DOWN (row ACTIVE in any device bank). CKE is synchronous for POWER-DOWN entry and exit, and for SELF REFRESH entry. CKE is asynchronous for SELF REFRESH exit and for disabling the outputs. CKE must be maintained HIGH throughout read and write accesses. Input buffers (excluding CK, CK# and CKE) are disabled during POWERDOWN. Input buffers (excluding CKE) are disabled during SELF REFRESH. CKE is an SSTL_2 input but will detect an LVCMOS LOW level after VDD is applied. Chip Select: S0# enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when S0# is registered HIGH. S0# is considered part of the command code. Bank Address: BA0 and BA1 define to which device bank an ACTIVE, READ, WRITE, or PRECHARGE command is being applied. Address Inputs: Provide the row address for ACTIVE commands, and the column address and auto precharge bit (A10) for READ/WRITE commands, to select one location out of the memory array in the respective device bank. A10 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one device bank (A10 LOW, device bank selected by BA0, BA1) or all device banks (A10 HIGH). The address inputs also provide the op-code during a MODE REGISTER SET command. BA0 and BA1 define which mode register (mode register or extended mode register) is loaded during the LOAD MODE REGISTER command. Serial Presence-Detect Data: SDA is a bidirectional pin used to transfer addresses and data into and out of the presencedetect portion of the module. Serial Clock for Presence-Detect: SCL is used to synchronize the presence-detect data transfer to and from the module. Presence-Detect Address Inputs: These pins are used to configure the presence-detect device. 09005aef806e1c40 DD5C8_16X72AG 16X72AG_C.fm - Rev. C 8/03 EN 4 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology. Inc. 64MB, 128MB 128MB (x72, ECC) 184-PIN 184-PIN DDR SDRAM DIMM Table 5: Pin Descriptions (Continued) Refer to Pin Assignment tables on page 3 for pin number and symbol correlation PIN NUMBERS SYMBOL TYPE 5, 14, 25, 36, 47, 56, 67, 78, 86, 97, 107, 119, 129, 140, 149, 159, 169, 177 DQS0-DQS17 DQS0-DQS17 Input/ Output 44, 45, 49, 51, 134, 135, 142, 144 2, 4, 6, 8, 12, 13, 19, 20, 23, 24, 28, 31, 33, 35, 39, 40, 53, 55, 57, 60, 61, 64, 68, 69, 72, 73, 79, 80, 83, 84, 87, 88, 94, 95, 98, 99, 105, 106, 109, 110, 114, 117, 121, 123, 126, 127, 131, 133, 146, 147, 150, 151, 153, 155, 161, 162, 165, 166, 170, 171, 174, 175, 178, 179 15, 22, 30, 54, 62, 77, 96, 104, 112, 128, 136, 143, 156, 164, 172, 180 7, 38, 46, 70, 85, 108, 120, 148, 168 3, 11, 18, 26, 34, 42, 50, 58, 66, 74, 81, 89, 93, 100, 116, 124, 132, 139, 145, 152, 160, 176 184 9, 71, 82, 90, 101, 102, 103, 113, 115 (64MB), 158, 163, 167, 173 10, 111 CB0-CB7 Input/ Output Input/ Output 09005aef806e1c40 DD5C8_16X72AG 16X72AG_C.fm - Rev. C 8/03 EN DQ0-DQ63 DQ0-DQ63 DESCRIPTION Data Strobe: DQS0-DQS8, Output with READ data, input with WRITE data. DQS is edge-aligned with READ data, centered in WRITE data. Used to capture data. Data Mask: DQS9-DQS17 DQS9-DQS17 function as DM0-DM8 to mask WRITE data when when HIGH. Check Bits: ECC 1-bit error detection and correction. Data I/Os: Data bus. VDDQ Supply DQ Power Supply: +2.5V +0.2V. Please see Note 51, on page 22 VDD Supply VSS Supply Power Supply: +2.5V +0.2V. Please see Note 51, on page 22. Ground. VDDSPD NC Supply ­ Serial EEPROM positive power supply: +2.3V to +3.6V. No Connect: These pins should be left unconnected. DNU ­ Do Not Use: These pins are not connected on this module but are assigned pins on other modules in this product family. 5 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology. Inc. 64MB, 128MB 128MB (x72, ECC) 184-PIN 184-PIN DDR SDRAM DIMM Figure 3: Functional Block Diagram S0# S0# DQS0 DM0/DQS9 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS1 DM1/DQS10 DM1/DQS10 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 UDQS UDM DQ DQ DQ DQ DQ DQ DQ DQ DQS5 DM5/DQS14 DM5/DQS14 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ DQ DQ DQ DQ DQ DQ DQ DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 LDQS LDM DQ DQ DQ DQ DQ DQ DQ DQ UDQS UDM DQ DQ DQ DQ DQ DQ DQ DQ DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 S0# DQS7 DM7/DQS16 DM7/DQS16 Resistor 7.5 BA0-BA1 SCL WP DDR SDRAMS A0-A11 A0-A11(64MB) DDR SDRAMS DDR SDRAMS A0-A12 A0-A12(128MB 128MB) RAS# CAS# WE# CKE0 VDD 100K U3 LDQS 100K LDM DQ NC DQ NC DQ NC DQ NC DQ NC DQ NC DQ NC DQ NC S0# U5 SERIAL PD U6 A0 A1 A2 SDA SPD/EEPROM VDDQ DDR SDRAMS VDD 120 VDDSPD DDR SDRAMS DDR SDRAMS DDR SDRAMS VREF DDR SDRAMS VSS DDR SDRAMS DDR SDRAM U3 DDR SDRAMs U1, U2 DDR SDRAMs U4, U5 Unless otherwise noted, resistor values are 22W unless otherwise specified. DQ wiring may differ from that described in this drawing; however DQ/DM/ DQS relationships are maintained as shown. Per industry standard, Micron modules utilize various component speed grades, as referenced in the module part numbering guide at www.micron.com/numberguide. 09005aef806e1c40 DD5C8_16X72AG 16X72AG_C.fm - Rev. C 8/03 EN VSS SA0 SA1 SA2 NOTE: 3. U4 DDR SDRAMS 3pF 1. 2. CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 S0# DDR SDRAMS CK0 CK0# CK1 CK1# CK2 CK2# UDQS UDM DQ DQ DQ DQ DQ DQ DQ DQ DQS8 DM8/DQS17 DM8/DQS17 LDQS LDM DQ DQ DQ DQ DQ DQ DQ DQ DQS6 DM6/DQS15 DM6/DQS15 U2 S0# LDQS LDM DQ DQ DQ DQ DQ DQ DQ DQ DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ DQ DQ DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQS3 DM3/DQS12 DM3/DQS12 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 U1 LDQS LDM DQ DQ DQ DQ DQ UDQS UDM DQS2 DM2/DQS11 DM2/DQS11 UDQS UDM DQ DQ DQ DQ DQ DQ DQ DQ DQS4 DM4/DQS13 DM4/DQS13 6 U1-U5 = MT46V8M16TG MT46V8M16TG DDR SDRAMs for 64MB module U1-U5 = MT46V16M16TG MT46V16M16TG DDR SDRAMs for 128MB 128MB module Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology. Inc. 64MB, 128MB 128MB (x72, ECC) 184-PIN 184-PIN DDR SDRAM DIMM General Description The MT5VDDT872A MT5VDDT872A and MT5VDDT1672A MT5VDDT1672A are highspeed CMOS, dynamic random-access, 64MB and 128MB 128MB memory modules organized in a x72 (ECC) configuration. These modules use internally configured quad-bank DDR SDRAM devices. These DDR SDRAM modules use a double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2nprefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the DDR SDRAM module effectively consists of a single 2n-bit wide, oneclock-cycle data transfer at the internal DRAM core and two corresponding n-bit wide, one-half-clockcycle data transfers at the I/O pins. A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in data capture at the receiver. DQS is an intermittent strobe transmitted by the DDR SDRAM during READs and by the memory controller during WRITEs. DQS is edge-aligned with data for READs and center-aligned with data for WRITEs. These DDR SDRAM modules operate from differential clocks (CK, CK#); the crossing of CK going HIGH and CK# going LOW will be referred to as the positive edge of CK. Commands (address and control signals) are registered at every positive edge of CK. Input data is registered on both edges of DQS, and output data is referenced to both edges of DQS, as well as to both edges of CK. Read and write accesses to the DDR SDRAM modules are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the device bank and row to be accessed (BA0, BA1 select devices bank, A0­A11 (64MB) or A0­A12 (128MB 128MB) select device row ). The address bits registered coincident with the READ or WRITE command are used to select the device bank and the starting device column location for the burst access. These DDR SDRAM modules provide for programmable read or write burst lengths of 2, 4, or 8 locations. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. The pipelined, multibank architecture of DDR SDRAM modules allows for concurrent operation, 09005aef806e1c40 DD5C8_16X72AG 16X72AG_C.fm - Rev. C 8/03 EN thereby providing high effective bandwidth by hiding row precharge and activation time. An auto refresh mode is provided, along with a power-saving power-down mode. All inputs are compatible with the JEDEC Standard for SSTL_2. All outputs are SSTL_2, Class II compatible. For more information regarding DDR SDRAM operation, refer to the 128Mb and 256Mb DDR SDRAM component data sheets. Serial Presence-Detect Operation These DDR SDRAM modules incorporate serial presence-detect (SPD). The SPD function is implemented using a 2,048-bit EEPROM. This nonvolatile storage device contains 256 bytes. The first 128 bytes can be programmed by Micron to identify the module type and various SDRAM organizations and timing parameters. The remaining 128 bytes of storage are available for use by the customer. System READ/ WRITE operations between the master (system logic) and the slave EEPROM device (DIMM) occur via a standard I2C bus using the DIMM's SCL (clock) and SDA (data) signals, together with SA (2:0), which provide eight unique DIMM/EEPROM addresses. Write protect (WP) is tied to ground on the module, permanently disabling hardware write protect. Mode Register Definition The mode register is used to define the specific mode of operation of the DDR SDRAM. This definition includes the selection of a burst length, a burst type, a CAS latency and an operating mode, as shown in Figure 4, Mode Register Definition Diagram, on page 8. The mode register is programmed via the MODE REGISTER SET command (with BA0 = 0 and BA1 = 0) and will retain the stored information until it is programmed again or the device loses power (except for bit A8, which is self-clearing). Reprogramming the mode register will not alter the contents of the memory, provided it is performed correctly. The mode register must be loaded (reloaded) when all device banks are idle and no bursts are in progress, and the controller must wait the specified time before initiating the subsequent operation. Violating either of these requirements will result in unspecified operation. Mode register bits A0­A2 specify the burst length, A3 specifies the type of burst (sequential or interleaved), A4­A6 specify the CAS latency, and A7­A11 (64MB), or A7­A12 (128MB 128MB) specify the operating mode. 7 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology. Inc. 64MB, 128MB 128MB (x72, ECC) 184-PIN 184-PIN DDR SDRAM DIMM Burst Length When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached. The block is uniquely selected by A1­A8 when the burst length is set to two, by A2­A8 when the burst length is set to four and by A3­A8 when the burst length is set to eight (where A8 is the most significant column address bit for a given configuration). The remaining (least significant) address bit(s) is (are) used to select the starting location within the block. The programmed burst length applies to both read and write bursts. Read and write accesses to the DDR SDRAM are burst oriented, with the burst length being programmable, as shown in Figure 4, Mode Register Definition Diagram. The burst length determines the maximum number of column locations that can be accessed for a given READ or WRITE command. Burst lengths of 2, 4, or 8 locations are available for both the sequential and the interleaved burst types. Reserved states should not be used, as unknown operation or incompatibility with future versions may result. Figure 4: Mode Register Definition Diagram BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 64MB Modules 13 12 0* 0* 11 10 9 8 7 6 5 4 3 2 1 0 Operating Mode CAS Latency BT Burst Length Table 6: Address Bus BURST LENGTH Mode Register (Mx) * M13 and M12 (BA1 and BA0) must be "0, 0" to select the base mode register (vs. the extended mode register). 2 BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 128MB 128MB Modules 14 13 12 11 10 9 8 Operating Mode 0* 0* 7 6 5 4 3 2 1 0 CAS Latency BT Burst Length * M14 and M13 (BA1 and BA0) must be "0, 0" to select the base mode register (vs. the extended mode register). Address Bus Burst Length M3 = 0 M3 = 1 0 0 0 Reserved Reserved 0 0 1 2 2 0 1 0 4 4 0 1 1 8 8 1 0 0 Reserved Reserved 1 0 1 Reserved Reserved 1 1 0 Reserved Reserved 1 1 1 Reserved Reserved 8 Burst Type M3 0 Sequential 1 Interleaved 0 0 0 A0 0 1 A1 A0 0 0 0 1 1 0 1 1 A2 A1 A0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 TYPE = SEQUENTIAL TYPE = INTERLEAVED 0-1 1-0 0-1 1-0 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0 0 1 Reserved 0 1 0 2 0 1 1 Reserved 1 0 0 Reserved 1 0 1 Reserved 1 1 0 2.5 1 1 1 NOTE: Reserved 0 Reserved M12 M11 M10 M9 M8 M7 STARTING COLUMN ADDRESS ORDER OF ACCESSES WITHIN A BURST CAS Latency M6 M5 M4 M6-M0 1. For a burst length of two, A1­A8 select the two-dataelement block; A0 selects the first access within the block. 2. For a burst length of four, A2­A8 select the four- dataelement block; A0­A1 select the first accesswithin the block. 3. For a burst length of eight, A3­A8 select the eightdata-element block; A0­A2 select the first access within the block. 4. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block. Operating Mode 0 0 0 0 0 0 Valid Normal Operation 0 0 0 0 1 0 Valid Normal Operation/Reset DLL - 09005aef806e1c40 DD5C8_16X72AG 16X72AG_C.fm - Rev. C 8/03 EN 4 Mode Register (Mx) M2 M1 M0 Burst Definition Table - - - - - - All other states reserved 8 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology. Inc. 64MB, 128MB 128MB (x72, ECC) 184-PIN 184-PIN DDR SDRAM DIMM Burst Type Table 7: Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit M3. The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in Table 6, Burst Definition Table, on page 8. ALLOWABLE OPERATING CLOCK FREQUENCY (MHZ) SPEED The READ latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first bit of output data. The latency can be set to 2 or 2.5 clocks, as shown in Figure 5, CAS Latency Diagram. If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available nominally coincident with clock edge n + m. Table 7, CAS Latency (CL) Table, indicates the operating frequencies at which each CAS latency setting can be used. Reserved states should not be used as unknown operation or incompatibility with future versions may result. T2 READ NOP T2n NOP T3 T3n CK NOP CL = 2 DQS The extended mode register controls functions beyond those controlled by the mode register; these additional functions are DLL enable/disable and output drive strength. These functions are controlled via the bits shown in Figure 6, Extended Mode Register Definition Diagram, on page 10. The extended mode register is programmed via the LOAD MODE REGISTER command to the mode register (with BA0 = 1 and BA1 = 0) and will retain the stored information until it is programmed again or the device loses power. The enabling of the DLL should always be followed by a LOAD MODE REGISTER command to the mode register (BA0/BA1 both low) to reset the DLL. The extended mode register must be loaded when all device banks are idle and no bursts are in progress, and the controller must wait the specified time before initiating any subsequent operation. Violating either of these requirements could result in unspecified operation. T0 T1 T2 READ NOP T2n T3 NOP T3n CK COMMAND 75 £ f £ 167 75 £ f £ 133 75 £ f £ 133 75 £ f £ 133 75 £ f £ 125 Extended Mode Register DQ CK# 75 £ f £ 133 75 £ f £ 133 75 £ f £ 133 75 £ f £ 100 75 £ f £ 100 The normal operating mode is selected by issuing a MODE REGISTER SET command with bits A7­A11 (64MB) or A7­A12 (128MB 128MB) each set to zero, and bits A0­A6 set to the desired values. A DLL reset is initiated by issuing a MODE REGISTER SET command with bits A7 and A9­A11 (64MB) or A9­A12 (128MB 128MB) each set to zero, bit A8 set to one, and bits A0­A6 set to the desired values. Although not required by the Micron device, JEDEC specifications recommend when a LOAD MODE REGISTER command is issued to reset the DLL, it should always be followed by a LOAD MODE REGISTER command to select normal operating mode. All other combinations of values for A7­A11 (64MB) or A7­A12 (128MB 128MB) are reserved for future use and/or test modes. Test modes and reserved states should not be used because unknown operation or incompatibility with future versions may result. CK# COMMAND CL = 2.5 Operating Mode Figure 5: CAS Latency Diagram T1 CL = 2 -335 -26A -262 -265 -202 Read Latency T0 CAS Latency (CL) Table NOP CL = 2.5 DQS DQ Burst Length = 4 in the cases shown Shown with nominal tAC, tDQSCK, and tDQSQ TRANSITIONING DATA 09005aef806e1c40 DD5C8_16X72AG 16X72AG_C.fm - Rev. C 8/03 EN DON'T CARE 9 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology. Inc. 64MB, 128MB 128MB (x72, ECC) 184-PIN 184-PIN DDR SDRAM DIMM Output Drive Strength Figure 6: Extended Mode Register Definition Diagram The normal full drive strength for all outputs is specified to be SSTL2, Class II. The x16 supports an option for reduced drive. This option is intended for the support of the lighter load and/or point-to-point environments. The selection of the reduced drive strength will alter the DQ and DQS from SSTL2, Class II drive strength to a reduced drive strengh, which is approximately 54 percent of the SSTL2, Class II drive strength. For detailed information on programmable and reduced drive strength option, refer to the 128Mb or 256Mb DDR SDRAM component data sheets. BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 64MB Module 13 12 11 10 9 8 7 6 5 4 Operating Mode 01 11 3 1 2 0 DS DLL BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 128MB 128MB Module 14 13 12 11 10 9 8 7 6 5 Operating Mode 01 11 4 3 2 1 0 DS DLL DLL Enable/Disable Address Bus Extended Mode Register (Ex) Address Bus Extended Mode Register (Ex) E0 Enable 1 E12 DLL 0 The DLL must be enabled for normal operation. DLL enable is required during power-up initialization and upon returning to normal operation after having disabled the DLL for the purpose of debug or evaluation. (When the device exits self refresh mode, the DLL is enabled automatically.) Any time the DLL is enabled, 200 clock cycles must occur before a READ command can be issued. Disable Drive Strength 0 E11 E10 E9 E8 E7 E6 E5 E4 E3 E23 E1, E0 0 0 0 0 0 0 0 0 0 0 Valid ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ Normal 1 Reduced Operating Mode Normal Operation All other states reserved NOTE: 1. E13 and E12 (64MB) or E14 andE13 (128MB 128MB) must be "0, 1"to select the Extended Mode Register (vs. the base Mode Register). 2. The reduced drive strength option is only available on the D3 version of the x16 device. 3. QFC# is not supported. 09005aef806e1c40 DD5C8_16X72AG 16X72AG_C.fm - Rev. C 8/03 EN 10 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology. Inc. 64MB, 128MB 128MB (x72, ECC) 184-PIN 184-PIN DDR SDRAM DIMM Commands Truth Table 1 provides a general reference of available commands. For a more detailed description of Table 8: commands and operations, refer to the Micron 128Mb or 256Mb DDR SDRAM component data sheet. Commands Truth Table CKE is HIGH for all commands shown except SELF REFRESH NAME (FUNCTION) CS# DESELECT (NOP) NO OPERATION (NOP) ACTIVE (Select device bank and activate row) READ (Select device bank and column, and start READ burst) WRITE (Select device bank and column, and start WRITE burst) BURST TERMINATE PRECHARGE (Deactivate row in device bank or banks) AUTO REFRESH or SELF REFRESH (Enter self refresh mode) LOAD MODE REGISTER H L L L L L L L L RAS# CAS# X H L H H H L L L X H H L L H H L L WE# ADDR NOTES X H H H L L L H L X X Bank/Row Bank/Col Bank/Col X Code X Op-Code 1 1 2 3 3 4 5 6, 7 8 NOTE: 1. DESELECT and NOP are functionally interchangeable. 2. BA0­BA1 provide device bank address and A0­A11 (64MB) or A0­A12 (128MB 128MB) provide row address. 3. BA0­BA1 provide device bank address; A0­A8 provide column address; A10 HIGH enables the auto precharge feature (nonpersistent), and A10 LOW disables the auto precharge feature. 4. Applies only to read bursts with auto precharge disabled; this command is undefined (and should not be used) for READ bursts with auto precharge enabled and for WRITE bursts. 5. A10 LOW: BA0­BA1 determine which device bank is precharged. A10 HIGH: all device banks are precharged and BA0­ BA1 are "Don't Care." 6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW. 7. Internal refresh counter controls row addressing; all inputs and I/Os are "Don't Care" except for CKE. 8. BA0­BA1 select either the mode register or the extended mode register (BA0 = 0, BA1 = 0 select the mode register; BA0 = 1, BA1 = 0 select extended mode register; other combinations of BA0-BA1 are reserved). A0­A11 (64MB) or A0­A12 (128MB 128MB) provide the op-code to be written to the selected mode register. Table 9: DM Operation Truth Table Used to mask write data; provided coincident with the corresponding data. NAME (FUNCTION) DM L H Write Enable Write Inhibit 09005aef806e1c40 DD5C8_16X72AG 16X72AG_C.fm - Rev. C 8/03 EN 11 DQ Valid X Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology. Inc. 64MB, 128MB 128MB (x72, ECC) 184-PIN 184-PIN DDR SDRAM DIMM Absolute Maximum Ratings Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the opera- tional sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. VDD Supply Voltage Relative to VSS . . . . -1V to +3.6V VDDQ Supply Voltage Relative to VSS . . . -1V to +3.6V VREF and Inputs Voltage Relative to VSS . . . . . . . . . . . . . . . . . . . . -1V to +3.6V I/O Pins Voltage Relative to VSS . . . . . . . . . . . . . -0.5V to VDDQ +0.5V Operating Temperature, TA (ambient) . . . . . . . . . . . . . . . . . . . . . .0°C to +70°C Storage Temperature (plastic) . . . . . . -55°C to +150°C Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . 5W Short Circuit Output Current. . . . . . . . . . . . . . . . 50mA Table 10: DC Electrical Characteristics and Operating Conditions Notes: 1­5, 14, 51; notes appear on pages 19­22; 0°C £ TA £ +70°C PARAMETER/CONDITION Supply Voltage I/O Supply Voltage I/O Reference Voltage I/O Termination Voltage (system) Input High (Logic 1) Voltage Input Low (Logic 0) Voltage INPUT LEAKAGE CURRENT Any input, 0V £ VIN £ VDD, VREF pin 0V £ VIN £ 1.35V (All other pins not under test = 0V) SYMBOL Command/Address, S#, CKE0# CK0, CK0# CK1, CK1#, CK2, CK2#, DM DQ OUTPUT LEAKAGE CURRENT (DQs are disabled; 0V £ VOUT £ VDDQ) OUTPUT LEVELS: Full drive option High Current (VOUT = VDDQ - 0.373V, minimum VREF, minimum VTT) Low Current (VOUT = 0.373V, maximum VREF,maximum VTT) OUTPUT LEVELS: Reduced drive option High Current (VOUT = VDDQ -0.763V, minimum VREF, minimum VTT) Low Current (VOUT = 0.763V, maximum VREF,maximum VTT) MIN MAX UNITS NOTES VDD VDDQ VREF VTT VIH(DC) VIL(DC) 2.3 2.3 0.49 x VDDQ VREF - 0.04 VREF + 0.15 -0.3 -10 2.7 2.7 0.51 x VDDQ VREF + 0.04 VDD + 0.3 VREF - 0.15 10 V V V V V V 32, 38 32, 38, 41 6, 41 7, 41 25 25 II 2 4 5 µA 50 IOZ -2 -4 -5 µA 50 IOH IOL -16.8 16.8 ­ ­ mA mA 33, 36 IOHR IOLR -9 9 ­ ­ mA mA 34, 36 34 Table 11: AC Input Operating Conditions Notes: 1­5, 14, 51; notes appear on pages 19­22; 0°C £ TA £ +70°C; VDD = VDDQ = +2.5V ±0.2V PARAMETER/CONDITION SYMBOL MIN MAX UNITS NOTES Input High (Logic 1) Voltage Input Low (Logic 0) Voltage I/O Reference Voltage VIH(AC) VIL(AC) VREF(AC) VREF + 0.310 ­ 0.49 x VDDQ ­ VREF - 0.310 0.51 x VDDQ V V V 12, 25, 37 12, 25, 37 6 09005aef806e1c40 DD5C8_16X72AG 16X72AG_C.fm - Rev. C 8/03 EN 12 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology. Inc. 64MB, 128MB 128MB (x72, ECC) 184-PIN 184-PIN DDR SDRAM DIMM Table 12: IDD Specifications and Conditions (64MB) DDR SDRAM components only Notes: 1­5, 8, 10, 12, 51; notes appear pages 19­22; 0°C £ TA £ +70°C; VDD = VDDQ = +2.5V ±0.2V MAX SYM PARAMETER/CONDITION t OPERATING CURRENT: One device bank; Active-Precharge; RC = t RC (MIN); tCK = tCK (MIN); DQ, DM, and DQS inputs changing once per clock cycle; Address and control inputs changing once every two clock cycles. OPERATING CURRENT: One device bank; Active-Read-Precharge; Burst = 2; tRC = tRC (MIN); tCK = tCK (MIN); IOUT = 0mA; Address and control inputs changing once per clock cycle. PRECHARGE POWER-DOWN STANDBY CURRENT: All device banks idle; Power-down mode; tCK = tCK (MIN); CKE = LOW. IDLE STANDBY CURRENT: CS# = HIGH; All device banks idle; tCK = CK (MIN); CKE = HIGH; Address and other control inputs changing once per clock cycle. VIN = VREF for DQ, DQS, and DM. ACTIVE POWER-DOWN STANDBY CURRENT: One device bank active; Power-down mode; tCK = tCK (MIN); CKE = LOW. ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One device bank; Active-Precharge; RC = tRAS (MAX); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle. OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); IOUT = 0mA. OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle. t AUTO REFRESH CURRENT RC = tRFC (MIN) -335 -262 -26A/ -26A/ -265 -202 UNITS NOTES IDD0 TBD TBD 550 525 mA 20, 45 IDD1 TBD TBD 650 600 mA 20, 45 IDD2P TBD TBD 15 15 mA 21, 28, 47 IDD2F TBD TBD 225 175 mA 48 IDD3P TBD TBD 100 100 mA 21, 28, 47 IDD3N TBD TBD 225 200 mA 44 IDD4R TBD TBD 725 675 mA 20, 45 IDD4W TBD TBD 625 575 mA 20 t t RC = 15.625µs Standard Low Power (L) OPERATING CURRENT: Four device bank interleaving READs (BL = 4) with auto precharge, tRC = tRC (MIN); tCK = tCK (MIN); Address and control inputs change only during Active, READ, or WRITE commands. SELF REFRESH CURRENT: CKE £ 0.2V 09005aef806e1c40 DD5C8_16X72AG 16X72AG_C.fm - Rev. C 8/03 EN 13 IDD5 TBD TBD 1,050 950 mA 20, 47 IDD6 TBD TBD 25 25 mA 24, 47 IDD7 IDD7 IDD8 TBD TBD TBD TBD TBD TBD 10 5 1,675 10 5 1,550 mA mA mA 9 9 20, 46 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology. Inc. 64MB, 128MB 128MB (x72, ECC) 184-PIN 184-PIN DDR SDRAM DIMM Table 13: IDD Specifications and Conditions (128MB 128MB) DDR SDRAM components only Notes: 1­5, 8, 10, 12, 51; notes appear pages 19­22; 0°C £ TA £ +70°C; VDD = VDDQ = +2.5V ±0.2V MAX SYM PARAMETER/CONDITION t t OPERATING CURRENT: One device bank; Active-Precharge; RC = RC (MIN); tCK = tCK (MIN); DQ, DM, and DQS inputs changing once per clock cycle; Address and control inputs changing once every two clock cycles. OPERATING CURRENT: One device bank; Active-Read-Precharge; Burst = 2; tRC = tRC (MIN); tCK = tCK (MIN); IOUT = 0mA; Address and control inputs changing once per clock cycle. PRECHARGE POWER-DOWN STANDBY CURRENT: All device banks idle; Power-down mode; tCK = tCK (MIN); CKE = LOW. IDLE STANDBY CURRENT: CS# = HIGH; All device banks idle; t CK = tCK (MIN); CKE = HIGH; Address and other control inputs changing once per clock cycle. VIN = VREF for DQ, DQS, and DM. ACTIVE POWER-DOWN STANDBY CURRENT: One device bank active; Power-down mode; tCK = tCK (MIN); CKE = LOW. ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One device bank; Active-Precharge; RC = tRAS (MAX); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle. OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); IOUT = 0mA. OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; t CK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle. t AUTO REFRESH CURRENT RC = tRFC (MIN) t RC = 7.8125µs SELF REFRESH CURRENT: CKE £ 0.2V Standard Low Power (L) OPERATING CURRENT: Four device bank interleaving READs (BL = 4) with auto precharge, tRC = tRC (MIN); tCK = tCK (MIN); Address and control inputs change only during Active, READ, or WRITE commands. -335 -262 -26A/ -26A/ -265 IDD0 625 625 600 575 mA 20, 45 IDD1 900 850 825 775 mA 20, 45 IDD2P 20 20 20 20 mA 21, 28, 47 IDD2F 250 225 200 200 mA 48 IDD3P 150 125 150 125 mA 21, 28, 47 IDD3N 300 250 225 200 mA 44 IDD4R 1,100 925 1,250 1,075 mA 20, 45 IDD4W 725 1,250 950 mA 20 1,225 1,075 mA 20, 47 30 30 mA 24, 47 20 10 2,000 20 10 1,875 mA mA mA 9 9 20, 46 IDD5 IDD6 IDD7 IDD7 IDD8 825 1,275 1,175 30 30 20 20 10 10 2,200 1,900 -202 UNITS NOTES Table 14: Capacitance Note: 11; notes appear on page 19­22 PARAMETER SYMBOL 09005aef806e1c40 DD5C8_16X72AG 16X72AG_C.fm - Rev. C 8/03 EN 14 MAX UNITS CIO CI1 CI2 CI3 Input/Output Capacitance: DQ, DQS/DM Input Capacitance: Command and Address, S#, CKE Input Capacitance: CK0, CK0# Input Capacitance: CK1, CK1#, CK2, CK2# MIN 4.0 10.0 2.0 4.0 5.0 15.0 3.0 6.0 pF pF pF pF Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology. Inc. 64MB, 128MB 128MB (x72, ECC) 184-PIN 184-PIN DDR SDRAM DIMM Table 15: Electrical Characteristics and Recommended AC Operating Conditions (-335 and -262 Speeds) DDR SDRAM components only Notes: 1­5, 12­15, 29, 51; notes appear pages 19­22; 0°C £ TA £ +70°C; VDD = VDDQ = +2.5V ±0.2V AC CHARACTERISTICS -335 PARAMETER SYMBOL -262 MIN MAX MIN MAX UNITS NOTES ns Access window of DQs from CK/CK# t -0.70 +0.70 -0.75 +0.75 CK high-level width t CH 0.45 0.55 0.45 0.55 t 26 t CL 0.45 0.55 0.45 0.55 t 6 CK (2.5) 6.0 13 7.5 7.5 13 7.5/10 AC CK low-level width Clock cycle time CL = 2.5 t CK 13 CK ns 41, 49 13 ns 41, 49 DH 0.45 0.5 ns 23, 27 t DS 0.45 0.5 ns 23, 27 t DIPW 1.75 1.75 ns 27 DQSCK -0.60 DQS input high pulse width t DQSH 0.35 0.35 t DQS input low pulse width t 0.35 0.35 t DQS-DQ skew, DQS to last DQ valid, per group, per access t Write command to first DQS latching transition t CL = 2 t CK (2) DQ and DM input hold time relative to DQS t DQ and DM input setup time relative to DQS DQ and DM input pulse width (for each input) Access window of DQS from CK/CK# t DQSL +0.60 +0.75 0.75 0.5 1.25 ns CK 0.45 DQSQ DQSS -0.75 0.75 1.25 CK ns 22, 23 t CK DQS falling edge to CK rising - setup time t DSS 0.2 0.2 t DQS falling edge from CK rising - hold time t DSH 0.2 0.2 t t Half clock period HP t t CH, CL t CK CK ns CH, CL 30 ns 16, 39 t +0.70 +0.75 Data-out high-impedance window from CK/CK# t Data-out low-impedance window from CK/CK# t LZ -0.70 -0.75 ns 16, 41 Address and control input hold time (slow slew rate) t IHS .75 1 ns 12 Address and control input setup time (slow slew rate) t ISS .75 1 ns 12 Address and control input hold time (fast slew rate) t IHF 0.8 0.9 ns 12 Address and control input setup time (fast slew rate) t ISF 0.8 0.9 ns 12 MRD 12 HZ t LOAD MODE REGISTER command cycle time t DQ-DQS hold, DQS to first DQ to go non-valid, per access QH t 15 t t HP - QHS 0.60 ns t HP - QHS 0.75 ns 22, 23 ns Data Hold Skew Factor t ACTIVEto PRECHARGE command t RAS 42 64MB t RAP 18 128MB 128MB t RAP 18 t RC 65 60 ns ACTIVEto READ with auto precharge command QHS ACTIVEto ACTIVE/AUTO REFRESH command period 70,000 40 120,000 ns 31 RAS(MIN) - (burst length * tCK/2) 15 ns 43 ns 43 t AUTO REFRESH command period t RFC 72 75 ns ACTIVE to READ or WRITE delay t RCD 18 15 ns t RP 18 15 RPRE 0.9 PRECHARGE command period DQS read preamble 09005aef806e1c40 DD5C8_16X72AG 16X72AG_C.fm - Rev. C 8/03 EN t 15 1.1 0.9 47 ns 1.1 t CK 39 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology. Inc. 64MB, 128MB 128MB (x72, ECC) 184-PIN 184-PIN DDR SDRAM DIMM Table 15: Electrical Characteristics and Recommended AC Operating Conditions (-335 and -262 Speeds) (Continued) DDR SDRAM components only Notes: 1­5, 12­15, 29, 51; notes appear pages 19­22; 0°C £ TA £ +70°C; VDD = VDDQ = +2.5V ±0.2V AC CHARACTERISTICS -335 PARAMETER SYMBOL -262 MIN MAX MIN MAX 0.6 0.4 0.6 DQS read postamble t RPST 0.4 ACTIVE bank a to ACTIVE bank b command t RRD 12 15 WPRE 0.25 0.25 WPRES 0 0 DQS write preamble t t DQS write preamble setup time WPST 0.4 t WR 15 DQS write postamble WTR na 1 t Internal WRITE to READ command delay Data valid output window (DVW) t 0.6 t t CK ns CK ns 1 Write recovery time NOTES t 15 t UNITS 0.4 0.6 t CK ns 18, 19 17 t QH - DQSQ 140.6 CK ns 22 µs 21 t t t REFC t REFC 70.3 70.3 µs 21 64MB t 15.6 15.6 µs 21 128MB 128MB Average periodic refresh interval 64MB 128MB 128MB REFRESH to REFRESH command interval QH - DQSQ 140.6 t µs 21 REFI 7.8 REFI 7.8 VTD 0 Exit SELF REFRESH to non-READ command t XSNR 75 75 Exit SELF REFRESH to READ command t 200 200 Terminating voltage delay to VDD 09005aef806e1c40 DD5C8_16X72AG 16X72AG_C.fm - Rev. C 8/03 EN t XSRD 16 0 ns ns t CK Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology. Inc. 64MB, 128MB 128MB (x72, ECC) 184-PIN 184-PIN DDR SDRAM DIMM Table 16: Electrical Characteristics and Recommended AC Operating Conditions (-26A, -265, and -202 Speeds) DDR SDRAM components only Notes: 1­5, 12­15, 29, 51; notes appear pages 19­22; 0°C £ TA £ +70°C; VDD = VDDQ = +2.5V ±0.2V AC CHARACTERISTICS -26A/-265 -26A/-265 PARAMETER MIN MAX MIN MAX Access window of DQs from CK/CK# t -0.75 +0.75 -0.8 +0.8 CK high-level width t CH 0.45 0.55 0.45 CK low-level width t CL 0.45 0.55 0.45 CK (2.5) 7.5 13 8 7.5/10 13 10 Clock cycle time SYMBOL -202 AC CL = 2.5 CL = 2 t t CK (2) UNITS NOTES ns 0.55 t 26 0.55 t 6 CK 13 CK ns 41, 49 13 ns 41, 49 DQ and DM input hold time relative to DQS t DH 0.5 0.6 ns 23, 27 DQ and DM input setup time relative to DQS t 0.5 0.6 ns 23, 27 ns 27 DS t DIPW DQ and DM input pulse width (for each input) 1.75 2 DQSCK -0.75 DQS input high pulse width t DQSH 0.35 0.35 t DQS input low pulse width t 0.35 0.35 t DQS-DQ skew, DQS to last DQ valid, per group, per access t Write command to first DQS latching transition t t Access window of DQS from CK/CK# DQSL -0.8 +0.8 0.75 1.25 ns CK 0.5 DQSQ DQSS +0.75 0.6 0.75 1.25 CK ns 22, 23 t CK DSS 0.2 0.2 t DSH 0.2 0.2 t DQS falling edge to CK rising - setup time t DQS falling edge from CK rising - hold time t Half clock period t HP t CK CK ns t CH, CL CH, CL t 30 t ns 16, 39 LZ -0.75 -0.8 ns 16, 41 IHS 1 1.1 ns 12 Address and control input setup time (slow slew rate) t ISS 1 1.1 ns 12 Address and control input hold time (fast slew rate) t IHF 0.9 1.1 ns 12 Address and control input setup time (fast slew rate) t ISF 0.9 1.1 ns 12 MRD 15 16 ns t t ns Data-out high-impedance window from CK/CK# Data-out low-impedance window from CK/CK# t Address and control input hold time (slow slew rate) t +0.75 t HZ LOAD MODE REGISTER command cycle time t t DQ-DQS hold, DQS to first DQ to go non-valid, per access QH t Data Hold Skew Factor QHS HP -tQHS 0.75 40 HP -tQHS 1 ns 43 RAP RAS(MIN) - (burst length * CK/2) 20 20 ns 43 t RC 65 70 ns RFC 75 80 ns RCD 20 20 ns t RP 20 20 ns RPRE 0.9 1.1 0.9 1.1 t 0.4 0.6 0.4 0.6 t ACTIVEto READ with auto precharge command 64MB 128MB 128MB t RAS RAP ACTIVEto ACTIVE/AUTO REFRESH command period AUTO REFRESH command period t ACTIVE to READ or WRITE delay t PRECHARGE command period DQS read preamble t DQS read postamble t 09005aef806e1c40 DD5C8_16X72AG 16X72AG_C.fm - Rev. C 8/03 EN 17 RPST t 120,000 ns 31 t t 40 22, 23 ns ACTIVEto PRECHARGE command 120,000 +0.8 t CK 47 39 CK Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology. Inc. 64MB, 128MB 128MB (x72, ECC) 184-PIN 184-PIN DDR SDRAM DIMM Table 16: Electrical Characteristics and Recommended AC Operating Conditions (-26A, -265, and -202 Speeds) (Continued) DDR SDRAM components only Notes: 1­5, 12­15, 29, 51; notes appear pages 19­22; 0°C £ TA £ +70°C; VDD = VDDQ = +2.5V ±0.2V AC CHARACTERISTICS -26A/-265 -26A/-265 PARAMETER SYMBOL MIN MAX -202 MIN RRD 15 15 WPRE 0.25 0.25 WPRES 0 0 t ACTIVE bank a to ACTIVE bank b command t DQS write preamble DQS write preamble setup time t WPST 0.4 t WR 15 WTR na Internal WRITE to READ command delay t Data valid output window (DVW) t t CK ns QH - DQSQ 140.6 0.4 t NOTES t 1 Write recovery time 0.6 UNITS ns 15 1 t DQS write postamble MAX 0.6 t CK ns 18, 19 17 t t QH - DQSQ 140.6 CK ns 22 µs 21 Terminating voltage delay to VDD t t REFC 70.3 70.3 µs 21 64MB t 15.6 15.6 µs 21 128MB 128MB Average periodic refresh interval 64MB 128MB 128MB REFRESH to REFRESH command interval t 7.8 7.8 µs 21 REFC REFI REFI Exit SELF REFRESH to non-READ command t Exit SELF REFRESH to READ command t 09005aef806e1c40 DD5C8_16X72AG 16X72AG_C.fm - Rev. C 8/03 EN 0 0 ns XSNR 75 80 ns XSRD 200 200 tVTD 18 t CK Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology. Inc. 64MB, 128MB 128MB (x72, ECC) 184-PIN 184-PIN DDR SDRAM DIMM Notes 1. All voltages referenced to VSS. 2. Tests for AC timing, IDD, and electrical AC and DC characteristics may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. 3. Outputs measured with equivalent load: 12. VTT Output (VOUT) 50 Reference Point 30pF 13. 4. AC timing and IDD tests may use a VIL-to-VIH swing of up to 1.5V in the test environment, but input timing is still referenced to VREF (or to the crossing point for CK/CK#), and parameter specifications are guaranteed for the specified AC input levels under normal use conditions. The minimum slew rate for the input signals used to test the device is 1V/ns in the range between VIL(AC) and VIH(AC). 5. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e., the receiver will effectively switch as a result of the signal crossing the AC input level, and will remain in that state as long as the signal does not ring back above [below] the DC input LOW [HIGH] level). 6. VREF is expected to equal VDDQ/2 of the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise (non-common mode) on Vref may not exceed ±2 percent of the DC value. Thus, from VDDQ/2, VREF is allowed ±25mV for DC error and an additional ±25mV for AC noise. This measurement is to be taken at the nearest VREF bypass capacitor. 7. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF and must track variations in the DC level of VREF. 8. IDD is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle time at CL = 2 for -26A and -202, CL = 2.5 for -335 and -265 with the outputs open. 9. Enables on-chip refresh and address counters. 10. IDD specifications are tested after the device is properly initialized, and is averaged at the defined cycle rate. 11. This parameter is sampled. VDD = +2.5V ±0.2V, VDDQ = +2.5V ±0.2V, VREF = VSS, f = 100 MHz, TA = 09005aef806e1c40 DD5C8_16X72AG 16X72AG_C.fm - Rev. C 8/03 EN 14. 15. 16. 17. 18. 19. 20. 21. 19 25°C, VOUT(DC) = VDDQ/2, VOUT (peak to peak) = 0.2V. DM input is grouped with I/O pins, reflecting the fact that they are matched in loading. Command/Address input slew rate = 0.5V/ns. For -335 and -265 with slew rates 1V/ns and faster, tIS and tIH are reduced to 900ps. If the slew rate is less than 0.5V/ns, timing must be derated: tIS has an additional 50ps per each 100mV/ns reduction in slew rate from the 500mV/ns and tIH remains constant. If the slew rate exceeds 4.5V/ns, functionality is uncertain. The CK/CK# input reference level (for timing referenced to CK/CK#) is the point at which CK and CK# cross; the input reference level for signals other than CK/CK# is VREF. Inputs are not recognized as valid until VREF stabilizes. Exception: during the period before VREF stabilizes, CKE £ 0.3 x VDDQ is recognized as LOW. The output timing reference level, as measured at the timing reference point indicated in Note 3, is VTT. t HZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referenced to a specific voltage level, but specify when the device output is no longer driving (HZ) or begins driving (LZ). If DQS transitions to HIGH above VIHDC MIN), then it must not transition to LOW below VIHDC (MIN) prior to tDQSH (MIN). This is not a device limit. The device will operate with a negative value, but system performance could be degraded due to bus turnaround. It is recommended that DQS be valid (HIGH or LOW) on or before the WRITE command. The case shown (DQS going from High-Z to logic LOW) applies when no WRITEs were previously in progress on the bus. If a previous WRITE was in progress, DQS could be HIGH during this time, depending on tDQSS. MIN (tRC or tRFC) for IDD measurements is the smallest multiple of tCK that meets the minimum absolute value for the respective parameter. tRAS (MAX) for IDD measurements is the largest multiple of tCK that meets the maximum absolute value for tRAS. The refresh period 64ms. This equates to an average refresh rate of 15.625µs (64MB modules), or 7.821µs (128MB 128MB modules). However, an AUTO REFRESH command must be asserted at least Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology. Inc. 64MB, 128MB 128MB (x72, ECC) 184-PIN 184-PIN DDR SDRAM DIMM 22. 23. 24. 25. once every 140.6µs (64MB modules) or 70.3µs (128MB 128MB modules); burst refreshing or posting by the DRAM controller greater than eight refresh cycles is not allowed. The valid data window is derived by achieving other specifications - tHP (tCK/2), tDQSQ, and t QH (tQH = tHP - tQHS). The data valid window derates directly porportional with the clock duty cycle and a practical data valid window can be derived. The clock is allowed a maximum duty cycle variation of 45/55. Functionality is uncertain when operating beyond a 45/55 ratio. Figure 7, Derating Data Valid Window, shows derating curves for duty cycles ranging between 50/50 and 45/55. Referenced to each output group: LDQS with DQ0­DQ7; and UDQS with DQ8­DQ15. This limit is actually a nominal value and does not result in a fail value. CKE is HIGH during REFRESH command period (tRFC [MIN]) else CKE is LOW (i.e., during standby). To maintain a valid level, the transitioning edge of the input must: a) Sustain a constant slew rate from the current AC level through to the target AC level, VIL(AC) or VIH(AC). 26. 27. 28. 29. 30. 31. b) Reach at least the target AC level c) After the AC target level is reached, continue to maintain at least the target DC level, VIL(DC) or VIH(DC). JEDEC specifies CK and CK# input slew rate must be £ 1V/ns (2V/ns differentially). DQ and DM input slew rates must not deviate from DQS by more than 10 percent. If the DQ/ DM/DQS slew rate is less than 0.5V/ns, timing must be derated: 50ps must be added to tDS and t DH for each 100mv/ns reduction in slew rate. If slew rate exceeds 4V/ns, functionality is uncertain. VDD must not vary more than 4 percent if CKE is not active while any bank is active. The clock is allowed up to ±150ps of jitter. Each timing parameter is allowed to vary by the same amount. t HP min is the lesser of tCL minimum and tCH minimum actually applied to the device CK and CK# inputs, collectively during bank active. READs and WRITEs with auto precharge are not allowed to be issued until tRAS(min) can be satisfied prior to the internal precharge command being issued. Figure 7: Derating Data Valid Window t t ( QH - DQSQ) 3.8 3.750 3.700 3.6 3.400 3.4 3.350 3.650 3.600 3.550 3.500 3.450 3.300 3.400 3.250 3.200 3.150 3.2 3.100 tCK -26A/-265 -26A/-265 @ = 10ns -202 @ tCK = 10ns -26A/-265 -26A/-265 @ tCK = 7.5ns -202 @ tCK = 8ns TBD -335 @ tCK = 6ns ns 3.0 2.8 2.6 2.500 2.463 2.425 3.350 2.388 2.350 2.313 2.275 3.250 3.050 3.000 2.4 3.300 2.238 2.200 2.950 2.163 2.2 2.900 2.125 2.0 1.8 50/50 49.5/50.5 49/51 48.5/52.5 48/52 47.5/53.5 47/53 46.5/54.5 46/54 45.5/55.5 45/55 Clock Duty Cycle 09005aef806e1c40 DD5C8_16X72AG 16X72AG_C.fm - Rev. C 8/03 EN 20 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology. Inc. 64MB, 128MB 128MB (x72, ECC) 184-PIN 184-PIN DDR SDRAM DIMM 32. Any positive glitch must be less than 1/3 of the clock and not more than +400mV or 2.9Vs, whichever is less. Any negative glitch must be less than 1/3 of the clock cycle and not exceed either 300mV or 2.2V, whichever is more positive. 33. Normal Output Drive Curves: a) The full variation in driver pull-down current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the V-I curve of Figure 8, PullDown Characteristics. b) The variation in driver pull-down current within nominal limits of voltage and temperature is expected, but not guaranteed, to lie within the inner bounding lines of the V-I curve of Figure 8, Pull-Down Characteristics. c) The full variation in driver pull-up current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the V-I curve of Figure 9, Pull-Up Characteristics. d) The variation in driver pull-up current within nominal limits of voltage and temperature is expected, but not guaranteed, to lie within the inner bounding lines of the V-I curve of Figure 9, Pull-Up Characteristics. e) The full variation in the ratio of the maximum to minimum pull-up and pull-down current should be between 0.71 and 1.4, for device drain-to-source voltages from 0.1V to 1.0V, and at the same voltage and temperature. f ) The full variation in the ratio of the nominal pull-up to pull-down current should be unity ±10 percent, for device drain-to-source voltages from 0.1V to 1.0 Volt. 34. Reduced Output Drive Curves: a) The full variation in driver pull-down current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the V-I curve of Figure 10, Reduced Drive Pull-Down Characteristics, on page 22. b) The variation in driver pull-down current within nominal limits of voltage and temperature is expected, but not guaranteed, to lie within the inner bounding lines of the V-I curve of Figure 10, Reduced Drive Pull-Down Characteristics, on page 22. c) The full variation in driver pull-up current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the V-I curve of Figure 11, Reduced Drive Pull-Up Characteristics, on page 22. d) The variation in driver pull-up current within nominal limits of voltage and temperature is expected, but not guaranteed, to lie within the inner bounding lines of the V-I curve of Figure 11, Reduced Drive Pull-Up Characteristics, on page 22. 35. The full variation in the ratio of the maximum to minimum pull-up and pull-down current should be between 0.71 and 1.4, for device drain-tosource voltages from 0.1V to 1.0V, and at the same voltage. a) The full variation in the ratio of the nominal pull-up to pull-down current should be unity ±10 percent, for device drain-to-source voltages from 0.1V to 1.0V. Figure 8: Pull-Down Characteristics Figure 9: Pull-Up Characteristics 160 0 -20 um Maxim 140 Maximum -40 120 IOUT (mA) 80 Nominal low 60 -80 -100 Nom -120 inal -140 Minimum 40 Nominal high -60 high IOUT (mA) Nominal 100 Min -160 20 low imu m -180 0 -200 0.0 0.5 1.0 1.5 2.0 2.5 0.0 VOUT (V) 09005aef806e1c40 DD5C8_16X72AG 16X72AG_C.fm - Rev. C 8/03 EN 0.5 1.0 1.5 2.0 2.5 VDDQ - VOUT (V) 21 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology. Inc. 64MB, 128MB 128MB (x72, ECC) 184-PIN 184-PIN DDR SDRAM DIMM 36. The voltage levels used are derived from a minimum VDD level and the referenced test load. In practice, the voltage levels obtained from a properly terminated bus will provide significantly different voltage values. 37. VIH overshoot: VIH(MAX) = VDDQ+1.5V for a pulse width £ 3ns and the pulse width can not be greater than 1/3 of the cycle rate. VIL undershoot: VIL(MIN) = -1.5V for a pulse width £ 3ns and the pulse width can not be greater than 1/3 of the cycle rate. 38. VDD and VDDQ must track each other. 39. This maximum value is derived from the referenced test load. In practice, the values obtained in a typical terminated design may reflect up to 310ps less for tHZ (MAX) and the last DVW. tHZ (MAX) will prevail over tDQSCK (MAX) + tRPST (MAX) condition. tLZ (MIN) will prevail over t DQSCK (MIN) + tRPRE (MAX) condition. 40. For slew rates greater than 1V/ns the (LZ) transition will start about 310ps earlier. 41. During initialization, VDDQ, VTT, and VREF must be equal to or less than VDD + 0.3V. Alternatively, Vtt may be 1.35V maximum during power up, even if VDD/VDDQ are 0V, provided a minimum of 42W of series resistance is used between the VTT supply and the input pin. 42. The current Micron part operates below the slowest JEDEC operating frequency of 83 MHz. As such, future die may not reflect this option. 43. tRAP £ tRCD. 44. For the -335, -262, -26A, and -265 modules, IDD3N is specified to be 35mA at 100 MHz. 45. Random addressing changing and 50 percent of data changing at every transfer. 46. Random addressing changing and 100 percent of data changing at every transfer. 47. CKE must be active (high) during the entire time a refresh command is executed. That is, from the time the AUTO REFRESH command is registered, CKE must be active at each rising clock edge, until t REF later. 48. IDD2N specifies the DQ, DQS, and DM to be driven to a valid high or low logic level. IDD2Q is similar to IDD2F except IDD2Q specifies the address and control inputs to remain stable. Although IDD2F, IDD2N, and IDD2Q are similar, IDD2F is "worst case." 49. Whenever the operating frequency is altered, not including jitter, the DLL is required to be reset. This is followed by 200 clock cycles. 50. Leakage number reflects the worst case leakage possible through the module pin, not what each memory device contributes. 51. The -335 module speed grade, using the -6R speed device, has VDD (MIN) = 2.4V. Figure 10: Reduced Drive Pull-Down Characteristics Figure 11: Reduced Drive Pull-Up Characteristics 80 0 -5 imum Max 70 -10 60 -15 IOUT (mA) 40 IOUT (mA) Nominal high 50 Nominal low Minimum -20 Nomin al low Nom inal high -25 -30 30 -35 Minimum 20 Ma xim -40 um -45 10 -50 0 0.0 0.0 0.5 1.0 1.5 2.0 2.5 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 VDDQ - VOUT (V) VOUT (V) 09005aef806e1c40 DD5C8_16X72AG 16X72AG_C.fm - Rev. C 8/03 EN 22 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology. Inc. 64MB, 128MB 128MB (x72, ECC) 184-PIN 184-PIN DDR SDRAM DIMM SPD Clock and Data Conventions SPD Acknowledge Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions ( as shown in Figure 12, Data Validity, and Figure 13, Definition of Start and Stop). Acknowledge is a software convention used to indicate successful data transfers. The transmitting device, either master or slave, will release the bus after transmitting eight bits. During the ninth clock cycle, the receiver will pull the SDA line LOW to acknowledge that it received the eight bits of data (as shown in Figure 14, Acknowledge Response from Receiver). The SPD device will always respond with an acknowledge after recognition of a start condition and its slave address. If both the device and a write operation have been selected, the SPD device will respond with an acknowledge after the receipt of each subsequent eight-bit word. In the read mode the SPD device will transmit eight bits of data, release the SDA line and monitor the line for an acknowledge. If an acknowledge is detected and no stop condition is generated by the master, the slave will continue to transmit data. If an acknowledge is not detected, the slave will terminate further data transmissions and await the stop condition to return to standby power mode. SPD Start Condition All commands are preceded by the start condition, which is a HIGH-to-LOW transition of SDA when SCL is HIGH. The SPD device continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition has been met. SPD Stop Condition All communications are terminated by a stop condition, which is a LOW-to-HIGH transition of SDA when SCL is HIGH. The stop condition is also used to place the SPD device into standby power mode. Figure 12: Data Validity Figure 13: Definition of Start and Stop SCL SCL SDA SDA DATA STABLE DATA CHANGE DATA STABLE START BIT STOP BIT Figure 14: Acknowledge Response from Receiver SCL from Master 8 9 Data Output from Transmitter Data Output from Receiver Acknowledge 09005aef806e1c40 DD5C8_16X72AG 16X72AG_C.fm - Rev. C 8/03 EN 23 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology. Inc. 64MB, 128MB 128MB (x72, ECC) 184-PIN 184-PIN DDR SDRAM DIMM Table 17: EEPROM Device Select Code Most significant bit (b7) is sent first DEVICE TYPE IDENTIFIER SELECT CODE CHIP ENABLE RW b7 b6 b5 b4 b3 b2 b1 b0 1 0 0 1 1 1 0 0 SA2 SA2 SA1 SA1 SA0 SA0 RW RW Memory Area Select Code (two arrays) Protection Register Select Code Table 18: EEPROM Operating Modes MODE RW BIT WC BYTES 1 0 1 1 0 0 VIH or VIL VIH or VIL VIH or VIL VIH or VIL VIL VIL 1 1 1 ³1 1 £ 16 Current Address Read Random Address Read Sequential Read Byte Write Page Write INITIAL SEQUENCE START, Device Select, RW = "1" START, Device Select, RW = "0", Address reSTART, Device Select, RW = "1" Similar to Current or Random Address Read START, Device Select, RW = "0" START, Device Select, RW = "0" Figure 15: SPD EEPROM Timing Diagram tF t HIGH tR t LOW SCL t SU:STA t HD:STA t SU:DAT t HD:DAT t SU:STO SDA IN t DH t AA t BUF SDA OUT UNDEFINED 09005aef806e1c40 DD5C8_16X72AG 16X72AG_C.fm - Rev. C 8/03 EN 24 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology. Inc. 64MB, 128MB 128MB (x72, ECC) 184-PIN 184-PIN DDR SDRAM DIMM Table 19: Serial Presence-Detect EEPROM DC Operating Conditions All voltages referenced to VSS; VDDSPD = +2.3V to +3.6 PARAMETER/CONDITION SYMBOL VDD VIH VIL VOL ILI ILO ISB IDD SUPPLY VOLTAGE INPUT HIGH VOLTAGE: Logic 1; All inputs INPUT LOW VOLTAGE: Logic 0; All inputs OUTPUT LOW VOLTAGE: IOUT = 3mA INPUT LEAKAGE CURRENT: VIN = GND to VDD OUTPUT LEAKAGE CURRENT: VOUT = GND to VDD STANDBY CURRENT: SCL = SDA = VDD - 0.3V; All other inputs = VSS or VDD POWER SUPPLY CURRENT: SCL clock frequency = 100 KHz MIN MAX 2.2 5.5 VDD x 0.7 VDD + 0.5 -1 VDD x 0.3 ­ 0.4 ­ 10 ­ 10 ­ 30 ­ 2 UNITS V V V V µA µA µA mA Table 20: Serial Presence-Detect EEPROM AC Operating Conditions All voltages referenced to VSS; VDDSPD = +2.3V to +3.6 PARAMETER/CONDITION SYMBOL MIN MAX UNITS AA 0.3 3.5 µs µs ns SCL LOW to SDA data-out valid t Time the bus must be free before a new transition can start t BUF 4.7 Data-out hold time t 300 DH 300 t SDA and SCL fall time F NOTES ns Data-in hold time t HD:DAT 0 µs Start condition hold time t HD:STA 4 µs t 4 µs ClockHIGHperiod HIGH 100 t Noise suppression time constant at SCL, SDA inputs I Clock LOW period t LOW 4.7 ns µs R 1 µs SCL 100 KHz t SDA and SCL rise time t SCL clock frequency SU:DAT 250 ns Start condition setup time t SU:STA 4.7 µs Stop condition setup time t SU:STO 4.7 µs Data-in setup time t WRITE cycle time t WRC 10 ms 1 NOTE: 1. The SPD EEPROM WRITE cycle time (tWRC) is the time from a valid stop condition of a write sequence to the end of the EEPROM internal erase/program cycle. During the WRITE cycle, the EEPROM bus interface circuit is disabled, SDA remains HIGH due to pull-up resistor, and the EEPROM does not respond to its slave address. 09005aef806e1c40 DD5C8_16X72AG 16X72AG_C.fm - Rev. C 8/03 EN 25 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology. Inc. 64MB, 128MB 128MB (x72, ECC) 184-PIN 184-PIN DDR SDRAM DIMM Table 21: Serial Presence-Detect Matrix (64MB, 128MB 128MB) "1"\"0": Serial Data, "driven to HIGH"/"driven to LOW" BYTE 0 1 2 3 4 5 6 7 8 9 ENTRY (VERSION) MT5VDDT872A MT5VDDT872A MT5VDDT1672A MT5VDDT1672A 128 256 SDRAM DDR 11 or 12 9 1 72 0 SSTL 2.5V 6ns (-335) 7ns (-262) 7ns (-26A) 7.5ns (-265) 8ns (-202) 0.70ns (-335) 0.75ns (-262/-26A/-265 -262/-26A/-265) 0.80ns (-202) ECC 15.6µs or 7.8µs/SELF x16 None 1 clock 80 08 07 0C 09 01 48 00 04 60 70 70 75 80 70 75 80 02 80 10 00 01 80 08 07 0D 09 01 48 00 04 60 70 70 75 80 70 75 80 02 82 10 00 01 2, 4, 8 4 2, 2.5 0 1 Unbuffered, Diff CLK Fast / Auto Precharge (No/Yes) 7.5ns (-335/-262/-26A -335/-262/-26A) 10ns (-265/-202) 0.70ns (-335) 0.75ns (-262/-26A/-265 -262/-26A/-265) 0.8ns (-202) N/A 0E 04 0C 01 02 20 C1 0E 04 0C 01 02 20 C1 75 A0 70 75 80 00 75 A0 70 75 80 00 N/A 00 00 18ns (-335) 20ns (-262) 20ns (-26A/-265/-202 -26A/-265/-202) 12ns (-335) 15ns (-262/-26A/-265/-202 -262/-26A/-265/-202) 18ns (-335) 20ns (-262) 20ns (-26A/-265/-202 -26A/-265/-202) 48 3C 50 30 3C 48 3C 50 48 3C 50 30 3C 48 3C 50 DESCRIPTION Number of SPD Bytes Used by Micron Total Number of Bytes in SPD Device Fundamental Memory Type Number of Row Addresses on Assembly Number of Column Addresses on Assembly Number of Physical Ranks on DIMM Module Data Width Module Data Width (Continued) Module Voltage Interface Levels SDRAM Cycle Time, (tCK); CAS Latency = 2.5 (See note 1) 10 SDRAM Access From Clock,( tAC); CAS Latency = 2.5 (See note 1) 11 12 13 14 15 16 17 18 19 20 21 22 Module Configuration Type Refreshrate/Type SDRAM Device Width (Primary SDRAM) Error-Checking SDRAM Data Width Minimum Clock Delay Back-to-Back Random Column Access Burst Lengths Supported Number of Banks on SDRAM Device CAS Latencies Supported CS Latency WE Latency SDRAM Module Attributes SDRAM Device Attributes: General 23 SDRAM Cycle Time, (tCK) CAS Latency = 2 24 SDRAM Access from CK , (tAC) CAS Latency = 2 25 SDRAM Cycle Time,(tCK) CAS Latency = 1.5 26 SDRAM Access From CK , (tAC) CAS Latency = 1.5 27 Minimum Row Precharge Time, ( tRP) 28 Minimum Row Active to Row Active, (tRRD) 29 Minimum RAS# to CAS# Delay, (tRCD) 09005aef806e1c40 DD5C8_16X72AG 16X72AG_C.fm - Rev. C 8/03 EN 26 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology. Inc. 64MB, 128MB 128MB (x72, ECC) 184-PIN 184-PIN DDR SDRAM DIMM Table 21: Serial Presence-Detect Matrix (64MB, 128MB 128MB) "1"\"0": Serial Data, "driven to HIGH"/"driven to LOW" BYTE 30 Minimum RAS# Pulse Width, RAS) (See note 2) 31 32 Module Rank Density 33 Address and Command Hold Time (tIH) (See note 3) 34 Data/Data Mask Input Setup Time (tDS) 35 Data/ Data Mask Input Hold Time (tDH) 36-40 41 42 43 44 45 46-61 47 46-61 62 63 64 65-71 72 73-90 91 92 ENTRY (VERSION) DESCRIPTION (t Address and Command Setup Time (tIS) (See note 3) 42ns (-335) 45ns (-262/-26A/-265 -262/-26A/-265) 40ns (-202) 64MB or 128MB 128MB 0.8ns (-335) 1.0ns(-262/-26A/-265 -262/-26A/-265) 1.1ns (-202) 0.8ns (-335) 1.0ns(-262/-26A/-265 -262/-26A/-265) 1.1ns (-202) 0.45 (-335) 0.5 (-262/-26A/-265 -262/-26A/-265) 0.6 (-202) 0.45 (-335) 0.5 (-262/-26A/-265 -262/-26A/-265) 0.6 (-202) Reserved 60ns (-335/-262) 65ns (-26A/-265 -26A/-265) 70ns (-202) 72ns (-335) Minimum Auto Refresh To Active/ Auto Refresh 75ns (-262/-26A/-265 -262/-26A/-265) Command Period (tRFC) 80ns (-202) t 12.0ns (-335) Maximum Cycle Time ( CK (MAX) 13.0ns (-262/-202/ -265/ -26A) t 0.45ns (-335) Maximum DQS-DQ Skew Time ( DQSQ) 0.5ns(-262/-26A/-265 -262/-26A/-265) 0.6ns (-202) t 0.55ns (-335) Maximum Read Data Hold Skew Factor ( QHS) 0.75ns(-262/-26A/-265 -262/-26A/-265) 1.0ns (-202) Reserved DIMM Height Reserved Release 1.0 SPD Revision -335 Checksum for Bytes 0-62 -262 -26A -265 -202 MICRON Manufacturer's JEDEC ID Code Manufacturer's JEDEC ID Code (continued) 1 - 11 Manufacturing Location Module Part Number (ASCII) 1-9 PCB Identification Code 0 Identification Code (Continued) Minimum Active/ Auto Refresh Time (tRC) 09005aef806e1c40 DD5C8_16X72AG 16X72AG_C.fm - Rev. C 8/03 EN 27 MT5VDDT872A MT5VDDT872A MT5VDDT1672A MT5VDDT1672A 2A 2D 28 10 80 A0 B0 80 A0 B0 45 50 60 45 50 60 00 3C 41 46 48 4B 50 30 34 2D 32 3C 55 75 A0 00 01 00 10 16 A9 D6 06 A1 2C FF 01 - 0B Variable Data 01 - 09 00 2A 2D 28 20 80 A0 B0 80 A0 B0 45 50 60 45 50 60 00 3C 41 46 48 4B 50 30 34 2D 32 3C 55 75 A0 00 01 00 10 29 BC E9 19 B4 2C FF 01 - 0B Variable Data 01 - 09 00 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology. Inc. 64MB, 128MB 128MB (x72, ECC) 184-PIN 184-PIN DDR SDRAM DIMM Table 21: Serial Presence-Detect Matrix (64MB, 128MB 128MB) "1"\"0": Serial Data, "driven to HIGH"/"driven to LOW" BYTE 93 94 95-98 99-127 ENTRY (VERSION) DESCRIPTION MT5VDDT1672A MT5VDDT1672A Variable Data Variable Data Variable Data ­ Year of Manufacture in BCD Week of Manufacture in BCD Module Serial Number Manufacturer-Specific Data (RSVD) MT5VDDT872A MT5VDDT872A Variable Data Variable Data Variable Data ­ NOTE: 1. Value for -26A tCK set to 7ns (0x70) for optimum BIOS compatibility. Actual device spec value is 7.5ns. 2. The value of tRAS used for the -26A/-265 -26A/-265 module is calculated from tRC- tRP. Actual device spec. value is 40ns. 3. The JEDEC SPD specification allows fast or slow slew rate values for these bytes. The worst-case (slow slew rate) value is represented here. Systems requiring the fast slew rate setup and hold values are supported, provided the faster minimum slew rate is met. 09005aef806e1c40 DD5C8_16X72AG 16X72AG_C.fm - Rev. C 8/03 EN 28 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology. Inc. 64MB, 128MB 128MB (x72, ECC) 184-PIN 184-PIN DDR SDRAM DIMM Figure 16: 184-Pin DIMM Dimensions 0.125 (3.18) MAX FRONT VIEW 5.256 (133.50) 5.244 (133.20) 0.079 (2.00) R (4X) U1 U3 U2 U4 U5 1.256 (30.63) 1.244 (30.33) U6 0.700 (17.78) TYP. 0.098 (2.50) D (2X) 0.091 (2.30) TYP. 0.035 (0.90) R PIN 1 0.091 (2.30) TYP. PIN 92 0.250 (6.35) TYP. 0.050 (1.27) TYP. 0.054 (1.37) 0.046 (1.17) 0.040 (1.02) TYP. 4.750 (120.65) TYP. BACK VIEW No Components This Side of Module PIN 93 PIN 184 1.95 (49.53) TYP. 2.55 (64.77) TYP. 0.150 (3.80) 0.394 (10.00) TYP. TYP. NOTE: All dimensions in inches (millimeters) MAX MIN or typical where noted. Data Sheet Designation Released: This data sheet contains minimum and maximum limits specified over the complete power supply and temperature range for production devices. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. ® 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992 Micron, the M logo, and the Micron logo are trademarks and/or service marks of Micron Technology, Inc. 09005aef806e1c40 DD5C8_16X72AG 16X72AG_C.fm - Rev. C 8/03 EN 29 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc