500 MILLION PARTS FROM 12000 MANUFACTURERS
500 MILLION PARTS FROM 12000 MANUFACTURERS
PAN0704111 - Datasheet Archive
Replacing Crystals and Oscillators Doc ID: PAN0704111 Author: Eddy van Keulen Date: 11-Apr-07 One PhaseLink IC can replace
PhaseLink Application Note Replacing Crystals and Oscillators Doc ID: PAN0704111 PAN0704111 Author: Eddy van Keulen Date: 11-Apr-07 One PhaseLink IC can replace multiple crystals or oscillator modules. However, some care has to be taken about connecting the PhaseLink IC output to the target crystal pin or CMOS input. This application note will describe the following connections: 1) Replacing a crystal: How to connect the PhaseLink IC output to a crystal pin. 2) Replacing an oscillator module: How to connect the PhaseLink IC output to a CMOS input with the following conditions: a) VDD1 = VDD2* b) VDD1 > VDD2 c) VDD1 < VDD2 * VDD1 is the supply voltage of the PhaseLink IC and VDD2 is the supply voltage of the circuit with the target input. 1) Replacing a Crystal PhaseLink IC's often replace a number of crystals in the application. This means that a Clock Output needs to drive a pin of the crystal oscillator. I would like to make the following suggestions for driving a crystal pin: 1) Use the XIN pin or "crystal oscillator input" pin to drive the clock signal into. 2) Use AC coupling from Clock Output to the crystal oscillator pin. This allows the biasing of the crystal oscillator to do its job. However if the signal amplitude from the Clock Output is large enough, C1 may not be necessary. 3) Select a low VDD value for the PhaseLink IC, if possible. When using AC coupling it is not necessary to have a large amplitude from the Clock Output. Depending on the crystal oscillator circuit, it may be better to have a lower amplitude to make the signal more similar to a crystal signal. The biggest advantage may be a very low power consumption of the PhaseLink IC at a low voltage (e.g. 1.8V). 4) Use low drive strength for the Clock Output buffer. When using a crystal the waveform will be a sine wave. Low drive strength would slow down rising and falling edges of the signal and making it look as much as possible like a sine wave. The drive strength can be further reduced with a series resistor (see R1 in the circuit on the next page). 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com 4/11/07 Page 1 PhaseLink Application Note Replacing Crystals and Oscillators VDD1 VDD2 PhaseLink IC 0.1µF VDD VDD Clock Output XIN C1 R1 XOUT GND GND (Diagram 1) The value of C1 is difficult to determine in this document, not knowing any details about the XIN pin. As mentioned above, we can take the easy way out and select a large value like 1000pF or larger. Sometimes a more square wave looking signal with a large amplitude on XIN causes more cross-talk of this signal to other circuitry. Using a series resistor R1 can solve the issue. The best value for R1 depends upon the frequency and the XIN input capacitance (CXIN). This capacitance can be quite large, like 20pF or 30pF. The best value for R1 can be calculated as follows: R1 = 1 / (2 × F × CXIN) Example: F = 20MHz and C = 30pF R1 = 1 / (2 × 20MHz × 30pF) = 265 The closest commercially available value would be 270. 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com 4/11/07 Page 2 PhaseLink Application Note Replacing Crystals and Oscillators 2a) Replacing an oscillator When driving a CMOS input from a clock output on a PhaseLink IC, the general advice is to use the same VDD voltage on both the PhaseLink IC and the IC that is receiving the signal. You can make a direct connection without the need of additional components. When the distance between the Clock Output and the CMOS Input is large so you see reflections on the signal at the CMOS Input, you can use R1 to match the Clock Output impedance to the trace impedance. The output impedance of the Clock Output usually is near 20 and when the trace is designed for a 50 impedance, you would need R1 = 30. PhaseLink IC 0.1µF VDD Clock Output VDD R1 CMOS Input GND GND (Diagram 2) This is the simplest application and probably the most used also. However there are situations where the VDD on the PhaseLink IC and the circuit with the CMOS input is different. The following pages will address a number of different situations and suggest circuits to deal with those situations. 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com 4/11/07 Page 3 PhaseLink Application Note Replacing Crystals and Oscillators 2b) Replacing an oscillator When driving a CMOS input on a chip with a lower supply voltage, the clock signal needs to be attenuated. This can be done with two resistors and a capacitor: VDD1 PhaseLink IC 0.1µF VDD2 VDD Clock Output R1 GND VDD C1 R2 CMOS Input GND (Diagram 3) In this case VDD2 is smaller than VDD1. The resistor divider attenuates the amplitude and C1 corrects the rise/fall time speed. C1 may not be necessary depending on rise/fall time requirements. Configuring R1, R2 and C1: R1 and R2 will cause some extra supply current. The current can be calculated with the following formula: INetwork = VDD1 / (2×(R1+R2). Lets say that we want INetwork to be 0.1mA with VDD1=3.3V, then R1+R2 = 16500. Next we can calculate R2: R2 = (R1+R2) × VDD2 / VDD1. Finally we can calculate R1: R1 = (R1+R2) R2. Example: VDD1=3.3V, VDD2=1.8V and INetwork = 0.1mA (R1+R2) = 3.3 / (2×0.1mA) = 16500. R2 = 16500 × 1.8 / 3.3 = 9000. R1 = 16500 9000 = 7500. Without C1 the rise/fall times will be at least CInput × R1×R2/(R1+R2) where CInput is the input capacitance of the CMOS input. Lets assume CInput is 3pF with above network, the rise/fall will be at least 3pF × 9000×7500/(9000+7500) = 12.3ns. If this is too slow, the rise/fall times can be corrected with C1. The formula is: C1 = CInput × R2 / R1. In case of the example, C1 = 3pF × 9000 / 7500 = 3.6pF. The ratio between R1 and R2 is more important than the absolute values of R1 and R2. When we use R1 = 10000 and R2 = 12000, we have the same ratio but with easy commercially available values. The current through the network is now 0.075mA, all other properties will remain the same. 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com 4/11/07 Page 4 PhaseLink Application Note Replacing Crystals and Oscillators 2c) Replacing an oscillator When VDD on the PhaseLink IC is lower than VDD on the circuit with the CMOS input, we need to use a different network. VDD1 PhaseLink IC 0.1µF VDD2 VDD Clock Output R1 VDD C1 CMOS Input GND R2 GND In this case VDD1 is smaller than VDD2. This network with R1, R2 and C1 will shift the average level of the Clock Output signal to the threshold point of the CMOS Input. For most CMOS inputs this VThreshold is 50% of VDD which makes R1 = R2. In this case also the network draws a little bit of current. The current will be VDD2/(R1+R2). With 0.1mA and VDD2=3.3V, R1+R2 = 33000 and R1 = R2 = 16500. For commercially available values we can use 18000 or 22000, where the network current reduces to resp. 0.092mA and 0.075mA. When VThreshold is not 50%VDD then we can calculate R1 and R2 as follows: R2 = (R1+R2) × VThreshold / VDD2 R1 = (R1+R2) R2. C1 simply needs to be large enough to not cause any significant attenuation. The -3dB point of the highpass network with C1, R1 and R2 is: F-3dB = (R1+R2) / (2 × R1×R2×C1) or C1 = (R1+R2) / (2 × F-3dB × R1×R2) Lets say the lowest Clock Output frequency is 10MHz and we want F-3dB to be at least 10× below this point at 1MHz maximum. With R1 = R2 = 22000 : C1 > (22000+22000) / (2 × 1000000 × 22000 × 22000) = 14.5pF. So C1=15pF or larger should be OK. The easy way out is to select C1 = 1000pF or larger to be able to pass almost any signal. There is one issue with this method: The signal on the CMOS Input will not swing rail-to-rail on this input. The amplitude is set by VDD1. For example when VDD1 = 1.8V, then the signal amplitude is 1.8Vpp. When VDD2 = 3.3V, then the signal on the CMOS Input will swing between 0.75V (=23%VDD) and 2.55V (=77%VDD). It depends upon the CMOS Input level requirements if this is OK or not. Usually CMOS inputs are fine with 40% / 60% level and certainly with 30% / 70% levels. 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com 4/11/07 Page 5 PhaseLink Application Note Replacing Crystals and Oscillators When VDD1 and VDD2 are close, you may consider not using the network and simply connect straight from Clock Output to CMOS Input. VDD1 PhaseLink IC 0.1µF VDD VDD2 Clock Output VDD GND CMOS Input GND For example with VDD1=2.5V and VDD2=3.3V, the signal high level on the CMOS Input is 2.5V or 76% of VDD2. It still complies with a 30% / 70% signal level requirement. So without the network you will have signal levels of 0% / 76% and with the network with R1, R2 and C1 the levels would improve to 12% / 88%. 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com 4/11/07 Page 6