OV6645 ITU-656 3000K 30FPS 356X292 U10Y10 V11Y11 2F-33 - Datasheet Archive

 

Preliminary OV6645 OV6645 SINGLE-CHIP CMOS CIF COLOR DIGITAL CAMERA Description Applications The OV6645 (color) CMOS Image sensor

 

Advanced Information Preliminary OV6645 OV6645 OV6645 OV6645 SINGLE-CHIP CMOS CIF COLOR DIGITAL CAMERA Description Applications The OV6645 OV6645 (color) CMOS Image sensor is a single-chip video/imaging camera device designed to provide a high level of functionality in a single, small-footprint package. The device incorporates a 352 x 288 image array capable of operating at up to 60 frames per second. Proprietary sensor technology utilizes advanced algorithms to cancel Fixed Pattern Noise (FPN), eliminate smearing, and drastically reduce blooming. All required camera functions including exposure control, gamma, gain, white balance, color matrix, color saturation, hue control, windowing, and more, are programmable through the serial SCCB interface. The device can be programmed to provide image output in different 8-bit formats. . Picture Phones . Cell Phones . Toys . PC Multimedia . PDAs Key Specifications Array Element(CIF) (QCIF) Pixel Size Image Area Max Frames/Sec Features ! 101,376 pixels, 1/5" lens, CIF/QCIF format ! Progressive scan ! 8-bit Data output formats - YCrCb 4:2:2 ITU-656 ITU-656, GRB 4:2:2 & RGB Raw Data ! Wide dynamic range, anti-blooming, zero smearing ! Electronic exposure/gain/white balance control ! Image Controls - brightness, contrast, gamma, saturation, sharpness, windowing, hue, etc. ! Internal & external synchronization 352x288 (176x144) 7.6µm x 7.6µm 2.7mm x 2.18mm Up to 60 FPS Electronics Exposure Up to 320:1 (at the selected frame rate) Scan Mode Progressive Gamma Correction 0.45/0.55/1.0 Min. Illumination (3000K 3000K) S/N Ratio < 3lux @ f1.2 > 48 dB (AGC off, Gamma=1) < 0.03% VPP Dark Current ! Line exposure option ! 3.3-Volt operation, low power dissipation - < 20 mA active power at 30FPS 30FPS FPN < 1.3nA/cm2 Dynamic Range > 72 dB Power Supply 3.0-3.6VDC Power Requirements < 20mA active < 10µA Standby Package PWDN SIO_C Y0 24 23 22 6 DOVDD 1 5 VCCHG 2 4 VREQ 1 SIO_D 3 Ordering Information AGND 24 pin LCC AVDD balance, N/C - < 10 µA in power-down mode ! Built in Gamma correction (0.45/0.55/1.00) ! SCCB programmable: - Color saturation, brightness, hue, white exposure time, gain, etc. Y2 19 Y3 7 18 Y4 8 17 Y5 9 16 Y6 OmniVision Technologies, Inc. 930 Thompson Place Sunnyvale, CA 94085 U.S.A. Tel: (408) 733-3030 Fax: (408) 733-3061 e-mail: info@ovt.com Website: http://www.ovt.com 11 12 13 14 15 Y7 10 DGND OV6645 OV6645 RESET 2 20 PCLK 0.400 in COLOR, CIF, Digital, SCCB interface XCLK1 24 LCC Description DVDD OV6645 OV6645 Y1 HREF Package 21 VSYNC Product Version 4.6, July 27, 2001 Page 1 Advanced Information Preliminary OV6645 OV6645 OV6645 OV6645 SINGLE-CHIP CMOS CIF COLOR DIGITAL CAMERA Figure 1. OV6645 OV6645 Pin Diagram OmniVision Technologies, Inc. 930 Thompson Place Sunnyvale, CA 94085 U.S.A. Tel: (408) 733-3030 Fax: (408) 733-3061 e-mail: info@ovt.com Website: http://www.ovt.com Version 4.6, July 27, 2001 Page 2 Advanced Information Preliminary OV6645 OV6645 OV6645 OV6645 SINGLE-CHIP CMOS CIF COLOR DIGITAL CAMERA Pin Description Table 1. Pin Description Pin 01 02 03 04 Name AGND AVDD N/C PWDN Pin Type VIN VIN NC Function (Default=0) 05 06 07 08 09 10 11 12 13 VREQ VrCHG DOVDD VSYNC HREF PCLK DVDD XCLK1 RESET 14 15 16 17 18 19 20 21 22 23 24 DGND Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 SIO-C SIO-D VREF (1.5V) VREF (2.7V) VIN O O O VIN I Function (Default=0) VIN O O O O O O O O I I/O Function/Description Analog ground Analog power supply (+3.3VDC), Bypass to ground with a 0.1µF capacitor Not connected internally Enable Power Down, or sleep mode. All control register settings are maintained. "0" ­ Operating "1" ­ Powered Down Array reference. Bypass to ground with a 0.1µF capacitor. Internal voltage reference. Bypass to ground with a 1µF capacitor. Power supply for digital output drive (3.3V) Vertical sync output HREF output (active video), used for horizontal sync. PCLK (Pixel Clock) output Digital power supply (+3.3VDC), Bypass to ground with a 0.1µF capacitor Clock input Chip reset, active high. When asserted high, the control register settings are reset to the factory defaults. Digital ground Bit 7 of Y/UV video data output Bit 6 of Y/UV video data output Bit 5 of Y/UV video data output Bit 4 of Y/UV video data output Bit 3 of Y/UV video data output Bit 2 of Y/UV video data output Bit 1 of Y/UV video data output Bit 0 of Y/UV video data output SCCB serial control interface clock input. SCCB serial control interface data input and output. Legend: (I=Input), (O=Output), (I/O=Bi-directional), (P=Power), (A=Analog) OmniVision Technologies, Inc. 930 Thompson Place Sunnyvale, CA 94085 U.S.A. Tel: (408) 733-3030 Fax: (408) 733-3061 e-mail: info@ovt.com Website: http://www.ovt.com Version 4.6, July 27, 2001 Page 3 Advanced Information Preliminary OV6645 OV6645 OV6645 OV6645 SINGLE-CHIP CMOS CIF COLOR DIGITAL CAMERA Electrical and Mechanical Characteristics Table 2. General Characteristics Descriptions Min Operating temperature (guaranteed performance) Operating temperature (chip functional) Storage temperature Operating humidity Storage humidity Max Units 0 -10 -40 TBD TBD 40 70 125 TBD TBD °C °C °C Table 3. DC Characteristics (0°C TA 85°C, Voltages referenced to GND) ° ° Symbol Descriptions Max Typ Min Units 3.6 30 3.3 3.0 V mA Supply VDD1 IDD1 Supply voltage (DEVDD, ADVDD, AVDD, SVDD) Supply current (@50Hz frame rate and 3.3V digital I/O with 25pF plus 1TTL loading on 10-bit data bus) IDD2 Supply current (VDD=3V, @50Hz frame rate without digital I/O loading) IDD3 Standby supply current Digital Inputs VIL Input voltage LOW VIH Input voltage HIGH CIN Input capacitor Input pin impedance Digital Outputs (standard loading 25pF, 1.2K to 3V) VOH Output voltage HIGH VOL Output voltage LOW Output pin source Output sink current SCCB Input VIL SIO-C and SIO-D (VDD2=3V) VIH SIO-C and SIO-D (VDD2=3V) 10 12 5 mA µA 0.8 V V PF 2 10 2.4 V V -0.5 2.5 V V 0.6 1 VDD+0.5 0 3 Table 4. AC Characteristics (TA=25°C, VDD=3V) ° Symbol Descriptions Min Typ RGB/TCrCb Output ISO Maximum sourcing current VY DC level at zero signal YPP 100% amplitude (without sync) Sync amplitude ADC Parameters B Analog bandwidth DIFF DLE DC differential linearity error ILE DC integral linearity error Max 15 1.2 1 0.4 Units mA V MHz 0.5 1 LSB LSB Table 5. Timing Characteristics Symbol Descriptions Oscillator and Clock Input fOSC Frequency (XCLK1) tr , tf Clock input rise/fall time Clock input duty cycle OmniVision Technologies, Inc. 930 Thompson Place Sunnyvale, CA 94085 U.S.A. Tel: (408) 733-3030 Fax: (408) 733-3061 e-mail: info@ovt.com Website: http://www.ovt.com Max Typ Min Units 27 5 55 17.734 10 50 45 MHz ns % Version 4.6, July 27, 2001 Page 4 Advanced Information Preliminary OV6645 OV6645 OV6645 OV6645 SINGLE-CHIP CMOS CIF COLOR DIGITAL CAMERA Symbol Descriptions SCCB Timing (400Kbit/s) tBUF Bus free time between STOP and START tHD:SAT SIO-D change after START status tLOW SIO-D low period tHIGH SIO-D high period tHD:DAT Data hold time tSU:DAT Data setup time tSU:STP Setup time for STOP status Digital Timing tPCLK PCLK cycle time 8-bit operation tr , tf PCLK rise/fall time tPDD PCLK to data valid tPHD PCLK to HREF delay Max Typ Min Units 1.3 0.6 1.3 0.6 0 0.1 0.6 ms µs µs µs µs µs µs 5 ns ns ns ns 56 15 15 20 10 Notes: 1. In Interlaced Mode, there are even/odd field different (t8). When In Progressive Scan Mode, only frame timing same as Even field(t8). 2. After VSYNC falling edge, OV6645 OV6645 will output the black reference level. The line number is TVS, which is the line number between the 1st HREF rising edge after VSYNC falling edge and 1st valid data CHSYNC rising edge. Next is the valid data, then black reference. The line number is TVE, which is the line number between last valid data CHSYNC rising edge and 1st CHSYNC rising edge after VSYNC rising edge. The black reference output line number is dependent on vertical window setting. 3. When in default setting, TVE = 14 × TLINE, which is changed with register VS[7:0]. VS[7:0] step equal to 1 line. 4. When in default setting, TVE = 4 × TLINE for Odd Field, TVE = 3 × TLINE for Even Field, which is changed with register VE[7:0]. VE[7:0] step equal to 1 line. OmniVision Technologies, Inc. 930 Thompson Place Sunnyvale, CA 94085 U.S.A. Tel: (408) 733-3030 Fax: (408) 733-3061 e-mail: info@ovt.com Website: http://www.ovt.com Version 4.6, July 27, 2001 Page 5 Advanced Information Preliminary OV6645 OV6645 OV6645 OV6645 SINGLE-CHIP CMOS CIF COLOR DIGITAL CAMERA Figure 2. OV6645 OV6645 Light Response OmniVision Technologies, Inc. 930 Thompson Place Sunnyvale, CA 94085 U.S.A. Tel: (408) 733-3030 Fax: (408) 733-3061 e-mail: info@ovt.com Website: http://www.ovt.com Version 4.6, July 27, 2001 Page 6 Advanced Information Preliminary OV6645 OV6645 OV6645 OV6645 SINGLE-CHIP CMOS CIF COLOR DIGITAL CAMERA Function Description Overview MUX A/D Analog Processing Y Cb Cr MUX Row Select Column Sense Amp Exposure/Gain Detect Y [7:0] WB Detect (356X292 356X292) Image Array Registers Video Timing Generator WB Control SCCB Interface SIO-C PWDN RESET VSYNC PCLK HREF Exposure/GAIN Control SIO-D clock XCLK1 A/D Video port R G B The OV6645 OV6645 sensor is a 0.2" CMOS imaging device. The sensor contains approximately 101,376 pixels (352x288). Its design is based on a field integration readout system with lineby-line transfer and an electronic shutter with a synchronous pixel readout scheme. The color filter of the sensor consists of a primary color RG/GB array arranged in line-alternating fashion. Formatter Referring to Figure 3 below, the OV6645 OV6645 sensor includes a 356 x 292 resolution image array, an analog signal processor, dual 8-bit A/D converters, analog video multiplexer, digital data formatter, video port, SCCB interface, registers, and digital controls that include timing block, exposure control, black level control, and white balance. Figure 3. OV6645 OV6645 CMOS Image Sensor Block Diagram OmniVision Technologies, Inc. 930 Thompson Place Sunnyvale, CA 94085 U.S.A. Tel: (408) 733-3030 Fax: (408) 733-3061 e-mail: info@ovt.com Website: http://www.ovt.com Version 4.6, July 27, 2001 Page 7 Advanced Information Preliminary OV6645 OV6645 OV6645 OV6645 SINGLE-CHIP CMOS CIF COLOR DIGITAL CAMERA Analog Processor Circuits YCrCb format is also supported, based on the formula below: Y = 0.59G + 0.31R + 0.11B Cr = 0.713 (R ­ Y) Cb = 0.564 (B ­ Y) The on-chip 8-bit A/D operates at up to 9 MHz, and is fully synchronous to the pixel rate. Actual conversion rate is related to the frame rate. A/D black-level calibration circuitry ensures: · The black level of Y/RGB is normalized to a value of 16 · The peak white level is limited to 240 · CrCb black level is 128 · CrCb Peak/bottom is 240/16 · RGB raw data output range is 16/240 (Note: Values 0 and 255 are reserved for sync flag) Image Processing The algorithm used for the electronic exposure control is based on the brightness of the full image. The exposure is optimized for a "normal" scene that assumes the subject is well lit relative to the background. In situations where the image is not well lit, the automatic exposure control (AEC) white/black ratio may be adjusted to suit the needs of the application. OmniVision Technologies, Inc. 930 Thompson Place Sunnyvale, CA 94085 U.S.A. Tel: (408) 733-3030 Fax: (408) 733-3061 e-mail: info@ovt.com Website: http://www.ovt.com The windowing feature of the OV6645 OV6645 image sensors allows user-definable window sizing as required by the application (See Figure 4). Window size setting (in pixels) ranges from 2 x 2 to 356 x 292, and can be positioned anywhere inside the 356 x 292 boundary. Note that modifying window size and/or position does not change frame or data rate. The OV6645 OV6645 imager alters the assertion of the HREF signal to be consistent with the programmed horizontal and vertical region. The default output window is 352 x 288. column start column end HREF row The YCrCb/RGB data signal from the analog processing section is fed to two on-chip 8-bit analog-to-digital (A/D) converters: one for the Y/RG channel and one shared by the CrCb/BG channels. The converted data stream is further conditioned in the digital formatter. The processed signal is delivered to the digital video port through the video multiplexer which routes the user-selected 8-, or 4-bit video data to the correct output pins. Windowing column row start Y = 0.59G + 0.31R + 0.11B U=R­Y V=B­Y Where R,G,B are the equivalent color components in each pixel. The OV6645 OV6645 image sensor also provides control over the White Balance ratio for increasing/decreasing the image field Red/Blue component ratio. The sensor provides a default setting that may be sufficient for many applications. HREF The image is captured by the 356 x 292 pixel image array and routed to the analog processing section where the majority of signal processing occurs. This block contains the circuitry that performs color separation, color correction, automatic gain control (AGC), gamma correction, color balance, black level calibration, "knee" smoothing, aperture correction, controls for picture luminance and chrominance, and hue control for color. The analog video signals are based on the following formula: Additional on-chip functions include: · AGC that provides a gain boost of up to 24dB · White balance control that enables setting of proper color temperature and can be programmed for automatic or manual operation. · Separate saturation, brightness, hue, and sharpness adjustments allow for further fine-tuning of the picture quality and characteristics. Display Window row end Overview Sensor Array Bondary Figure 4. Windowing QCIF Format A QCIF mode is available for applications where higher resolution image capture is not required. Only half of the pixel rate is required when programmed in this mode. Default resolution is 176 x 144 pixels and can be programmed for other resolutions. Refer to Table 10. QCIF Digital Output Format (YUV beginning of line) Video Output The video output port of the OV6645 OV6645 image sensors provides a number of output format/standard options to suit many different application requirements. Version 4.6, July 27, 2001 Page 8 Advanced Information Preliminary OV6645 OV6645 OV6645 OV6645 SINGLE-CHIP CMOS CIF COLOR DIGITAL CAMERA Table 6. Digital Output Format indicates the output formats available. These formats are user-programmable through the SCCB interface. The OV6645 OV6645 imager supports ITU-656 ITU-656 output formats in the following configurations: 8-bit data mode · (In this mode, video information is output in Cb Y Cr Y order using the one port only and running at twice the pixel rate. See Table 7. 4:2:2 8-bit Format below) 4-bit nibble mode · (In the nibble mode, video output data appears at bits Y4-Y7. The clock rate for the output runs at twice the normal output speed when in B/W mode, and 4 times the normal pixel clock.) · 704 x 288 format (When programmed in this mode, the pixel clock is doubled and the video output sequence is Y0Y0Y1Y1 ··· and U0U0V0V0 ···. See Figure 5. Pixel Data Bus (YUV Output) below.) The OV6645 OV6645 imager provides VSYNC, HREF, PCLK, as standard output video timing signals. The OV6645 OV6645 imager can also be programmed to provide RGB data 8-bit, and 4-bit format. The output sequence is matched to the OV6645 OV6645 color filter pattern (See Figure 6. Pixel Data Bus (RGB Output). The output sequence is B G R G. In RGB data ITU-656 ITU-656 modes, the OV6645 OV6645 imager asserts SAV (Start of Active Video) and EAV (End of Active Video) to indicate the beginning and the ending of HREF window. As a result, SAV and EAV change with the active pixel window. The 8-bit RGB data is also accessible without SAV and EAV information. Another useful format is RGB one line RAW data format. It output data one line with each horizontal HREF, in the even line, the sequence is BGBG and odd line is GRGR, it exactly matches the Bayer pattern color filter. The OV6645 OV6645 imager offers flexibility in YUV output format. The device may be programmed as standard YUV 4:2:2. The device may also be configured to "swap" the U V sequence. When swapped, the 8-bit configuration becomes: · V Y U Y···. The third format available in the 8-bit configuration is the Y/UV sequence swap: · Y U Y V···. The MSB and LSB of Y/UV or RGB output can be reversed. Y7 is MSB and Y0 is LSB in the default setting. Y7 becomes LSB and Y0 becomes MSB in the reverse order configuration. Y2-Y6 are also reversed appropriately. OmniVision Technologies, Inc. 930 Thompson Place Sunnyvale, CA 94085 U.S.A. Tel: (408) 733-3030 Fax: (408) 733-3061 e-mail: info@ovt.com Website: http://www.ovt.com Table 6. Digital Output Format Resolution Pixel Clock YUV 8-bit ITU-656 ITU-656 Nibble 8-bit RGB 1 Y/UV swap ITU-656 ITU-656 Single-line 3 YUV 4 RGB 8-bit 8-bit 2 U/V swap Single Line MSB/LSB swap 352 x 288 Y Y Y Y 704 x 288 Y Y Y Y 176 x 144 Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Note: ("Y" indicates mode/combination is supported by OV6645 OV6645) Output is 8-bit in RGB ITU-656 ITU-656 format. SAV and EAV are inserted at the beginning and ending of HREF, which synchronize the acquisition of VSYNC and HSYNC. 8-bit data bus configuration (without VSYNC and CHSYNC) can provide timing and data in this format. Y/UV swap is valid in 8-bit format only. Y channel output sequence is Y U Y V ··· U/V swap means neighbor row B R output sequence swaps in RGB format. Refer to RGB raw data output format for further details. Table 7. 4:2:2 8-bit Format Data Bus Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 Y Frame UV Frame Pixel Byte Sequence U7 U6 U5 U4 U3 U2 U1 U0 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 V7 V6 V5 V4 V3 V2 V1 V0 0 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 1 01 U7 U6 U5 U4 U3 U2 U1 U0 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 2 V7 V6 V5 V4 V3 V2 V1 V0 3 23 Version 4.6, July 27, 2001 Page 9 Advanced Information Preliminary OV6645 OV6645 OV6645 OV6645 SINGLE-CHIP CMOS CIF COLOR DIGITAL CAMERA TCLK PCLK THD TSU HREF Y[7:0] 10 80 10 U Y V Y 80 10 Repeat for all data bytes Pixel Data 8-bit Timing (PCLK rising edge latches data bus) Note: TCLK is pixel clock period.TCLK=56ns for 8-bit output if the system clock is 17.73MHz. TSU is the setup time of HREF. The maximum is 15ns. THD is the hold time of HREF. The maximum is 15ns. Figure 5. Pixel Data Bus (YUV Output) TCLK PCLK THD TSU HREF Y[7:0] 10 10 10 B G R G 10 10 Repeat for all data bytes Pixel Data 8-bit Timing (PCLK rising edge latches data bus) Note: TCLK is pixel clock period. TCLK=112ns for 1-line mode output and TCLK=56ns for 8-bit output if the system clock is 17.73MHz. TSU is the setup time of HREF. The maximum is 15ns. THD is the hold time of HREF. The maximum is 15ns. Figure 6. Pixel Data Bus (RGB Output) OmniVision Technologies, Inc. 930 Thompson Place Sunnyvale, CA 94085 U.S.A. Tel: (408) 733-3030 Fax: (408) 733-3061 e-mail: info@ovt.com Website: http://www.ovt.com Version 4.6, July 27, 2001 Page 10 Advanced Information Preliminary OV6645 OV6645 OV6645 OV6645 SINGLE-CHIP CMOS CIF COLOR DIGITAL CAMERA The default U/UV channel output port relation before MSB/LSB swap: Table 8. Default Output Sequence Output port Internal output data MSB Y7 Y7 Y6 Y6 Y5 Y5 Y4 Y4 Y3 Y3 Y1 Y1 LSB Y0 Y0 Y1 Y6 Y2 Y2 LSB Y0 Y7 The relation after MSB/LSB swap changes to: Table 9. Swapped MSB/LSB Output Sequence Output port Internal output data MSB Y7 Y0 Y6 Y1 Y5 Y2 Y4 Y3 Y3 Y4 Y2 Y5 Table 10. QCIF Digital Output Format (YUV beginning of line) Pixel # 1 2 3 4 5 6 7 8 Y Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 UV U0, V0 U1, V1 U2, V2 U3, V3 U4, V4 U5, V5 U6, V6 U7, V7 - Y channel output U2Y2V3 Y3U6 Y6V7 Y7 U10Y10 U10Y10 V11Y11 V11Y11 ··· - Half (176 pixels) data are outputted every line and only half line data (every other line, total 144 lines) in one frame. Table 11. QCIF Digital Output Format (RGB raw data beginning of line) Pixel # Line 1 Line 2 1 B0 G0 2 G1 R1 3 B2 G2 4 G3 R3 5 B4 G4 6 G5 R5 7 B6 G6 8 G7 R7 Default RGB two line output mode: ­ Y channel outputB0G1 G0 R1B4G5 G4 R5 B8G9G8 R9 ··· ­ Every line outputs half data (176 pixels) and all lines (144 lines) data in one frame will be output. RGB Raw data one line output mode: - Y channel output B0 G1 B4 G5 B8 G9 ··· at even lines and G0R1G4R5G8R9··· at odd lines - Every other 2 lines output (1,2,5,6,9,10···) OV6645 OV6645 provides raw data format. The following format is defined. The format is based on Bayer pattern color filter format. Table 12. RGB Raw Data Format R\C 1 2 3 4 1 B1,1 G2,1 B3,1 G4,1 2 G1,2 R2,2 G3,2 R4,2 3 B1,3 G2,3 B3,3 G4,3 4 G1,4 R2,4 G3,4 R4,4 289 290 291 292 B289,1 G290,1 B291,1 G292,1 G289,2 R290,2 G291,2 R292,2 B289,3 G290,3 B291,3 G292,3 G289,4 R290,4 G291,4 R292,4 OmniVision Technologies, Inc. 930 Thompson Place Sunnyvale, CA 94085 U.S.A. Tel: (408) 733-3030 Fax: (408) 733-3061 e-mail: info@ovt.com Website: http://www.ovt.com ··· 353 B1,353 G2,353 B3,353 G4,353 354 G1,354 R2,354 G3,354 R4,354 355 B1,355 G2,355 B3,355 G4,355 356 G1,356 R2,356 G3,356 R4,356 B289,353 G290,353 B291,353 G292,353 G289,354 R290,354 G291,354 R292,354 B289,355 G290,355 B291,355 G292,355 G289,356 R290,356 G291,356 R292,356 Version 4.6, July 27, 2001 Page 11 Advanced Information Preliminary OV6645 OV6645 OV6645 OV6645 SINGLE-CHIP CMOS CIF COLOR DIGITAL CAMERA Notes: One line mode: - 1st HREF Y channel output B11 G12 B13 G14 ··· - 2nd HREF Y channel output G21 R22 G23 R24 ··· 8-bit Format (Total 292 HREFs): - 1st HREF Y channel output unstable data. - 2nd HREF Y channel output B11 G21 R22 G12 ··· - 3rd HREF Y channel output B31 G21 R22 G32 ··· - PCLK timing is doubled and PCLK rising edge latch data bus. UV channel tri-state. Every line data output twice. 4-bit Nibble Mode Output Format: - Uses higher 4 bits of Y port (Y[7:4]) as output port. - Supports YCrCb/RGB data,ITU-656 ITU-656 timing, Color/B&W. - Output sequence: High order 4 bits followed by lower order 4 bits Y0H Y0L Y1H Y1L ··· U0H U0L V0H V0L ··· For B/W or one-line RGB raw data, the output data clock speed is doubled. In color mode, sensor must be set to 8-bit mode, and the nibble timing, clock divided by 2. Output sequence: U0H U0L Y0H Y0L V0H V0L Y1H Y1L ··· Table 13. CIF Digital Output Format (RGB raw data beginning of line) Pixel # Line 1 Line 2 1 B0 G0 2 G1 R1 3 B2 G2 4 G3 R3 5 B4 G4 6 G5 R5 7 B6 G6 8 G7 R7 Default RGB two line output mode: ­ Y channel outputB0G1 G0 R1B4G5 G4 R5 B8G9G8 R9 ··· ­ Every line output half data (176 pixels) and all lines (144 lines) data in one frame will be output. RGB Raw data one line output mode: - Y channel output B0 G1 B4 G5 B8 G9 ··· at even lines and G0R1G4R5G8R9··· at odd lines - Every other 2 lines output (1,2,5,6,9,10···) Reset OV6645 OV6645 includes a RESET pin (pin 13) that forces a complete hardware reset when it is pulled high (VCC). OV6645 OV6645 clears all registers and resets to their default values when a hardware reset occurs. Reset can also be initiated through the SCCB interface. Power-down Mode Two methods are available to place OV6645 OV6645 into power-down mode: hardware power-down and SCCB software power-down. All internal register settings remain unchanged when OV6645 OV6645 is in the power-down mode. To initiate hardware power-down, the PWDN pin (pin 4) must be tied to high (+3.3VDC). When this occurs, OV6645 OV6645 internal device clock is halted and all internal counters are reset. The current draw is less than 10µA in this standby mode. Executing a software power-down through the SCCB interface suspends internal circuit activity, but does not halt the device OmniVision Technologies, Inc. 930 Thompson Place Sunnyvale, CA 94085 U.S.A. Tel: (408) 733-3030 Fax: (408) 733-3061 e-mail: info@ovt.com Website: http://www.ovt.com clock. The current requirements drop to less than 1mA in this mode. Configure OV6645 OV6645 Two methods are provided to configure OV6645 OV6645 for specific application requirements. At power-up, OV6645 OV6645 reads the status of certain pins to determine what, if any, power up pin programming default settings are requested. Once the reading of the external pins' status is completed, the device configures its internal registers according to the specified pins. Not all device functions are available for configuration through external pins. Power-up pin programming occurs in 1024 system clock-cycles from the time power is applied to the chip. A more flexible and comprehensive method to configure OV6645 OV6645 is to use its on-chip SCCB register programming capability. The SCCB interface provides access to all the programmable internal registers. Version 4.6, July 27, 2001 Page 12 OV6645 OV6645 SINGLE IC CMOS CIF DIGITAL CAMERAS Register Set The table below provides a list and description of available SCCB registers contained in the OV6645 OV6645 image sensor. Table 14. SCCB Registers Subaddress (hex) 00 Register Default (hex) Read/ Write GAIN 00 RW 01 BLUE 80 RW 02 RED 80 RW 03 SAT 80 RW 04 HUE 10 RW 05 ARL A0 RW 06 BRT 80 RW 07 SHP C6 RW 08 OFC 00 RW 09 CPP 08 RW 0A 0B 0C PID VER ABLU 66 40 20 R R RW Descriptions AGC gain control GC[7:6] ­ Unimplemented. GC[5:0] ­ The current gain setting. This register is updated automatically if AGC is enabled. The internal controller stores the optimal gain value in this register. The current value is stored in this register if AGC is not enabled. Blue gain control BLU[7:0] ­ blue channel gain balance value. "FFh" is highest and "00h" is lowest. This register is updated automatically if AWB is enabled. Red gain control RED[7:0] ­ red channel balance value. "FFh" is highest and "00h" is lowest. This register is updated automatically if AWB is enabled. Color saturation control SAT[7:4] ­ Saturation adjustment. "F8h" is highest and "00h" is lowest. SAT[3:2] ­ YUV/YCrCB selection: "00" U = u, V = v "01" U = 0.938u, V = 0.838v "10" U = 0.563u, V = 0.714v "11" U = 0.5u, V = 0.877v SAT[1:0] ­ ­ Y channel delay selection: 0 ~ 3tp Color hue control HUE[7:6] ­ UV delay selection. "00" ­ no delay. "01" ­ 2tp delay with 3 points average. "10" ­ 4tp delay. "11" same as "01" . HUE[5] ­ Enable smart color HUE[4:0] ­ HUE control, range -30°~30° AEC/AGC reference level ARL[7:5] ­ Voltage reference selection (Higher voltage = brighter final stable image) "000" = Lowest reference level "111" = Highest reference level ARL[4:0] ­ Reserved Brightness control BRT[7:0] ­ Brightness adjustment. "FFh" is highest and "00h" is lowest. Sharpness control SHP[7:4] ­ Coring adjustment. Range: 0~80mV with step 5mV. SHP[3:0] ­ Strength adjustment. Range: 0~8× with step 0.5×. Dark current compensation OFC[7] ­ sign bit of offset. "0" positive offset and "1" negative offset. OFC[6:0] ­ add an offset before AGC to compensate the dark current. Color processing parameter control CPP[7:5] ­ reserved CPP[4] ­ 1" aperture correction enable. Correction strength and threshold value will be decided by SHP[7:0]. CPP[4:0] ­ reserved Product ID number read only Product version number, read only White balance background: Blue channel ABLU[7:6] ­ reserved ABLU[5] ­ "0" decrease background blue component, "1" increase background OmniVision Technologies, Inc. 930 Thompson Place Sunnyvale, CA 94085 U.S.A. Tel: (408) 733-3030 Fax: (408) 733-3061 e-mail: info@ovt.com Website: http://www.ovt.com Version 4.6, July 27, 2001 Page 13 OV6645 OV6645 Subaddress (hex) SINGLE IC CMOS CIF DIGITAL CAMERAS Register Default (hex) Read/ Write 0D ARED 20 RW 0E COMR 0D RW 0F COMS A8 RW 10 AEC 9A RW 11 CLKRC 00 RW 12 COMA 24 RW 13 COMB 01 RW 14 COMC 00 RW Descriptions blue component ABLU[4:0] - White balance blue ratio adjustment White balance background: Red channel ARED[7:6] ­ rsvd ARED[5] ­ "0" decrease background red component, "1" increase background red component ARED[4:0] - White balance red ratio adjustment Common control R COMR[7] ­ Analog signal 1.5x gain control bit. "1" - Additional 1.5x gain, "0" normal. COMR[6:4] ­ Reserved. COMR[3:2] ­ Red channel pre-amplifier gain. 1~1.6x COMR[1:0] ­ Blue channel pre-amplifier gain 1~1.6x Common control S COMS[7:6] ­ Reserved COMS[5] ­ Luminance gamma function on/off COMS[4] ­ Bypass RGB matrix function COMS[3] ­ Enable Analog luminance output. COMS[2:0] ­ Reserved. Automatic exposure control AEC[7:0] - Set exposure time TEX = 2 × TLINE × AEC[7:0] Clock rate control CLKRC[7:6] ­ Sync output polarity selection "00" ­ HSYNC=Neg, CHSYNC=Neg, VSYNC=Pos "01" ­ HSYNC=Neg, CHSYNC=Neg, VSYNC=Neg "10" ­ HSYNC=Pos, CHSYNC=Neg, VSYNC=Pos "11" ­ HSYNC=Pos, CHSYNC=Pos, VSYNC=Pos CLKRC[5:0] ­ Clock pre-scaler CLK = (MAIN_CLOCK / (CLKRC[5:0] + 1) × 2) / n Where n=1 if register [3E], COMO is set to "1" and n=2 otherwise. Common control A COMA[7] ­ SRST, "1" initiates soft reset. All registers are set to default values and chip is reset to known state and resumes normal operation. This bit is automatically cleared after reset. COMA[6] ­ MIRR, "1" selects mirror image COMA[5] ­ AGCEN, "1" enables AGC, COMA[4] ­ Digital output format, "1" selects 8-bit: Y U Y V Y U Y V. "0" selects 8-bit UYVYUYVY COMA[3] ­ Select video data output: "1" - select RGB, "0" - select YCrCb COMA[2] ­ Auto white balance "1" - Enable AWB, "0" - Disable AWB COMA[1] ­ Color bar test pattern: "1" - Enable color bar test pattern COMA[0] ­ reserved Common control B COMB[7] ­ Enable TV timing. At this mode, analog luminance output can drove TV. COMB[6] ­ Enable nibble mode. COMB[5] ­ Reserved. COMB[4] ­ "1" - enable digital output in ITU-656 ITU-656 format COMB[3] ­ CHSYNC output. "1" - horizontal sync, "0" - composite sync COMB[2] ­ "1" ­ Tri-state Y and UV busses. "0" - enable both busses COMB[1] ­ Reserved. COMB[0] ­ "1" - Enable auto adjust mode. Common control C COMC[7] ­ reserved OmniVision Technologies, Inc. 930 Thompson Place Sunnyvale, CA 94085 U.S.A. Tel: (408) 733-3030 Fax: (408) 733-3061 e-mail: info@ovt.com Website: http://www.ovt.com Version 4.6, July 27, 2001 Page 14 OV6645 OV6645 Subaddress (hex) SINGLE IC CMOS CIF DIGITAL CAMERAS Register Default (hex) Read/ Write 15 COMD 01 RW 16 FSD 03 RW 17 HREFST 38 RW 18 HREFEND EA RW Descriptions COMC[6] ­ "1" Enable one frame drop when AEC change to keep data valid when Banding filter mode enable. COMC[5] ­ QCIF digital output format selection. 1 - 176x144; 0 - 352x288. COMC[4] ­ Field/Frame vertical sync output in VSYNC port selection: 1 - frame sync, only ODD field vertical sync; 0 - field vertical sync, effect in Interlaced mode COMC[3] ­ HREF polarity selection: 0 - HREF positive effective, 1 - HREF negative. COMC[2] ­ gamma selection: 1 - RGB Gamma on ; 0 - RGB gamma is 1. COMC[1:0] ­ Select the maximum AGC. "00" maximum gain=6dB, step 1/16 "01" maximum gain=12dB, step 1/16 "10" maximum gain=6dB, step 1/16 "11" maximum gain=18dB, step 1/8reserved Common Control D COMD[7] ­ Optical black output enable. "1" HREF has extra line at the beginning of the frame to output black signal. Effective only COMD[5] high COMD[6] ­ PCLK polarity selection. "0" - OV6645 OV6645 output data at PCLK falling edge and data bus will be stable at PCLK rising edge; "1" - rising edge output data and stable at PCLK falling edge. This bit is disable and should use PCLK rising edge latch data bus in ITU-656 ITU-656 format (COMB[4]=1). COMD[5] ­ Enable optical black function COMD[4] ­ Enable BLC with optical black line COMD[3:1] ­ Reserved. COMD[0] ­ U V digital output sequence exchange control. 1 - U Y V Y ··· for 8bit; 0 -V Y U Y ··· for 8-bit. Field slot division FSD[7:2] ­ Field interval selection. It has functional in EVEN and ODD mode defined by FSD[1:0]. It is disabled in OFF and FRAME mode. The purpose of FSD[7:2] is to divide the video signal into programmed number of time slots, and allows HREF to be active only one field in every FSD[7:2] fields. It does not affect the video data or pixel rate. FSD[7:2] disables digital data output, there is only black reference level at the output. FSD[7:2]=1 outputs every field. FSD[7:2]=2 outputs one field and disables one field, etc. FSD[1:0] ­ field mode selection. Each frame consists of two fields: Odd and Even, FSD[1:0] define the assertion of HREF in relation to the two fields. "00" ­ OFF mode; HREF is not asserted in both fields, one exception is the single frame transfer operation (see the description for the register 13) "01" ­ ODD mode; HREF is asserted in odd field only. "10" ­ EVEN mode; HREF is asserted in even field only. "11" ­ FRAME mode; HREF is asserted in both odd field and even field. FSD[7:2] disabled. Horizontal HREF start HS[7:0] ­ selects the starting point of HREF window, each LSB represents two pixels for CIF resolution mode, one pixels for QCIF resolution mode, this value is set based on an internal column counter, the default value corresponds to 352 horizontal window. Maximum window size is 356. See window description below. HS[7:0] programmable range is [38] - [EB], and should less than HE[7:0]. HS[7:0] should be programmable to value larger than or equal to [38]. Value larger than [EC] is invalid. See window description below. Horizontal HREF end HE[7:0] ­ selects the ending point of HREF window, each LSB represents two pixels for full resolution and one pixels for QCIF resolution, this value is set based on an internal column counter, the default value corresponds to the last available pixel. The HE[7:0] programmable range is [39] - [EC]. HE[7:0] OmniVision Technologies, Inc. 930 Thompson Place Sunnyvale, CA 94085 U.S.A. Tel: (408) 733-3030 Fax: (408) 733-3061 e-mail: info@ovt.com Website: http://www.ovt.com Version 4.6, July 27, 2001 Page 15 OV6645 OV6645 Subaddress (hex) SINGLE IC CMOS CIF DIGITAL CAMERAS Register Default (hex) Read/ Write 19 VSTRT 03 RW 1A VEND 92 RW 1B PSHFT 00 RW 1C MIDH 7F R 1D MIDL A2 R 1E HSST 0F RW 1F HSEND 3C RW 20 COME 00 RW 21 YOFF 80 RW 22 UOFF 80 RW Descriptions should be larger than HS[7:0] and less than or equal to [EC]. Value larger than [EC] is invalid. See window description below. Vertical line start VS[7:0] ­ selects the starting row of vertical window, in full resolution mode, each LSB represents 1 scan line in one frame. See window description below. Min. is [03], max. is [93] and should less than VE[7:0]. Vertical line end VE[7:0] ­ selects the ending row of vertical window, in full resolution mode, each LSB represents 1 scan line in one frame, see window description below. Min. is [04], max. is [94] and should larger than VS[7:0]. Pixel shift PS[7:0] ­ to provide a way to fine tune the output timing of the pixel data relative to that of HREF, it physically shifts the video data output time late in unit of pixel clock as shown in the figure below. This function is different from changing the size of the window as defined by HS[7:0] and HE[7:0] in registers 17 and 18. Higher than default number delay the pixel output relative to HREF. The highest number is "FF" and the maximum shift number is delay 256 pixels. Manufacture ID byte: High MIDH[7:0] ­ read only, always returns "7F" as manufacturer's ID no. Manufacture ID byte: Low MIDL[7:0] ­ read only, always returns "A2" as manufacturer's ID no. Horizontal sync start position HSST[7:0] ­ lower 8 bit of horizontal sync starting position, combined with register bit of COMI[4], total 9 bit control. range: [00] - [FF]. HSEND[8:0] must be less than HSST[8:0] Horizontal sync end position HEND[7:0] ­ lower 8 bit of horizontal sync ending position, combined with register bit of COMI[3], total 9 bit control. range: [00] - [FF]. HSEND[8:0] must be larger than HSST[8:0] Common control E COME[7] ­ HREF pixel number selection. "1" - HREF include 704 PCLK, every data output twice. COME[6] ­ AWB value in Reg and Reg can be updated by manual in auto mode. COME[5] ­ Central 1/4 image area rather whole image used to calculate AWB. "0" uses whole image area to calculate AWB. COME[4] ­ Digital output driver capability increase selection: "1" Double digital output driver current; "0" low output driver current status. Independent control with COME[0]. COME[3] ­ Enable system reset when write Reg. COME[2:1] ­ AWB fast/slow mode selection. "11" - AWB is the fastest mode, that is register [01] and [02] is changed every field. "10" AWB change every 4 fields. "00" AWB change every 16 fields, is the slowest mode. COME[0] ­ Digital output driver capability increase selection: "1" Double digital output driver current; "0" low output driver current status. Y channel offset adjustment YOFF[7] ­ Offset adjustment direction 0 - Add Y[6:0]; 1 -Subtract Y[6:0]. YOFF[6:0] ­Y channel digital output offset adjustment. Range: +127 ~ -127. If COMG[2]=0, this register will be updated by internal circuit. Write a value to this register through SCCB has no effect. COMG[2]=1, Y channel offset adjustment will use the stored value which can be changed through SCCB. This register has no effect to A/D output data if COMF[1]=0. If output RGB raw data, this register will adjust R/G/B data. U Channel offset adjustment UOFF[7] ­ Offset adjustment direction: 0 - Add U[6:0]; 1 - Subtract U[6:0]. OmniVision Technologies, Inc. 930 Thompson Place Sunnyvale, CA 94085 U.S.A. Tel: (408) 733-3030 Fax: (408) 733-3061 e-mail: info@ovt.com Website: http://www.ovt.com Version 4.6, July 27, 2001 Page 16 OV6645 OV6645 Subaddress (hex) SINGLE IC CMOS CIF DIGITAL CAMERAS Register Default (hex) Read/ Write 23 CLKC 04 RW 24 AEW 33 RW 25 AEB 97 RW 26 COMF B0 RW 27 COMG A0 RW Descriptions UOFF[6:0] ­ U channel digital output offset adjustment. Range: +128 ~ -128. If COMG[2]=0, this register will be updated by internal circuit. Write a value to this register through SCCB has no effect. COMG[2]=1, U channel offset adjustment will use the stored value which can be changed through SCCB. This register has no effect to A/D output data if COMF[1]=1. If output RGB raw data, this register will adjust R/G/B data. Oscillator circuit control CLKC[7:6] ­ Select different crystal circuit power level ("11" = minimum). CLKC[5] ­ Enable smart banding filter mode. It means banding filter limited exposure time will out of limited when light is too strong. CLKC[4] ­ AEC/AGC change mode selection CLKC[3] ­ AEC/AGC change mode selection CLKC[2] ­ AEC/AGC change fastest mode CLKC[1] ­ AEC/AGC change fast mode CLKC[0] ­ AEC/AGC change slowest mode Automatic exposure control: Bright pixel ratio adjustment AEW[7:0] ­ Used as calculate bright pixel ratio. OV6645 OV6645 AEC algorithm is count whole field bright pixel (its luminance level is higher than a fixed level) and black pixel (its luminance level is lower than a fixed level) number. When bright/black pixel ratio is same as the ratio defined by register [25] and [26], image stable. This register is used to define bright pixel ratio, default is 25%, each LSB represent step: 0.5% Change range is: [01] ~ [CA]; Increase AEW[7:0] will increase bright pixel ratio. For same light condition, the image brightness will increase if AEW[7:0] increase. Note: AEW[7:0] must combine with register [26] AEB[7:0]. The relation must be as follows: AEW[7:0] + AEB[7:0] > [CA]. Automatic Exposure Control: Black pixel ratio adjustment AEB[7:0] ­ used as calculate black pixel ratio. OV6645 OV6645 AEC algorithm is count whole field/ frame bright pixel (its luminance level is higher than a fixed level) and black pixel (its luminance level is lower than a fixed level) number. When bright/black pixel ratio is same as the ratio defined by register [25] and [26], image stable. This register is used to define black pixel ratio, default is 80%, each LSB represent step: 0.5%; Change range is: [01] ~ [CA]; Increase AEB[7:0] will increase black pixel ratio. For same light condition, the image brightness will decrease if AEB[7:0] increase. Note: AEB[7:0] must e combined with register [25] AEW[7:0]. The relation must be as follows: AEW[7:0] + AEB[7:0] > [CA]. Common control F COMF[7] ­ Input main clock divided by 2 or 4 selection. "1" - 2; "0" ­ 4 COMF[6] ­ Enable Minimum exposure time is 4 line. Default is 1 line COMF[5] ­ Reserved. COMF[4] ­ PCLK output timing selection. "1" - PCLK valid only when HREF is high; "0" - PCLK is free running. COMF[3] ­ UV offset difference. "1" use separate offsets for U and V; "0" use one offset for both U and V. COMF[2] ­ Digital data MSB/LSB swap. "1" LSBbit7, MSBbit0; "0" normal. COMF[1] ­ "1" digital offset adjustment enable. "0" disable. COMF[0] ­ "1" Output first 4 line black level before valid data output. HREF number will increase 4 relatively. "0" no black level output. Common control G COMG[7:5] ­ reserved COMG[4] ­ Soft chip power down enable, can be waked up by disable this bit COMG[3] ­ Tri-state all control signal output (VSYNC, HREF, PCLK). COMG[2] ­ "1" digital offset adjustment manually mode enable. Digital data will OmniVision Technologies, Inc. 930 Thompson Place Sunnyvale, CA 94085 U.S.A. Tel: (408) 733-3030 Fax: (408) 733-3061 e-mail: info@ovt.com Website: http://www.ovt.com Version 4.6, July 27, 2001 Page 17 OV6645 OV6645 Subaddress (hex) SINGLE IC CMOS CIF DIGITAL CAMERAS Register Default (hex) Read/ Write 28 COMH 01 RW 29 COMI 00 RW 2A COMJ 80 RW 2B FRARL 5E RW 2C 2D 2E Rsvd 2C Rsvd 2D VCOFF 88 B6 80 RW RW RW Descriptions be add/subtract a value defined by register [21] and [22], the contents are programmed through SCCB. "0" - digital data will be added/subtract a value defined by register [21] and [22], which are updated by internal circuit. COMG[1] ­ Digital output full range selection. OV6645 OV6645 default output data range is [10] - [F0]. The output range changes to [01] - [FE] with signal overshoot and undershoot level if COMG[1]=1. COMG[0] ­ reserved. Common control H COMH[7] ­ "1" selects one-line RGB raw data output format, "0" selects normal two-line RGB raw data output. COMH[6:5] ­ Reserved COMH[4] ­ Freeze AEC/AGC value, effective only at COMB[0]=1. "1" - register [00] and [10] will not be updated and hold latest value. "0" - AEC/AGC normal working status. COMH[3] ­ AGC disable. "1" - when COMB[0]=1 and COMA[5]=1, internal circuit will not update register [00], register [00] will kept latest updated value before COMH[3]=1. "0" - when COMB0=1 and COMA[5]=1, register [00] will be updated by internal algorithm. COMH[2:0] ­ Reserved. Common control I COMI[7] ­ AEC disable. "1" If COMB[0]=1, AEC stop and register [10] value will be held at last AEC value and not be updated by internal circuit. "0" - if COMB[0]=1, register [10] value will be updated by internal circuit COMI[6] ­ "1" select CHSYNC output from HREF port. "0" normal COMI[5] ­ reserved COMI[4] ­ Central 1/4 image area rather whole image used to calculate AEC/AGC. "0" use whole image area to calculate AEC/AGC. COMI[3] ­ Highest 1 bit of horizontal sync starting position, combined with register [1E] COMI[2] ­ Highest 1 bit of horizontal sync ending position, combined with register [1F] COMI[1:0] ­ Version flag. For version A, value is [00], these two bits are read only. Common control J OOMJ7] ­ Vertical sync only with valid data when "1", otherwise always output VSYNC. COMJ[6] ­ reserved COMJ[5] ­ Highest 1bit of frame rate adjust control byte. See explanation below. COMJ[4] ­ Tri-state Y port output when in power down mode. COMJ[3] ­ Y channel brightness adjustment enable. When COMF[2]=1 active. COMJ[2] ­ "1" update white balance update only if AGC/AEC is stable. "0" update white balance independent with AEC/AGC. COMJ[1] ­ Reserved. COMJ[0] ­ Banding filter on. Frame rate adjust low FRARL[7:0] ­ Lowest 8 bit of frame rate adjust control byte. Frame rate adjustment resolution is 0.21%. Control byte is 10 bit. Every LSB equal decrease frame rate 0.21%. Range is 0.21% - 109%. IF frame rate adjustment enable, COME[7] must set to "0". Reserved Reserved V channel offset adjustment VCOFF[7] ­ Offset adjustment direction: "0" = Add V[6:0]; "1" = Subtract V[6:0]. VCOFF[6:0] ­ V channel digital output offset adjustment. Range: +128 ~ -128. If COMG[2]=0, this register will be updated by internal circuit. Write to this OmniVision Technologies, Inc. 930 Thompson Place Sunnyvale, CA 94085 U.S.A. Tel: (408) 733-3030 Fax: (408) 733-3061 e-mail: info@ovt.com Website: http://www.ovt.com Version 4.6, July 27, 2001 Page 18 OV6645 OV6645 Subaddress (hex) SINGLE IC CMOS CIF DIGITAL CAMERAS Register Default (hex) Read/ Write 2F ­33 34 Rsvd 2F-33 2F-33 RGAM ×× 8F RW RW 35 YGAM 8F RW Descriptions register through SCCB has no effect. If COMG[2] =1, V channel offset adjustment will use the stored value which can be changed through SCCB. If COMF[1] =1, this register has no effect to digital output data. If output RGB raw data, this register will adjust R/G/B data. Reserved RGB gamma control RGAM[7:6] Gamma curve saturation level selection for luminance. RGAM[5:4] Gamma curve turning point selection for luminance. RGAM[3:0] Different gamma curve selection. Luminance gamma control YGAM[7:6] Gamma curve saturation level selection for luminance. YGAM[5:4] Gamma curve turning point selection for luminance. YGAM[3:0] Different gamma curve selection. OmniVision Technologies, Inc. 930 Thompson Place Sunnyvale, CA 94085 U.S.A. Tel: (408) 733-3030 Fax: (408) 733-3061 e-mail: info@ovt.com Website: http://www.ovt.com Version 4.6, July 27, 2001 Page 19 OV6645 OV6645 SINGLE IC CMOS CIF DIGITAL CAMERAS .250 + - .005 [P= .050 X 5] .040 + - .007 [23] .050 + - .005 24 PIN NO. 1 .085 + - .010 Bottom View PIN NO. 1 INDEX [24] .025 + - .003 ) 08 .0 ] (R [24X .076 + - .007 Top View .065 + - .007 .015 + - .002 .030 + - .003 .020 + - .002 Note: Die thickness=0.0275 .400 +.010 - .005 .320 ±.006 .270 ±.006 PIN NO. 1 24 PIN NO.1 INDEX .010* 45 CHAMFER (R .0 Ty 12) p. ) 09 .0 . (R Typ OmniVision Technologies, Inc. 930 Thompson Place Sunnyvale, CA 94085 U.S.A. Tel: (408) 733-3030 Fax: (408) 733-3061 e-mail: info@ovt.com Website: http://www.ovt.com Version 4.6, July 27, 2001 Page 20 OV6645 OV6645 SINGLE IC CMOS CIF DIGITAL CAMERAS Figure 7. OV6645 OV6645 Package Diagram Array Center (25µm, -50.7µm) 1 DIE Sensor Array Package Center (0, 0) Figure 8. OV6645 OV6645 Sensor array center location Note: Most optical systems invert and mirror the image so the chip is usually mounted on the board with pin 1 down. OmniVision Technologies, Inc. reserves the right to make changes without further notice to any product herein to improve reliability, function, or design. OmniVision Technologies, Inc. does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. No part of this publication may be copied or reproduced, in any form, without the prior written consent of OmniVision Technologies, Inc. OmniVision Technologies, Inc. 930 Thompson Place Sunnyvale, CA 94085 U.S.A. Tel: (408) 733-3030 Fax: (408) 733-3061 e-mail: info@ovt.com Website: http://www.ovt.com Version 4.6, July 27, 2001 Page 21