82C491/82C392/82C206 82C491/82C392 82C491 82C392 486WB 82C206 64-MB 16KX9 32KX8 - Datasheet Archive

 

(82C491/82C392/82C206) Preliminary 82C491/82C392 DATA BOOK Version 1.1 April 26, 1991 Disclaimer This specification is subject to

 

OPTi-486WB PC/AT Chipset (82C491/82C392/82C206 82C491/82C392/82C206) Preliminary 82C491/82C392 82C491/82C392 DATA BOOK Version 1.1 April 26, 1991 Disclaimer This specification is subject to change without notice. OPTi, Incorporated assumes no responsibility for any errors contained within. Copyright by OPTi, Inc. All rights reserved OPTI, Inc. 2525 Walsh Ave. Santa Clara, California 95051 Tel. (408) 980-8178 Fax (408) 980-8860 2 TABLE OF CONTENTS 1. OVERVIEW 1.1 Introduction 1.2 Features 1.3 System Block Diagram 2. 82C491 82C491 SYSTEM CONTROLLER (SYSC) 2.1 Reset Logic 2.2 System Clock Generation 2.3 Cache Subsystem 2.4 CPU Burst Mode Control 2.5 Local DRAM Control Subsystem 2.6 Shadow RAM 2.7 AT Bus State Machine 2.8 Bus Arbitration Logic 2.9 Refresh Logic 2.10 System BIOS ROM and I/O Ports 2.11 Turbo Switch 2.12 Flexible Multiplexed DRAM Address 3. 82C491 82C491 PIN DESCRIPTION 3.1 Clock and Reset 3.2 CPU Interface 3.3 NP Interface 3.4 Cache Control Interface 3.5 Local DRAM Interface 3.6 DBC Interface 3.7 Bus Arbitration 3.8 AT-Bus Interface 4. 82C491 82C491 REGISTER DESCRIPTION 5. 82C392 82C392 DATA BUFFER CONTROLLER (DBC) 5.1 Data Bus Conversion 5.2 Parity Generation/Detection Logic 5.3 Clock Generation and Reset Control 5.4 Numeric Processor Interface 6. 82C392 82C392 PIN DESCRIPTION 6.1 Clock and Reset Logic 6.2 Bus Interface 6.3 Bus Arbitration 6.4 SYSC Interface 6.5 Numeric Processor Interface 6.6 Miscellaneous Pins 7. 82C392 82C392 REGISTER DESCRIPTION 3 LIST OF FIGURES 1. 2. 3. 4. System Block Diagram SYSC Pin-out DBC Pin-out Mechanical Dimensions 4 1 486WB 486WB OVERVIEW (82C491/82C392/82C206 82C491/82C392/82C206 CHIPSET) 1.1 Introduction The OPTi 486WB 486WB is a three-chip solution offering optimal performance for high-end, 486-based AT systems. The OPTi 486WB 486WB is designed for systems running from 33 Mhz, to 40 Mhz, and up to 50 Mhz and combines three major functions: the 82C491 82C491 System Controller (SYSC), the 82C392 82C392 Data Buffer Controller (DBC), and the 82C206 82C206 Integrated Peripheral Controller (IPC). Refer to the data book supplied by your third-party source for information on the 82C206 82C206. 1.2 Features OPTi 486WB 486WB features include: o o o o o o o o o o o o o o o o o o o o 1X clock source, supporting systems running up to 50 Mhz two 160-pin CMOS Plastic Flat Package (PFP), and one 84-pin PLCC Copy-Back Direct-Mapped Cache with size of 64 KB, 128 KB, 256 KB and 512 KB up to 10% performance enhancement from write-through cache scheme supports 2,1,1,1 cache burst cycle as well as 3,1,1,1 cycle on-chip comparitor determines cache hit or miss up to 64-MB 64-MB of local high-speed, page-mode, DRAM memory space burst-line-fill during Cache-Read-Miss control of two non-cacheable regions shadow RAM support optional caching of shadowed Video BIOS hidden refresh slow refresh available for a laptop application. 8042 emulation for fast CPU-reset and gateA20 generation turbo/slow speed selection AT bus clock selectable from CLKIN/4 or CLKIN/6 0 or 1 wait state selectable for 16-bit AT bus cycle CAS# before RAS# refresh reduces power comsumption optional 0 or 1 wait state for Cache-Write-Hit WEITEK 4167 coprocessor support 5 1.3 SYSTEM BLOCK DIAGRAM Figure 1 is a block diagram of a 486WB-based system Figure 1. 486WB 486WB Based System Block Diagram 6 2 82C491 82C491 SYSTEM CONTROLLER (SYSC) 2.0 Features The SYSC is a 160-pin PFP (Plastic Flat Package) device. The SYSC integrates a write-backcache controller, local DRAM control, AT bus interface, and CPU interface. 82C491 82C491 features include: o o o o o o o o o o CPU reset control CPU internal cache control CPU burst mode control CPU interface control. integrated write-back cache controller with tag comparitor. page-mode DRAM controller burst line fill control logic two noncacheable address comparators decoupling refresh for local DRAM and AT-bus memory 2 DMA upper address latches 2.1 Reset Logic The SYSC handles two reset inputs, RST1# and RST2#, to generate the CPU reset signal, CPURST. RST1# is a "cold reset". output by the DBC when either PWRGD# (Powergood) goes low (from the power supply and indicating a low power condition) or the system reset button is pressed. RST2# is a "warm reset," asserted by a keyboard reset (CNTL + ALT + DEL simultaneously). Note that the keyboard reset is at first handled by either the keyboard controller (8042 or 8742 IC) or the DBC, and using the DBC may be advantageous, because it routes the reset faster to the SYSC. A software reset is also available. Programming bit 0 (from 0b to 1b) of Index Register 20h, then executing a "HALT" instruction causes the CPU to assert CPURST. 2.2 System Clock Generation The SYSC has two high frequency clock inputs, CLKI and CLK2I. CLK2I clocks the internal cache controller. CLKI, which is driven by a single-phase output from a crystal oscillator, clocks the CPU as well as the SYSC's internal state machine. The SYSC generates the AT bus clock, ATCLK, depending on the level of the BCLKS input. ATCLK is derived from either CLK2I/4 (BCLKS high) or CLK2I/6 (BCLKS low). An onboard, 2position jumper establishes the level of BCLKS. 7 2.3 Cache Subsystem The SYSC has a non-pipeline mode with a 16-byte line size to simplify design without increasing cost or degrading system performance. Note that a buffer is required between the cache and the CPU data bus. A tag comparitor is built inside the SYSC to improve system performance and reduce board real-estate. The comparitor asserts HIT# when the addressed location points to a current cache entry. If HIT# is negated or NCA# (Non-Cacheable Address) is asserted, the current cycle is a cache-miss; otherwise the cycle is a cache-hit. Descriptions of possible cache cycles follow. Cache-Read-Miss with the cache location's DIRTY bit negated. The cache controller does not need to update memory with the cache's current data, because that data is unmodified. The cache controller asserts TAGWE#, causing the tag RAMs to update with the new address, and asserts CAWE(3:0)#, causing cache memory to update with data from DRAM. Cache-Read-Miss with DIRTY asserted. The cache controller must update memory with data from the cache location that is going to be overwritten. The controller writes the 16-byte line from cache memory to the DRAM, then reads the new line from DRAM into cache memory. The controller asserts TAGWE# and CAWE(3:0). This cycle is called a two-way interleave cache read/write. Cache-Write-Hit. The cache controller does not need to update memory. The controller updates the tag RAMs and cache memory and sets the DIRTY bit. (DIRTY may already be set, but that does not affect this cycle.) Cache-Write-Miss. The cache controller bypasses the cache entirely and writes the line directly into DRAM. DIRTY is unchanged. The following table shows the cache sizes supported by the 82C491 82C491, with the corresponding tag RAM address bits, tag RAM size, cache RAM address bits, cache RAM size, and cacheable main memory size Cache Size (Kb) Tag Field Address/ Tag RAM size Cache RAM Address /Cache RAMs Cachable Main Memory(Mb) 64 A23 - A16 4KX9 A24 -A17 8KX9 A25 - A18 16KX9 16KX9 A25 - A19 32KX8 32KX8 A15 - A4 8 8KX8 A16 - A4 16 8KX8 A17 - A4 8 32KX8 32KX8 A18 - A4 16 32KX8 32KX8 16 Cache SRAM Tag SRAM DRAM* 20ns 12.5ns 80ns 80ns 128 256 512 Speed 33MHz 25ns 50MHz 20ns *DRAM at minimum wait state 8 32 64 64 2.4 CPU Burst Mode Control The use of a secondary cache guarantees that data is burst immediately into the CPU when a cacheable location is read, whether it is a read-hit or read-miss. BRDY# (Burst Ready) is asserted at the middle of the first T2 state when zero wait states are required and at the middle of the second T2 state when one wait state is required, except during a cache read miss; then, BRDY# is asserted after cache memory is updated. Once asserted, BRDY# stays high until BLST# (Burst Last) is detected. BRDY# is never active during DMA and MASTER cycles. 2.5 Local DRAM Control Subsystem The SYSC supports up to 4 banks of page-mode local memory. DRAM devices are either 256Kb,1-Mb or 4-Mb large. Total memory is between 1 Mb and 64 Mb. The following table illustrates the configurations supported. 9 Bank 0 Bank 1 Bank 2 Bank 3 Total 256K 256K 1M 256K 256K 1M 256K 256K 1M 256K 1M 4M 1M 4M 1M 1M 4M 1M 1M 4M 1M 1M 4M 4M 4M 1M 4M 4M 4M 4M 1M 4M 4M x 256K x 1M 256K 1M 1M 256K 1M 1M 1M x 4M 1M 1M 4M 1M 1M 4M 1M 4M 4M 1M 4M 1M 4M 1M 4M 4M 4M 1M 4M 4M x x x x 1M x 1M 1M 1M 1M 1M x x x 4M 1M 1M 1M 1M 1M x 4M 4M 1M 4M 4M 4M 1M 4M 4M 4M 4M 4M x x x x x x x 1M x 1M 1M x x X x x x 4M 1M 1M x x x x 4M 1M 1M 1M x 4M 4M 1M 4M 1M 2M 4M 5M 6M 8M 9M 10M 12M 13M 16M 16M 20M 20M 24M 24M 24M 28M 28M 28M 32M 36M 36M 36M 40M 40M 40M 40M 48M 52M 52M 52M 64M 10 2.6 Shadow RAM Because DRAM accesses are much faster than EPROM accesses, the SYSC provides shadow RAM capability to enhance system performance. BIOS is copied, then writeprotected, into a dedicated area in DRAM. Accesses to BIOS address space are redirected to the corresponding DRAM location. Shadow RAM addresses range from C0000h to FFFFFh. C0000h to EFFFFh are enabled in 16-Kb memory chucks. F0000h-FFFFFh, the location of system BIOS shadowing, are enabled in 64-Kb chucks. When shadowing is disabled (bit 7 of Index Register 22h is reset), BIOS is read from EPROM and (if applicable) written to DRAM. 2.7 AT Bus State Machine The AT state machine monitors status signals, M16#, IO16#, Chrdy and Nows# from the AT bus. The machine outputs AT bus signals, including command, bus conversion, and control. The AT bus state machine also routes data and address when an AT bus master or DMA controller accesses memory. 2.8 Bus Arbitration Logic 82C391 82C391 arbitration is based on first-come, first serve basis. The SYSC arbitrates between memory requests from the CPU, DMA controller, AT bus masters, and refresh logic. During DMA and AT bus master write cycles, the SYSC asserts HOLD to the CPU, then the CPU relinquishes bus control, returning HLDA. The SYSC asserts AHOLD and BOFF# during an AT memory code read cycle. During refresh (and when hidden refresh is enabled), HOLD remains negated, and the CPU continues its current program execution as long as it achieves cache hits. 2.9 Refresh Logic The SYSC supports both normal refresh and hidden refresh. The average refresh period (time between refresh cycles) is either 16us or 64us, the latter when slow refresh is enabled. (Slowrefresh DRAMs must be used with slow refresh.) Hidden refresh separates refreshing of ATbus memory and local DRAM; the AT-bus controller arbitrates between CPU accesses to the AT bus, DMA, and AT refresh, while the DRAM controller arbitrates between CPU DRAM accesses and DRAM refresh cycles. Note that the DBC generates the refresh address during AT-bus refresh cycles. 2.10 System BIOS ROM and I/O Ports The SYSC supports both 8-bit and 16-bit EPROM cycles. If the system BIOS is eight bits wide, the system BIOS EPROM resides on the XD bus. If the system BIOS is 16 bits wide, the EPROM resides on the SD bus, and ROMCS# is connected to M16# through a open collector; ROMCS# informs the SYSC that the current system BIOS is 16 bits wide. The XDbus data buffers always drive toward the XD bus, except during an I/O read cycle at an address smaller than F0h (byte-wide I/O) or during an 8-bit BIOS ROM cycle. 11 2.11 Turbo Switch The system is operating at the full speed if the TURBO pin is asserted high. When TURBO is low, the SYSC holds the CPU during two thirds of the cycle, decreasing CPU performance by a factor of three. OUT1, which is connected to the TURBO pin and input to the 82C391 82C391, tells the SYSC whether or not to hold the CPU. 2.12 Flexible Multiplexed DRAM Address The following table describes how the DRAM address lines are multiplexed when different memory devices types are used. Address to MA bus Mapping Mem addr MA0 MA1 MA2 MA3 MA4 MA5 MA6 MA7 MA8 MA9 MA10 256K Col Row Col A2 A3 A4 A5 A6 A7 A8 A9 A10 X X A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 X A12 A13 A14 A15 A16 A17 A18 A19 A11 X X 12 1M Row A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 X Col A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 4M Row A23 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 3 SYSC SIGNALS DESCRIPTIONS 3.1 Clock and Reset Name Type Pin No Description CLK2I I 82 CLKI I 79 BCLKS I 142 ATCLK O 159 RST1# I 134 RST2# I 135 CPURST O 25 Crystal oscillator Input which has a frequency equal to twice the rated CPU clock. This signal is used for secondary cache early write option only. Clk2 input for SYSC internal state machine. Single phase. ATCLK Selection. Low ATCLK = CLKI/6. High ATCLK = CLKI/4. ATCLK to AT bus; it is a free running clock. It could be either CLKI/4 or CLKI/6. Cold reset input either from Powergood signal of power supply or from Reset Switch CPU Reset input from Keyboard Controller or from DBC's ERST2# pin. Reset for 486 processor. Name CA(31:24) Type B Pin No 88-83,68-67 CA(23:21) CA20 I B 66-64 63 CA(19:17) CA(16:8) I B 62-60 59-51 CA(7:2) BE(3:0) I B 49-44 31-34 3.2 CPU Interface Description CPU Address Lines 31-24. They are input pins during CPU cycle, and forced to be low for DMA and MASTER cycles which allow 486 invalidating the internal TAGs. Note that the CPU isn't on HOLD when AT refresh cycle undergoing. CPU Address Lines 23-21; Input only. CPU Address Lines 20; it's an input pin during CPU and DMA cycles, and becomes an output pin during MASTER cycle. CPU Address Lines 19-17; Input only. CPU Address Lines 16-8. These are input pins during CPU and MASTER cycles. CA(16:9) are output pins for DMA address A16-A9 A16-A9 by latching XD(7:0) during 16-bit DMA cycle and CA(15:8) are DMA address A15-A8 A15-A8 for 8-bit DMA cycle. CPU Address Lines 7-2; Input only. Byte Enable 3-0. These are inputs during CPU cycle and are outputs during DMA and MASTER cycle, derived from SA0, SA1 and SBHE# from AT bus. 13 Name Type Pin No Description ADS# I 43 WR# I 36 DC# I 35 MIO# I 37 LDEV# I 18 BLST# I 42 RDY# O 38 RDYI# I 19 BRDY# O 39 KEN# O 29 BOFF# O 27 TURBO I 140 TLB# O 110 Status input from CPU. This active low signal indicates the CPU is starting a new cycle. CPU Write or Read Cycle Status. It indicates a write cycle if high and read cycle if low. CPU Data or Code Cycle Status. It indicates data transfer operations when high, or control operations(code fetch, halt, etc.) when low. CPU Memory or I/O Cycle Status. It indicates a memory cycle if high, and I/O cycle if low. Indication of CPU local Bus device Cycle, i.e. Weitek 4167 coprocessor. This signal is sampled at the end of 1st T2. 486 burst last cycle indication, SYSC terminates the burst cycle as long as the BLST# sampled low at the end of each T2 when BRDY# is active. Ready output for CPU to terminate the current cycle.This pin is not a tri-state output. Local Device Ready Input, It will be synchronized by SYSC before sending to CPU. Burst ready output for CPU to sample the read data during burst cycles. This pin is a tri-state output. Cachable or non-cachable status for the internal cache of CPU. This signal is low normally, and is brought high at the end of T1. The SYSC will assert KEN# again if it is a cachable cycle. Backoff output for CPU. This output forces the 80486 microprocessor to float its bus in the next clock. Turbo Mode Selection. I f Turbo pin is tied to low; the system runs at full speed, otherwise, the SYSC will hold two third of the CPU time. 486 TLB Problem Fix. 14 3.3 Numeric Processor Interface Name Type Pin No Description NPERR# I 24 IGERR# O 21 Numeric Processor Error Indication. Used to generate IGERR# for CPU. This is a normally high signal and will become low as soon as the NPERR# is asserted. An IO write to either port F0h or F1h, or CPU reset will force this signal back to high. 3.4 External Cache Control Name Type Pin No Descriptions TAG(7:0) DRTY B B 77-71,69 78 TAGWE# O 93 DTYWE# CAOE# CAWE(3:0)# O O O 94 89 105-102 BECS# O 91 BOCS# O 92 BEOE# O 98 BOOE# O 97 BDIR# O 96 TAG RAM Output Lines 7-0. Dirty Bit of Tag RAM to indicate its line has been written into. TAG RAM Write Enable. It is used to update the TAG RAM. Write strobe to Dirty Bit of TAG RAM External Cache Output Enable. External Cache Write Enable; each signal corresponds to one byte of data External Cache Even Bank Chip Select; it is normally active and becomes high if CA2 is high during cache write cycle. Also it will toggle during cache line fill cycle. External Cache Odd Bank Chip Select; it is normally active and becomes high if CA2 is low during cache write cycle. It will be a complement of BECS# during cache line fills. External Cache Even Bank Data Buffers Enable; Activated for cache write cycle and, if CA2 is low, cache read cycle. Also, toggles during dirty write backs and CPU burst reads. External Cache Odd Bank Data Buffers Enable. It is activated for cache write cycle and, if CA2 is high, cache read cycle. It will become a complement of BEOE# during dirty write back and CPU burst read cycle. External Cache Data Buffers Direction Control. It is normally high and forced to be low when writing data into cache. 15 BEA3 O 101 BOA3 O 99 CA3S# O External Cache Even Bank Address Bit 3.It is tri-stated during T1 and first half T2 cycle. Then it simply reflects the status of CA3 and will toggle during dirty write back, cache line fill, and CPU burst read cycles. External cache oven bank address bit 3.It is tri-stated during T1 and first half T2 cycle. Then it reflects the status of CA3 and will toggle during dirty write back, cache line fill, and CPU burst read cycles. External cache address bit 3 select; use this signal to choose between CA3 and BEA3 for even bank cache address bit 3, or BOA3 for odd bank cache address bit 3 respectively. becomes active for T1 and the first T2 cycles. 95 3.5 Local DRAM Interface Name Type Pin No DWE# RAS(3:0)# O O CAS(3:0)# MA(10:0) O O 133 132,131,129, 128 127-124 123,122, 119-111 Description 16 DRAM Write Enable signal. DRAM Row Address Strobe. DRAM Column Address Strobe. DRAM Row/Column Address Line 10-0. 3.6 DBC Interface Name LMEN# Type O Pin No 109 DLE O 107 MIO16 MIO16# O 143 PCKEN# O 106 ATCYC# O 154 Name HRQ OUT1 HLDA ADS8 Type I I I I Pin NO 145 146 41 152 AEN8# ADS16 ADS16 I I 147 153 AEN16 AEN16# HOLD I O 148 28 HLDA1 RFSH# O B 7 158 AHOLD O 22 EADS# O Description Local Memory Acessed Indication. Used by DBC to control the bus flow. DRAM Read Data Latch Enable; used for parity checking. Latched AT-bus 16-bit Slave Status; used for bus conversion. Parity Checking Enable; used by DBC to perform parity checking. AT Cycle Indication for CPU cycle. 23 3.7 Bus Arbitration Description DMA or Master Cycle Request from 82C206 82C206 Refresh Request from Timer1 Output. CPU Hold Acknowledge. 8-bit DMA Transfer Address Strobe. The SYSC has to latch XD(7:0) by using ADS8 and translate to CA(15:8) outputs. 8-bit DMA Cycle Indication. 16-bit DMA Transfer Address Strobe. The SYSC has to latch XD(7:0) by using ADS16 ADS16 and translate to CA(16:9) outputs. 16-bit DMA Transfer Indication. HOLD Request to CPU. Hidden refresh will not hold the CPU. DMA or Master Cycle Granted Notice. AT Refresh Cycle Indication. It is an input pin during master or DMA cycle. Address hold request to CPU; It will be activated when HLDA is active and CPURST isn't active, or right after AT memory code read cycle if HOLD is pending. AHOLD will last until HOLD is end. 486 address snooping strobe; it's asserted for two T states during DMA or MASTER cycles. 17 3.8 AT-BUS Interface Name XA0 Type B Pin No 156 XA1 B 157 CHRDY NOWS# I I 139 138 IO16# M16# GATEA20 GATEA20 I I I 137 136 141 A20M# O 26 XD(7:0) B 9-11,13-17 IORD# B 4 IOWR# B 5 MRD# B 2 MWR# B 3 SMRD# O 149 SBHE# SMWR# O O 155 151 ALE O 6 INTA O 144 ROMCS# O 8 Description System Address Line 0. Input during master or 8-bit DMA cycles; output pin during CPU, 16-bit DMA, or refresh cycle. System Address Line 1, it is an input pin during master or DMA cycle; becomes output pin during CPU or refresh cycle. Channel Ready Input from AT-BUS. Schmit trigger input pin. Zero Wait State Input from AT-BUS. It is a schmit trigger input pin. The system BIOS ROM is treated as AT one wait state cycle. 16-bit IO Slave Cycle Status. It is a schmit trigger input pin. 16-bit Memory Slave Cycle Status; Schmitt trigger input pin. Gate A20 Input from 8042 or DBC emulated gateA20 pin. By default, SYSC uses this signal to qualify CA20 during CPU cycle. GateA20 ANDed with fast GATEA20 GATEA20 output to CPU; it will remain high during power up CPU reset period. Peripheral Data Bus Line 7-0.Two purposes for these pins: program the internal index register.* latch the DMA high order address. AT IO Read Command. It is an input pin during DMA or master cycle. AT IO Write Command. It is an input pin during DMA or master cycle. AT Memory Read Command. It is an input pin during DMA or master cycle. AT Memory Write Command. It is an input pin during DMA or master cycle. AT Memory Read Command, for address below 1 Meg. It has to be activated during refresh cycle. AT Bus High Enable. It is an input pin during master cycle. AT Memory Write Command, for address below 1 MB memory space. AT Bus Address Latch Enable to represent that the AT cycle has started. It is brought to high during non-CPU cycle. Interrupt Acknowledge Cycle Indication. Hold will not send to CPU between the INTA* cycles. System BIOS ROM Output Enable. System BIOS ROM accessing could be either 8-bit or 16-bit. This signal will be asserted from the end of the first T2 to the end of the last T2. 18 3.9 Ground and VCC Name Type Pin No Description VCC GND I I 1,20,40,81,100,120 12,30,50,70,80,90,108,121,130,150,160 +5V VSS or Ground 4 SYSC REGISTERS DESCRIPTIONS There are twelve configuration registers inside the 82C491 82C491. An indexing scheme is used to access all the registers of OPTi-486WB chipset. Port 22h is the index register and port 24h is the data register. The index resets after every access; thus, every data access (via port 24h) must be preceded by a write to port 22h, even if the same register is being accessed. All reserved bits are set to zero by default and must be set to zero for future compatibility purpose. Control Register 1 Index: 20h BIT 7-6 4 3 2 1 0 FUNCTION Revision of 82C493 82C493 and is read-only. Cache memory data buffer output enable control 0 = disable 1 = enable When enabled, it will be activated half T stste earlier during read hit cycle. Single ALE Enable- SYSC will activate single ALE instead of multiple ALEs during bus conversion cycle if this bit is enabled. 0 =disable 1 =enable Extra AT Cycle Wait State Enable. Insert one extra wait state in standard AT bus cycle. 0 = disable 1 =enable Keyboard and Fast Reset Control - turn on this bit requires "Halt" instruction to be executed before SYSC generates CPURST. .from keyboard reset 0 =disable 1= enable Fast Reset Enable- alternative fast CPU reset. 0 = disable 1 =enable 19 FAULT 00 0 0 0 0 0 Control Register 2 Index: 21h BIT 7 6 5 4 3-2 1 0 FUNCTION Master Mode Byte Swap Enable 0 = disable 1 = enable Fast Keyboard Reset Delay Control 0 = Generate reset pulse 2 us later 1 = Generate reset pulse immediately Parity Check 0 = enable 1 =disable Cache Enable 0 = Cache is disabled and DRAM burst mode is enbled 1 = Cache enable and DRAM burst mode is disabled Cache Size 3 2 Cache Size 00 64KB 01 128KB 128KB 10 256KB 256KB 11 512KB 512KB Secondary Cache Read Burst Cycles Control 0 = 3 - 1 - 1 - 1 Cycle 1 = 2 - 1 - 1 - 1 Cycle Cache Write Wait State Control 0 = 1 Wait state 1 = 0 Wait state 20 DEFAULT 0 0 0 0. 00 0 0 Shadow RAM Control Register I Index: 22h BIT FUNCTION DEFAULT 7 ROM Enable 1 = read from ROM, write to DRAM. 0 = read/write on RAM and DRAM is write-protected Shadow RAM at D0000h - DFFFFh Area 0 = Disable 1 = Enable Shadow RAM at E0000h - EFFFFh Area 0 = Disable 1 = Enable Shadow RAM at D0000h - DFFFFh Area Write Protect Enable 0 = Disable 1 = Enable Shadow RAM at E0000h - EFFFFh Area Write Protect Enable 0 = Disable 1 = Enable Hidden refresh enable (without holding CPU) 1 = Disable 0 = Enable Unused Bit Slow Refresh Enable (4 times slower than the normal refresh) 0 = Disable 1 = Enable 1 6 5 4 3 2 1 0 0 0 0 0 1 0 0 Shadow RAM Control Register II Index: 23h BIT 7 6 5 4 3 2 1 0 FUNCTION Shadow RAM at EC000h-EFFFFh area 0 = Disable 1 = Enable Shadow RAM at E8000h-EBFFFh area 0 = Disable 1 = Enable Shadow RAM at E4000h-E7FFFh area 0 = Disable 1 = Enable Shadow RAM at E0000h-E3FFFh area 0 = Disable 1 = Enable Shadow RAM at DC000h-DFFFFh area 0 = Disable 1 = Enable Shadow RAM at D8000h-DBFFFh area 0 = Disable 1 = Enable Shadow RAM at D4000h-D7FFFh area 0 = Disable 1 = Enable Shadow RAM at D0000h-D3FFFh area 0 = Disable 1 = Enable 21 DEFAULT 0 0 0 0 0 0 0 0 DRAM Control Register I Index: 24h BIT FUNCTION DEFAULT 7 0 = 256 K DRAM mode 1 = 1M and 4 M DRAM mode. See the following table DRAM types used for bank0 and bank1. See the following table Fast decode enable. This function may be enabled in 20/25 Mhz operation to speed up the DRAM access. 0 = Disable fast decode, DRAM wait state is not changed 1 = Enable fast decode, DRAM wait state is decreased by 1 This bit is automatically disabled even when it is set to 1 when bit 4 of Index register 21h(cache enable bit) is enabled. DRAM types used for bank 2 and bank 3. See the following table. 1 6-4 3 2-0 Bits 7654 0000 0001 0010 0011 01XX 1000 1001 1010 1011 1100 1101 111X Bank 0 Bank 1 256K 256K 1M X X 1M 1M 1M 4M 4M 4M X X 256K 256K X X X 1M 4M 1M X 4M X Bits 7210 1000 1001 1010 1011 1100 1101 111X Bank 2 Bank 3 1M 1M X 4M 4M 4M X X 1M X 1M X 4M X 22 000 0 111 DRAM Control Register II Index: 25h BIT 7-6 5-3 2 1-0 FUNCTION Read cycle wait state 7 6 Additional wait States 00 Not used 01 0 10 1 11 2 Note: Base wait states is "3". Write cycle wait state 5 4 3 Additional wait states 0 0 0 0 0 1 0 1 1 0 0 2 1 1 0 3 0 0 1 not used Note: Base wait states is "2". unused ATCLK selection, bit 0 will reflect the BCLKS pin status when 82C493 82C493 is reset. Bit 0 is 0 if BCLKS is tighted low and 1 if BCLKS is high 1 0 ATCLK selection 0 0 (default) : ATCLK = CLKI/6 0 1 (default) ATCLK = CLKI/4 1 0 ATCLK = CLKI/3 1 1 ATCLK = CLK2I/5 DEFAULT 11 110 0 00 or 01 depending the low or high of BCLKS respectively Shadow RAM Control Register III Index: 26h BIT 7 6 5 4 FUNCTION Not used Shadow RAM copy enable for address area C0000h-CFFFFh 0 = Read/write at AT bus 1 = Read from AT bus and write into shadow RAM Shadow write protect at address area C0000h-CFFFFh 0 = Write protect disable . 1 = Write protect enable Shadow RAM enable at C0000h- CFFFFh area 0 = Enable 1 = Disable 23 DEFAULT 0 0 0 0 3 2 1 0 Enable shadow RAM at CC000h-CFFFF area 0 = Disable 1 = Enable Enable shadow RAM at C8000h-CBFFF area 0 = disable 1 = Enable Enable shadow RAM at C4000h-C7FFFh area 0 = Disable 1 = Enable Enable shadow RAM at C0000h-C3FFFh area 0 = Disable 1 = Enable 24 0 0 0 0 Control Register 3 Index: 27h BIT 7 6-5 4 3-0 FUNCTION Enable NCA# pin to low state, 0=Disable 1 =Enable Unused Video BIOS at C0000h-C8000h area non-cacheable 0 = Cacheable 1 = Non-cacheable Cacheable address range for local memory, see following table DEFAULT 1 00 1 0001 Note. Memory area at 640K-1M 640K-1M is defaulted to be non-cacheable. Bits 3210 Cachable Address range 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0 - 64 Mb 0 - 4 Mb 0 - 8 Mb 0 - 12 Mb 0 - 16 Mb 0 - 20 Mb 0 - 24 Mb 0 - 28 Mb 0 - 32 Mb 0 - 36 Mb 0 - 40 Mb 0 - 44 Mb 0 - 48 Mb 0 - 52 Mb 0 - 56 Mb 0 - 60 Mb Note: If total memory is 1 Mb or 2Mb, the cacheable range is 0 - 1 or 0 - 2Mb respectively and indendent of the value of bit 0-3. . 25 Non-cachable Block 1 Register Index: 28h This register is used in conjunction with Index 29h register to define a non-cacheable block. The starting address for the Non-Cacheable Block must have the same granularity as the block size. For example, if a 512 Kb non-cacheable block is selected, its starting address is a multiple of 512 Kb; consequently, only address bits of A19-A23 A19-A23 are significant, A16-A18 A16-A18 are "don't care". BIT 7-5 4-2 1-0 765 000 001 010 011 1xx FUNCTION DEFAULT Size of non-cachable memory block 1, See following table Unused Address bits of A25 and A24 of non-cachable memory block 1 100 000 00 Block Size 64K 128K 256K 512K Disabled Non-cachable Block 1 Register II Index: 29h BIT 7-0 FUNCTION Address bits A23-A16 A23-A16 of non-cachable memory block 1 Default 0001xxxx Valid Starting Address Bits Block Size A23 A22 A21 A20 A19 A18 A17 A16 64K 128K 256K 512K V V V V V V V V V V V V V V V V V V V V V V V x V V x x V x x x x = Don't Care V = Valid Bit 26 Non-cachable Block 2 Register I Index: 2Ah This register is used in conjunction with Index 2Bh register to define a non-cacheable block. The starting address for the Non-Cacheable Block must have the same granularity as the block size. For example, if a 512 Kb non-cacheable block is selected, its starting address is a multiple of 512 Kb; consequently, only address bits of A19-A23 A19-A23 are significant, A16-A18 A16-A18 are "don't care". BIT 7-5 4-2 1-0 FUNCTION DEFAULT Size of non-cacheable memory block 1, See following table Unused Address bits of A25 and A24 of non-cachable memory block 1 765 Block Size 000 001 010 011 1xx 100 000 00 64K 128K 256K 512K Disabled Non-cachable Block 1 Register II Index: 2Bh BIT FUNCTION Default 7-0 Address bit A23-A16 A23-A16 of non-cachable memory block 1 0001xxxx Valid Starting Address Bits Block Size A23 A22 A21 A20 A19 A18 A17 A16 64K 128K 256K 512K V V V V V V V V V V V V V V V V V V V V V V V x V V x x V x x x x = Don't Care V = Valid Bit 27 5 82C392 82C392 DATA BUFFER CONTROLLER(DBC) The DBC is a 160-pin PFP (Plastic Flat Package) device. The DBC integrates data buffers, AT bus control, decode logic for an external keyboard controller, reset logic, and clock generation logic. It performs the following functions: o o o o o o o o o o data bus conversion parity generation/detection AT-BUS direction control reset logic clock source for 206 and 8042 chip select for keyboard controller and RTC speaker control port B, 70H and NMI Logic floating-point coprocessor interface keyboard reset and gate A20 emulation logic 5.1 Data Bus Conversion The DBC performs data bus conversion when the CPU accesses 16- or 8-bit devices through 32- and 16-bit instructions. The DBC also handles DMA and AT bus master cycles that transfer data between local DRAM or cache memory and locations on the AT bus. The DBC provides all of the signals necessary to control external bidirectional data buffers. 5.2 Parity Generation/Detection Logic During local DRAM write cycles, the DBC generates a parity bit for each byte of write data from the processor. Parity bits are stored in dedicated local DRAM. Within the timing window of "PCKEN" during a DRAM read, the DBC checks if each parity bit is correct for its corresponding data byte. If it detects incorrect parity, the DBC generates a parity error. 5.3 Clock Generation and Reset Control The DBC provides the clock sources for timer 1 of the 80C206 80C206 and for the 8042 keyboard controller to reduce the components count. The clocks are derived from 14.3 Mhz. The 00C206 00C206 clock is 1.19 Mhz. (14.3Mhz divided by 12). The 8042 clock is 7.15 Mhz. (14.3Mhz divided by 2.) The DBC also monitors both the PWGD# (Powergood) signal from power supply and the reset signal, RST1. from the reset switch. The DBC routes RST1 to the SYSC to generate the "cold reset". The DBC can also supply the RST2 keyboard controller "warm reset" sequence, or RST2 can come from the keyboard controller. The reset sequence is much faster when the DBC supplies RST2. 28 5.4 Floating-Point Coprocessor Interface The DBC monitors NPERR# and NPBUSY# to provide support for 387 and 3167 floating-point coprocessors. (The 486 has an internal coprocessor and does not need this support.) A coprocessor asserts NPERR# during a power on reset. to indicate it is there. The coprocessor asserts NPBUSY# while executing a floating-point calculation, and asserts READY# when it is finished. If NPBUSY# is active and a coprocessor error occurs (the coprocessor asserts NPERR#), the DBC latches NPBUSY# and generates INT13 INT13. INT13 INT13 also come from WINT# from the Weitek 3167 coprocessor. Latched BUSY# and INT13 INT13 can be cleared by a I/O port F0H write command. 6 82C392 82C392 (DBC) PIN DESCRIPTIONS 6.1 Clock and Reset Name Type Pin No OSCX1 OSCX2 OSC OSC12 OSC12 OSC2 OSC2# PWGD# I O O O O O I 43 42 82 83 85 84 16 RSTSW I 4 RST1# O Description 10 14.3 Mhz osc. input. 14.3 Mhz osc. output. 14.3 Mhz osc. Output to AT bus. 1.19 Mhz output to 206 14.3 Mhz/2 output for 8042 clock. 14.3 Mhz/2 inverted output for 8042 clock. Power Good Status from power supply. It is buffered through a Schmitt-trigger gate. Reset Switch Input. It is buffered through a Schmitt-trigger gate. Power-up or cold Reset signal derived from PWGD# or RSTSW. 29 6.2 Address and Data Buses Name Type Pin No D(31:23) D(22:14) D(13:5) D(4:0) A(9:0) SBHE# BE(3:0)# B B B B I I I 79-71 69-61 59-51 49-45 119-110 25 39-36 MD(31:26) MD(25:17) MD(16:8) MD(7:0) MP(3:0) XD(7:4) XD(3:0) B B B B B B B 156-151 149-141 139-131 129-122 2,159-157 104-101 99-96 Name Type Pin No HLDA I 32 AEN8# AEN16 AEN16# AEN# MASTER# RFSH# I I O I I Description 28 27 106 26 24 CPU Data Bus CPU Data Bus CPU Data Bus CPU Data Bus Buffered AT SA (9:0) address lines. Byte High Enable from AT bus and SYSC. CPU Byte Enables; used for data bus parity checking of valid byte. Local DRAM Data Bus. Local DRAM Data Bus Local DRAM Data Bus Local DRAM Data Bus Local DRAM data bus Parity Bits. XD Data Lines 7-4. XD Data Lines 3-0. 6.3 Bus Arbitration Description Hold Acknowledge from CPU in response to hold request. 8-bit DMA Cycle Indication. 16-bit DMA Cycle Indication. DMA Cycle Indication. Master Cycle Indication. Refresh Cycle Indication. 30 6.4 SYSC Interface Name INTA# ROMCS# Type I I Pin No 23 22 LMEN# I 21 WR# DLE I I 31 17 DWE# ATCYC# I I 3 15 PCKEN# I 18 MIO16 MIO16 I 30 IOWR# IORD# MEMRD# MEMWR# I I I I Description Interrupt Acknowledge; for data flow direction. System BIOS ROM Chip Select, used to direct the data bus flow. Local Memory Enable. Indicate the current cycle is local DRAM Access. It is used to control the bus direction. CPU Write or Read Cycle Indication. DRAM Read Data Latch, used to latch the data for parity checking. DRAM Write Enable, to enable DRAM write. AT Cycle Indication. If asserted, the current access is AT bus cycle. Parity Checking Enable, to enable the Parity error signal if any. 16-bit slave devices access indication. It is used to control the data flow path. AT bus I/O Write Command. AT bus I/O Read Command. AT bus Memory Read Command. AT bus Memory Write Command. 11 12 14 13 6.5 Floating-Point Coprocessor Interfaces * Note these signals won't be necessary in 486 processor. Name Type Pin No Description NPERR# I 87 NPBUSY# I 88 NPRST BUSY# O O 89 34 BSYTOG# I 9 Error from the coprocessor. It is an active low input indicating that an unmasked error happens. Busy from the coprocessor to indicate a coprocessor instruction is under execution. Reset Numeric Processor Latched Coprocessor Busy Output to 80386 to indicate a NPBUSY# or NPERR# signals has occurred. Busy Toggled Control; used to toggle the BUSY# signal when the coprocessor is not installed. 31 Name INT13 INT13 Type O Pin No 91 ERR# O 33 WINT PREQI PREQO I I O 92 90 35 Description Coprocessor Interrupt; is an active high output. It is an interrupt request from numeric coprocessor and connected to IRQ13 IRQ13 of interrupt controller. Error signal to 80386. It reflect the NPERR# signal during the period from RST4# active to first ROMCS#. Weitek 3167 Co-processor Interrupt Request. 80387 coprocessor Request Input. Numeric Processor Request to 80386. 6.6 Miscellaneous Signals Name Type Pin No Description KBDCS# NMI O O 105 95 SPKD O 8 GATE2 ASRTC CHCK# OUT2 FAST O O I O I 93 94 29 44 5 EGTA20 EGTA20 O 7 ERST2# O 6 M16# SDEN# SDIR1# SDIR2# O O O O 19 107 109 108 Keyboard Controller Chip Select. Non-maskable Interrupt; due to parity error from local memory or AT bus channel check. Speaker Data Output, derived from the function of OUT2 and port 61H bit1. Timer 2 Gate Control. Real Time Clock Address Strobe. AT-BUS Channel Check. Timer 2 output. FAST is an active high input which will enable the emulation of Fast GATEA20 GATEA20 and Reset Control Enable. GateA20 output. It is generated by emulating Keyboard GATEA20 GATEA20. RST2# output. It is generated by emulating keyboard RST2#. Master Access Local DRAM invalidation. MD-bus to SD-bus Buffer Enable Signal. MD(7:0) to SD(7:0) Buffer Direction Control. MD(15:8) to SD(15:8) Buffer Direction Control. 32 6.7 Ground and VCC Name Type Pin No Description VCC GND I I 20,40,86,100,140 1,40,41,50,70,80,81,120,121,130,150,160 +5V VSS or Ground 7 82C392 82C392(DBC) REGISTERS DESCRIPTIONS Control Register Index 21h(write only) Bit 7-4 is a duplication of control register index 21h of 82C491 82C491. Bit 3-0 are not used. I/O Port 60h Port 60h and 64h emulate the registers of a keyboard controller, allowing the generation of a fast gate A20 signal. The sequence here is BIOS transparent, and there is no need for the modification of the current BIOS. The fast gate A20 generation is enabled when the "Fast" pin is wired high. The sequence involves writing data D1h to port 64h, then writing data 02h to port 60h.When "Fast" is asserted, I/O port 60h indicates the status of a system reset (bit 0) and gate A20 (bit 1). I/O Port 61h(Port B) Bit 0 1 2 3 4 5 6 7 Read/Write R/W R/W R/W R/W R R R R Function Timer 2 Gate. Speaker Output Enable. Parity Check Enable. I/O Channel Check Enable. Refresh Detect. Timer OUT2 Detect. I/O Channel Check. System Parity Check. 33 I/O Port 64h I/O port 64h emulate the register inside a keyboard controller by generating a fast reset pulse. Writing data FEh to port 64h asserts the reset pulse. The pulse is generated immediately after the I/O write if bit 6 of Index 21h is set, otherwise the pulse is asserted 2us after the write. Port 70h Bit Read/write Function Polarity 7 R/W NMI Enable 0 34