OMC942723159 H8/3927 H8/3926 H8/3925 H8/3924 H8/300L H8/300 HD6433927F - Datasheet Archive

 

H8/3927 Series H8/3927, H8/3926, H8/3925, H8/3924 Hardware Manual Preface The H8/300L Series of single-chip microcomputers has

 

OMC942723159 OMC942723159 H8/3927 H8/3927 Series H8/3927 H8/3927, H8/3926 H8/3926, H8/3925 H8/3925, H8/3924 H8/3924 Hardware Manual Preface The H8/300L H8/300L Series of single-chip microcomputers has the high-speed H8/300L H8/300L CPU at its core, with many necessary peripheral functions on-chip. The H8/300L H8/300L CPU instruction set is compatible with the H8/300 H8/300 CPU. The H8/3927 H8/3927 Series has a system-on-a-chip architecture that includes such peripheral functions as a D/A converter, ten timers, a 14-bit PWM, a two-channel serial communication interface, and an A/D converter. This makes it ideal for use in advanced control systems. This manual describes the hardware of the H8/3927 H8/3927 Series. For details on the H8/3927 H8/3927 Series instruction set, refer to the H8/300L H8/300L Series Programming Manual. Contents Section 1 1.1 1.2 1.3 Overview . Overview. Internal Block Diagram . Pin Arrangement and Functions . 1.3.1 Pin Arrangement. 1.3.2 Pin Functions . Section 2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 CPU . Overview. 2.1.1 Features. 2.1.2 Address Space. 2.1.3 Register Configuration. Register Descriptions. 2.2.1 General Registers. 2.2.2 Control Registers . 2.2.3 Initial Register Values . Data Formats. 2.3.1 Data Formats in General Registers . 2.3.2 Memory Data Formats. Addressing Modes . 2.4.1 Addressing Modes . 2.4.2 Effective Address Calculation . Instruction Set. 2.5.1 Data Transfer Instructions . 2.5.2 Arithmetic Operations . 2.5.3 Logic Operations . 2.5.4 Shift Operations . 2.5.5 Bit Manipulations . 2.5.6 Branching Instructions. 2.5.7 System Control Instructions . 2.5.8 Block Data Transfer Instruction . Basic Operational Timing. 2.6.1 Access to On-Chip Memory (RAM, ROM) . 2.6.2 Access to On-Chip Peripheral Modules . CPU States . 2.7.1 Overview. 2.7.2 Program Execution State . 2.7.3 Program Halt State. 2.7.4 Exception-Handling State. Memory Map . 2.8.1 Memory Map . 1 1 5 6 6 8 13 13 13 14 14 15 15 15 17 17 18 19 20 20 22 26 28 30 31 31 33 37 39 40 42 42 43 45 45 46 46 46 47 47 2.9 Application Notes . 2.9.1 Notes on Data Access . 2.9.2 Notes on Bit Manipulation. 2.9.3 Notes on Use of the EEPMOV Instruction. Section 3 3.1 3.2 3.3 3.4 Exception Handling . Overview. Reset . 3.2.1 Overview. 3.2.2 Reset Sequence . 3.2.3 Interrupt Immediately after Reset. Interrupts. 3.3.1 Overview. 3.3.2 Interrupt Control Registers . 3.3.3 External Interrupts . 3.3.4 Internal Interrupts . 3.3.5 Interrupt Operations. 3.3.6 Interrupt Response Time. Application Notes . 3.4.1 Notes on Stack Area Use . 3.4.2 Notes on Rewriting Port Mode Registers . Section 4 4.1 4.2 4.3 4.4 4.5 5.1 5.2 5.3 5.4 57 57 57 57 57 59 59 59 61 71 72 73 78 79 79 80 Clock Pulse Generators . 83 Overview. 4.1.1 Block Diagram. 4.1.2 System Clock and Subclock . System Clock Generator . Subclock Generator . Prescalers . Note on Oscillators . Section 5 48 48 50 56 83 83 83 84 87 89 90 Power-Down Modes. 91 Overview. 91 5.1.1 System Control Registers . 94 Sleep Mode . 98 5.2.1 Transition to Sleep Mode. 98 5.2.2 Clearing Sleep Mode . 98 5.2.3 Clock Frequency in Sleep (Medium-Speed) Mode . 98 Standby Mode. 99 5.3.1 Transition to Standby Mode . 99 5.3.2 Clearing Standby Mode . 99 5.3.3 Oscillator Settling Time after Standby Mode is Cleared. 100 Watch Mode. 101 5.5 5.6 5.7 5.8 5.4.1 Transition to Watch Mode . 101 5.4.2 Clearing Watch Mode. 101 5.4.3 Oscillator Settling Time after Watch Mode is Cleared . 101 Subsleep Mode. 102 5.5.1 Transition to Subsleep Mode . 102 5.5.2 Clearing Subsleep Mode. 102 Subactive Mode . 103 5.6.1 Transition to Subactive Mode. 103 5.6.2 Clearing Subactive Mode . 103 5.6.3 Operating Frequency in Subactive Mode . 103 Active (Medium-Speed) Mode . 104 5.7.1 Transition to Active (Medium-Speed) Mode . 104 5.7.2 Clearing Active (Medium-Speed) Mode . 104 5.7.3 Operating Frequency in Active (Medium-Speed) Mode . 104 Direct Transfer. 105 Section 6 6.1 6.2 6.3 6.4 ROM . 107 Overview. 107 6.1.1 Block Diagram. 107 PROM Mode. 108 6.2.1 Setting to PROM Mode . 108 6.2.2 Socket Adapter Pin Arrangement and Memory Map . 108 Programming . 111 6.3.1 Writing and Verifying. 111 6.3.2 Programming Precautions. 116 Reliability of Programmed Data. 117 Section 7 7.1 RAM . 119 Overview. 119 7.1.1 Block Diagram. 119 Section 8 8.1 8.2 8.3 I/O Ports . 121 Overview. 121 Port 1 . 123 8.2.1 Overview. 123 8.2.2 Register Configuration and Description . 123 8.2.3 Pin Functions . 127 8.2.4 Pin States . 128 8.2.5 MOS Input Pull-Up. 128 Port 3 . 129 8.3.1 Overview. 129 8.3.2 Register Configuration and Description . 129 8.3.3 Pin Functions . 134 8.4 8.5 8.6 8.7 8.8 8.9 8.10 8.3.4 8.3.5 Port 4 8.4.1 8.4.2 8.4.3 8.4.4 Port 5 8.5.1 8.5.2 8.5.3 8.5.4 8.5.5 Port 6 8.6.1 8.6.2 8.6.3 8.6.4 8.6.5 Port 7 8.7.1 8.7.2 8.7.3 8.7.4 Port 8 8.8.1 8.8.2 8.8.3 8.8.4 Port B 8.9.1 8.9.2 8.9.3 8.9.4 Port C 8.10.1 8.10.2 8.10.3 8.10.4 Section 9 9.1 9.2 Pin States . 136 MOS Input Pull-Up. 136 . 137 Overview. 137 Register Configuration and Description . 137 Pin Functions . 138 Pin States . 138 . 139 Overview. 139 Register Configuration and Description . 139 Pin Functions . 141 Pin States . 142 MOS Input Pull-Up. 142 . 143 Overview. 143 Register Configuration and Description . 143 Pin Functions . 145 Pin States . 145 Operation . 146 . 148 Overview. 148 Register Configuration and Description . 148 Pin Functions . 150 Pin States . 150 . 151 Overview. 151 Register Configuration and Description . 151 Pin Functions . 153 Pin States . 154 . 155 Overview. 155 Register Configuration and Description . 155 Pin Functions . 156 Pin States . 156 . 157 Overview. 157 Register Configuration and Description . 157 Pin Functions . 158 Pin States . 158 Timers . 159 Overview. 159 Timer A. 161 9.3 9.4 9.5 9.6 9.7 9.8 9.9 9.2.1 Overview. 161 9.2.2 Register Descriptions. 163 9.2.3 Timer Operation. 165 9.2.4 Timer A Operation States . 166 Timer B1. 167 9.3.1 Overview. 167 9.3.2 Register Descriptions. 168 9.3.3 Timer Operation. 170 9.3.4 Timer B1 Operation States . 171 Timer B2. 172 9.4.1 Overview. 172 9.4.2 Register Descriptions. 173 9.4.3 Timer Operation. 175 9.4.4 Timer B2 Operation States . 176 Timer B3. 177 9.5.1 Overview. 177 9.5.2 Register Descriptions. 178 9.5.3 Timer Operation. 180 9.5.4 Timer B3 Operation States . 181 Timer C. 182 9.6.1 Overview. 182 9.6.2 Register Descriptions. 183 9.6.3 Timer Operation. 186 9.6.4 Timer C Operation States . 187 Timer E . 188 9.7.1 Overview. 188 9.7.2 Register Descriptions. 189 9.7.3 Timer Operation. 192 9.7.4 Timer E Operation States. 194 Timer V. 195 9.8.1 Overview. 195 9.8.2 Register Descriptions. 198 9.8.3 Timer Operation. 204 9.8.4 Timer V Operation Modes. 209 9.8.5 Interrupt Sources. 209 9.8.6 Application Examples. 210 9.8.7 Application Notes . 212 Timer X. 218 9.9.1 Overview. 218 9.9.2 Register Descriptions. 222 9.9.3 CPU Interface . 233 9.9.4 Timer Operation. 236 9.9.5 Timer X Operation Modes. 245 9.10 9.11 9.9.6 Interrupt Sources. 245 9.9.7 Timer X Application Example. 246 9.9.8 Application Notes . 247 Timer Y. 252 9.10.1 Overview. 252 9.10.2 Register Descriptions. 253 9.10.3 CPU Interface . 256 9.10.4 Timer Operation. 259 9.10.5 Timer Y Operation States . 260 Watchdog Timer . 261 9.11.1 Overview. 261 9.11.2 Register Descriptions. 262 9.11.3 Timer Operation. 265 9.11.4 Watchdog Timer Operation States. 266 Section 10 Serial Communication Interface . 267 10.1 10.2 10.3 Overview. 267 SCI1 . 267 10.2.1 Overview. 267 10.2.2 Register Descriptions. 269 10.2.3 Operation . 274 10.2.4 Interrupts. 277 SCI2 . 278 10.3.1 Overview. 278 10.3.2 Register Descriptions. 280 10.3.3 Operation . 285 10.3.4 Interrupts. 292 Section 11 14-Bit PWM . 293 11.1 11.2 11.3 Overview. 293 11.1.1 Features. 293 11.1.2 Block Diagram. 293 11.1.3 Pin Configuration. 294 11.1.4 Register Configuration. 294 Register Descriptions. 295 11.2.1 PWM Control Register (PWCR) . 295 11.2.2 PWM Data Registers U and L (PWDRU, PWDRL) . 296 Operation . 297 Section 12 A/D Converter. 299 12.1 Overview. 299 12.1.1 Features. 299 12.1.2 Block Diagram. 299 12.2 12.3 12.4 12.5 12.6 12.1.3 Pin Configuration. 300 12.1.4 Register Configuration. 300 Register Descriptions. 301 12.2.1 A/D Result Register (ADRR) . 301 12.2.2 A/D Mode Register (AMR) . 301 12.2.3 A/D Start Register (ADSR) . 303 Operation . 304 12.3.1 A/D Conversion Operation . 304 12.3.2 Start of A/D Conversion by External Trigger Input . 304 Interrupts. 305 Typical Use. 305 Application Notes . 308 Section 13 D/A Converter. 309 13.1 13.2 13.3 13.4 13.5 Overview. 309 13.1.1 Features. 309 13.1.2 Block Diagram. 310 13.1.3 Pin Configuration. 311 13.1.4 Register Configuration. 311 Register Descriptions. 312 13.2.1 D/A Data Registers 3 to 0 (DADR3 to DADR0) . 312 13.3.2 D/A Control Register 0 (DACR0) . 312 Operation . 314 D/A Converter Operation States. 315 Application Notes . 315 Section 14 Electrical Characteristics . 317 14.1 14.2 14.3 14.4 Absolute Maximum Ratings . 317 Electrical Characteristics . 318 14.2.1 Power Supply Voltage and Operating Range . 318 14.2.2 DC Characteristics . 320 14.2.3 AC Characteristics . 326 14.2.4 A/D Converter Characteristics. 329 14.2.5 D/A Converter Characteristics. 330 Operation Timing. 331 Output Load Circuit. 335 Appendix A CPU Instruction Set . 337 A.1 A.2 A.3 Instructions . 337 Operation Code Map. 345 Number of Execution States . 347 Appendix B On-Chip Registers . 354 B.1 B.2 I/O Registers (1) . 354 I/O Registers (2) . 358 Appendix C I/O Port Block Diagrams. 411 C.1 C.2 C.3 C.4 C.5 C.6 C.7 C.8 C.9 Block Diagrams of Port 1 . Block Diagrams of Port 3 . Block Diagram of Port 4. Block Diagrams of Port 5 . Block Diagram of Port 6. Block Diagrams of Port 7 . Block Diagrams of Port 8 . Block Diagram of Port B . Block Diagram of Port C . 411 418 426 427 431 432 436 444 445 Appendix D Port States in the Different Processing States . 446 Appendix E Package Dimensions. 447 Section 1 Overview 1.1 Overview The H8/300L H8/300L Series is a series of single-chip microcomputers (MCU: microcomputer unit), built around the high-speed H8/300L H8/300L CPU and equipped with peripheral system functions on-chip. Within the H8/300L H8/300L Series, the H8/3927 H8/3927 Series of microcomputers are equipped with D/A converters. Other on-chip peripheral functions include 10 timers, a 14-bit pulse width modulator (PWM), two serial communication interface channels, an A/D converter, and a realtime output port. Together, these functions make the H8/3927 H8/3927 Series ideally suited for embedded applications in advanced control systems. The size of the on-chip ROM is 60 kbytes in the H8/3927 H8/3927, 48 kbytes in the H8/3926 H8/3926, 40 kbytes in the H8/3925 H8/3925, and 32 kbytes in the H8/3924 H8/3924. Each model has 1 kbyte of on-chip RAM. The ZTATTM* versions of the H8/3927 H8/3927 come with user-programmable PROM. Table 1 summarizes the features of the H8/3927 H8/3927 Series. Note: * ZTAT is a trademark of Hitachi, Ltd. Table 1-1 Features Item Description CPU High-speed H8/300L H8/300L CPU · General-register architecture General registers: Sixteen 8-bit registers (can be used as eight 16-bit registers) · Operating speed - Max. operating speed: 5 MHz - Add/subtract: 0.4 µs (operating at 5 MHz) - Multiply/divide: 2.8 µs (operating at 5 MHz) - Can run on 32.768 kHz subclock · Instruction set compatible with H8/300 H8/300 CPU - Instruction length of 2 bytes or 4 bytes - Basic arithmetic operations between registers - MOV instruction for data transfer between memory and registers Typical instructions · Multiply (8 bits × 8 bits) · Divide (16 bits ÷ 8 bits) · Bit accumulator · Register-indirect designation of bit position 1 Table 1-1 Features (cont) Item Description Interrupts 35 interrupt sources · 13 external interrupt sources (NMI, IRQ3 to IRQ0, INT7 to INT0) · 22 internal interrupt sources Clock pulse generators Two on-chip clock pulse generators · System clock pulse generator: 1 to 10 MHz · Subclock pulse generator: 32.768 kHz Power-down modes Seven power-down modes · Sleep (high-speed) mode · Sleep (medium-speed) mode · Standby mode · Watch mode · Subsleep mode · Subactive mode · Active (medium-speed) mode Memory Large on-chip memory · H8/3927 H8/3927: 60-kbyte ROM; 1-kbyte RAM · H8/3926 H8/3926: 48-kbyte ROM; 1-kbyte RAM · H8/3925 H8/3925: 40-kbyte ROM; 1-kbyte RAM · H8/3924 H8/3924: 32-kbyte ROM; 1-kbyte RAM I/O ports 68 pins · 56 I/O pins (including 8-pin realtime output port) · 12 input pins Timers Ten on-chip timers · Timer A: 8-bit timer Count-up timer with selection of eight internal clock signals divided from the system clock (ø)* and four clock signals divided from the watch clock (øw)* · Timer B1: 8-bit timer - Count-up timer with selection of seven internal clock signals or event input from external pin - Auto-reloading Note: * ø and øW are defined in section 4, Clock Pulse Generators. 2 Table 1-1 Features (cont) Item Description Timers · Timer B2: 8-bit timer - Count-up timer with selection of seven internal clock signals - Auto-reloading · Timer B3: 8-bit timer - Count-up timer with selection of seven internal clock signals - Auto-reloading · Timer C: 8-bit timer - Count-up/count-down timer with selection of seven internal clock signals or event input from external pin - Auto-reloading · Timer E: 8-bit timer - Count-up timer with selection of eight internal clock signals - Square-wave output with 50% duty cycle · Timer V: 8-bit timer - Count-up timer with selection of six internal clock signals or event input from external pin - Compare-match waveform output - Externally triggerable · Timer X: 16-bit timer - Count-up timer with selection of three internal clock signals or event input from external pin - Output compare (2 output pins) - Input capture (4 input pins) · Timer Y: 16-bit timer - Count-up timer with selection of seven internal clock signals or event input from external pin - Auto-reloading · Watchdog timer - Reset signal generated by 8-bit counter overflow 3 Table 1-1 Features (cont) Item Specification Serial communication interface Two channels on chip · SCI1: synchronous serial interface Choice of 8-bit or 16-bit data transfer · SCI2: 8-bit synchronous serial interface Automatic transfer of 32-byte data segments 14-bit PWM Pulse-division PWM output for reduced ripple · Can be used as a 14-bit D/A converter by connecting to an external low-pass filter. A/D converter Successive approximations using a resistance ladder · Resolution: 8 bits · Conversion time: 31/ø or 62/ø per channel D/A converter 8-bit R-2R-type D/A converter · 4 analog output channels Product lineup Product Code Mask ROM Version ZTATTM Version HD6433927F HD6433927F HD6473927F HD6473927F HD6433926F HD6433926F - ROM: 48 kbytes RAM: 1 kbyte HD6433925F HD6433925F - ROM: 40 kbytes RAM: 1 kbyte HD6433924F HD6433924F - ROM: 32 kbytes RAM: 1 kbyte HD6433927X HD6433927X HD6473927X HD6473927X HD6433926X HD6433926X - ROM: 48 kbytes RAM: 1 kbyte HD6433925X HD6433925X - ROM: 40 kbytes RAM: 1 kbyte HD6433924X HD6433924X - ROM: 32 kbytes RAM: 1 kbyte 4 Package ROM/RAM Size 80-pin QFP (FP-80B FP-80B) ROM: 60 kbytes RAM: 1 kbyte 80-pin TQFP (TFP-80F TFP-80F) ROM: 60 kbytes RAM: 1 kbyte 1.2 Internal Block Diagram SCI1 P67/RP7 P67/RP7 P66/RP6 P66/RP6 P65/RP5 P65/RP5 P64/RP4 P64/RP4 P63/RP3 P63/RP3 P62/RP2 P62/RP2 P61/RP1 P61/RP1 P60/RP0 P60/RP0 P57/INT7/TMIY P57/INT7/TMIY P56/INT6/TMIB P56/INT6/TMIB P55/INT5/ADTRG P55/INT5/ADTRG P54/INT4 P54/INT4 P53/INT3 P53/INT3 P52/INT2 P52/INT2 P51/INT1 P51/INT1 P50/INT0 P50/INT0 Timer B1 Port 3 SCI2 Timer B2 Timer X Timer Y Timer E Timer V Watchdog timer 14-bit PWM D/A converter A/D converter Port C PB0/AN0 PB1/AN1 PB2/AN2 PB3/AN3 PB4/AN4 PB5/AN5 PB6/AN6 PB7/AN7 AVCC AVSS Port B PC0/DA0 PC1/DA1 PC2/DA2 PC3/DA3 Port 4 Timer B3 Timer C P40 P41 P42 P43 P44 P45 P46 P47 P77 P76/TMOV P76/TMOV P75/TMCIV P75/TMCIV P74/TMRIV P74/TMRIV P73 P72 P71 P70 RAM (1 kbyte) Timer A P30/SCK1 P30/SCK1 P31/SI1 P31/SI1 P32/SO1 P32/SO1 P33/SCK2 P33/SCK2 P34/SI2 P34/SI2 P35/SO2 P35/SO2 P36/STRB P36/STRB P37/CS P37/CS Port 8 Port 7 ROM P87 P86/FTID P86/FTID P85/FTIC P85/FTIC P84/FTIB P84/FTIB P83/FTIA P83/FTIA P82/FTOB P82/FTOB P81/FTOA P81/FTOA P80/FTCI P80/FTCI Port 6 P10/TMOW P10/TMOW P11/TMOE P11/TMOE P12/UD P12/UD P13/TMIC P13/TMIC P14/PWM P14/PWM P15/IRQ1 P15/IRQ1 P16/IRQ2 P16/IRQ2 P17/IRQ3/TRGV P17/IRQ3/TRGV Port 1 Data bus (lower) Port 5 Data bus (upper) CPU H8/300L H8/300L Address bus VSS VCC RES NMI IRQ0 TEST X1 X2 Subclock generator System clock generator OSC1 OSC2 Figure 1-1 shows a block diagram of the H8/3927 H8/3927 Series. Figure 1-1 Block Diagram 5 1.3 Pin Arrangement and Functions 1.3.1 Pin Arrangement P13/TMIC P13/TMIC P12/UD P12/UD P11/TMOE P11/TMOE P10/TMOW P10/TMOW VCC 64 62 61 AVCC 70 64 PC3/DA3 71 65 PC2/DA2 72 P14/PWM P14/PWM PC1/DA1 73 P15/IRQ1 P15/IRQ1 PC0/DA0 74 66 PB7/AN7 75 67 PB6/AN6 76 P17/IRQ3/TRGV P17/IRQ3/TRGV PB5/AN5 77 P16/IRQ2 P16/IRQ2 PB4/AN4 78 68 PB3/AN3 79 69 PB2/AN2 80 The H8/3927 H8/3927 Series pin arrangement is shown in figures 1-2 and 1-3. PB1/AN1 1 60 P30/SCK1 P30/SCK1 PB0/AN0 2 59 P31/SI1 P31/SI1 AVSS 3 58 P32/SO1 P32/SO1 TEST 4 57 P33/SCK2 P33/SCK2 X2 5 56 P34/SI2 P34/SI2 39 40 P74/TMRIV P74/TMRIV P73 41 P72 20 38 P75/TMCIV P75/TMCIV IRQ0 P71 P76/TMOV P76/TMOV 42 37 43 19 36 18 P47 P70 P46 P67/RP7 P67/RP7 P77 35 P80/FTCI P80/FTCI 44 34 45 17 P66/RP6 P66/RP6 16 P45 P65/RP5 P65/RP5 P44 33 P81/FTOA P81/FTOA P64/RP4 P64/RP4 46 32 15 31 P82/FTOB P82/FTOB P43 P63/RP3 P63/RP3 P83/FTIA P83/FTIA 47 P62/RP2 P62/RP2 48 14 30 13 P42 29 P41 P60/RP0 P60/RP0 P84/FTIB P84/FTIB P61/RP1 P61/RP1 P85/FTIC P85/FTIC 49 28 50 12 P57/INT7/TMIY P57/INT7/TMIY 11 P40 27 NMI 26 P86/FTID P86/FTID P56/INT6/TMIB P56/INT6/TMIB 51 P55/INT5/ADTRG P55/INT5/ADTRG 10 25 P87 RES 24 P37/CS P37/CS 52 P54/INT4 P54/INT4 53 9 P53/INT3 P53/INT3 8 OSC2 23 OSC1 P52/INT2 P52/INT2 P36/STRB P36/STRB 22 P35/SO2 P35/SO2 54 21 55 7 P51/INT1 P51/INT1 6 P50/INT0 P50/INT0 X1 VSS Figure 1-2 Pin Arrangement (TFP-80F TFP-80F: Top View) 6 P14/PWM P14/PWM P13/TMIC P13/TMIC P12/UD P12/UD P11/TMOE P11/TMOE 66 65 AVCC 72 67 PC3/DA3 73 68 PC2/DA2 74 P15/IRQ1 P15/IRQ1 PC1/DA1 75 69 PC0/DA0 76 P17/IRQ3/TRGV P17/IRQ3/TRGV PB7/AN7 77 P16/IRQ2 P16/IRQ2 PB6/AN6 78 70 PB5/AN5 79 71 PB4/AN4 80 PB3/AN3 1 64 P10/TMOW P10/TMOW PB2/AN2 2 63 VCC PB1/AN1 3 62 P30/SCK1 P30/SCK1 PB0/AN0 4 61 P31/SI1 P31/SI1 AVSS 5 60 P32/SO1 P32/SO1 TEST 6 59 P33/SCK2 P33/SCK2 X2 7 58 P34/SI2 P34/SI2 X1 8 57 P35/SO2 P35/SO2 VSS P46 20 45 P76/TMOV P76/TMOV P47 21 44 P75/TMCIV P75/TMCIV IRQ0 22 43 P74/TMRIV P74/TMRIV P50/INT0 P50/INT0 23 42 P73 P51/INT1 P51/INT1 24 41 P72 P52/INT2 P52/INT2 40 P77 P71 46 39 19 P70 P45 38 P80/FTCI P80/FTCI 37 P81/FTOA P81/FTOA 47 P67/RP7 P67/RP7 48 18 P66/RP6 P66/RP6 17 P44 36 P43 P65/RP5 P65/RP5 P82/FTOB P82/FTOB 35 49 34 16 P64/RP4 P64/RP4 P42 P63/RP3 P63/RP3 P83/FTIA P83/FTIA 33 P84/FTIB P84/FTIB 50 P62/RP2 P62/RP2 51 15 32 14 P41 31 P40 P60/RP0 P60/RP0 P85/FTIC P85/FTIC P61/RP1 P61/RP1 52 30 13 P56/INT6/TMIB P56/INT6/TMIB NMI P57/INT7/TMIY P57/INT7/TMIY P86/FTID P86/FTID 29 P87 53 28 54 12 P55/INT5/ADTRG P55/INT5/ADTRG 11 RES 27 OSC2 P54/INT4 P54/INT4 P37/CS P37/CS P53/INT3 P53/INT3 P36/STRB P36/STRB 55 26 56 10 25 9 OSC1 Figure 1-3 Pin Arrangement (FP-80B FP-80B: Top View) 7 1.3.2 Pin Functions Table 1-2 outlines the pin functions of the H8/3927 H8/3927 Series. Table 1-2 Pin Functions Pin No. Type Symbol TFP-80F TFP-80F FP-80B FP-80B I/O Name and Functions 61 63 Input Power supply: All VCC pins should be connected to the system power supply (+5 V) VSS 7 9 Input Ground: All VSS pins should be connected to the system power supply (0 V) AVCC 70 72 Input Analog power supply: This is the power supply pin for the A/D converter. When the A/D converter is not used, connect this pin to the system power supply (+5 V). AVSS 3 5 Input Analog ground: This is the A/D converter ground pin. It should be connected to the system power supply (0 V). OSC1 8 10 Input OSC2 9 11 Output System clock: These pins connect to a crystal or ceramic oscillator, or can be used to input an external clock. See section 4, Clock Pulse Generators, for a typical connection diagram. X1 6 8 Input X2 5 7 Output RES 10 12 Input Reset: When this pin is driven low, the chip is reset TEST 4 6 Input Test: This is a test pin, not for use in application systems. It should be connected to VSS. Power VCC source pins Clock pins System control 8 Subclock: These pins connect to a 32.768-kHz crystal oscillator. See section 4, Clock Pulse Generators, for a typical connection diagram. Table 1-2 Pin Functions (cont) Pin No. Type Symbol TFP-80F TFP-80F FP-80B FP-80B I/O Name and Functions Interrupt pins NMI 11 13 Input Nonmaskable interrupt: This is an input pin for an edge-sensitive nonmaskable interrupt, with a selection of rising or falling edge. IRQ0 IRQ1 IRQ2 IRQ3 20 67 68 69 22 69 70 71 Input IRQ interrupt request 0 to 3: These are input pins for edge-sensitive external interrupts, with a selection of rising or falling edge. INT7 to INT0 28 to 21 30 to 23 Input INT interrupt request 0 to 7: These are input pins for edge-sensitive external interrupts, with a selection of rising or falling edge. TMOW 62 64 Output Clock output: This is an output pin for waveforms generated by the timer A output circuit TMIB 27 29 Input Timer B1 event counter input: This is an event input pin for input to the timer B1 counter TMIC 65 67 Input Timer C event counter input: This is an event input pin for input to the timer C counter UD 64 66 Input Timer C up/down select: This pin selects whether timer C counts up or down. High input selects up-counting. Low input selects down-counting. TMOE 63 65 Output Timer E output: This is an output pin for a square wave generated by counter overflow in timer E TMOV 43 45 Output Timer V output: This is an output pin for waveforms generated by the timer V output compare function TMCIV 42 44 Input Timer V event input: This is an event input pin for input to the timer V counter TMRIV 41 43 Input Timer V counter reset: This is a counter reset input pin for timer V Timer pins 9 Table 1-2 Pin Functions (cont) Pin No. Type Symbol TFP-80F TFP-80F FP-80B FP-80B I/O Name and Functions Timer pins TRGV 69 71 Input Timer V counter trigger input: This is a trigger input pin for the timer V counter and realtime output port. FTCI 45 47 Input Timer X clock input: This is an external clock input pin for input to the timer X counter FTOA 46 48 Output Timer X output compare A output: This is an output pin for timer X output compare A FTOB 47 49 Output Timer X output compare B output: This is an output pin for timer X output compare B FTIA 48 50 Input Timer X input capture A input: This is an input pin for timer X input capture A FTIB 49 51 Input Timer X input capture B input: This is an input pin for timer X input capture B FTIC 50 52 Input Timer X input capture C input: This is an input pin for timer X input capture C FTID 51 53 Input Timer X input capture D input: This is an input pin for timer X input capture D TMIY 28 30 Input Timer Y clock input: This is an external clock input pin for input to the timer Y counter 14-bit PWM pin PWM 66 68 Output 14-bit PWM output: This is an output pin for waveforms generated by the 14-bit PWM I/O ports PB7 to PB0 75 to 80, 1 to 2 77 to 80, 1 to 4 Input Port B: This is an 8-bit input port PC3 to PC0 71 to 74 73 to 76 Input Port C: This is a 4-bit input port P17 to P10 69 to 62 71 to 64 I/O Port 1: This is an 8-bit I/O port. Input or output can be designated for each bit by means of port control register 1 (PCR1). P37 to P30 53 to 60 55 to 62 I/O Port 3: This is an 8-bit I/O port. Input or output can be designated for each bit by means of port control register 3 (PCR3). 10 Table 1-2 Pin Functions (cont) Pin No. Type Symbol TFP-80F TFP-80F I/O ports P47 to P40 19 to 12 P57 to P50 I/O Name and Functions 21 to 14 I/O Port 4: This is an 8-bit I/O port. Input or output can be designated for each pin by means of port control register 4 (PCR4). 28 to 21 30 to 23 I/O Port 5: This is an 8-bit I/O port. Input or output can be designated for each bit by means of port control register 5 (PCR5). P67 to P60 36 to 29 38 to 31 I/O Port 6: This is an 8-bit I/O port. Input or output can be designated for each bit by means of port control register 6 (PCR6). RP7 to RP0 36 to 29 38 to 31 Output Port 6: This is an 8-bit realtime output port P77 to P70 44 to 37 46 to 39 I/O Port 7: This is an 8-bit I/O port. Input or output can be designated for each bit by means of port control register 7 (PCR7). P87 to P80 Serial communication interface (SCI) FP-80B FP-80B 52 to 45 54 to 47 I/O Port 8: This is an 8-bit I/O port. Input or output can be designated for each bit by means of port control register 8 (PCR8). SI1 59 61 Input SCI1 receive data input: This is the SCI1 data input pin SO1 58 60 Output SCI1 send data output: This is the SCI1 data output pin SCK1 60 62 I/O SCI1 clock I/O : This is the SCI1 clock I/O pin SI2 56 58 Input SCI2 receive data input: This is the SCI2 data input pin SO2 55 57 Output SCI2 send data output: This is the SCI2 data output pin SCK2 57 59 I/O SCI2 clock I/O : This is the SCI2 clock I/O pin CS 53 55 Input SCI2 chip select input: This pin controls the start of SCI2 transfers STRB 54 56 Output SCI2 strobe output: This pin outputs a strobe pulse each time a byte of data is transferred 11 Table 1-2 Pin Functions (cont) Pin No. Type Symbol TFP-80F TFP-80F FP-80B FP-80B I/O Name and Functions A/D converter AN7 to AN0 79 to 80, 1 to 2 77 to 80, 1 to 4 Input Analog input channels 7 to 0: These are analog data input channels to the A/D converter ADTRG 26 28 Input A/D converter trigger input: This is the external trigger input pin to the A/D converter DA3 to DA0 71 to 74 73 to 76 Output Analog output channels 3 to 0: These are analog data output channels from the D/A converter D/A converter 12 Section 2 CPU 2.1 Overview The H8/300L H8/300L CPU has sixteen 8-bit general registers, which can also be paired as eight 16-bit registers. Its concise instruction set is designed for high-speed operation. 2.1.1 Features Features of the H8/300L H8/300L CPU are listed below. · General-register architecture Sixteen 8-bit general registers, also usable as eight 16-bit general registers · Instruction set with 55 basic instructions, including: - Multiply and divide instructions - Powerful bit-manipulation instructions · Eight addressing modes - Register direct - Register indirect - Register indirect with displacement - Register indirect with post-increment or pre-decrement - Absolute address - Immediate - Program-counter relative - Memory indirect · 64-kbyte address space · High-speed operation - All frequently used instructions are executed in two to four states - High-speed arithmetic and logic operations - 8- or 16-bit register-register add or subtract: 0.4 µs* - 8 × 8-bit multiply: 2.8 µs* - 16 ÷ 8-bit divide: 2.8 µs* · Low-power operation modes SLEEP instruction for transfer to low-power operation Note: * These values are at ø = 5 MHz. 13 2.1.2 Address Space The H8/300L H8/300L CPU supports an address space of up to 64 kbytes for storing program code and data. See 2.8, Memory Map, for details of the memory map. 2.1.3 Register Configuration Figure 2-1 shows the register structure of the H8/300L H8/300L CPU. There are two groups of registers: the general registers and control registers. General registers (Rn) 7 0 7 0 R0H R0L R1H R1L R2H R2L R3H R3L R4H R4L R5H R5L R6H R6L R7H (SP) SP: Stack pointer R7L Control registers (CR) 15 0 PC CCR PC: Program counter 7 6 5 4 3 2 1 0 I UHUNZ VC CCR: Condition code register Carry flag Overflow flag Zero flag Negative flag Half-carry flag Interrupt mask bit User bit User bit Figure 2-1 CPU Registers 14 2.2 Register Descriptions 2.2.1 General Registers All the general registers can be used as both data registers and address registers. When used as data registers, they can be accessed as 16-bit registers (R0 to R7), or the high bytes (R0H to R7H) and low bytes (R0L to R7L) can be accessed separately as 8-bit registers. When used as address registers, the general registers are accessed as 16-bit registers (R0 to R7). R7 also functions as the stack pointer (SP), used implicitly by hardware in exception processing and subroutine calls. When it functions as the stack pointer, as indicated in figure 2-2, SP (R7) points to the top of the stack. Lower address side [H'0000] Unused area SP (R7) Stack area Upper address side [H'FFFF] Figure 2-2 Stack Pointer 2.2.2 Control Registers The CPU control registers include a 16-bit program counter (PC) and an 8-bit condition code register (CCR). Program Counter (PC): This 16-bit register indicates the address of the next instruction the CPU will execute. All instructions are fetched 16 bits (1 word) at a time, so the least significant bit of the PC is ignored (always regarded as 0). 15 Condition Code Register (CCR): This 8-bit register contains internal status information, including the interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. These bits can be read and written by software (using the LDC, STC, ANDC, ORC, and XORC instructions). The N, Z, V, and C flags are used as branching conditions for conditional branching (Bcc) instructions. Bit 7-Interrupt Mask Bit (I): When this bit is set to 1, interrupts are masked. This bit is set to 1 automatically at the start of exception handling. The interrupt mask bit may be read and written by software. For further details, see section 3.3, Interrupts. Bit 6-User Bit (U): Can be used freely by the user. Bit 5-Half-Carry Flag (H): When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, or NEG.B instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and is cleared to 0 otherwise. The H flag is used implicitly by the DAA and DAS instructions. When the ADD.W, SUB.W, or CMP.W instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 11, and is cleared to 0 otherwise. Bit 4-User Bit (U): Can be used freely by the user. Bit 3-Negative Flag (N): Indicates the most significant bit (sign bit) of the result of an instruction. Bit 2-Zero Flag (Z): Set to 1 to indicate a zero result, and cleared to 0 to indicate a non-zero result. Bit 1-Overflow Flag (V): Set to 1 when an arithmetic overflow occurs, and cleared to 0 at other times. Bit 0-Carry Flag (C): Set to 1 when a carry occurs, and cleared to 0 otherwise. Used by: · · · Add instructions, to indicate a carry Subtract instructions, to indicate a borrow Shift and rotate instructions, to store the value shifted out of the end bit The carry flag is also used as a bit accumulator by bit manipulation instructions. Some instructions leave some or all of the flag bits unchanged. Refer to the H8/300L H8/300L Series Programming Manual for the action of each instruction on the flag bits. 16 2.2.3 Initial Register Values When the CPU is reset, the program counter (PC) is initialized to the value stored at address H'0000 in the vector table, and the I bit in the CCR is set to 1. The other CCR bits and the general registers are not initialized. In particular, the stack pointer (R7) is not initialized. The stack pointer should be initialized by software, by the first instruction executed after a reset. 2.3 Data Formats The H8/300L H8/300L CPU can process 1-bit data, 4-bit (BCD) data, 8-bit (byte) data, and 16-bit (word) data. · Bit manipulation instructions operate on 1-bit data specified as bit n in a byte operand (n = 0, 1, 2, ., 7). · All arithmetic and logic instructions except ADDS and SUBS can operate on byte data. · The MOV.W, ADD.W, SUB.W, CMP.W, ADDS, SUBS, MULXU (8 bits × 8 bits), and DIVXU (16 bits ÷ 8 bits) instructions operate on word data. · The DAA and DAS instructions perform decimal arithmetic adjustments on byte data in packed BCD form. Each nibble of the byte is treated as a decimal digit. 17 2.3.1 Data Formats in General Registers Data of all the sizes above can be stored in general registers as shown in figure 2-3. Data Type Register No. Data Format 7 1-bit data RnH 1-bit data 7 0 6 5 RnL 4 3 2 1 0 don't care 7 don't care 7 7 Byte data RnH Byte data Rn LSB RnL Word data 5 4 3 2 1 0 0 MSB 0 6 don't care 7 0 MSB don't care LSB 15 0 MSB LSB 7 4-bit BCD data RnH 4-bit BCD data 4 3 Upper digit RnL 0 Lower digit don't care 7 4 Upper digit don't care 0 3 Lower digit Notation: RnH: Upper byte of general register RnL: Lower byte of general register MSB: Most significant bit LSB: Least significant bit Figure 2-3 Register Data Formats H8/3834 H8/3834 '92 Fig. 2-3 18 2.3.2 Memory Data Formats Figure 2-4 indicates the data formats in memory. For access by the H8/300L H8/300L CPU, word data stored in memory must always begin at an even address. In word access the least significant bit of the address is regarded as 0. If an odd address is specified, the access is performed at the preceding even address. This rule affects the MOV.W instruction, and also applies to instruction fetching. Data Type Address Data Format 7 1-bit data Address n 7 Byte data Address n MSB Even address MSB 0 Word data Odd address 6 5 4 3 2 1 0 LSB Upper 8 bits Lower 8 bits LSB Word data on stack Even address MSB CCR LSB Odd address Byte data (CCR) on stack MSB CCR* LSB Even address MSB Odd address LSB CCR: Condition code register Note: * Ignored on return Figure 2-4 Memory Data Formats When the stack is accessed using R7 as an address register, word access should always be performed. When the CCR is pushed on the stack, two identical copies of the CCR are pushed to make a complete word. When they are restored, the lower byte is ignored. H8/3834 H8/3834 '92 Fig. 2-4 19 2.4 Addressing Modes 2.4.1 Addressing Modes The H8/300L H8/300L CPU supports the eight addressing modes listed in table 2-1. Each instruction uses a subset of these addressing modes. Table 2-1 Addressing Modes No. Address Modes Symbol 1 Register direct Rn 2 Register indirect @Rn 3 Register indirect with displacement @(d:16, Rn) 4 Register indirect with post-increment Register indirect with pre-decrement @Rn+ @­Rn 5 Absolute address @aa:8 or @aa:16 6 Immediate #xx:8 or #xx:16 7 Program-counter relative @(d:8, PC) 8 Memory indirect @@aa:8 1. Register Direct-Rn: The register field of the instruction specifies an 8- or 16-bit general register containing the operand. Only the MOV.W, ADD.W, SUB.W, CMP.W, ADDS, SUBS, MULXU (8 bits × 8 bits), and DIVXU (16 bits ÷ 8 bits) instructions have 16-bit operands. 2. Register Indirect-@Rn: The register field of the instruction specifies a 16-bit general register containing the address of the operand in memory. 3. Register Indirect with Displacement-@(d:16, Rn): The instruction has a second word (bytes 3 and 4) containing a displacement which is added to the contents of the specified general register to obtain the operand address in memory. This mode is used only in MOV instructions. For the MOV.W instruction, the resulting address must be even. 20 4. Register Indirect with Post-Increment or Pre-Decrement-@Rn+ or @­Rn: · Register indirect with post-increment-@Rn+ The @Rn+ mode is used with MOV instructions that load registers from memory. The register field of the instruction specifies a 16-bit general register containing the address of the operand. After the operand is accessed, the register is incremented by 1 for MOV.B or 2 for MOV.W. For MOV.W, the original contents of the 16-bit general register must be even. · Register indirect with pre-decrement-@­Rn The @­Rn mode is used with MOV instructions that store register contents to memory. The register field of the instruction specifies a 16-bit general register which is decremented by 1 or 2 to obtain the address of the operand in memory. The register retains the decremented value. The size of the decrement is 1 for MOV.B or 2 for MOV.W. For MOV.W, the original contents of the register must be even. 5. Absolute Address-@aa:8 or @aa:16: The instruction specifies the absolute address of the operand in memory. The absolute address may be 8 bits long (@aa:8) or 16 bits long (@aa:16). The MOV.B and bit manipulation instructions can use 8-bit absolute addresses. The MOV.B, MOV.W, JMP, and JSR instructions can use 16-bit absolute addresses. For an 8-bit absolute address, the upper 8 bits are assumed to be 1 (H'FF). The address range is H'FF00 to H'FFFF (65280 to 65535). 6. Immediate-#xx:8 or #xx:16: The instruction contains an 8-bit operand (#xx:8) in its second byte, or a 16-bit operand (#xx:16) in its third and fourth bytes. Only MOV.W instructions can contain 16-bit immediate values. The ADDS and SUBS instructions implicitly contain the value 1 or 2 as immediate data. Some bit manipulation instructions contain 3-bit immediate data in the second or fourth byte of the instruction, specifying a bit number. 7. Program-Counter Relative-@(d:8, PC): This mode is used in the Bcc and BSR instructions. An 8-bit displacement in byte 2 of the instruction code is sign-extended to 16 bits and added to the program counter contents to generate a branch destination address. The possible branching range is ­126 to +128 bytes (­63 to +64 words) from the current address. The displacement should be an even number. 21 8. Memory Indirect-@@aa:8: This mode can be used by the JMP and JSR instructions. The second byte of the instruction code specifies an 8-bit absolute address. The word located at this address contains the branch destination address. The upper 8 bits of the absolute address are assumed to be 0 (H'00), so the address range is from H'0000 to H'00FF (0 to 255). Note that with the H8/300L H8/300L Series, the lower end of the address area is also used as a vector area. See 3.3, Interrupts, for details on the vector area. If an odd address is specified as a branch destination or as the operand address of a MOV.W instruction, the least significant bit is regarded as 0, causing word access to be performed at the address preceding the specified address. See 2.3.2, Memory Data Formats, for further information. 2.4.2 Effective Address Calculation Table 2-2 shows how effective addresses are calculated in each of the addressing modes. Arithmetic and logic instructions use register direct addressing (1). The ADD.B, ADDX, SUBX, CMP.B, AND, OR, and XOR instructions can also use immediate addressing (6). Data transfer instructions can use all addressing modes except program-counter relative (7) and memory indirect (8). Bit manipulation instructions use register direct (1), register indirect (2), or absolute addressing (5) to specify a byte operand, and 3-bit immediate addressing (6) to specify a bit position in that byte. The BSET, BCLR, BNOT, and BTST instructions can also use register direct addressing (1) to specify the bit position. 22 23 4 3 2 8 7 rm op 7 6 rm 4 3 4 3 rn 0 0 op disp 7 6 rm op 7 6 rm 4 3 4 3 0 0 15 op 7 6 rm 4 3 0 Register indirect with pre-decrement, @­Rn 15 Register indirect with post-increment, @Rn+ 15 Register indirect with displacement, @(d:16, Rn) 15 Register indirect, @Rn op Register direct, Rn 1 15 Addressing Mode and Instruction Format No. Table 2-2 Effective Address Calculation 0 0 0 Contents (16 bits) of register indicated by rm 0 1 or 2 Contents (16 bits) of register indicated by rm disp Contents (16 bits) of register indicated by rm Contents (16 bits) of register indicated by rm 3 rm 0 3 rn Effective Address (EA) 0 15 15 15 15 0 0 0 0 Operand is contents of registers indicated by rm/rn Incremented or decremented by 1 if operand is byte size, 1 or 2 and by 2 if word size 15 15 15 15 Effective Address Calculation Method 24 7 6 5 No. op op IMM op 8 7 abs op 8 7 IMM abs 15 op 8 7 disp Program-counter relative @(d:8, PC) 15 #xx:16 15 Immediate #xx:8 15 @aa:16 15 Absolute address @aa:8 Addressing Mode and Instruction Format 0 0 0 0 0 Table 2-2 Effective Address Calculation (cont) PC contents Sign extension 15 disp 0 Effective Address Calculation Method H'FF 8 7 0 0 15 0 Operand is 1- or 2-byte immediate data 15 15 Effective Address (EA) 25 8 7 Notation: rm, rn: Register field Operation field op: disp: Displacement IMM: Immediate data abs: Absolute address op abs Memory indirect, @@aa:8 8 15 Addressing Mode and Instruction Format No. 0 Table 2-2 Effective Address Calculation (cont) 15 abs Memory contents (16 bits) H'00 8 7 0 Effective Address Calculation Method 15 Effective Address (EA) 0 2.5 Instruction Set The H8/300L H8/300L Series can use a total of 55 instructions, which are grouped by function in table 2-3. Table 2-3 Instruction Set Function Instructions PUSH*1, Number POP*1 Data transfer MOV, 1 Arithmetic operations ADD, SUB, ADDX, SUBX, INC, DEC, ADDS, SUBS, DAA, DAS, MULXU, DIVXU, CMP, NEG 14 Logic operations AND, OR, XOR, NOT 4 Shift SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR 8 Bit manipulation BSET, BCLR, BNOT, BTST, BAND, BIAND, BOR, BIOR, BXOR, BIXOR, BLD, BILD, BST, BIST 14 Branch Bcc*2, JMP, BSR, JSR, RTS 5 System control RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, NOP 8 Block data transfer EEPMOV 1 Total: 55 Notes: 1. PUSH Rn is equivalent to MOV.W Rn, @­SP. POP Rn is equivalent to MOV.W @SP+, Rn. 2. Bcc is a conditional branch instruction in which cc represents a condition code. The following sections give a concise summary of the instructions in each category, and indicate the bit patterns of their object code. The notation used is defined next. 26 Notation Rd General register (destination) Rs General register (source) Rn General register (EAd), Destination operand (EAs), Source operand CCR Condition code register N N (negative) flag of CCR Z Z (zero) flag of CCR V V (overflow) flag of CCR C C (carry) flag of CCR PC Program counter SP Stack pointer #IMM Immediate data disp Displacement + Addition ­ Subtraction × Multiplication ÷ Division AND logical OR logical Exclusive OR logical Move ~ Logical negation (logical complement) :3 3-bit length :8 8-bit length :16 16-bit length ( ), < > Contents of operand indicated by effective address 27 2.5.1 Data Transfer Instructions Table 2-4 describes the data transfer instructions. Figure 2-5 shows their object code formats. Table 2-4 Data Transfer Instructions Instruction Size* Function MOV B/W (EAs) Rd, Rs (EAd) Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. The Rn, @Rn, @(d:16, Rn), @aa:16, #xx:16, @­Rn, and @Rn+ addressing modes are available for byte or word data. The @aa:8 addressing mode is available for byte data only. The @­R7 and @R7+ modes require word operands. Do not specify byte size for these two modes. POP W @SP+ Rn Pops a 16-bit general register from the stack. Equivalent to MOV.W @SP+, Rn. PUSH W Rn @­SP Pushes a 16-bit general register onto the stack. Equivalent to MOV.W Rn, @­SP. Notes: * Size: Operand size B: Byte W: Word Certain precautions are required in data access. See 2.9.1, Notes on Data Access, for details. 28 15 8 7 0 op rm 15 8 rn 0 rm rn rm rn rm 8 RmRn 7 op 15 MOV rn @RmRn 7 0 op @(d:16, Rm)Rn disp 15 8 7 0 op 15 8 op 7 0 rn 15 @Rm+Rn, or Rn @­Rm abs 8 @aa:8Rn 7 0 op rn @aa:16Rn abs 15 8 op 7 0 rn 15 IMM 8 #xx:8Rn 7 0 op rn #xx:16Rn IMM 15 8 op 7 0 1 1 1 rn PUSH, POP @SP+ Rn, or Rn @­SP Notation: op: Operation field rm, rn: Register field disp: Displacement abs: Absolute address IMM: Immediate data Figure 2-5 Data Transfer Instruction Codes 29 H8/3834 H8/3834 '92 Fig. 2-5 2.5.2 Arithmetic Operations Table 2-5 describes the arithmetic instructions. Table 2-5 Arithmetic Instructions Instruction Size* Function ADD SUB B/W Rd ± Rs Rd, Rd + #IMM Rd Performs addition or subtraction on data in two general registers, or addition on immediate data and data in a general register. Immediate data cannot be subtracted from data in a general register. Word data can be added or subtracted only when both words are in general registers. ADDX SUBX B Rd ± Rs ± C Rd, Rd ± #IMM ± C Rd Performs addition or subtraction with carry or borrow on byte data in two general registers, or addition or subtraction on immediate data and data in a general register. INC DEC B Rd ± 1 Rd Increments or decrements a general register ADDS SUBS W Rd ± 1 Rd, Rd ± 2 Rd Adds or subtracts 1 or 2 to or from a general register DAA DAS B Rd decimal adjust Rd Decimal-adjusts (adjusts to packed BCD) an addition or subtraction result in a general register by referring to the CCR MULXU B Rd × Rs Rd Performs 8-bit × 8-bit unsigned multiplication on data in two general registers, providing a 16-bit result DIVXU B Rd ÷ Rs Rd Performs 16-bit ÷ 8-bit unsigned division on data in two general registers, providing an 8-bit quotient and 8-bit remainder CMP B/W Rd ­ Rs, Rd ­ #IMM Compares data in a general register with data in another general register or with immediate data, and indicates the result in the CCR. Word data can be compared only between two general registers. NEG B 0 ­ Rd Rd Obtains the two's complement (arithmetic complement) of data in a general register Notes: * Size: Operand size B: Byte W: Word 30 2.5.3 Logic Operations Table 2-6 describes the four instructions that perform logic operations. Table 2-6 Logic Operation Instructions Instruction Size* Function AND B Rd Rs Rd, Rd #IMM Rd Performs a logical AND operation on a general register and another general register or immediate data OR B Rd Rs Rd, Rd #IMM Rd Performs a logical OR operation on a general register and another general register or immediate data XOR B Rd Rs Rd, Rd #IMM Rd Performs a logical exclusive OR operation on a general register and another general register or immediate data NOT B ~ Rd Rd Obtains the one's complement (logical complement) of general register contents Notes: * Size: Operand size B: Byte 2.5.4 Shift Operations Table 2-7 describes the eight shift instructions. Table 2-7 Shift Instructions Instruction Size* Function SHAL SHAR B Rd shift Rd SHLL SHLR B ROTL ROTR B ROTXL ROTXR B Performs an arithmetic shift operation on general register contents Rd shift Rd Performs a logical shift operation on general register contents Rd rotate Rd Rotates general register contents Rd rotate through carry Rd Rotates general register contents through the C (carry) bit Notes: * Size: Operand size B: Byte 31 Figure 2-6 shows the instruction code format of arithmetic, logic, and shift instructions. 15 8 7 op 0 rm 15 8 7 0 op 15 8 7 0 rm 8 op 8 0 8 0 rn 7 rn 15 ADD, ADDX, SUBX, CMP (#XX:8) 7 rm 15 MULXU, DIVXU IMM op op rn 7 rn 15 ADDS, SUBS, INC, DEC, DAA, DAS, NEG, NOT rn op 15 ADD, SUB, CMP, ADDX, SUBX (Rm) rn AND, OR, XOR (Rm) 0 IMM 8 AND, OR, XOR (#xx:8) 7 0 op rn SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR Notation: op: Operation field rm, rn: Register field IMM: Immediate data Figure 2-6 Arithmetic, Logic, and Shift Instruction Codes H8/3834 H8/3834 '92 Fig. 2-6 32 2.5.5 Bit Manipulations Table 2-8 describes the bit-manipulation instructions. Figure 2-7 shows their object code formats. Table 2-8 Bit-Manipulation Instructions Instruction Size* Function BSET B 1 ( of ) Sets a specified bit in a general register or memory to 1. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. BCLR B 0 ( of ) Clears a specified bit in a general register or memory to 0. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. BNOT B ~ ( of ) ( of ) Inverts a specified bit in a general register or memory. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. BTST B ~ ( of ) Z Tests a specified bit in a general register or memory and sets or clears the Z flag accordingly. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. BAND B C ( of ) C ANDs the C flag with a specified bit in a general register or memory, and stores the result in the C flag. BIAND B C [~ ( of )] C ANDs the C flag with the inverse of a specified bit in a general register or memory, and stores the result in the C flag. The bit number is specified by 3-bit immediate data. BOR B C ( of ) C ORs the C flag with a specified bit in a general register or memory, and stores the result in the C flag. BIOR B C [~ ( of )] C ORs the C flag with the inverse of a specified bit in a general register or memory, and stores the result in the C flag. The bit number is specified by 3-bit immediate data. Notes: * Size: Operand size B: Byte 33 Table 2-8 Bit-Manipulation Instructions (cont) Instruction Size* Function BXOR B C ( of ) C XORs the C flag with a specified bit in a general register or memory, and stores the result in the C flag. BIXOR B C [~( of )] C XORs the C flag with the inverse of a specified bit in a general register or memory, and stores the result in the C flag. The bit number is specified by 3-bit immediate data. BLD B ( of ) C Copies a specified bit in a general register or memory to the C flag. BILD B ~ ( of ) C Copies the inverse of a specified bit in a general register or memory to the C flag. The bit number is specified by 3-bit immediate data. BST B C ( of ) Copies the C flag to a specified bit in a general register or memory. BIST B ~ C ( of ) Copies the inverse of the C flag to a specified bit in a general register or memory. The bit number is specified by 3-bit immediate data. Notes: * Size: Operand size B: Byte Certain precautions are required in bit manipulation. See 2.9.2, Notes on Bit Manipulation, for details. 34 BSET, BCLR, BNOT, BTST 15 8 7 op 0 IMM 15 8 7 op 0 rm 15 8 Operand: register direct (Rn) Bit No.: immediate (#xx:3) rn Operand: register direct (Rn) Bit No.: register direct (Rm) rn 7 0 rn 0 0 0 0 Operand: register indirect (@Rn) IMM 0 0 0 0 Bit No.: op rn 0 0 0 0 Operand: register indirect (@Rn) op rm 0 0 0 0 Bit No.: op op 15 8 15 8 7 0 7 abs IMM 15 8 0 Operand: absolute (@aa:8) 0 0 7 0 Bit No.: immediate (#xx:3) 0 op abs op register direct (Rm) 0 op op immediate (#xx:3) rm 0 Operand: absolute (@aa:8) 0 0 0 Bit No.: register direct (Rm) BAND, BOR, BXOR, BLD, BST 15 8 7 op 0 IMM 15 8 Operand: register direct (Rn) Bit No.: immediate (#xx:3) rn 7 0 rn op 15 8 0 0 0 0 Operand: register indirect (@Rn) IMM op 0 0 0 0 Bit No.: 7 0 op abs op immediate (#xx:3) IMM 0 Operand: absolute (@aa:8) 0 0 0 Bit No.: immediate (#xx:3) Notation: op: Operation field rm, rn: Register field abs: Absolute address IMM: Immediate data Figure 2-7 Bit Manipulation Instruction Codes H8/3834 H8/3834 '92 Fig. 2-7 35 BIAND, BIOR, BIXOR, BILD, BIST 15 8 7 op 0 IMM 15 8 Operand: register direct (Rn) Bit No.: immediate (#xx:3) rn 7 0 rn op 15 8 0 0 0 0 Operand: register indirect (@Rn) IMM op 0 0 0 0 Bit No.: 7 0 op abs op immediate (#xx:3) IMM 0 Operand: absolute (@aa:8) 0 0 0 Bit No.: immediate (#xx:3) Notation: op: Operation field rm, rn: Register field abs: Absolute address IMM: Immediate data Figure 2-7 Bit Manipulation Instruction Codes (cont) H8/3834 H8/3834 '92 Fig. 2-7 (cont) 36 2.5.6 Branching Instructions Table 2-9 describes the branching instructions. Figure 2-8 shows their object code formats. Table 2-9 Branching Instructions Instruction Size Function Bcc - Branches to the designated address if condition cc is true. The branching conditions are given below. Mnemonic Description Condition BRA (BT) Always (true) Always BRN (BF) Never (false) Never BHI High CZ=0 BLS Low or same CZ=1 BCC (BHS) Carry clear (high or same) C=0 BCS (BLO) Carry set (low) C=1 BNE Not equal Z=0 BEQ Equal Z=1 BVC Overflow clear V=0 BVS Overflow set V=1 BPL Plus N=0 BMI Minus N=1 BGE Greater or equal NV=0 BLT Less than NV=1 BGT Greater than Z (N V) = 0 BLE Less or equal Z (N V) = 1 JMP - Branches unconditionally to a specified address BSR - Branches to a subroutine at a specified address JSR - Branches to a subroutine at a specified address RTS - Returns from a subroutine 37 15 8 op 7 0 cc 15 disp 8 7 op 0 rm 15 Bcc 8 0 0 0 7 0 JMP (@Rm) 0 op JMP (@aa:16) abs 15 8 7 0 op abs 15 8 JMP (@@aa:8) 7 0 op disp 15 8 7 op 0 rm 15 BSR 8 0 0 0 7 0 JSR (@Rm) 0 op JSR (@aa:16) abs 15 8 7 0 op abs 15 8 7 JSR (@@aa:8) 0 op RTS Notation: op: Operation field cc: Condition field rm: Register field disp: Displacement abs: Absolute address Figure 2-8 Branching Instruction Codes H8/3834 H8/3834 '9 Fig. 2-8 38 2.5.7 System Control Instructions Table 2-10 describes the system control instructions. Figure 2-9 shows their object code formats. Table 2-10 System Control Instructions Instruction Size* Function RTE - Returns from an exception-handling routine SLEEP - Causes a transition from active mode to a power-down mode. See section 5, Power-Down Modes, for details. LDC B Rs CCR, #IMM CCR Moves immediate data or general register contents to the condition code register STC B CCR Rd Copies the condition code register to a specified general register ANDC B CCR #IMM CCR Logically ANDs the condition code register with immediate data ORC B CCR #IMM CCR Logically ORs the condition code register with immediate data XORC B CCR #IMM CCR Logically exclusive-ORs the condition code register with immediate data NOP - PC + 2 PC Only increments the program counter Notes: * Size: Operand size B: Byte 39 15 8 7 0 op 15 8 RTE, SLEEP, NOP 7 0 op 15 rn 8 7 LDC, STC (Rn) 0 op IMM ANDC, ORC, XORC, LDC (#xx:8) Notation: op: Operation field rn: Register field IMM: Immediate data Figure 2-9 System Control Instruction Codes 2.5.8 Block Data Transfer Instruction Table 2-11 describes the block data transfer instruction. Figure 2-10 shows its object code format. Table 2-11 Block Data Transfer Instruction Instruction Size EEPMOV - H8/3834 H8/3834 '92 Fig. 2-9 Function If R4L 0 then repeat until @R5+ @R6+ R4L ­ 1 R4L R4L = 0 else next; Moves a data block according to parameters set in general registers R4L, R5, and R6. R4L: Size of block (bytes) R5: Starting source address R6: Starting destination address Execution of the next instruction starts as soon as the block transfer is completed. Certain precautions are required in using the EEPMOV instruction. See 2.9.3, Notes on Use of the EEPMOV Instruction, for details. 40 15 8 7 0 op op Notation: op: Operation field Figure 2-10 Block Data Transfer Instruction Code H8/3 Fig. 2 41 2.6 Basic Operational Timing CPU operation is synchronized by a system clock (ø) or a subclock (øSUB). For details on these clock signals see section 4, Clock Pulse Generators. The period from a rising edge of ø or øSUB to the next rising edge is called one state. A bus cycle consists of two states or three states. The cycle differs depending on whether access is to on-chip memory or to on-chip peripheral modules. 2.6.1 Access to On-Chip Memory (RAM, ROM) Access to on-chip memory takes place in two states. The data bus width is 16 bits, allowing access in byte or word size. Figure 2-11 shows the on-chip memory access cycle. Bus cycle T1 state T2 state ø or ø SUB Internal address bus Address Internal read signal Internal data bus (read access) Read data Internal write signal Internal data bus (write access) Write data Figure 2-11 On-Chip Memory Access Cycle H8/3834 H8/3834 '92 Fig. 2-11&2-12 42 2.6.2 Access to On-Chip Peripheral Modules On-chip peripheral modules are accessed in two states or three states. The data bus width is 8 bits, so access is by byte size only. This means that for accessing word data, two instructions must be used. Figures 2-12 and 2-13 show the on-chip peripheral module access cycle. Two-state access to on-chip peripheral modules Bus cycle T1 state T2 state ø or ø SUB Internal address bus Address Internal read signal Internal data bus (read access) Read data Internal write signal Internal data bus (write access) Write data Figure 2-12 On-Chip Peripheral Module Access Cycle (2-State Access) H8/3834 H8/3834 '92 Fig. 2-12 43 Three-state access to on-chip peripheral modules Bus cycle T1 state T2 state T3 state ø or ø SUB Internal address bus Address Internal read signal Internal data bus (read access) Read data Internal write signal Internal data bus (write access) Write data Figure 2-13 On-Chip Peripheral Module Access Cycle (3-State Access) H8/3834 H8/3834 '92 Fig. 2-13 44 2.7 CPU States 2.7.1 Overview There are four CPU states: the reset state, program execution state, program halt state, and exception-handling state. The program execution state includes active (high-speed or mediumspeed) mode and subactive mode. In the program halt state there are a sleep (high-speed or medium-speed) mode, standby mode, watch mode, and sub-sleep mode. These states are shown in figure 2-14. Figure 2-15 shows the state transitions. CPU state Reset state The CPU is initialized Program execution state Active (high speed) mode The CPU executes successive program instructions at high speed, synchronized by the system clock Active (medium speed) mode The CPU executes successive program instructions at reduced speed, synchronized by the system clock Subactive mode The CPU executes successive program instructions at reduced speed, synchronized by the subclock Low-power modes Sleep (high-speed) mode Program halt state A state in which some or all of the chip functions are stopped to conserve power Sleep (medium-speed) mode Standby mode Watch mode Subsleep mode Exceptionhandling state A transient state in which the CPU changes the processing flow due to a reset or an interrupt Note: See section 5, Power-Down Modes, for details on the modes and their transitions. Figure 2-14 CPU Operation States 45 Reset cleared Reset state Exception-handling state Reset occurs Reset occurs Reset occurs Interrupt source Program halt state Exception- Exceptionhandling handling request complete Program execution state SLEEP instruction executed Figure 2-15 State Transitions 2.7.2 Program Execution State In the program execution state the CPU executes program instructions in sequence. There are three modes in this state, two active modes (high speed and medium speed) and one subactive mode. Operation is synchronized with the system clock in active mode (high speed and medium speed), and with the subclock in subactive mode. See section 5, Power-Down Modes for details on these modes. 2.7.3 Program Halt State In the program halt state there are four modes: sleep mode, standby mode, watch mode, and subsleep mode. See section 5, Power-Down Modes for details on these modes. 2.7.4 Exception-Handling State H037 '92 H8/343 H8/343 U.M. Fig. 2-15 The exception-handling state is a transient state occurring when exception handling is started by a reset or interrupt and the CPU changes its normal processing flow. In exception handling caused by an interrupt, SP (R7) is referenced and the PC and CCR values are saved on the stack. For details on interrupt handling, see section 3.3, Interrupts. 46 2.8 Memory Map 2.8.1 Memory Map Figure 2-16 shows a memory map of the H8/3927 H8/3927 Series. H'0000 Interrupt vectors H'002F H'0030 On-chip ROM H8/3924 H8/3924 H8/3925 H8/3925 H8/3926 H8/3926 H8/3927 H8/3927 32 kbytes 40 kbytes H'7FFF 48 kbytes 60 kbytes H'9FFF H'BFFF H'EDFF Reserved H'F740 Internal I/O registers (64 bytes) H'F77F Reserved H'FB80 On-chip RAM H'FF7F H'FF80 1024 bytes 32-byte serial data buffer H'FF9F H'FFA0 Internal I/O registers (96 bytes) H'FFFF Figure 2-16 H8/3927 H8/3927 Series Memory Map 47 2.9 Application Notes 2.9.1 Notes on Data Access 1. The address space of the H8/300L H8/300L CPU includes empty areas in addition to the RAM, registers, and ROM areas available to the user. If these empty areas are mistakenly accessed by an application program, the following results will occur. Data transfer from CPU to empty area: The transferred data will be lost. This action may also cause the CPU to misoperate. Data transfer from empty area to CPU: Unpredictable data is transferred. 2. Internal data transfer to or from on-chip modules other than the ROM and RAM areas makes use of an 8-bit data width. If word access is attempted to these areas, the following results will occur. Word access from CPU to I/O register area: Upper byte: Will be written to I/O register. Lower byte: Transferred data will be lost. Word access from I/O register to CPU: Upper byte: Will be written to upper part of CPU register. Lower byte: Unpredictable data will be written to lower part of CPU register. Byte size instructions should therefore be used when transferring data to or from I/O registers other than the on-chip ROM and RAM areas. Figure 2-17 shows the data size and number of states in which on-chip peripheral modules can be accessed. 48 Access Word Byte States H'0000 H'002F H'0030 Interrupt vector area (48 bytes) 2 60 kbytes*1 On-chip ROM H'EDFF*1 Reserved H'F77F Internal I/O registers (64 bytes) × Reserved H'F740 - - - - 2 or 3*2 - - H'FB80 On-chip RAM 1,024 bytes 2 H'FF7F H'FF80 32-byte serial data buffer × 2 Internal I/O registers (96 bytes) H'FF9F × 2 or 3*2 H'FFA0 H'FFFF : Access possible × : Not possible Notes: The H8/3927 H8/3927 is shown as an example. 1. The H8/3926 H8/3926 ROM occupies 48 kbytes up to address H'BFFF. The H8/3925 H8/3925 ROM occupies 40 kbytes up to address H'9FFF. The H8/3924 H8/3924 ROM occupies 32 kbytes up to address H'7FFF. 2. Internal I/O registers defined in areas assigned to timer X (H'F770 to H'F77F) and timer V (H'FFB8 to H'FFBD) are accessed in three states. Figure 2-17 Data Size and Number of States for Access to and from On-Chip Peripheral Modules 49 2.9.2 Notes on Bit Manipulation The BSET, BCLR, BNOT, BST, and BIST instructions read one byte of data, modify the data, then write the data byte again. Special care is required when using these instructions in cases where two registers are assigned to the same address, in the case of registers that include write-only bits, and when the instruction accesses an I/O port. Order of Operation Operation 1 Read Read byte data at the designated address 2 Modify Modify a designated bit in the read data 3 Write Write the altered byte data to the designated address 1. Bit manipulation in two registers assigned to the same address Example 1: timer load register and timer counter Figure 2-18 shows an example in which two timer registers share the same address. When a bit manipulation instruction accesses the timer load register and timer counter of a reloadable timer, since these two registers share the same address, the following operations take place. Order of Operation Operation 1 Read Timer counter data is read (one byte) 2 Modify The CPU modifies (sets or resets) the bit designated in the instruction 3 Write The altered byte data is written to the timer load register The timer counter is counting, so the value read is not necessarily the same as the value in the timer load register. As a result, bits other than the intended bit in the timer load register may be modified to the timer counter value. R Count clock Timer counter R: Read W: Write Reload W Timer load register Internal bus Figure 2-18 Timer Configuration Example 50 Example 2: BSET instruction executed designating port 3 P37 and P36 are designated as input pins, with a low-level signal input at P37 and a high-level signal at P36. The remaining pins, P35 to P30, are output pins and output low-level signals. In this example, the BSET instruction is used to change pin P30 to high-level output. [A: Prior to executing BSET] P37 P36 P35 P34 P33 P32 P31 P30 Input/output Input Input Output Output Output Output Output Output Pin state Low level High level Low level Low level Low level Low level Low level Low level PCR3 0 0 1 1 1 1 1 1 PDR3 1 0 0 0 0 0 0 0 [B: BSET instruction executed] BSET #0 , @PDR3 The BSET instruction is executed designating port 3. [C: After executing BSET] P37 P36 P35 P34 P33 P32 P31 P30 Input/output Input Input Output Output Output Output Output Output Pin state Low level High level Low level Low level Low level Low level Low level High level PCR3 0 0 1 1 1 1 1 1 PDR3 0 1 0 0 0 0 0 1 [D: Explanation of how BSET operates] When the BSET instruction is executed, first the CPU reads port 3. Since P37 and P36 are input pins, the CPU reads the pin states (low-level and high-level input). P35 to P30 are output pins, so the CPU reads the value in PDR3. In this example PDR3 has a value of H'80, but the value read by the CPU is H'40. Next, the CPU sets bit 0 of the read data to 1, changing the PDR3 data to H'41. Finally, the CPU writes this value (H'41) to PDR3, completing execution of BSET. 51 As a result of this operation, bit 0 in PDR3 becomes 1, and P30 outputs a high-level signal. However, bits 7 and 6 of PDR3 end up with different values. To avoid this problem, store a copy of the PDR3 data in a work area in memory. Perform the bit manipulation on the data in the work area, then write this data to PDR3. [A: Prior to executing BSET] MOV. B MOV. B MOV. B #80, R0L, R0L, R0L @RAM0 @PDR3 The PDR3 value (H'80) is written to a work area in memory (RAM0) as well as to PDR3. P37 P36 P35 P34 P33 P32 P31 P30 Input/output Input Input Output Output Output Output Output Output Pin state Low level High level Low level Low level Low level Low level Low level Low level PCR3 0 0 1 1 1 1 1 1 PDR3 1 0 0 0 0 0 0 0 RAM0 1 0 0 0 0 0 0 0 [B: BSET instruction executed] BSET #0 , @RAM0 The BSET instruction is executed designating the PDR3 work area (RAM0). 52 [