OMAP5910 SPRS197A SPRS197 OSC32K TI925T TMS320 XDS510 GPIO11/HDQ MPUIO12 - Datasheet Archive

 

Dual-Core Processor Data Manual Literature Number: SPRS197A August 2002 ­ Revised April 2003 PRODUCT PREVIEW information

 

OMAP5910 OMAP5910 Dual-Core Processor Data Manual Literature Number: SPRS197A SPRS197A August 2002 ­ Revised April 2003 PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third­party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Mailing Address: Texas Instruments Post Office Box 655303 Dallas, Texas 75265 Copyright 2003, Texas Instruments Incorporated Revision History REVISION HISTORY This data sheet revision history highlights the technical changes made to the SPRS197 SPRS197 device-specific data sheet to make it an SPRS197A SPRS197A revision. Scope: This document has been reviewed for technical accuracy; the technical content is up-to-date as of the specified release date and includes the following changes. PAGE(S) NO. ADDITIONS/CHANGES/DELETIONS Section 1, Added 289-ball GDY MicroStar BGA to Package Options feature. 2 Section 2.1, Revised list under "Mobile communications." 4 Section 2.2, Terminal Assignments: Added GDY information. Added Figure 2­2, OMAP5910 OMAP5910 GDY MicroStar BGA Package (Bottom View). Added Table 2­2, GDY BGA Terminal Assignments. 10 Revised Section 2.3, Terminal Characteristics and Multiplexing. 19­27 PRODUCT PREVIEW 1 Added footnote about VSS considerations to Table 2­4 and revised the descriptions of the following signals: FLASH.RP, LCD.VS, LCD.HS, LCD.AC, LCD.PCLK, and USB1.VM. 28 Figure 3­1, OMAP5910 OMAP5910 Functional Block DIagram: "Clock/Reset/Power Management" block: replaced "12 MHz" with "12 MHz or 13 MHz". 31 Added EMIFS, EMIFF, and IMIF references to Table 3­1. 36 and 37 Added EMIFS, EMIFF, and IMIF references to Figure 3­2 and Figure 3­3. 38 Section 3.5.5, LCD Controller: Appended two features to "principle features" list. 44 Section 3.7.2, Multichannel Serial Interface (MCSI): Added 13 MHz as an option for the base oscillator. 44 Section 3.8.1, Universal Asynchronous Receiver/Transmitter (UART): Added "(autobauding on UART1 and UART2)" to first bullet. 50 Added section header 3.14.1, Core and I/O Voltage Supply Connections. 51 Added Section 3.14.2, Core Voltage Noise Isolation. 52 Added Figure 3­6, External RC Circuit for DPLL CVDD Noise Isolation. 94 Table 3­73, MPU Level 1 and Level 2 Interrupt Mappings: Updated row for Level 2 Mapping = IRQ_7. 96 Table 3­74, DSP Level 1 Interrupt Mappings: Updated PRIORITY column. 103 Section 5.6.1, 32-kHz Oscillator and Input cLock: In "NOTE", replaced "OSC1_IN" with "OSC32K OSC32K_IN" and replaced "OSC1_OUT" with "OSC32K OSC32K_OUT". 105­136 137 Updated numerous Timing Requirements and Switching Characteristics tables in the Electrical Specifications section. Added Section 5.17, HDQ/1-Wire Interface Timings. Added Table 5­34, HDQ/1-Wire Timing Requirements. Added Table 5­35, HDQ/1-Wire Switching Characteristics. August 2002 ­ Revised April 2003 SPRS197A SPRS197A iii Revision History PAGE(S) NO. ADDITIONS/CHANGES/DELETIONS Added Figure 5­36, OMAP5910 OMAP5910 HDQ Interface Reading From HDQ Slave Device. Added Figure 5­37, OMAP5910 OMAP5910 HDQ Interface Writing to HDQ Slave Device. Added Figure 5­38, Typical Communication Between OMAP5910 OMAP5910 HDQ and HDQ Slave. Added Figure 5­39, HDQ/1-Wire Break (Reset) Timing 143 Added Mechanical Data for the 289-ball GDY package. PRODUCT PREVIEW 138 iv SPRS197A SPRS197A August 2002 ­ Revised April 2003 Contents Contents Section Page 1 OMAP5910 OMAP5910 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1.1 TMS320C55x DSP Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1.2 TI-Enhanced TI925T TI925T RISC Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 Terminal Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3 Terminal Characteristics and Multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2 2 3 4 10 19 3 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 Functional Block Diagram Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 MPU Memory Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.1 MPU Global Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.2 MPU Subsystem Registers Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 DSP Memory Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.1 DSP Global Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.2 On-Chip Dual-Access RAM (DARAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.3 On-Chip Single-Access RAM (SARAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.4 DSP I/O Space Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4 DSP External Memory (Managed by MMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5 MPU and DSP Private Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.1 Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.2 32k Timer (MPU only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.3 Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.4 Interrupt Handlers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.5 LCD Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6 MPU Public Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.1 USB2.0 Host Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.2 USB2.0 Function Peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.3 Multichannel Buffered Serial Port (McBSP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.4 I2C Master/Slave Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.5 Microwire Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.6 Multimedia Card/Secure Digital (MMC/SD) Interface . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.7 HDQ/1-Wire Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.8 Camera Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.9 MPUIO/Keyboard Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.10 Pulse-Width Light (PWL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.11 Pulse-Width Tone (PWT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.12 LED Pulse Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.13 Real-Time Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.14 Frame Adjustment Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7 DSP Public Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7.1 Multichannel Buffered Serial Port (McBSP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7.2 Multichannel Serial Interface (MCSI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 29 31 31 32 33 33 34 34 35 36 38 38 38 38 38 38 39 39 40 40 41 41 41 42 42 42 42 42 43 43 43 43 43 44 August 2002 ­ Revised April 2003 SPRS197A SPRS197A v Contents Section 3.8 Page Shared Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8.1 Universal Asynchronous Receiver/Transmitter (UART) . . . . . . . . . . . . . . . . . . . . . . . 3.8.2 General-Purpose I/O (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8.3 Mailbox Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . System DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DSP DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Traffic Controller (Memory Interfaces) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interprocessor Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.12.1 MPU/DSP Mailbox Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.12.2 MPU Interface (MPUI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.12.3 MPU/DSP Shared Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DSP Hardware Accelerators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.13.1 DCT/iDCT Accelerator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.13.2 Motion Estimation Accelerator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.13.3 Pixel Interpolation Accelerator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Supply Connection Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.14.1 Core and I/O Voltage Supply Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.14.2 Core Voltage Noise Isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MPU Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.15.1 MPU Private Peripheral Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.15.2 MPU Public Peripheral Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.15.3 MPU Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DSP Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.16.1 DSP Private Peripheral Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.16.2 DSP Public Peripheral Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.16.3 DSP Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.16.4 MPU/DSP Shared Peripheral Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 44 45 45 46 47 47 48 48 48 49 49 49 49 49 50 50 51 52 53 60 69 76 76 82 87 89 94 4 Documentation Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1 Device and Development-Support Tool Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 98 5 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3 Electrical Characteristics Over Recommended Operating Case Temperature Range (Unless Otherwise Noted) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4 Package Thermal Resistance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 Timing Parameter Symbology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.6 Clock Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.6.1 32-kHz Oscillator and Input Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.6.2 Base Oscillator (12 MHz or 13 MHz) and Input Clock . . . . . . . . . . . . . . . . . . . . . . . . . 5.6.3 Internal Clock Speed Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.7 Reset Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.7.1 OMAP5910 OMAP5910 Device Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.7.2 OMAP5910 OMAP5910 MPU Core Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 99 100 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 vi SPRS197A SPRS197A 101 102 102 103 103 104 105 106 106 107 August 2002 ­ Revised April 2003 Contents Section 5.8 Page External Memory Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.8.1 EMIFS/Flash Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.8.2 EMIFF/SDRAM Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multichannel Buffered Serial Port (McBSP) Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.9.1 McBSP Transmit and Receive Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.9.2 McBSP as SPI Master or Slave Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multichannel Serial Interface (MCSI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Camera Interface Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LCD Controller Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multimedia Card/Secure Digital (MMC/SD) Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Universal Serial Bus (USB) Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Microwire Interface Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HDQ/1-Wire Interface Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 108 115 119 119 123 127 129 130 132 134 135 136 137 6 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 7 Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1 GZG Ball Grid Array Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2 GDY Ball Grid Array Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 142 143 5.9 5.10 5.11 5.12 5.13 5.14 5.15 5.16 5.17 August 2002 ­ Revised April 2003 SPRS197A SPRS197A vii Figures List of Figures Figure Page 2­1 OMAP5910 OMAP5910 GZG MicroStar BGA Package (Bottom View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2­2 OMAP5910 OMAP5910 GDY MicroStar BGA Package (Bottom View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3­1 OMAP5910 OMAP5910 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3­2 DSP MMU Off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3­3 DSP MMU On . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3­4 Supply Connections for a Typical System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 3­5 Supply Connections for a System with 1.8-V SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 3­6 External RC Circuit for DPLL CVDD Noise Isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 5­1 3.3-V Test Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 5­2 32-kHz Oscillator External Crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 5­3 32-kHz Input Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 5­4 Internal System Oscillator External Crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 5­5 Device Reset Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 5­6 MPU Core Reset Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 5­7 Asynchronous Memory Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 5­8 Asynchronous 32-Bit Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 5­9 Asynchronous Read ­ Page Mode ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 5­10 Asynchronous Memory Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 5­11 Synchronous Burst Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 5­12 Two SDRAM RD (Read) Commands (Active Row) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 5­13 Two SDRAM WRT (Write) Commands (Active Row) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 5­14 SDRAM ACTV (Activate Row) Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 5­15 SDRAM DCAB (Precharge/Deactivate Row) Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 5­16 SDRAM REFR (Refresh) Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 5­17 SDRAM MRS (Mode Register Set) Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 5­18 McBSP Receive Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 5­19 McBSP Transmit Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 5­20 McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 . . . . . . . . . . . . . . . . . . . . . . . . 123 5­21 McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 . . . . . . . . . . . . . . . . . . . . . . . . 124 5­22 McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 . . . . . . . . . . . . . . . . . . . . . . . . 125 5­23 McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 . . . . . . . . . . . . . . . . . . . . . . . . 126 5­24 MCSI Master Mode Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 5­25 MCSI Slave Mode Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 5­26 Camera Interface Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 5­27 TFT Mode (LCD.HS/LCD.VS on Falling and LCD.Px on Rising LCD.PCLK) . . . . . . . . . . . . . . . . . . 130 5­28 TFT Mode (LCD.HS/LCD.VS on Rising and LCD.Px on Falling LCD.PCLK) . . . . . . . . . . . . . . . . . . 131 August 2002 ­ Revised April 2003 SPRS197A SPRS197A ix Figures Figure Page 5­29 5­30 5­31 5­32 5­33 5­34 5­35 5­36 5­37 5­38 5­39 MMC/SD Host Command Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MMC/SD Card Response Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MMC/SD Host Write Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MMC/SD Host Read and Card CRC Status Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . USB Integrated Transceiver Interface Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Microwire Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OMAP5910 OMAP5910 HDQ Interface Reading From HDQ Slave Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OMAP5910 OMAP5910 HDQ Interface Writing to HDQ Slave Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Typical Communication Between OMAP5910 OMAP5910 HDQ and HDQ Slave . . . . . . . . . . . . . . . . . . . . . . . . . HDQ/1-Wire Break (Reset) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 132 133 133 134 135 136 138 138 138 138 7­1 7­2 OMAP5910 OMAP5910 289-Ball MicroStar BGA Plastic Ball Grid Array (GZG) Package . . . . . . . . . . . . . . . . . OMAP5910 OMAP5910 289-Ball MicroStar BGA Plastic Ball Grid Array (GDY) Package . . . . . . . . . . . . . . . . . 142 143 x SPRS197A SPRS197A August 2002 ­ Revised April 2003 Tables List of Tables Table Page 2­1 2­2 2­3 2­4 GZG BGA Terminal Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GDY BGA Terminal Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Terminal Characteristics and Multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 8 11 19 3­1 3­2 3­3 3­4 3­5 3­6 3­7 3­8 3­9 3­10 3­11 3­12 3­13 3­14 3­15 3­16 3­17 3­18 3­19 3­20 3­21 3­22 3­23 3­24 3­25 3­26 3­27 3­28 3­29 3­30 3­31 3­32 3­33 3­34 3­35 3­36 3­37 3­38 3­39 3­40 3­41 OMAP5910 OMAP5910 MPU Global Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MPU Private Peripheral Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MPU Public Peripheral Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MPU/DSP Shared Peripheral Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DSP Public Peripheral Registers (Accessible via MPUI Port) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MPU Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DSP Global Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DARAM Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SARAM Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DSP Private Peripheral Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DSP Public Peripheral Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DSP/MPU Shared Peripheral Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DSP Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MPU Timer 1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MPU Timer 2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MPU Timer 3 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MPU Watchdog Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MPU Level 1 Interrupt Handler Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MPU Level 2 Interrupt Handler Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . System DMA Controller Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LCD Controller Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . McBSP2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Microwire Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HDQ/1-Wire Interface Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MMC/SD Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . USB Function Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . USB Host Controller Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Camera Interface Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MPU I/O/Keyboard Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PWL Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PWT Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LED Pulse Generator 1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LED Pulse Generator 2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32k Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Real-Time Clock Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Frame Adjustment Counter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OMAP 5910 Pin Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Local Bus Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Local Bus MMU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DSP MMU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 32 32 32 33 33 33 34 34 35 35 35 35 53 53 53 53 54 55 56 59 61 61 62 62 63 64 66 66 67 67 67 67 67 67 68 68 70 70 71 72 August 2002 ­ Revised April 2003 SPRS197A SPRS197A xi Tables Table Page 3­42 3­43 3­44 3­45 3­46 3­47 3­48 3­49 3­50 3­51 3­52 3­53 3­54 3­55 3­56 3­57 3­58 3­59 3­60 3­61 3­62 3­63 3­64 3­65 3­66 3­67 3­68 3­69 3­70 3­71 3­72 3­73 3­74 3­75 MPUI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TIPB (Private) Bridge 1 Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TIPB (Public) Bridge 2 Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MPU UART TIPB Bus Switch Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Traffic Controller Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MPU Clock/Reset/Power Mode Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DPLL1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ultra Low-Power Device Module Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Device Die Identification Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . JTAG Identification Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DSP DMA Controller Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DSP Timer 1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DSP Timer 2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DSP Timer 3 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DSP Watchdog Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DSP Interrupt Interface Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DSP Level 2 Interrupt Handler Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . McBSP1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . McBSP3 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MCSI1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MCSI2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DSP Instruction Cache Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DSP EMIF Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DSP TIPB Bridge Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DSP UART TIPB Bus Switch Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DSP Clock Mode Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UART1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UART2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UART3/IrDA Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MPU/DSP Shared GPIO Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MPU/DSP Shared Mailbox Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MPU Level 1 and Level 2 Interrupt Mappings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DSP Level 1 Interrupt Mappings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DSP Level 2 Interrupt Mappings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 72 73 73 74 74 74 75 75 75 77 80 80 80 80 80 81 82 83 85 86 87 87 87 88 88 90 91 92 93 93 94 96 97 5­1 5­2 5­3 5­4 5­5 5­6 5­7 5­8 5­9 5­10 5­11 5­12 5­13 Thermal Resistance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-kHz Oscillator Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-kHz Input Clock Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Base Oscillator Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal Clock Speed Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OMAP5910 OMAP5910 Device Reset Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OMAP5910 OMAP5910 Device Reset Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MPU_RST Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MPU_RST Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EMIFS/Flash Interface Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EMIFS/Flash Interface Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EMIFF/SDRAM Interface Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EMIFF/SDRAM Interface Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 103 104 105 105 106 106 107 107 108 109 115 115 xii SPRS197A SPRS197A August 2002 ­ Revised April 2003 Tables Table 5­14 5­15 5­16 5­17 5­18 5­19 5­20 5­21 5­22 5­23 5­24 5­25 5­26 5­27 5­28 5­29 5­30 5­31 5­32 5­33 5­34 5­35 Page McBSP Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . McBSP Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0) . . . . . . . . . . McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0) . . . . . . McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0) . . . . . . . . . . McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0) . . . . . . . McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1) . . . . . . . . . . McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1) . . . . . . McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1) . . . . . . . . . . McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1) . . . . . . . MCSI Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MCSI Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Camera Interface Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LCD Controller Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MMC/SD Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MMC/SD Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C Signals (I2C.SDA and I2C.SCL) Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . USB Integrated Transceiver Interface Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . Microwire Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Microwire Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HDQ/1-Wire Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HDQ/1-Wire Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . August 2002 ­ Revised April 2003 SPRS197A SPRS197A 119 121 123 123 124 124 125 125 126 126 127 127 129 130 132 132 134 135 136 136 137 137 xiii Features OMAP5910 OMAP5910 Features D Low-Power, High-Performance CMOS D D D D D D D D Technology ­ 0.13-µm Technology ­ 1.6-V Core Voltage TI925T TI925T (MPU) ARM9TDMI Core ­ Support 32-Bit and 16-Bit (Thumb Mode) Instruction Sets ­ 16K-Byte Instruction Cache ­ 8K-Byte Data Cache ­ Data and Program Memory Management Units (MMUs) ­ Two 64-Entry Translation Look-Aside Buffers (TLBs) for MMUs ­ 17-Word Write Buffer TMS320C55x (C55x) DSP Core ­ One/Two Instructions Executed per Cycle ­ Dual Multipliers (Two MultiplyAccumulates per Cycle) ­ Two Arithmetic/Logic Units ­ One Internal Program Bus ­ Five Internal Data/Operand Buses (3 Read Buses and 2 Write Buses) ­ 32K x 16-Bit On-Chip Dual-Access RAM (DARAM) (64K Bytes) ­ 48K x 16-Bit On-Chip Single-Access RAM (SARAM) (96K Bytes) ­ 16K x 16-Bit On-Chip ROM (32K Bytes) ­ Instruction Cache (24K Bytes) ­ Video Hardware Accelerators for DCT, iDCT, Pixel Interpolation, and Motion Estimation for Video Compression 192K Bytes of Shared Internal SRAM Memory Traffic Controller (TC) ­ 16-Bit EMIFS External Memory Interface to Access up to 128M Bytes of Flash, ROM, or ASRAM ­ 16-Bit EMIFF External Memory Interface to Access up to 64M Bytes of SDRAM 9-Channel System DMA Controller DSP Memory Management Unit Endianism Conversion Logic Digital Phase-Locked Loop (DPLL) for MPU/DSP/TC Clocking Control D DSP Peripherals D D D D D D ­ Three 32-Bit Timers and Watchdog Timer ­ Level1/Level2 Interrupt Handlers ­ Six-Channel DMA Controller ­ Two Multichannel Buffered Serial Ports ­ Two Multichannel Serial Interfaces TI925T TI925T Peripherals ­ Three 32-Bit Timers and Watchdog Timer ­ 32-kHz Timer ­ Level1/Level2 Interrupt Handlers ­ USB2.0 Host Interface With up to 3 Ports ­ USB2.0 Function Interface ­ One Integrated USB Transceiver for Either Host or Function ­ Multichannel Buffered Serial Port ­ Inter-Integrated Circuit (I2C) Master and Slave Interface ­ Microwire Serial Interface ­ Multimedia Card (MMC) and Secure Digital (SD) Interface ­ HDQ/1-Wire Interface ­ Camera Interface for CMOS Sensors ­ ETM9 Trace Module for TI925T TI925T Debug ­ Keyboard Matrix Interface (6 x 5 or 8 x 8) ­ Up to Ten MPU General-Purpose I/Os ­ Pulse-Width Tone (PWT) Interface ­ Pulse-Width Light (PWL) Interface ­ Two LED Pulse Generators (LPGs) ­ Real-Time Clock (RTC) ­ LCD Controller With Dedicated System DMA Channel Shared Peripherals ­ Three Universal Asynchronous Receiver/Transmitters (UARTs) (One Supporting SIR Mode for IrDA) ­ Four Interprocessor Mailboxes ­ Up to 14 Shared General-Purpose I/Os Individual Power-Saving Modes for MPU/DSP/TC On-Chip Scan-Based Emulation Logic IEEE Std 1149.1 (JTAG) Boundary Scan Logic Two 289-Ball MicroStar BGA (Ball Grid Array) Package Options (GZG and GDY Suffixes) PRODUCT PREVIEW 1 TMS320C55x, C55x, and MicroStar BGA are trademarks of Texas Instruments. ARM9TDMI is a trademark of ARM Limited. Thumb is a registered trademark of ARM Limited. Microwire is a trademark of National Semiconductor Corporation. 1-Wire is a registered trademark of Dallas Semiconductor Corporation. IEEE Standard 1149.1-1990 Standard Test-Access Port and Boundary Scan Architecture. August 2002 ­ Revised April 2003 SPRS197A SPRS197A 1 Introduction 2 Introduction This section describes the main features of the OMAP5910 OMAP5910 device, lists the terminal assignments, and describes the function of each terminal. This data manual also provides a detailed description section, electrical specifications, parameter measurement information, and mechanical data about the available packaging. 2.1 Description The OMAP5910 OMAP5910 is a highly integrated hardware and software platform, designed to meet the application processing needs of next-generation embedded devices. The OMAP platform enables OEMs and ODMs to quickly bring to market devices featuring rich user interfaces, high processing performance, and long battery life through the maximum flexibility of a fully integrated mixed processor solution. The dual-core architecture provides benefits of both DSP and RISC technologies, incorporating a TMS320C55x DSP core and a high-performance TI925T TI925T ARM core. PRODUCT PREVIEW The OMAP5910 OMAP5910 device is designed to run leading open and embedded RISC-based operating systems, as well as the Texas Instruments (TI) DSP/BIOS software kernel foundation, and is available in a 289-ball MicroStar BGA package. The OMAP5910 OMAP5910 is targeted at the following applications: · · Applications processing devices Mobile communications ­ ­ ­ ­ ­ · · · · · · 802.11 Bluetooth wireless technology GSM (including GPRS and EDGE) CDMA Proprietary government and other Video and image processing (MPEG4, JPEG, Windows Media Video, etc.) Advanced speech applications (text-to-speech, speech recognition) Audio processing (MPEG-1 Audio Layer3 [MP3], AMR, WMA, AAC, and other GSM speech codecs) Graphics and video acceleration Generalized web access Data processing (fax, encryption/decryption, authentication, signature verification and watermarking) 2.1.1 TMS320C55x DSP Core The DSP core of the OMAP5910 OMAP5910 device is based on the TMS320C55x DSP generation CPU processor core. The C55x DSP architecture achieves high performance and low power through increased parallelism and total focus on reduction in power dissipation. The CPU supports an internal bus structure composed of one program bus, three data read buses, two data write buses, and additional buses dedicated to peripheral and DMA activity. These buses provide the ability to perform up to three data reads and two data writes in a single cycle. In parallel, the DMA controller can perform up to two data transfers per cycle independent of the CPU activity. OMAP and DSP/BIOS are trademarks of Texas Instruments. Bluetooth is a trademark owned by Bluetooth SIG, Inc. Windows is a registered trademark of Microsoft Corporation. Other trademarks are the property of their respective owners. 2 SPRS197A SPRS197A August 2002 ­ Revised April 2003 Introduction The C55x CPU provides two multiply-accumulate (MAC) units, each capable of 17-bit x 17-bit multiplication in a single cycle. A central 40-bit arithmetic/logic unit (ALU) is supported by an additional 16-bit ALU. Use of the ALUs is under instruction set control, providing the ability to optimize parallel activity and power consumption. These resources are managed in the address unit (AU) and data unit (DU) of the C55x CPU. The C55x DSP generation supports a variable byte width instruction set for improved code density. The instruction unit (IU) performs 32-bit program fetches from internal or external memory and queues instructions for the program unit (PU). The program unit decodes the instructions, directs tasks to AU and DU resources, and manages the fully protected pipeline. Predictive branching capability avoids pipeline flushes on execution of conditional instructions. The OMAP5910 OMAP5910 DSP core also includes a 24K-byte instruction cache to minimize external memory accesses, improving data throughput and conserving system power. DSP Tools Support The 55x DSP core is supported by the industry's leading eXpressDSP software environment including the Code Composer Studio integrated development environment, DSP/BIOS software kernel foundation, the TMS320 TMS320 DSP Algorithm Standard, and the industry's largest third-party network. Code Composer Studio features code generation tools including a C-Compiler, Visual Linker, simulator, Real-Time Data Exchange (RTDX), XDS510 XDS510 emulation device drivers, and Chip Support Libraries (CSL). DSP/BIOS is a scalable real-time software foundation available for no cost to users of Texas Instruments' DSP products providing a preemptive task scheduler and real-time analysis capabilities with very low memory and megahertz overhead. The TMS320 TMS320 DSP Algorithm Standard is a specification of coding conventions allowing fast integration of algorithms from different teams, sites, or third parties into the application framework. Texas Instruments' extensive DSP third-party network of over 400 providers brings focused competencies and complete solutions to customers. 2.1.1.2 DSP Software Support Texas Instruments has also developed foundation software available for the 55x DSP core. The C55x DSP Library (DSPLIB) features over 50 C-callable software kernels (FIR/IIR filters, Fast Fourier Transforms (FFTs), and various computational functions). The DSP Image/Video Processing Library (IMGLIB) contains over 20 software kernels highly optimized for C55x DSPs and is compiled with the latest revision of the C55x DSP code generation tools. These imaging functions support a wide range of applications that include compression, video processing, machine vision, and medical imaging. 2.1.2 TI-Enhanced TI925T TI925T RISC Processor The MPU core is a TI925T TI925T reduced instruction set computer (RISC) processor. The TI925T TI925T is a 32-bit processor core that performs 32-bit or 16-bit instructions and processes 32-bit, 16-bit, or 8-bit data. The core uses pipelining so that all parts of the processor and memory system can operate continuously. The MPU core incorporates: · A coprocessor 15 (CP15) and protection module · Data and program Memory Management Units (MMUs) with table look-aside buffers. · A separate 16K-byte instruction cache and 8K-byte data cache. Both are two-way associative with virtual index virtual tag (VIVT). · A 17-word write buffer (WB) The OMAP5910 OMAP5910 device uses the TI925T TI925T core in little endian mode only. To reduce effective memory access time, the TI925T TI925T has an instruction cache, a data cache, and a write buffer. In general, these are transparent to program execution. eXpressDSP, Code Composer Studio, TMS320 TMS320, RTDX, and XDS510 XDS510 are trademarks of Texas Instruments. August 2002 ­ Revised April 2003 SPRS197A SPRS197A 3 PRODUCT PREVIEW 2.1.1.1 Introduction 2.2 Terminal Assignments Figure 2­1 illustrates the ball locations for the 289-ball GZG ball grid array (BGA) package and is used in conjunction with Table 2­1 to locate signal names and ball grid numbers. GZG BGA ball numbers in Table 2­1 are read from left-to-right, top-to-bottom. Y V T P M K H F PRODUCT PREVIEW D B AA W U R N L J G E C A 1 3 2 5 4 7 6 9 11 13 15 17 19 21 8 10 12 14 16 18 20 Figure 2­1. OMAP5910 OMAP5910 GZG MicroStar BGA Package (Bottom View) · signal1/signal2/signal3 (for example, GPIO11/HDQ GPIO11/HDQ) Signals which are associated with specific peripherals are denoted by using the peripheral name, followed by a period, and then the signal name; as follows: · peripheral1.signal1 (for example, MCBSP1.DR) Table 2­1. GZG BGA Terminal Assignments GZG BGA BALL # SIGNAL GZG BGA BALL # SIGNAL GZG BGA BALL # SIGNAL A1 DVDD4 A2 A7 DVDD4 A9 A15 DVDD1 A17 SDRAM.RAS A3 CVDD LCD.P[13] A11 A21 VSS SDRAM.D[13] B1 B4 A19 VSS VSS B2 B5 B6 GZG BGA BALL # SIGNAL CVDD1 A5 DVDD4 VSS DVDD1 A13 A20 VSS LCD.P[5] VSS SDRAM.D[8] B3 SDRAM.DQML B7 VSS DVDD4 B8 B9 SDRAM.D[0] B10 B14 SDRAM.A[0] B15 DVDD4 LCD.AC B12 CVDD3 B17 LCD.P[11] B18 LCD.P[6] B20 LCD.P[1] C1 VSS FLASH.A[3] B19 B21 C2 SDRAM.D[14] C5 SDRAM.D[11] C6 DVDD5 SDRAM.D[9] C3 C4 C7 SDRAM.D[6] C8 SDRAM.D[2] C9 SDRAM.CLK C10 SDRAM.BA[0] C11 SDRAM.A[10] C12 SDRAM.A[7] C13 SDRAM.A[4] C14 SDRAM.A[1] C15 LCD.PCLK C16 LCD.P[14] C17 LCD.P[10] C18 LCD.P[7] C19 LCD.P[2] C20 KB.C[5] C21 KB.C[4] D2 FLASH.A[5] D3 FLASH.A[2] D4 4 SDRAM.D[4] B13 SDRAM.DQMU D5 SDRAM.D[15] D6 SDRAM.D[12] D7 SDRAM.D[7] SPRS197A SPRS197A B16 VSS CVDD3 SDRAM.WE August 2002 ­ Revised April 2003 Introduction Table 2­1. GZG BGA Terminal Assignments (Continued) SIGNAL GZG BGA BALL # SIGNAL GZG BGA BALL # SIGNAL GZG BGA BALL # SIGNAL D8 SDRAM.D[5] D9 SDRAM.CKE D10 SDRAM.BA[1] D11 SDRAM.A[9] D12 SDRAM.A[6] D13 SDRAM.A[3] D14 LCD.VS D15 LCD.P[15] D16 LCD.P[9] D17 LCD.P[8] D18 LCD.P[0] D19 KB.C[2] D20 KB.C[1] E1 DVDD5 E2 E3 FLASH.A[7] E4 FLASH.A[4] E5 RSVD E18 VSS KB.C[3] E19 KB.R[4] E20 KB.R[3] E21 F18 F19 CVDD KB.R[1] FLASH.A[9] FLASH.A[6] DVDD1 KB.C[0] F3 F4 F20 G1 VSS SDRAM.D[3] G2 FLASH.A[12] G3 FLASH.A[11] G4 VSS FLASH.A[10] G9 SDRAM.D[1] G10 SDRAM.A[12] G11 SDRAM.A[8] G12 SDRAM.A[2] G13 LCD.P[12] G14 LCD.P[3] G18 KB.R[0] G19 PWRON_RESET G20 MCBSP1.CLKS G21 MCBSP1.CLKX H2 H3 FLASH.A[15] H4 FLASH.A[14] H7 FLASH.RDY H8 DVDD5 SDRAM.D[10] H9 SDRAM.CAS H10 SDRAM.A[11] H11 SDRAM.A[5] H12 LCD.HS H13 LCD.P[4] H14 KB.R[2] H15 MCBSP1.FSX/ MCBSP1.DX H18 MCBSP1.DX/ MCBSP1.FSX H19 CAM.EXCLK/ ETM.SYNC/ UWIRE.SDO H20 MCBSP1.DR J1 FLASH.A[20] J2 FLASH.A[17] J3 FLASH.A[19] J4 FLASH.A[18] J7 FLASH.A[8] J8 FLASH.A[1] J14 CAM.D[5]/ ETM.D[5]/ UWIRE.SDI J15 CAM.LCLK/ ETM.CLK/ UWIRE.SCLK J18 CAM.D[7]/ ETM.D[7]/ UWIRE.CS0 J19 CAM.D[6]/ ETM.D[6]/ UWIRE.CS3 J20 VSS J21 CVDD3 K2 VSS K3 FLASH.A[23] G8 F2 K4 FLASH.A[22] K7 FLASH.A[16] K8 FLASH.A[13] K14 CAM.D[1]/ETM.D[1]/ UART3.RTS K15 CAM.D[2]/ ETM.D[2]/ UART3.CTS K18 CAM.D[4]/ ETM.D[4]/ UART3.TX K19 CAM.D[3]/ ETM.D[3]/ UART3.RX K20 VSS L1 DVDD5 L3 FLASH.BE[0] L4 FLASH.ADV L7 FLASH.A[24] L8 FLASH.A[21] L14 UART3.RX/PWL/ UART2.RX L15 CAM.HS/ ETM.PSTAT[1]/ UART2.CTS L18 CAM.VS/ ETM.PSTAT[2] L19 CAM.D[0]/ ETM.D[0]/ MPUIO12 MPUIO12 L21 DVDD1 M2 CVDD4 M3 FLASH.CS1 M4 FLASH.CS2/ FLASH.BAA M7 FLASH.CS0 M8 FLASH.BE[1] M14 GPIO2/ SPI.CLK M15 GPIO7/ MMC.DAT2 M18 UART3.TX/ PWT/ UART2.TX M19 CAM.RSTZ/ ETM.PSTAT[0]/ UART2.RTS M20 GPIO15/ GPIO15/ KB.R[7] N1 VSS N2 FLASH.D[1] N3 FLASH.CLK N4 FLASH.D[0] N15 MPUIO2/ EXT_DMA_REQ0 N7 FLASH.D[2] N8 FLASH.CS3 N14 UWIRE.CS0/ MCBSP3.CLKX N18 GPIO12/ GPIO12/ MCBSP3.FSX N19 GPIO13/ GPIO13/ KB.R[5] N20 GPIO11/ GPIO11/ HDQ N21 GPIO14/ GPIO14/ KB.R[6] P2 FLASH.D[3] P3 DVDD5 P4 FLASH.D[4] P7 FLASH.D[5] P11 MMC.CMD/SPI.DO P15 UWIRE.CS3/ KB.C[6] P8 FLASH.D[11] P9 USB0.DP P10 MCBSP2.DR/ MCBSP2.DX P12 CVDD P13 CLK32K CLK32K_IN P14 RST_HOST_OUT/ MCBSP3.DX/ USB1.SE0 August 2002 ­ Revised April 2003 SPRS197A SPRS197A 5 PRODUCT PREVIEW GZG BGA BALL # Introduction Table 2­1. GZG BGA Terminal Assignments (Continued) GZG BGA BALL # SIGNAL GZG BGA BALL # SIGNAL GZG BGA BALL # SIGNAL GZG BGA BALL # SIGNAL P18 GPIO3/ SPI.CS3/ MCBSP3.FSX/LED1 P19 GPIO6/ SPI.CS1/ MCBSP3.FSX P20 GPIO4/ SPI.CS2/ MCBSP3.FSX R1 DVDD5 R2 FLASH.D[6] R3 FLASH.D[7] R4 FLASH.D[8] R8 USB.DM R9 UART2.RX/ USB2.VM R10 MCLKREQ/EXT_ MASTER_REQ R11 MMC.DAT0/SPI.DI R12 OSC32K OSC32K_OUT R13 BCLKREQ/ UART3.CTS/ UART1.DSR R14 UART1.CTS R18 GPIO0/ SPI.RDY/ USB.VBUS R19 GPIO1/ UART3.RTS R20 CVDD3 R21 VSS T2 FLASH.D[9] T3 FLASH.D[10] T20 MPUIO5/ LOW_PWR FLASH.D[14] T18 I2C.SCL T19 U1 FLASH.D[12] U2 VSS U3 FLASH.D[13] U4 FLASH.OE U18 PRODUCT PREVIEW T4 MPUIO4/ EXT_DMA_REQ1/ LED2 UWIRE.SDI/ UART3.DSR/ UART1.DSR/ MCBSP3.DR U19 MPUIO1 U20 VSS U21 DVDD1 V3 FLASH.D[15] V4 FLASH.WP V5 V7 MCBSP2.CLKR/ GPIO11 GPIO11 V8 MPUIO3 V9 VSS MCSI2.SYNC/ GPIO7 MMC.CLK V12 VSS V13 MCSI1.SYNC/ USB1.VP V2 DVDD5 UART2.TX/ USB2.TXD V6 V10 MMC.DAT1/ MPUIO7 V11 V14 UART1.RX V15 MPU_RST V16 EMU0 V17 TMS V20 I2C.SDA W1 FLASH.RP V18 CONF V19 UWIRE.SCLK/ KB.C[7] W2 FLASH.WE W3 OSC1_OUT W4 USB.PUEN/ USB.CLKO W5 UART2.RTS/ USB2.SE0/ MPUIO5 W6 MCBSP2.FSR/ GPIO12 GPIO12 W7 MCBSP2.FSX W8 GPIO9 W9 MCSI2.DOUT/ USB2.TXEN W10 MMC.DAT2/ MPUIO11 MPUIO11 W11 MMC.DAT3/ MPUIO6 W12 OSC32K OSC32K_IN W13 MCSI1.DIN/ USB1.RCV W14 MCSI1.DOUT/ USB1.TXD W15 RST_OUT W16 MCBSP3.CLKX/ USB1.TXEN W17 EMU1 W20 VSS W21 UWIRE.SDO/ UART3.DTR/ UART1.DTR/ MCBSP3.DX W18 W19 Y1 CVDD2 Y2 OSC1_IN Y3 VSS Y4 UART2.BCLK Y5 UART2.CTS/ USB2.RCV/ GPIO7 Y6 MCBSP2.CLKX Y7 DVDD3 Y8 GPIO8 Y9 MCLK Y10 MCSI2.CLK/ USB2.SUSP Y12 CLK32K CLK32K_OUT/ MPUIO0/ USB1.SPEED Y13 BCLK/ UART3.RTS/ UART1.DTR Y14 UART1.TX Y15 VSS Y16 DVDD1 Y17 STAT_VAL/ WKUP Y18 TRST Y19 TDI Y20 CVDD Y21 AA1 VSS AA2 DVDD2 AA3 CVDD2 AA5 AA7 6 TCK BFAIL/ EXT_FIQ VSS AA9 MCSI2.DIN/ USB2.VP AA11 DVDD1 AA13 SPRS197A SPRS197A CVDDA MCBSP2.DX/ MCBSP2.DR MCSI1.CLK/ USB1.VM August 2002 ­ Revised April 2003 Introduction Table 2­1. GZG BGA Terminal Assignments (Continued) GZG BGA BALL # SIGNAL GZG BGA BALL # SIGNAL GZG BGA BALL # SIGNAL GZG BGA BALL # SIGNAL AA15 UART1.RTS AA17 MPU_BOOT/ MCBSP3.DR/ USB1.SUSP AA19 TDO AA20 CLK32K CLK32K_CTRL AA21 VSS Figure 2­2 illustrates the ball locations for the 289-ball GDY ball grid array (BGA) package and is used in conjunction with Table 2­1 to locate signal names and ball grid numbers. GDY BGA ball numbers in Figure 2­2 are read from left-to-right, top-to-bottom. PRODUCT PREVIEW A B C D E F G H J K L M N P R T U 1 2 3 4 5 6 7 8 9 10 11 1213 14 15 16 17 BOTTOM VIEW Figure 2­2. OMAP5910 OMAP5910 GDY MicroStar BGA Package (Bottom View) In Table 2­2, signals with multiplexed functions are highlighted in gray. Signals within a multiplexed pin name are separated with forward slashes as follows: Figure 2­2 illustrates the ball locations for the 289-ball GDY ball grid array (BGA) package and is used in conjunction with Table 2­1 to locate signal names and ball grid numbers. GDY BGA ball numbers in Table 2­2 are read from left-to-right, top-to-bottom. · signal1/signal2/signal3 (for example, GPIO11/HDQ GPIO11/HDQ) Signals which are associated with specific peripherals are denoted by using the peripheral name, followed by a period, and then the signal name; as follows: · peripheral1.signal1 (for example, MCBSP1.DR) August 2002 ­ Revised April 2003 SPRS197A SPRS197A 7 Introduction Table 2­2. GDY BGA Terminal Assignments SIGNAL GDY BGA BALL # SIGNAL GDY BGA BALL # A1 SDRAM.WE A2 SDRAM.DQMU A5 DVDD4 A6 SDRAM.D[0] A9 SDRAM.A[5] A10 SDRAM.A[1] A13 LCD.P[9] A14 A17 KB.C[5] B1 DVDD1 FLASH.A[1] B4 SDRAM.D[12] B5 SDRAM.D[11] B8 SDRAM.BA[0] B9 B12 LCD.P[13] B16 LCD.P[0] C3 FLASH.RDY C7 SDRAM.D[3] C11 C15 SIGNAL GDY BGA BALL # SIGNAL A3 SDRAM.D[9] A4 SDRAM.D[6] A7 SDRAM.CLK A8 SDRAM.A[9] A11 LCD.AC A12 LCD.PCLK A15 LCD.P[6] A16 LCD.P[3] B2 SDRAM.DQML B3 B6 SDRAM.D[5] B7 CVDD1 SDRAM.D[2] SDRAM.A[11] B10 SDRAM.A[2] B11 SDRAM.A[0] B13 LCD.P[11] B14 LCD.P[7] B15 LCD.P[4] B17 KB.C[3] C1 FLASH.A[3] C2 FLASH.A[4] C4 SDRAM.RAS C5 SDRAM.D[14] C6 SDRAM.D[10] C8 SDRAM.A[12] C9 SDRAM.BA[1] C10 SDRAM.A[8] SDRAM.A[3] C12 LCD.P[14] C14 LCD.P[8] C16 DVDD1 LCD.P[1] C13 LCD.P[5] C17 KB.C[0] D1 DVDD5 D2 FLASH.A[7] D3 SDRAM.D[15] D5 SDRAM.D[7] D7 DVDD4 SDRAM.CKE D4 D6 D8 DVDD4 D9 DVDD4 SDRAM.A[6] D10 SDRAM.A[4] D11 LCD.VS D12 LCD.P[15] D13 KB.R[0] D14 KB.R[1] D15 LCD.P[2] D16 KB.C[4] D17 KB.R[4] E1 FLASH.A[12] E2 FLASH.A[5] E4 FLASH.A[6] VSS SDRAM.A[10] CVDD SDRAM.D[8] E3 E5 PRODUCT PREVIEW GDY BGA BALL # E7 SDRAM.D[1] E8 E10 DVDD4 DVDD1 E11 LCD.HS E12 CVDD LCD.P[10] E9 E13 E6 VSS KB.R[3] E14 E15 KB.C[2] E16 KB.C[1] F2 FLASH.A[11] F3 FLASH.A[9] F5 DVDD5 FLASH.A[8] F4 FLASH.A[10] F8 SDRAM.CAS F6 SDRAM.D[4] SDRAM.A[7] F10 F11 LCD.P[12] VSS MCBSP1.FSX/ MCBSP1.DX F13 MCBSP1.CLKS F14 VSS CVDD3 PWRON_RESET F7 F9 F12 F15 KB.R[2] F17 MCBSP1.DX/ MCBSP1.FSX G1 FLASH.A[16] G2 FLASH.A[17] G3 FLASH.A[14] G4 FLASH.A[13] G5 FLASH.A[15] G6 FLASH.A[2] G7 VSS G8 SDRAM.D[13] G9 G10 G13 VSS CAM.EXCLK/ ETM.SYNC/ UWIRE.SDO CVDD3 CAM.D[7]/ ETM.D[7]/ UWIRE.CS0 E17 F16 F1 G11 G12 G15 MCBSP1.CLKX G16 MCBSP1.DR G17 CAM.D[3]/ ETM.D[3]/ UART3.RX H1 FLASH.ADV H2 FLASH.A[20] H3 FLASH.A[18] H4 FLASH.A[19] H5 FLASH.A[21] H6 FLASH.A[22] H7 DVDD5 H8 VSS VSS H11 CVDD3 H12 VSS UART3.RX/PWL/ UART2.RX H9 H10 H13 DVDD1 H14 CAM.D[1]/ETM.D[1]/ UART3.RTS H15 CAM.LCLK/ ETM.CLK/ UWIRE.SCLK H16 CAM.D[5]/ ETM.D[5]/ UWIRE.SDI H17 CAM.D[2]/ ETM.D[2]/ UART3.CTS J1 FLASH.BE[1] J2 FLASH.CS0 J3 FLASH.A[24] J4 FLASH.A[23] J5 FLASH.BE[0] J6 J10 VSS VSS J8 VSS VSS VSS J7 J9 8 VSS CAM.D[6]/ ETM.D[6]/ UWIRE.CS3 VSS VSS SPRS197A SPRS197A J11 G14 J12 August 2002 ­ Revised April 2003 Introduction Table 2­2. GDY BGA Terminal Assignments (Continued) GDY BGA BALL # SIGNAL GDY BGA BALL # SIGNAL GDY BGA BALL # SIGNAL GDY BGA BALL # SIGNAL J13 UART3.TX/ PWT/ UART2.TX J14 CAM.RSTZ/ ETM.PSTAT[0]/ UART2.RTS J15 CAM.D[4]/ ETM.D[4]/ UART3.TX J16 CAM.D[0]/ ETM.D[0]/ MPUIO12 MPUIO12 J17 CAM.VS/ ETM.PSTAT[2] K1 FLASH.CS1 K2 CVDD4 K3 FLASH.D[1] K4 FLASH.CLK K5 FLASH.CS2/ FLASH.BAA K6 DVDD5 K7 CVDD2 K8 VSS GPIO3/ SPI.CS3/ MCBSP3.FSX/LED1 K9 K10 VSS K11 K14 GPIO13/ GPIO13/ KB.R[5] K15 CVDD3 CAM.HS/ ETM.PSTAT[1]/ UART2.CTS K12 K13 VSS GPIO6/ SPI.CS1/ MCBSP3.FSX GPIO15/ GPIO15/ KB.R[7] K17 GPIO14/ GPIO14/ KB.R[6] L1 FLASH.CS3 L2 DVDD5 L3 DVDD5 L4 FLASH.D[2] L5 FLASH.D[0] L6 FLASH.D[3] L7 VSS L8 CVDD2 L9 VSS L10 BCLKREQ/ UART3.CTS/ UART1.DSR L11 VSS L12 UWIRE.CS3/ KB.C[6] L13 MPUIO5/ LOW_PWR L14 GPIO4/ SPI.CS2/ MCBSP3.FSX L15 GPIO12/ GPIO12/ MCBSP3.FSX L16 GPIO11/ GPIO11/ HDQ L17 GPIO7/ MMC.DAT2 M1 FLASH.D[4] M2 FLASH.D[5] M3 FLASH.D[11] M4 FLASH.D[6] M5 FLASH.D[7] M8 GPIO9 M9 MMC.DAT1/ MPUIO7 PRODUCT PREVIEW K16 M6 VSS M7 UART2.RX/ USB2.VM M10 UART1.CTS M11 RST_OUT M12 VSS M13 UWIRE.SCLK/ KB.C[7] M14 MPUIO1 M15 GPIO2/ SPI.CLK M16 GPIO0/ SPI.RDY/ USB.VBUS M17 GPIO1/ UART3.RTS N1 FLASH.D[9] N2 FLASH.D[13] N3 FLASH.OE N4 FLASH.D[8] N7 DVDD3 N8 MCLKREQ/ EXT_MASTER_REQ N5 VSS N6 UART2.CTS/ USB2.RCV/ GPIO7 N9 CLK32K CLK32K_IN N10 CLK32K CLK32K_OUT/ MPUIO0/ USB1.SPEED N11 RSVD N12 MCSI1.DOUT/ USB1.TXD N13 VSS N14 I2C.SDA N15 MPUIO4/ EXT_DMA_REQ1/ LED2 N16 DVDD1 N17 MPUIO2/ EXT_DMA_REQ0 P1 FLASH.D[10] P2 FLASH.WE P3 OSC1_OUT P4 USB.DM P5 USB0.DP P6 MCBSP2.FSR/ GPIO12 GPIO12 P7 MPUIO3 P8 MCSI2.DIN/ USB2.VP P9 DVDD1 P10 CVDD P11 BCLK/ UART3.RTS/ UART1.DTR P12 MPU_RST P13 UART1.TX P14 MCBSP3.CLKX/ USB1.TXEN P15 I2C.SCL P16 UWIRE.SDO/ UART3.DTR/ UART1.DTR/ MCBSP3.DX P17 UWIRE.SDI/ UART3.DSR/ UART1.DSR/ MCBSP3.DR R1 FLASH.D[12] R2 OSC1_IN August 2002 ­ Revised April 2003 SPRS197A SPRS197A 9 Introduction Table 2­2. GDY BGA Terminal Assignments (Continued) SIGNAL GDY BGA BALL # SIGNAL GDY BGA BALL # SIGNAL GDY BGA BALL # SIGNAL R3 FLASH.WP R4 UART2.TX/ USB2.TXD R5 MCBSP2.DX/ MCBSP2.DR R6 MCBSP2.DR/ MCBSP2.DX R7 MCSI2.SYNC/ GPIO7 R8 MMC.DAT2/ MPUIO11 MPUIO11 R9 MMC.DAT3/ MPUIO6 R10 MCSI1.DIN/ USB1.RCV R11 UART1.RX R12 MPU_BOOT/ MCBSP3.DR/ USB1.SUSP R13 TMS R14 BFAIL/ EXT_FIQ R15 CVDDA R16 UWIRE.CS0/ MCBSP3.CLKX R17 EMU0 T1 FLASH.D[14] T2 FLASH.RP T3 USB.PUEN/ USB.CLKO T4 UART2.BCLK T5 MCBSP2.CLKR/ GPIO11 GPIO11 T6 MCBSP2.FSX T7 MCSI2.DOUT/ USB2.TXEN T8 MCSI2.CLK/ USB2.SUSP T9 OSC32K OSC32K_OUT T10 OSC32K OSC32K_IN T11 MCSI1.SYNC/ USB1.VP T12 DVDD1 T13 EMU1 T14 PRODUCT PREVIEW GDY BGA BALL # TCK T15 CLK32K CLK32K_CTRL T16 CONF T17 U1 DVDD5 U2 FLASH.D[15] U3 DVDD2 U4 CVDD UART2.RTS/ USB2.SE0/ MPUIO5 U5 MCBSP2.CLKX U6 GPIO8 U7 MCLK U8 MMC.CMD/SPI.DO U9 MMC.DAT0/SPI.DI U10 MMC.CLK U11 MCSI1.CLK/ USB1.VM U12 UART1.RTS U13 RST_HOST_OUT/ MCBSP3.DX/ USB1.SE0 U14 STAT_VAL/ WKUP U15 TRST U16 TDO U17 TDI 2.3 Terminal Characteristics and Multiplexing Table 2­3 describes terminal characteristics and the signals multiplexed on each ball. The table column headers are explained below: · · TYPE: The terminal type when a particular signal is multiplexed on the terminal. · MUX CTRL SETTING: The register field that controls multiplexing on the terminal and the proper register field setting necessary to select the signal to be multiplexed on the terminal. The reset values of these register fields are indicated in bold type. · DESELECTED INPUT STATE: The logic level internally driven to the signal when it is not selected to be multiplexed on the corresponding terminal. · PULLUP/PULLDN: Denotes the presence of an internal pullup or pulldown. Pullups and pulldowns can be enabled or disabled via software. · BUFFER STRENGTH: Drive strength of the associated output buffer. · OTHER: Contains various terminal information, such as buffer type, boundary scan capability, and gating/inhibit functionality. [Certain terminals may be gated or 3-stated based on the state of other terminals and/or software configuration register settings. · 10 SIGNAL NAME: The names of all the signals that are multiplexed on each ball. RESET STATE: The state of the terminal at reset. SPRS197A SPRS197A August 2002 ­ Revised April 2003 Introduction · SUPPLY: The voltage supply which powers the terminal's I/O buffers. NOTE: Due to the extensive pin multiplexing options which are available on the OMAP5910 OMAP5910 device, a software utility is available to ease the process of configuring the pins based on the peripheral set required by a specific application. The 5910 OMAP Pin Configuration Utility is currently available from Texas Instruments. NOTE: Configuring two pins to the same input signal is not supported as it can yield unexpected results. This can be easily avoided with proper software configuration. Table 2­3. Terminal Characteristics and Multiplexing TYPE MUX CTRL SETTING DESELEC TED INPUT STATE SDRAM.WE O/Z NA SDRAM.RAS O/Z NA SDRAM.DQMU O/Z SDRAM.DQML SDRAM.D[15:0] SDRAM.CKE PULLUP/ PULLDN§ OTHER¶ RESET STATE# SUPPLY NA 4 mA A, H2 1 DVDD4 NA 4 mA A, H2 1 DVDD4 NA NA 4 mA A, H2 1 DVDD4 O/Z NA NA 4 mA A, H2 1 DVDD4 I/O/Z NA NA 4 mA E 0 DVDD4 O/Z NA NA 4 mA A, H2 1 DVDD4 SDRAM.CLK I/O/Z NA NA 8 mA E, H2 LZ DVDD4 SDRAM.CAS O/Z NA NA 4 mA A, H2 1 DVDD4 SDRAM.BA[1:0] O/Z NA NA 4 mA A, H2 0 DVDD4 SDRAM.A[12:0] O/Z NA NA 4 mA A, H2 0 DVDD4 LCD.VS O NA NA 4 mA J, A, G1 0 DVDD1 LCD.HS O NA NA 4 mA J, A, G1 0 DVDD1 LCD.AC O NA NA 4 mA J, A, G1 0 DVDD1 LCD.PCLK O NA NA 4 mA J, A, G1 0 DVDD1 LCD.P[15:0] O NA NA 4 mA J, A, G1 0 DVDD1 KB.C[5:0] O NA NA 4 mA A, J 0 DVDD1 KB.R[4:0] I NA NA A, J input DVDD1 PWRON_RESET I NA NA B, J input DVDD1 MCBSP1.CLKS I NA NA B, J input DVDD1 MCBSP1.CLKX I/O/Z NA NA 4 mA J, B, G1 Z DVDD1 MCBSP1.FSX I/O/Z reg4[14:12] = 000 0 4 mA J, B, G1 , , Z DVDD1 MCBSP1.DX O reg4[14:12] = 001 NA MCBSP1.DX O reg4[17:15] = 000 NA 4 mA J, B, G1 , , 0 DVDD1 MCBSP1.FSX I/O/Z reg4[17:15] = 001 0 PRODUCT PREVIEW BUFFER STRENGTH SIGNAL NAME MCBSP1.DR I NA NA PD20 B,J input DVDD1 I = Input, O = Output, Z = High-Impedance 'regx' denotes the terminal multiplexing register that controls the specified terminal where regx = FUNC_MUX_CTRL_x § PD20 = 20-µA internal pulldown, PD100 PD100 = 100-µA pulldown, PU20 = 20-µA internal pullup, PU100 PU100 = 100-µA internal pullup ¶ A = Standard LVCMOS input/output G1 = Terminal may be gated by BFAIL B = Fail-safe LVCMOS input/output G2 = Terminal may be gated by GPIO9 and MPUIO3 C = USB transceiver input/output G3 = Terminal may be gated by BFAIL and OMAP5910 OMAP5910 internal reset D = I2C input/output buffers H1 = Terminal may be 3-stated by BFAIL input E = Fail-safe LVCMOS input and Standard LVCMOS output H2 = Terminal may be 3-stated via software configuration F = analog oscillator terminals J = Boundary-scannable terminal # Z = High-Impedance, LZ = Low-Impedance (pin is driven), 1 = Output driven high, 0 = Output driven low || UART1 signals can be multiplexed to this pin via additional multiplexing in the USB module. August 2002 ­ Revised April 2003 SPRS197A SPRS197A 11 Introduction Table 2­3. Terminal Characteristics and Multiplexing (Continued) TYPE MUX CTRL SETTING DESELEC TED INPUT STATE CAM.EXCLK O reg4[23:21] = 000 NA ETM.SYNC O reg4[23:21] = 001 NA UWIRE.SDO O reg4[23:21] = 010 NA CAM.LCLK I reg4[26:24] = 000 0 ETM.CLK O reg4[26:24] = 001 NA UWIRE.SCLK O reg4[26:24] = 010 NA CAM.D[7] I reg4[29:27] = 000 NA ETM.D[7] O reg4[29:27] = 001 NA UWIRE.CS0 O reg4[29:27] = 010 NA CAM.D[6] I reg5[2:0] = 000 NA ETM.D[6] O reg5[2:0] = 001 NA UWIRE.CS3 O reg5[2:0] = 010 NA CAM.D[5] I reg5[5:3] = 000 NA ETM.D[5] O reg5[5:3] = 001 NA UWIRE.SDI I reg5[5:3] = 010 NA CAM.D[4] I reg5[8:6] = 000 NA ETM.D[4] O reg5[8:6] = 001 NA UART3.TX O reg5[8:6] = 010 NA CAM.D[3] I reg5[11:9] = 000 NA ETM.D[3] O reg5[11:9] = 001 NA UART3.RX I reg5[11:9] = 010 NA CAM.D[2] I reg5[14:12] = 000 NA ETM.D[2] O reg5[14:12] = 001 NA UART3.CTS I reg5[14:12] = 010 NA CAM.D[1] I reg5[17:15] = 000 NA ETM.D[1] O reg5[17:15] = 001 NA UART3.RTS O reg5[17:15] = 010 NA CAM.D[0] I reg5[20:18] = 000 NA ETM.D[0] O reg5[20:18] = 001 NA MPUIO12 MPUIO12 I/O/Z reg5[20:18] = 010 NA PRODUCT PREVIEW SIGNAL NAME PULLUP/ PULLDN§ BUFFER STRENGTH OTHER¶ RESET STATE# SUPPLY 8 mA J, A, G1 , , 0 DVDD1 8 mA B, J , input DVDD1 8 mA B, J , input DVDD1 8 mA B, J , input DVDD1 8 mA B, J , input DVDD1 8 mA B, J , input DVDD8 8 mA B, J , input DVDD1 8 mA B, J , input DVDD1 8 mA B, J , input DVDD1 8 mA B, J , input DVDD1 PD20 PD20 PD20 8 mA B, J , input DVDD1 NA ETM.PSTAT[2] O reg5[23:21] = 001 NA I = Input, O = Output, Z = High-Impedance 'regx' denotes the terminal multiplexing register that controls the specified terminal where regx = FUNC_MUX_CTRL_x § PD20 = 20-µA internal pulldown, PD100 PD100 = 100-µA pulldown, PU20 = 20-µA internal pullup, PU100 PU100 = 100-µA internal pullup ¶ A = Standard LVCMOS input/output G1 = Terminal may be gated by BFAIL B = Fail-safe LVCMOS input/output G2 = Terminal may be gated by GPIO9 and MPUIO3 C = USB transceiver input/output G3 = Terminal may be gated by BFAIL and OMAP5910 OMAP5910 internal reset D = I2C input/output buffers H1 = Terminal may be 3-stated by BFAIL input E = Fail-safe LVCMOS input and Standard LVCMOS output H2 = Terminal may be 3-stated via software configuration F = analog oscillator terminals J = Boundary-scannable terminal # Z = High-Impedance, LZ = Low-Impedance (pin is driven), 1 = Output driven high, 0 = Output driven low || UART1 signals can be multiplexed to this pin via additional multiplexing in the USB module. CAM.VS 12 SPRS197A SPRS197A I reg5[23:21] = 000 August 2002 ­ Revised April 2003 Introduction Table 2­3. Terminal Characteristics and Multiplexing (Continued) MUX CTRL SETTING DESELEC TED INPUT STATE CAM.HS I reg5[26:24] = 000 NA ETM.PSTAT[1] O reg5[26:24] = 001 NA UART2.CTS I reg5[26:24] = 010 NA CAM.RSTZ O reg5[29:27] = 000 NA ETM.PSTAT[0] O reg5[29:27] = 001 NA UART2.RTS O reg5[29:27] = 010 NA pin forced to drive low O reg6[2:0] = 000 NA UART3.TX O reg6[2:0] = 001 NA PWT O reg6[2:0] = 010 NA IRQ_OBS O reg6[2:0] = 011 NA UART2.TX O reg6[2:0] = 100 NA UART3.RX I reg6[5:3] = 000 1 PWL O reg6[5:3] = 001 NA DMA_REQ_OBS O reg6[5:3] = 010 NA UART2.RX I reg6[5:3] = 011 I/O/Z reg6[8:6] = 000 NA KB.R[7] I reg6[8:6] = 001 I/O/Z reg6[11:9] = 000 NA OTHER¶ RESET STATE# SUPPLY 8 mA B, J , input DVDD1 8 mA J, B, G1 , , 0 DVDD1 4 mA J, A, G1 , , 0 DVDD1 4 mA B, J , input DVDD1 PD20 4 mA J, B, G1 input DVDD1 PD20 4 mA J, B, G1 , , input DVDD1 PD20 4 mA J, B, G1 , , input DVDD1 4 mA J, B, G1 , , input DVDD1 4 mA J, B, G1 , , input DVDD1 PD20 1 GPIO14 GPIO14 BUFFER STRENGTH NA GPIO15 GPIO15 PULLUP/ PULLDN§ KB.R[6] I reg6[11:9] = 001 1 GPIO13 GPIO13 I/O/Z reg6[14:12] = 000 NA KB.R[5] I reg6[14:12] = 001 1 GPIO12 GPIO12 I/O/Z reg6[17:15] = 000 NA PD20 MCBSP3.FSX I/O/Z reg6[17:15] = 001 0 PD20 GPIO11 GPIO11 I/O/Z reg6[20:18] = 000 NA PD20 I/O reg6[20:18] = 001 NA PD20 GPIO7 I/O/Z reg6[23:21] = 000 NA PD20 4 mA J, B, G1 , , input DVDD1 MMC.DAT2 I/O/Z reg6[23:21] = 001 1 GPIO6 I/O/Z reg6[26:24] = 000 NA PD20 4 mA J, B, G1 , , input DVDD1 O reg6[26:24] = 001 NA 4 mA J, B, G1 , , input DVDD1 HDQ SPI.CS1 MCBSP3.FSX I/O/Z reg6[26:24] = 010 NA PD20 GPIO4 I/O/Z reg6[29:27] = 000 NA PD20 O reg6[29:27] = 001 NA SPI.CS2 MCBSP3.FSX I/O/Z reg6[29:27] = 010 NA PD20 I = Input, O = Output, Z = High-Impedance 'regx' denotes the terminal multiplexing register that controls the specified terminal where regx = FUNC_MUX_CTRL_x § PD20 = 20-µA internal pulldown, PD100 PD100 = 100-µA pulldown, PU20 = 20-µA internal pullup, PU100 PU100 = 100-µA internal pullup ¶ A = Standard LVCMOS input/output G1 = Terminal may be gated by BFAIL B = Fail-safe LVCMOS input/output G2 = Terminal may be gated by GPIO9 and MPUIO3 C = USB transceiver input/output G3 = Terminal may be gated by BFAIL and OMAP5910 OMAP5910 internal reset D = I2C input/output buffers H1 = Terminal may be 3-stated by BFAIL input E = Fail-safe LVCMOS input and Standard LVCMOS output H2 = Terminal may be 3-stated via software configuration F = analog oscillator terminals J = Boundary-scannable terminal # Z = High-Impedance, LZ = Low-Impedance (pin is driven), 1 = Output driven high, 0 = Output driven low || UART1 signals can be multiplexed to this pin via additional multiplexing in the USB module. August 2002 ­ Revised April 2003 SPRS197A SPRS197A 13 PRODUCT PREVIEW TYPE SIGNAL NAME Introduction Table 2­3. Terminal Characteristics and Multiplexing (Continued) SIGNAL NAME GPIO3 SPI.CS3 TYPE MUX CTRL SETTING DESELEC TED INPUT STATE PULLUP/ PULLDN§ BUFFER STRENGTH OTHER¶ RESET STATE# SUPPLY I/O/Z reg7[2:0] = 000 NA PD20 4 mA J, B, G1 , , input DVDD1 PD20 4 mA J, B, G1 , , input DVDD1 PD20 4 mA J, B, G1 , , input DVDD1 PD20 4 mA J, B, G1 , , input DVDD1 O reg7[2:0] = 001 NA I/O/Z reg7[2:0] = 010 NA LED1 O reg7[2:0] = 011 NA GPIO2 I/O/Z reg7[5:3] = 000 NA O reg7[5:3] = 001 NA I/O/Z reg7[8:6] = 000 NA MCBSP3.FSX SPI.CLK GPIO1 UART3.RTS GPIO0 SPI.RDY USB.VBUS PRODUCT PREVIEW MPUIO5 LOW_PWR MPUIO4 EXT_DMA_REQ1 LED2 O reg7[8:6] = 001 NA I/O/Z reg7[11:9] = 000 NA I reg7[11:9] = 001 PD20 NA I reg7[11:9] = 010 0 PD20 I/O/Z reg7[14:12] = 000 NA PD20 4 mA J, B, G1 , , input DVDD1 PD20 4 mA J, B, G1 , , input DVDD1 PD20 4 mA J, B, G1 , , input DVDD1 O reg7[14:12] = 001 NA I/O/Z reg7[17:15] = 000 NA I reg7[17:15] = 001 NA O reg7[17:15] = 010 NA I/O/Z reg7[20:18] = 000 NA I reg7[20:18] = 001 NA MPUIO1 I/O/Z NA NA 4 mA B, J input DVDD1 I2C.SCL I/O/Z NA NA 6 mA J, D, H1 Z DVDD1 I2C.SDA 6 mA J, D, H1 Z DVDD1 4 mA B, J , input DVDD1 4 mA J, A, G1 , , 0 DVDD1 MPUIO2 EXT_DMA_REQ0 I/O/Z NA NA UWIRE.SDI I reg8[2:0] = 000 NA PD20 UART3.DSR I reg8[2:0] = 001 1 PD20 UART1.DSR I reg8[2:0] = 010 1 PD20 MCBSP3.DR I reg8[2:0] = 011 NA PD20 UWIRE.SDO O reg8[5:3] = 000 NA UART3.DTR O reg8[5:3] = 001 NA UART1.DTR O reg8[5:3] = 010 NA MCBSP3.DX O reg8[5:3] = 011 NA 4 mA J, A, G1 , , 0 DVDD1 O reg8[8:6] = 000 NA KB.C[7] O reg8[8:6] = 001 NA I = Input, O = Output, Z = High-Impedance 'regx' denotes the terminal multiplexing register that controls the specified terminal where regx = FUNC_MUX_CTRL_x § PD20 = 20-µA internal pulldown, PD100 PD100 = 100-µA pulldown, PU20 = 20-µA internal pullup, PU100 PU100 = 100-µA internal pullup ¶ A = Standard LVCMOS input/output G1 = Terminal may be gated by BFAIL B = Fail-safe LVCMOS input/output G2 = Terminal may be gated by GPIO9 and MPUIO3 C = USB transceiver input/output G3 = Terminal may be gated by BFAIL and OMAP5910 OMAP5910 internal reset D = I2C input/output buffers H1 = Terminal may be 3-stated by BFAIL input E = Fail-safe LVCMOS input and Standard LVCMOS output H2 = Terminal may be 3-stated via software configuration F = analog oscillator terminals J = Boundary-scannable terminal # Z = High-Impedance, LZ = Low-Impedance (pin is driven), 1 = Output driven high, 0 = Output driven low || UART1 signals can be multiplexed to this pin via additional multiplexing in the USB module. UWIRE.SCLK 14 SPRS197A SPRS197A August 2002 ­ Revised April 2003 Introduction Table 2­3. Terminal Characteristics and Multiplexing (Continued) SIGNAL NAME TYPE MUX CTRL SETTING DESELEC TED INPUT STATE Z reg8[11:9] = 000 NA pin forced to high-z BUFFER STRENGTH OTHER¶ RESET STATE# SUPPLY 4 mA J, A , Z DVDD1 4 mA J, A , Z DVDD1 J, B input DVDD1 J, B input DVDD1 A input DVDD1 B input DVDD1 A 0 DVDD1 PD20 B input DVDD1 O reg8[11:9] = 001 NA I/O/Z reg8[11:9] = 010 NA pin forced to high-z Z reg8[14:12] = 000 NA UWIRE.CS3 O reg8[14:12] = 001 NA KB.C[6] O reg8[14:12] = 010 NA BFAIL/EXT_FIQ I NA NA CLK32K CLK32K_CTRL I NA NA CONF I NA NA PD100 PD100 TDI I NA NA PD20 TDO O NA NA TMS I NA NA TCK I NA NA PD20 B input DVDD1 TRST I NA NA PD100 PD100 B input DVDD1 EMU0 I/O/Z NA NA PU100 PU100 2 mA B Z DVDD1 EMU1 PU100 PU100 2 mA MCBSP3.CLKX 4 mA I/O/Z NA NA STAT_VAL/WKUP I NA NA MPU_BOOT I reg8[29:27] = 000 NA PD20 MCBSP3_DR I reg8[29:27] = 001 NA PD20 USB1_SUSP O reg8[29:27] = 010 NA RST_HOST_OUT O reg9[2:0] = 000 NA MCBSP3.DX O reg9[2:0] = 001 NA USB1.SE0 O reg9[2:0] = 010 NA pin forced to high-z B Z DVDD1 A input DVDD1 4 mA J, B , input DVDD1 4 mA J, A, G1 , , 0 DVDD1 4 mA J, A, G1 , , Z DVDD1 Z reg9[5:3] = 000 NA PD20 I/O/Z reg9[5:3] = 001 NA PD20 USB1.TXEN O reg9[5:3] = 010 NA MPU_RST I NA NA J, B input RST_OUT O NA NA 4 mA J, A 0 DVDD1 DVDD1 pin forced to drive low O reg9[14:12] = 000 NA 2 mA J, A, G1 , , 0 DVDD1 UART1.RTS O reg9[14:12] = 001 NA UART1.CTS I NA NA J, B input DVDD1 MCBSP3.CLKX PD20 UART1.RX I NA NA PD20 J, B input DVDD1 I = Input, O = Output, Z = High-Impedance 'regx' denotes the terminal multiplexing register that controls the specified terminal where regx = FUNC_MUX_CTRL_x § PD20 = 20-µA internal pulldown, PD100 PD100 = 100-µA pulldown, PU20 = 20-µA internal pullup, PU100 PU100 = 100-µA internal pullup ¶ A = Standard LVCMOS input/output G1 = Terminal may be gated by BFAIL B = Fail-safe LVCMOS input/output G2 = Terminal may be gated by GPIO9 and MPUIO3 C = USB transceiver input/output G3 = Terminal may be gated by BFAIL and OMAP5910 OMAP5910 internal reset D = I2C input/output buffers H1 = Terminal may be 3-stated by BFAIL input E = Fail-safe LVCMOS input and Standard LVCMOS output H2 = Terminal may be 3-stated via software configuration F = analog oscillator terminals J = Boundary-scannable terminal # Z = High-Impedance, LZ = Low-Impedance (pin is driven), 1 = Output driven high, 0 = Output driven low || UART1 signals can be multiplexed to this pin via additional multiplexing in the USB module. August 2002 ­ Revised April 2003 SPRS197A SPRS197A 15 PRODUCT PREVIEW UWIRE.CS0 PULLUP/ PULLDN§ Introduction Table 2­3. Terminal Characteristics and Multiplexing (Continued) TYPE MUX CTRL SETTING DESELEC TED INPUT STATE pin forced to drive low O reg9[23:21] = 000 NA UART1.TX O reg9[23:21] = 001 NA MCSI1.DOUT O reg9[26:24] = 000 NA USB1.TXD O NA UART1.TX O reg9[26:24] = 001 reg9[26:24] = 001|| BCLKREQ I reg9[29:27] = 000 0 PD20 UART3.CTS I reg9[29:27] = 001 0 PD20 UART1.DSR I reg9[29:27] = 010 1 PD20 BCLK O regA[2:0] = 000 NA UART3.RTS O regA[2:0] = 001 NA UART1.DTR O regA[2:0] = 010 NA MCSI1.SYNC I/O/Z regA[5:3] = 000 0 PD20 I regA[5:3] = 001 NA PD20 PRODUCT PREVIEW SIGNAL NAME USB1.VP MCSI1.CLK PULLUP/ PULLDN§ BUFFER STRENGTH OTHER¶ RESET STATE# SUPPLY 2 mA J, A, G1 , , 0 DVDD1 2 mA J, A, G1, , , , H1 0 DVDD1 J, B , input DVDD1 4 mA J, A, G1 , , 0 DVDD1 2 mA J, B, G1 , , input DVDD1 2 mA J, B, G1 , , input DVDD1 J, B , input DVDD1 J, A , LZ DVDD1 NA I/O/Z regA[8:6] = 000 0 PD20 USB1.VM I 0 PD20 UART1.RX I regA[8:6] = 001 regA[8:6] = 001|| 0 PD20 MCSI1.DIN I regA[11:9] = 000 NA PD20 USB1.RCV I PD20 I regA[11:9] = 001 regA[11:9] = 001|| 0 UART1.CTS 0 PD20 CLK32K CLK32K_OUT O regA[14:12] = 000 NA I/O/Z regA[14:12] = 001 NA O regA[14:12] = 010 NA CLK32K CLK32K_IN I NA NA J, B input DVDD1 OSC32K OSC32K_IN ­ NA NA F NA NA OSC32K OSC32K_OUT ­ NA NA F NA NA input DVDD1 MPUIO0 USB1.SPEED MMC.DAT3 I/O/Z regD[14:12] = 000 1 Reserved NA regD[14:12] = 001 I/O/Z regD[14:12] = 010 NA MMC.CLK PU20 4 mA NA MPUIO6 8 mA J, B, J B G1 PU20 O NA NA 4 mA J, A, G1 0 DVDD1 MMC.DAT0/SPI.DI I/O/Z NA NA PU20 4 mA J, B, G1 input DVDD1 MMC.DAT2 I/O/Z regA[20:18] = 000 1 PU20 4 mA J, B, G1 , , input DVDD1 Z regA[20:18] = 001 NA pin forced to hi-z MPUIO11 MPUIO11 I/O/Z regA[20:18] = 010 NA PU20 I = Input, O = Output, Z = High-Impedance 'regx' denotes the terminal multiplexing register that controls the specified terminal where regx = FUNC_MUX_CTRL_x § PD20 = 20-µA internal pulldown, PD100 PD100 = 100-µA pulldown, PU20 = 20-µA internal pullup, PU100 PU100 = 100-µA internal pullup ¶ A = Standard LVCMOS input/output G1 = Terminal may be gated by BFAIL B = Fail-safe LVCMOS input/output G2 = Terminal may be gated by GPIO9 and MPUIO3 C = USB transceiver input/output G3 = Terminal may be gated by BFAIL and OMAP5910 OMAP5910 internal reset D = I2C input/output buffers H1 = Terminal may be 3-stated by BFAIL input E = Fail-safe LVCMOS input and Standard LVCMOS output H2 = Terminal may be 3-stated via software configuration F = analog oscillator terminals J = Boundary-scannable terminal # Z = High-Impedance, LZ = Low-Impedance (pin is driven), 1 = Output driven high, 0 = Output driven low || UART1 signals can be multiplexed to this pin via additional multiplexing in the USB module. 16 SPRS197A SPRS197A August 2002 ­ Revised April 2003 Introduction Table 2­3. Terminal Characteristics and Multiplexing (Continued) MUX CTRL SETTING DESELEC TED INPUT STATE PULLUP/ PULLDN§ BUFFER STRENGTH OTHER¶ RESET STATE# SUPPLY I/O/Z regA[26:24] = 000 1 PU20 4 mA J, B, G1 , , input DVDD1 Reserved NA regA[26:24] = 001 NA MPUIO7 I/O/Z regA[26:24] = 010 NA PU20 MMC.CMD/SPI.DO I/O/Z NA NA PU100 PU100 4 mA J, B, G1 input DVDD1 MCSI2.CLK I/O/Z regB[5:3] = 000 0 PD20 4 mA J, E , input DVDD3 USB2.SUSP O regB[5:3] = 001 NA MCSI2.DIN I regB[8:6] = 000 NA PD20 J, B , input DVDD3 USB2.VP I regB[8:6] = 001 0 PD20 MCSI2.DOUT O regB[11:9] = 000 NA 4 mA J, A, G2 , , 0 DVDD3 USB2.TXEN O regB[11:9] = 001 NA MCSI2.SYNC I/O/Z regB[14:12] = 000 0 PD20 4 mA J, E , input DVDD3 GPIO7 I/O/Z regB[14:12] = 001 NA PD20 MCLK O NA NA MCLKREQ I regB[20:18] = 000 0 O regB[20:18] = 001 NA GPIO9 I/O/Z NA GPIO8 I/O/Z NA MPUIO3 I/O/Z NA MCBSP2.DR I MCBSP2.DX O MCBSP2.FSX MMC.DAT1 4 mA J, A, G1 0 DVDD3 PD20 4 mA J, E , input DVDD3 NA PD20 4 mA J, E, G3 input DVDD3 NA PD20 4 mA J, E, G3 input DVDD3 NA PD20 4 mA J, E, G1 input DVDD3 regC[2:0] = 000 NA PD20 4 mA J, B, G2 , , input DVDD3 regC[2:0] = 001 NA I/O/Z NA 0 PD20 4 mA J, E, G2 input DVDD3 MCBSP2.CLKR I/O/Z regC[8:6] = 000 0 4 mA J, E , Z DVDD3 GPIO11 GPIO11 I/O/Z regC[8:6] = 001 NA PD20 MCBSP2.CLKX I/O/Z NA NA PD20 4 mA J, E, G2 input DVDD3 MCBSP2.FSR I/O/Z regC[14:12] = 000 0 4 mA J, E , Z DVDD3 GPIO12 GPIO12 4 mA J, E, G2 , , 0 DVDD3 4 mA J, B , input DVDD3 4 mA J, B input DVDD3 EXT_MASTER_REQ I/O/Z regC[14:12] = 001 NA MCBSP2.DX O regC[17:15] = 000 NA PD20 MCBSP2.DR I regC[17:15] = 001 NA PD20 UART2.RX I regC[20:18] = 000 1 PD20 USB2.VM I regC[20:18] = 001 0 PD20 UART2.CTS I regC[23:21] = 000 1 PD20 USB2.RCV I regC[23:21] = 001 0 PD20 J, B GPIO7 I/O/Z regC[23:21] = 010 NA PD20 J, E I = Input, O = Output, Z = High-Impedance 'regx' denotes the terminal multiplexing register that controls the specified terminal where regx = FUNC_MUX_CTRL_x § PD20 = 20-µA internal pulldown, PD100 PD100 = 100-µA pulldown, PU20 = 20-µA internal pullup, PU100 PU100 = 100-µA internal pullup ¶ A = Standard LVCMOS input/output G1 = Terminal may be gated by BFAIL B = Fail-safe LVCMOS input/output G2 = Terminal may be gated by GPIO9 and MPUIO3 C = USB transceiver input/output G3 = Terminal may be gated by BFAIL and OMAP5910 OMAP5910 internal reset D = I2C input/output buffers H1 = Terminal may be 3-stated by BFAIL input E = Fail-safe LVCMOS input and Standard LVCMOS output H2 = Terminal may be 3-stated via software configuration F = analog oscillator terminals J = Boundary-scannable terminal # Z = High-Impedance, LZ = Low-Impedance (pin is driven), 1 = Output driven high, 0 = Output driven low || UART1 signals can be multiplexed to this pin via additional multiplexing in the USB module. August 2002 ­ Revised April 2003 SPRS197A SPRS197A 17 PRODUCT PREVIEW TYPE SIGNAL NAME Introduction Table 2­3. Terminal Characteristics and Multiplexing (Continued) TYPE MUX CTRL SETTING DESELEC TED INPUT STATE pin forced to drive low O regC[26:24] = 000 NA UART2.RTS O regC[26:24] = 001 NA USB2.SE0 O regC[26:24] = 010 NA I/O/Z regC[26:24] = 011 NA pin forced to drive low O regC[29:27] = 000 NA UART2.TX O regC[29:27] = 001 NA USB2.TXD O regC[29:27] = 010 NA UART2.BCLK O NA USB.PUEN O regD[5:3] = 000 USB.CLKO O regD[5:3] = 001 NA USB.DP I/O/Z NA USB.DM I/O/Z NA OSC1_IN ­ NA OSC1_OUT ­ NA FLASH.WP O/Z NA NA FLASH.WE O/Z NA FLASH.RP O/Z NA FLASH.OE O/Z FLASH.D[15:0] I/O/Z FLASH.CLK O/Z FLASH.CS3 FLASH.CS2 BUFFER STRENGTH OTHER¶ RESET STATE# SUPPLY 4 mA J, E, G2 , , 0 DVDD3 4 mA J, A, G2 , , 0 DVDD3 NA 4 mA J, A, G2 0 DVDD3 NA 8 mA J, B, G1 , , 0 DVDD2 NA 18.3 mA C Z DVDD2 NA 18.3 mA C Z DVDD2 NA F NA NA NA F NA NA 4 mA A, H2 0 DVDD5 NA 4 mA A, H2 1 DVDD5 NA 4 mA A, H2 0 DVDD5 NA NA 4 mA A, H2 1 DVDD5 NA NA 4 mA E 0 DVDD5 NA NA 8 mA E, G1, H2 0 DVDD5 O/Z NA NA 4 mA A, H2 1 DVDD5 O/Z regD[8:6] = 000 NA 4 mA A, H2 , 1 DVDD5 FLASH.BAA O/Z regD[8:6] = 001 NA FLASH.CS1 O/Z NA NA 4 mA A, H2 1 DVDD5 FLASH.CS0 O/Z NA NA 4 mA A, H2 1 DVDD5 FLASH.BE[1:0] O/Z NA NA 4 mA A, H2 0 DVDD5 FLASH.ADV O/Z NA NA 4 mA A, H2 1 DVDD5 FLASH.A[24:1] O/Z NA NA 4 mA A, G1, H2 0 DVDD5 SIGNAL NAME PRODUCT PREVIEW MPUIO5 PULLUP/ PULLDN§ FLASH.RDY I NA NA B input DVDD5 RSVD NA NA NA NA NA I = Input, O = Output, Z = High-Impedance 'regx' denotes the terminal multiplexing register that controls the specified terminal where regx = FUNC_MUX_CTRL_x § PD20 = 20-µA internal pulldown, PD100 PD100 = 100-µA pulldown, PU20 = 20-µA internal pullup, PU100 PU100 = 100-µA internal pullup ¶ A = Standard LVCMOS input/output G1 = Terminal may be gated by BFAIL B = Fail-safe LVCMOS input/output G2 = Terminal may be gated by GPIO9 and MPUIO3 C = USB transceiver input/output G3 = Terminal may be gated by BFAIL and OMAP5910 OMAP5910 internal reset D = I2C input/output buffers H1 = Terminal may be 3-stated by BFAIL input E = Fail-safe LVCMOS input and Standard LVCMOS output H2 = Terminal may be 3-stated via software configuration F = analog oscillator terminals J = Boundary-scannable terminal # Z = High-Impedance, LZ = Low-Impedance (pin is driven), 1 = Output driven high, 0 = Output driven low || UART1 signals can be multiplexed to this pin via additional multiplexing in the USB module. 18 SPRS197A SPRS197A August 2002 ­ Revised April 2003 Introduction 2.4 Signal Description Table 2­4 provides a description of the signals on OMAP5910 OMAP5910. Many signals are available on multiple pins depending upon the software configuration of the pin multiplexing options. Ball numbers which are italicized indicate the default pin muxings at reset. Ball numbers for busses are listed from MSB to LSB (left to right, top to bottom). Table 2­4. Signal Description SIGNAL TYPE DESCRIPTION EMIFF SDRAM Interface SDRAM write enable. SDRAM.WE is active (low) d