NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
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SPRS599 OMAP3525 OMAP3530 601/BT IEEE-1149 AF6/AB26 AE6/AB25 AF5/AA25 AE5/AD25 - Datasheet Archive
www.ti.com SPRS599 JUNE 2009 1 OMAP3525-HiRel and OMAP3530-HiRel Applications Processors · · OMAP3525 and
OMAP3525-HiRel and OMAP3530-HiRel Applications Processors www.ti.com SPRS599 SPRS599 JUNE 2009 1 OMAP3525-HiRel and OMAP3530-HiRel Applications Processors · · OMAP3525 OMAP3525 and OMAP3530 OMAP3530 Applications Processors: OMAPTM 3 Architecture MPU Subsystem · 600-MHz ARM CortexTM-A8 Core · NEONTM SIMD Coprocessor High Performance Image, Video, Audio (IVA2.2TM) Accelerator Subsystem · 430-MHz TMS320C64x+TM DSP Core · Enhanced Direct Memory Access (EDMA) Controller (128 Independent Channels) · Video Hardware Accelerators POWERVR SGXTM 2D/3D Graphics Accelerator (OMAP3530 OMAP3530 Device Only) · Tile Based Architecture Delivering up to 10 MPoly/sec · Universal Scalable Shader Engine: Multi-threaded Engine Incorporating Pixel and Vertex Shader Functionality · Industry Standard API Support: OpenGLES 1.1 and 2.0, OpenVG1.0 · Fine Grained Task Switching, Load Balancing, and Power Management · Programmable High Quality Image Anti-Aliasing Fully Software-Compatible With C64x and ARM9TM Commercial and Extended Temperature Grades Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x+TM DSP Core Eight Highly Independent Functional Units · +Six ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle · Two Multipliers Support Four 16 x 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 x 8-Bit Multiplies (16-Bit Results) per Clock Cycle Load-Store Architecture With Non-Aligned Support 64 32-Bit General-Purpose Registers Instruction Packing Reduces Code Size All Instructions Conditional · · · · Additional C64x+TM Enhancements · Protected Mode Operation · Exceptions Support for Error Detection and Program Redirection · Hardware Support for Modulo Loop Operation C64x+ L1/L2 Memory Architecture 32K-Byte L1P Program RAM/Cache (Direct Mapped) 80K-Byte L1D Data RAM/Cache (2-Way Set-Associative) 64K-Byte L2 Unified Mapped RAM/Cache (4-Way Set-Associative) 32K-Byte L2 Shared SRAM and 16K-Byte L2 ROM C64x+ Instruction Set Features Byte-Addressable (8-/16-/32-/64-Bit Data) 8-Bit Overflow Protection Bit-Field Extract, Set, Clear Normalization, Saturation. Bit-Counting Compact 16-Bit Instructions Additional Instructions to Support Complex Multiplies ARM CortexTM-A8 Core ARMv7 Architecture · Trust Zone® · Thumb®-2 · MMU Enhancements In-Order, Dual-Issue, Superscalar Microprocessor Core NEONTM Multimedia Architecture Over 2x Performance of ARMv6 SIMD Supports Both Integer and Floating Point SIMD Jazelle® RCT Execution Environment Architecture Dynamic Branch Prediction with Branch Target Address Cache, Global History Buffer, and 8-Entry Return Stack Embedded Trace Macrocell (ETM) Support for Non-Invasive Debug ARM CortexTM-A8 Memory Architecture: 16K-Byte Instruction Cache (4-Way Set-Associative) Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this document. POWERVR SGX is a trademark of Imagination Technologies Ltd. OMAP is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. Copyright © 2009, Texas Instruments Incorporated PRODUCT PREVIEW 1.1 Features OMAP3525-HiRel and OMAP3530-HiRel Applications Processors SPRS599 SPRS599 JUNE 2009 · · · · PRODUCT PREVIEW · · · 16K-Byte Data Cache (4-Way Set-Associative) 256K-Byte L2 Cache 112K-Byte ROM 64K-Byte Shared SRAM Endianess: ARM Instructions - Little Endian ARM Data Configurable DSP Instruction/Data - Little Endian External Memory Interfaces: SDRAM Controller (SDRC) · 16, 32-bit Memory Controller With 1G-Byte Total Address Space · Interfaces to Low-Power Double Data Rate (LPDDR) SDRAM · SDRAM Memory Scheduler (SMS) and Rotation Engine General Purpose Memory Controller (GPMC) · 16-bit Wide Multiplexed Address/Data Bus · Up to 8 Chip Select Pins With 128M-Byte Address Space per Chip Select Pin · Glueless Interface to NOR Flash, NAND Flash (With ECC Hamming Code Calculation), SRAM and Pseudo-SRAM · Flexible Asynchronous Protocol Control for Interface to Custom Logic (FPGA, CPLD, ASICs, etc.) · Nonmultiplexed Address/Data Mode (Limited 2K-Byte Address Space) System Direct Memory Access (sDMA) Controller (32 Logical Channels With Configurable Priority) Camera Image Signal Processing (ISP) CCD and CMOS Imager Interface Memory Data Input RAW Data Interface BT.601/BT 601/BT.656 Digital YCbCr 4:2:2 (8-/16-Bit) Interface A-Law Compression and Decompression Preview Engine for Real-Time Image Processing Glueless Interface to Common Video Decoders Histogram Module/Auto-Exposure, Auto-White Balance, and Auto-Focus Engine Resize Engine · Resize Images From 1/4x to 4x · Separate Horizontal/Vertical Control Display Subsystem Parallel Digital Output CopyrightNote OMAP3525-HiRel and OMAP3530-HiRel Applications Processors www.ti.com · · · · · · · Up to 24-Bit RGB HD Maximum Resolution Supports Up to 2 LCD Panels Support for Remote Frame Buffer Interface (RFBI) LCD Panels 2 10-Bit Digital-to-Analog Converters (DACs) Supporting: · Composite NTSC/PAL Video · Luma/Chroma Separate Video (S-Video) Rotation 90-, 180-, and 270-degrees Resize Images From 1/4x to 8x Color Space Converter 8-bit Alpha Blending Serial Communication 5 Multichannel Buffered Serial Ports (McBSPs) · 512 Byte Transmit/Receive Buffer (McBSP1/3/4/5) · 5K-Byte Transmit/Receive Buffer (McBSP2) · SIDETONE Core Support (McBSP2 and 3 Only) For Filter, Gain, and Mix Operations · Direct Interface to I2S and PCM Device and TDM Buses · 128 Channel Transmit/Receive Mode Four Master/Slave Multichannel Serial Port Interface (McSPI) Ports High-Speed/Full-Speed/Low-Speed USB OTG Subsystem (12-/8-Pin ULPI Interface) High-Speed/Full-Speed/Low-Speed Multiport USB Host Subsystem · 12-/8-Pin ULPI Interface or 6-/4-/3-Pin Serial Interface · Supports Transceiverless Link Logic (TLL) One HDQ/1-Wire Interface Three UARTs (One with Infrared Data Association [IrDA] and Consumer Infrared [CIR] Modes) Three Master/Slave High-Speed Inter-Integrated Circuit (I2C) Controllers Removable Media Interfaces: Three Multimedia Card (MMC)/ Secure Digital (SD) With Secure Data I/O (SDIO) One Memory Stick Pro Host Controller Universal Subscriber Identity Module (USIM) Comprehensive Power, Reset, and Clock Management SmartReflexTM Technology Dynamic Voltage and Frequency Scaling (DVFS) Submit Documentation Feedback OMAP3525-HiRel and OMAP3530-HiRel Applications Processors www.ti.com · · · · · · · · · Test Interfaces IEEE-1149 IEEE-1149.1 (JTAG) Boundary-Scan Compatible Embedded Trace Macro Interface (ETM) Serial Data Transport Interface (SDTI) 12 32-bit General Purpose Timers 2 32-bit Watchdog Timers 1 32-bit Secure Watchdog Timer 1 32-bit 32-kHz Sync Timer Up to 188 General-Purpose I/O (GPIO) Pins (Multiplexed With Other Device Functions) 65-nm CMOS Technology Package-On-Package (POP) Implementation for Memory Stacking Discrete Memory Interface (Not Available in CBC Package) Packages: 515-pin s-PBGA package (CBB Suffix), .5mm Ball Pitch (Top), .4mm Ball Pitch (Bottom) 515-pin s-PBGA package (CBC Suffix), .65mm Ball Pitch (Top), .5mm Ball Pitch · · (Bottom) 1.8-V I/O and 3.0-V (MMC1 only), 0.975-V to 1.35-V Adaptive Processor Core Voltage, 0.975-V to 1.35-V Adaptive Core Logic Voltage Note: These are default Operating Performance Point (OPP) voltages and could be optimized to lower values using SmartReflexTM AVS. Applications: Portable Navigation Devices Portable Media Player Advanced Portable Consumer Electronics Digital TV Digital Video Camera Portable Data Collection Point-of-Sale Devices Gaming Web Tablet Smart White Goods Smart Home Controllers Ultra Mobile Devices PRODUCT PREVIEW · SPRS599 SPRS599 JUNE 2009 1.2 SUPPORTS DEFENSE, AEROSPACE, AND MEDICAL APPLICATIONS · · · · · · Controlled Baseline One Assembly/Test Site One Fabrication Site Extended Product Life Cycle Extended Product-Change Notification Product Traceability Submit Documentation Feedback OMAP3525-HiRel and OMAP3530-HiRel Applications Processors 3 OMAP3525-HiRel and OMAP3530-HiRel Applications Processors SPRS599 SPRS599 JUNE 2009 www.ti.com 1.3 Description OMAP3530 OMAP3530 and OMAP3525 OMAP3525 high-performance, applications processors are based on the enhanced OMAPTM 3 architecture. The OMAPTM 3 architecture is designed to provide best-in-class video, image, and graphics processing sufficient to support the following: · Streaming video · 2D/3D mobile gaming · Video conferencing · High-resolution still image PRODUCT PREVIEW The device supports high-level operating systems (OSs), such as: · Linux · Windows CE · Symbian OS · Palm OS This OMAP device includes state-of-the-art power-management techniques required for high-performance mobile products. The following subsystems are part of the device: · Microprocessor unit (MPU) subsystem based on the ARM CortexTM-A8 microprocessor · IVA2.2 subsystem with a C64x+ digital signal processor (DSP) core · POWERVR SGXTM subsystem for 2D and 3D graphics acceleration to support display and gaming effects (3530only) · Camera image signal processor (ISP) that supports multiple formats and interfacing options connected to a wide variety of image sensors · Display subsystem with a wide variety of features for multiple concurrent image manipulation, and a programmable interface supporting a wide variety of displays. The display subsystem also supports NTSC/PAL video out. · Level 3 (L3) and level 4 (L4) interconnects that provide high-bandwidth data transfers for multiple initiators to the internal and external memory controllers and to on-chip peripherals The device also offers: · A comprehensive power and clock-management scheme that enables high-performance, low-power operation, and ultralow-power standby features. The device also supports SmartReflexTM adaptative voltage control. This power management technique for automatic control of the operating voltage of a module reduces the active power consumption. · Memory stacking feature using the package-on-package (POP) implementation (CBB and CBC packages only) OMAP3530 OMAP3530 is available in a 515-pin s-PBGA package (CBB suffix) and the OMAP3525 OMAP3525 is available in 515-pin s-PBGA (CBC suffix). Table 1-1 lists the differences between the CBB and CBC packages. 4 OMAP3525-HiRel and OMAP3530-HiRel Applications Processors Submit Documentation Feedback OMAP3525-HiRel and OMAP3530-HiRel Applications Processors www.ti.com SPRS599 SPRS599 JUNE 2009 Table 1-1. Differences Between CBB and CBC Packages FEATURE CBB PACKAGE CBC PACKAGE For CBC package pin assignments see Table 2-2, Ball Characteristics (CBC Pkg.) POP interface supported POP interface supported Discrete Memory Interface supported Discrete Memory Interface not supported Eight chip select pins available Eight chip select pins available Four wait pins available Four wait pins available UART1 CTS signal is available on 3 pins (triple muxed): uart1_cts (AG22 / W8 / T21), uart1_rts (AH22 / AA9), uart1_tx (F28 / Y8 / AE7), uart1_rx (E26 / AA8) The following signals are either available on two (double muxed) or three pins (triple muxed): uart1_cts (AE21 / T19 / W2), uart1_rts (AE22 / R2), uart1_rx (H3 / H25 / AE4), uart1_tx (L4 / G26) UART2 The following signals are available on two pins (double muxed): uart2_cts (AF6/AB26 AF6/AB26), uart2_rts (AE6/AB25 AE6/AB25), uart2_tx (AF5/AA25 AF5/AA25), uart2_rx (AE5/AD25 AE5/AD25) The following signals are available on two pins (double muxed): uart2_cts (Y24/P3 Y24/P3), uart2_rts (AA24/N3 AA24/N3), uart2_tx (AD22/U3 AD22/U3), uart2_rx (AD21/W3 AD21/W3) McBSP3 The following signals are available on three pins (triple muxed): mcbsp3_dx (AF6 / AB26 / V21), mcbsp3_dr (AE6 / AB25 / U21), mcbsp3_clkx (AF5 / AA25 / W21), and mcbsp3_fsx (AE5 / AD25 / K26) The following signals are available on two pins (triple muxed): mcbsp3_dx (U17/ Y24/ P3), mcbsp3_dr (T20/ AA24 / N3), mcbsp3_clkx (T17/ AD22 / U3), mcbsp3_fsx (P20/ AD21 / W3) GP Timer The following signals are available on three pins (triple muxed): gpt8_pwm_evt (N8 / AD25 / V3), gpt9_pwm_evt (T8 / AB26 / Y2), gpt10_pwm_evt (R8 / AB25 / Y3), and gpt11_pwm_evt (P8 / AA25 / Y4) The following signals are available on three pins (triple muxed): gpt8_pwm_evt (C5/AD21/V9 C5/AD21/V9), gpt9_pwm_evt (B4/W8/Y24 B4/W8/Y24), gpt10_pwm_evt(C4/U8/AA24 C4/U8/AA24), gpt11_pwm_evt(B5/V8/AD22 B5/V8/AD22) McBSP4 The following signals are available on two pins (double muxed): mcbsp4_clkx (T8/AE1), mcbsp4_dr (R8/AD1), mcbsp4_dx (P8/AD2), mcbsp4_fsx (N8/AC1) The following signals are available on two pins(double muxed): mcbsp4_clkx (B4 / V3), mcbsp4_dr (C4 / U4), mcbsp4_dx (B5 / R3), mcbsp4_fsx (C5 / T3) HSUSB3_TLL Supported Supported MM_FSUSB3 Pin Assignments Package-On-Package (POP) Interface Discrete Memory Interface GPMC PRODUCT PREVIEW For CBB package pin assignments seeTable 2-1, Ball Characteristics (CBB Pkg.) Supported Supported McSPI1 Four chip select pins are available Four chip select pins are available MMC3 The following signals are available on two pins (double muxed): mmc3_cmd (AC3 / AE10), and mmc3_clk (AB1 / AF10) The following signals are available on two pins (double muxed): mmc3_cmd (R8 / AB3), mmc3_clk (R9 / AB2) GPIO A maximum of 188 GPIO pins are supported. A maximum of 188 GPIO pins are supported. DSI Supported Supported SDI Supported Supported This OMAP3525 OMAP3525 and OMAP3530 OMAP3530 Applications Processors data manual presents the electrical and mechanical specifications for the OMAP3525 OMAP3525 and OMAP3530 OMAP3530 Applications Processors. The information contained in this data manual applies to both the commercial and extended temperature versions of the OMAP3525 OMAP3525 and OMAP3530 OMAP3530 Applications Processors unless otherwise indicated. It consists of the following sections: · A description of the OMAP3525 OMAP3525 and OMAP3530 OMAP3530 terminals: assignment, electrical characteristics, multiplexing, and functional description (Section 2) · A presentation of the electrical characteristics requirements: power domains, operating conditions, power consumption, and dc characteristics (Section 3) · The clock specifications: input and output clocks, DPLL and DLL (Section 4) · The video DAC specification (Section 5) · The timing requirements and switching characteristics (ac timings) of the interfaces (Section 6) · A description of thermal characteristics, device nomenclature, and mechanical data about the available packaging (Section 7) Submit Documentation Feedback OMAP3525-HiRel and OMAP3530-HiRel Applications Processors 5 OMAP3525-HiRel and OMAP3530-HiRel Applications Processors SPRS599 SPRS599 JUNE 2009 www.ti.com 1.4 Functional Block Diagram Figure 1-1 shows the functional block diagram of the OMAP3525/30 OMAP3525/30 Applications Processor. OMAP Applications Processor LCD Panel PRODUCT PREVIEW IVA 2.2 Subsystem TMS320DM64x+ DSP Imaging Video and Audio Processor 32K/32K 32K/32K L1$ 48K L1D RAM 64K L2$ 32K L2 RAM 16K L2 ROM Video Hardware Accelerators 64 32 Async 64 MPU Subsystem Camera (Parallel) Amp ARM CortexA8TM Core 16K/16K 16K/16K L1$ Parallel POWERVR SGXTM Graphics Accelerator (3530 only) L2$ 256K 64 64 CVBS or S-Video 32 32 32 Channel System DMA 32 32 TV Camera ISP Image Capture Hardware Image Pipeline and Preview Dual Output 3-Layer Display Processor (1xGraphics, 2xVideo) Temporal Dithering SDTV QCIF Support 32 64 HS USB Host (with USB TTL) HS USB OTG 32 Async 32 64 64 L3 Interconnect Network-Hierarchial, Performance, and Power Driven 32 32 64K On-Chip RAM 2KB Public/ 62KB Secure 112K On-Chip ROM 80KB Secure/ 32KB BOOT 64 SMS: SDRAM Memory Scheduler/ Rotation SDRC: SDRAM Memory Controller 32 32 32 L4 Interconnect GPMC: General Purpose Memory Controller NAND/ NOR Flash, SRAM External and Stacked Memories Peripherals: 3xUART, 3xHigh-Speed I2C, 5xMcBSP (2x with Sidetone/Audio Buffer) 4xMcSPI, 6xGPIO, 3xHigh-Speed MMC/SDIO, HDQ/1 Wire, 2xMailboxes 12xGPTimers, 2xWDT, 32K Sync Timer System Controls PRCM 2xSmartReflexTM Control Module External Peripherals Interfaces Emulation Debug: SDTI, ETM, JTAG, CoresightTM DAP Figure 1-1. OMAP3525/30 OMAP3525/30 Functional Block Diagram 6 OMAP3525-HiRel and OMAP3530-HiRel Applications Processors Submit Documentation Feedback OMAP3525-HiRel and OMAP3530-HiRel Applications Processors www.ti.com SPRS599 SPRS599 JUNE 2009 Contents 1.1 1.2 Features . 1 SUPPORTS DEFENSE, AEROSPACE, AND MEDICAL APPLICATIONS . 3 1.3 Functional Block Diagram . 6 Terminal Assignment . 8 2.2 Ball Characteristics . 12 2.3 Signal Description . 66 . 93 3.2 Absolute Maximum Ratings . 95 3.3 Recommended Operating Conditions . 97 3.4 DC Electrical Characteristics . 99 3.5 Core Voltage Decoupling . 102 3.6 Power-up and Power-down . 104 CLOCK SPECIFICATIONS . 107 4.1 Input Clock Specifications . 108 4 Power Domains Submit Documentation Feedback External Component Value Choice . 127 7 . 126 TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS . 128 . 6.2 Interface Clock Specifications . 6.3 Timing Parameters . 6.4 External Memory Interfaces. 6.5 Video Interfaces . 6.6 Serial Communications Interfaces . 6.7 Removable Media Interfaces . 6.8 Test Interfaces . PACKAGE CHARACTERISTICS . 7.1 Package Thermal Resistance . 7.2 Device Support. 6.1 ELECTRICAL CHARACTERISTICS. 93 3.1 Analog Supply (vdda_dac) Noise Requirements 5.4 6 Interface Description . 122 Electrical Specifications Over Recommended Operating Conditions . 124 5.3 Multiplexing Characteristics . 50 2.4 DPLL and DLL Specifications . 115 VIDEO DAC SPECIFICATIONS . 122 5.1 5.2 TERMINAL DESCRIPTION. 8 2.1 3 5 Output Clock Specifications. 113 4.3 Description . 4 1.4 2 4.2 OMAP3525-HiRel and OMAP3530-HiRel Applications Processors . 1 Timing Test Conditions Contents 128 128 129 130 159 179 212 227 233 233 233 7 PRODUCT PREVIEW 1 OMAP3525-HiRel and OMAP3530-HiRel Applications Processors SPRS599 SPRS599 JUNE 2009 www.ti.com 2 TERMINAL DESCRIPTION 2.1 Terminal Assignment Figure 2-1 through Figure 2-4 show the ball locations for the 515-ball plastic ball grid array (s-PBGA) packages. Table 2-1 and Table 2-2 indicate the signal names and ball grid numbers for both packages. AH AG AF AE AD PRODUCT PREVIEW AC AB AA Y W V U T R P N M L K J H G F E D C B A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 030-001 Figure 2-1. OMAP3525/30 OMAP3525/30 Applications Processor CBB s-PBGA-N515 Package (Bottom View) 8 TERMINAL DESCRIPTION Submit Documentation Feedback OMAP3525-HiRel and OMAP3530-HiRel Applications Processors www.ti.com SPRS599 SPRS599 JUNE 2009 AC AB AA Y W V U T R P PRODUCT PREVIEW N M L K J H G F E D C B A 23 22 21 19 20 17 18 15 16 11 13 14 12 9 10 5 7 8 6 1 3 4 2 030-002 Balls A1, A2, A22, A23, AB1, AB2, AB22, AB23, AC1, AC2, AC22, AC23, B1, B2, B22, and B23 are unused. Figure 2-2. OMAP3525/30 OMAP3525/30 Applications Processor CBB s-PBGA-N515 Package (Top View) Submit Documentation Feedback TERMINAL DESCRIPTION 9 OMAP3525-HiRel and OMAP3530-HiRel Applications Processors SPRS599 SPRS599 JUNE 2009 www.ti.com PRODUCT PREVIEW AF AE AD AC AB AA Y W V U T R P N M L K J H G F E D C B A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 Figure 2-3. OMAP3525/30 OMAP3525/30 Applications Processor CBC s-PBGA-515 Package (Bottom View) 10 TERMINAL DESCRIPTION Submit Documentation Feedback OMAP3525-HiRel and OMAP3530-HiRel Applications Processors www.ti.com SPRS599 SPRS599 JUNE 2009 AA Y W V U T R P N M PRODUCT PREVIEW L K J H G F E D C B A 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Figure 2-4. OMAP3525/30 OMAP3525/30 Applications Processor CBC s-PBGA-515 Package (Top View) Submit Documentation Feedback TERMINAL DESCRIPTION 11 OMAP3525-HiRel and OMAP3530-HiRel Applications Processors SPRS599 SPRS599 JUNE 2009 www.ti.com 2.2 Ball Characteristics Table 2-1 and Table 2-2 describe the terminal characteristics and the signals multiplexed on each pin for the CBB and CBC packages, respectively. The following list describes the table column headers. 1. BALL BOTTOM: Ball number(s) on the bottom side associated with each signal(s) on the bottom. 2. BALL TOP: Ball number(s) on the top side associated with each signal(s) on the top. 3. PIN NAME: Names of signals multiplexed on each ball (also notice that the name of the pin is the signal name in mode 0). PRODUCT PREVIEW Note: Table 2-1 and Table 2-2 do not take into account subsystem pin multiplexing options. Subsystem pin multiplexing options are described in Section 2.4, Signal Descriptions. 4. MODE: Multiplexing mode number. a. Mode 0 is the primary mode; this means that when mode 0 is set, the function mapped on the pin corresponds to the name of the pin. There is always a function mapped on the primary mode. Notice that primary mode is not necessarily the default mode. Note: The default mode is the mode which is automatically configured on release of the internal GLOBAL_PWRON reset; also see the RESET REL. MODE column. b. Modes 1 to 7 are possible modes for alternate functions. On each pin, some modes are effectively used for alternate functions, while some modes are not used and do not correspond to a functional configuration. 5. TYPE: Signal direction I = Input O = Output I/O = Input/Output D = Open drain DS = Differential A = Analog Note: In the safe_mode, the buffer is configured in high-impedance. 6. BALL RESET STATE: The state of the terminal at reset (power up). 0: The buffer drives VOL (pulldown/pullup resistor not activated) 0(PD): The buffer drives VOL with an active pulldown resistor. 1: The buffer drives VOH (pulldown/pullup resistor not activated) 1(PU): The buffer drives VOH with an active pullup resistor. Z: High-impedance L: High-impedance with an active pulldown resistor H : High-impedance with an active pullup resistor 7. BALL RESET REL. STATE: The state of the terminal at reset release. 0: The buffer drives VOL (pulldown/pullup resistor not activated) 0(PD): The buffer drives VOL with an active pulldown resistor. 1: The buffer drives VOH (pulldown/pullup resistor not activated) 1(PU): The buffer drives VOH with an active pullup resistor. Z: High-impedance L: High-impedance with an active pulldown resistor H : High-impedance with an active pullup resistor 8. RESET REL. MODE: This mode is automatically configured on release of the internal GLOBAL_PWRON reset. 9. POWER: The voltage supply that powers the terminal's I/O buffers. 10. HYS: Indicates if the input buffer is with hysteresis. 11. BUFFER STRENGTH: Drive strength of the associated output buffer. 12. PULL U/D - TYPE: Denotes the presence of an internal pullup or pulldown resistor. Pullup and pulldown resistors can be enabled or disabled via software. 12 TERMINAL DESCRIPTION Submit Documentation Feedback OMAP3525-HiRel and OMAP3530-HiRel Applications Processors www.ti.com SPRS599 SPRS599 JUNE 2009 Note: The pullup/pulldown drive strength is equal to 100 µA except for CBB balls P27, P26, R27, and R25, which the pulldown drive strength is equal to 1.8 k. 13. IO CELL: IO cell information. Note: Configuring two pins to the same input signal is not supported as it can yield unexpected results. This can be easily prevented with the proper software configuration. Table 2-1. Ball Characteristics (CBB Pkg.) (1) BALL TOP [2] PIN NAME [3] MODE [4] TYPE [5] BALL RESET STATE [6] BALL RESET REL. STATE [7] RESET REL. MODE [8] POWER [9] HYS [10] BUFFER STRENGTH (mA) [11] PULL U/D TYPE [12] IO CELL [13] D6 J2 sdrc_d0 0 IO L Z 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS C6 J1 sdrc_d1 0 IO L Z 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS B6 G2 sdrc_d2 0 IO L Z 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS C8 G1 sdrc_d3 0 IO L Z 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS C9 F2 sdrc_d4 0 IO L Z 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS A7 F1 sdrc_d5 0 IO L Z 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS B9 D2 sdrc_d6 0 IO L Z 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS A9 D1 sdrc_d7 0 IO L Z 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS C14 B13 sdrc_d8 0 IO L Z 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS B14 A13 sdrc_d9 0 IO L Z 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS C15 B14 sdrc_d10 0 IO L Z 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS B16 A14 sdrc_d11 0 IO L Z 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS D17 B16 sdrc_d12 0 IO L Z 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS C17 A16 sdrc_d13 0 IO L Z 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS B17 B19 sdrc_d14 0 IO L Z 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS D18 A19 sdrc_d15 0 IO L Z 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS D11 B3 sdrc_d16 0 IO L Z 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS B10 A3 sdrc_d17 0 IO L Z 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS C11 B5 sdrc_d18 0 IO L Z 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS D12 A5 sdrc_d19 0 IO L Z 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS C12 B8 sdrc_d20 0 IO L Z 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS A11 A8 sdrc_d21 0 IO L Z 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS B13 B9 sdrc_d22 0 IO L Z 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS D14 A9 sdrc_d23 0 IO L Z 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS C18 B21 sdrc_d24 0 IO L Z 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS A19 A21 sdrc_d25 0 IO L Z 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS B19 D22 sdrc_d26 0 IO L Z 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS B20 D23 sdrc_d27 0 IO L Z 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS D20 E22 sdrc_d28 0 IO L Z 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS A21 E23 sdrc_d29 0 IO L Z 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS B21 G22 sdrc_d30 0 IO L Z 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS C21 G23 sdrc_d31 0 IO L Z 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS H9 AB21 sdrc_ba0 0 O 0 0 0 VDDS_ MEM No 4 NA LVCMOS H10 AC21 sdrc_ba1 0 O 0 0 0 VDDS_ MEM No 4 NA LVCMOS A4 N22 sdrc_a0 0 O 0 0 0 VDDS_ MEM No 4 NA LVCMOS B4 N23 sdrc_a1 0 O 0 0 0 VDDS_ MEM No 4 NA LVCMOS B3 P22 sdrc_a2 0 O 0 0 0 VDDS_ MEM No 4 NA LVCMOS C5 P23 sdrc_a3 0 O 0 0 0 VDDS_ MEM No 4 NA LVCMOS C4 R22 sdrc_a4 0 O 0 0 0 VDDS_ MEM No 4 NA LVCMOS D5 R23 sdrc_a5 0 O 0 0 0 VDDS_ MEM No 4 NA LVCMOS C3 T22 sdrc_a6 0 O 0 0 0 VDDS_ MEM No 4 NA LVCMOS C2 T23 sdrc_a7 0 O 0 0 0 VDDS_ MEM No 4 NA LVCMOS C1 U22 sdrc_a8 0 O 0 0 0 VDDS_ MEM No 4 NA LVCMOS D4 U23 sdrc_a9 0 O 0 0 0 VDDS_ MEM No 4 NA LVCMOS D3 V22 sdrc_a10 0 O 0 0 0 VDDS_ MEM No 4 NA LVCMOS (1) PRODUCT PREVIEW BALL BOTTOM [1] NA in this table stands for Not Applicable. Submit Documentation Feedback TERMINAL DESCRIPTION 13 OMAP3525-HiRel and OMAP3530-HiRel Applications Processors SPRS599 SPRS599 JUNE 2009 www.ti.com Table 2-1. Ball Characteristics (CBB Pkg.) (continued) BALL BOTTOM [1] BALL TOP [2] PIN NAME [3] MODE [4] TYPE [5] BALL RESET STATE [6] BALL RESET REL. STATE [7] RESET REL. MODE [8] POWER [9] HYS [10] BUFFER STRENGTH (mA) [11] PULL U/D TYPE [12] IO CELL [13] D2 V23 sdrc_a11 0 O 0 0 0 VDDS_ MEM No 4 NA LVCMOS D1 W22 sdrc_a12 0 O 0 0 0 VDDS_ MEM No 4 NA LVCMOS E2 W23 sdrc_a13 0 O 0 0 0 VDDS_ MEM No 4 NA LVCMOS E1 Y22 sdrc_a14 0 O 0 0 0 VDDS_ MEM No 4 NA LVCMOS H11 M22 sdrc_ncs0 0 O 1 1 0 VDDS_ MEM No 4 NA LVCMOS H12 M23 sdrc_ncs1 0 O 1 1 0 VDDS_ MEM No 4 NA LVCMOS A13 A11 sdrc_clk 0 IO L 0 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS A14 B11 sdrc_nclk 0 O 1 1 0 VDDS_ MEM No 4 NA LVCMOS H16 J22 sdrc_cke0 0 O H 1 7 VDDS_ MEM Yes 4 PU/ PD LVCMOS safe_mode 7 O H 1 7 VDDS_ MEM Yes 4 PU/ PD LVCMOS H17 J23 PRODUCT PREVIEW sdrc_cke1 0 safe_mode 7 H14 L23 sdrc_nras 0 O 1 1 0 VDDS_ MEM No 4 NA LVCMOS H13 L22 sdrc_ncas 0 O 1 1 0 VDDS_ MEM No 4 NA LVCMOS H15 K23 sdrc_nwe 0 O 1 1 0 VDDS_ MEM No 4 NA LVCMOS B7 C1 sdrc_dm0 0 O 0 0 0 VDDS_ MEM No 4 NA LVCMOS A16 A17 sdrc_dm1 0 O 0 0 0 VDDS_ MEM No 4 NA LVCMOS B11 A6 sdrc_dm2 0 O 0 0 0 VDDS_ MEM No 4 NA LVCMOS C20 A20 sdrc_dm3 0 O 0 0 0 VDDS_ MEM No 4 NA LVCMOS A6 C2 sdrc_dqs0 0 IO L Z 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS A17 B17 sdrc_dqs1 0 IO L Z 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS A10 B6 sdrc_dqs2 0 IO L Z 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS A20 B20 sdrc_dqs3 0 IO L Z 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS N4 AC15 gpmc_a1 0 O L L 7 VDDS_ MEM Yes 4 PU/ PD LVCMOS gpio_34 4 IO safe_mode 7 gpmc_a2 0 O L L 7 VDDS_ MEM Yes 4 PU/ PD LVCMOS gpio_35 4 IO safe_mode 7 gpmc_a3 0 O L L 7 VDDS_ MEM Yes 4 PU/ PD LVCMOS gpio_36 4 IO safe_mode 7 gpmc_a4 0 O L L 7 VDDS_ MEM Yes 4 PU/ PD LVCMOS gpio_37 4 IO safe_mode 7 gpmc_a5 0 O L L 7 VDDS_ MEM Yes 4 PU/ PD LVCMOS gpio_38 4 IO safe_mode 7 gpmc_a6 0 O H H 7 VDDS_ MEM Yes 4 PU/ PD LVCMOS gpio_39 4 IO safe_mode 7 gpmc_a7 0 O H H 7 VDDS_ MEM Yes 4 PU/ PD LVCMOS gpio_40 4 IO safe_mode 7 gpmc_a8 0 O H H 7 VDDS_ MEM Yes 4 PU/ PD LVCMOS gpio_41 4 IO safe_mode 7 gpmc_a9 0 O H H 7 VDDS_ MEM Yes 4 PU/ PD LVCMOS sys_ ndmareq2 1 I IO H H 7 VDDS_ MEM Yes 4 PU/ PD LVCMOS M4 L4 K4 T3 R3 N3 M3 L3 AB15 AC16 AB16 AC17 AB17 AC18 AB18 AC19 gpio_42 K3 7 gpmc_a10 0 O sys_ ndmareq3 1 I gpio_43 14 AB19 4 safe_mode 4 IO TERMINAL DESCRIPTION Submit Documentation Feedback OMAP3525-HiRel and OMAP3530-HiRel Applications Processors www.ti.com SPRS599 SPRS599 JUNE 2009 Table 2-1. Ball Characteristics (CBB Pkg.) (continued) BALL TOP [2] PIN NAME [3] MODE [4] TYPE [5] BALL RESET STATE [6] BALL RESET REL. STATE [7] RESET REL. MODE [8] POWER [9] HYS [10] BUFFER STRENGTH (mA) [11] PULL U/D TYPE [12] IO CELL [13] K1 M2 safe_mode 7 gpmc_d0 L1 M1 gpmc_d1 0 IO H H 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS 0 IO H H 0 VDDS_ MEM Yes 4 PU/ PD L2 N2 LVCMOS gpmc_d2 0 IO H H 0 VDDS_ MEM Yes 4 PU/ PD P2 LVCMOS N1 gpmc_d3 0 IO H H 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS T1 R2 gpmc_d4 0 IO H H 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS V1 R1 gpmc_d5 0 IO H H 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS V2 T2 gpmc_d6 0 IO H H 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS W2 T1 gpmc_d7 0 IO H H 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS H2 AB3 gpmc_d8 0 IO H H 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS gpio_44 4 IO safe_mode 7 gpmc_d9 0 IO H H 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS gpio_45 4 IO safe_mode 7 gpmc_d10 0 IO H H 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS gpio_46 4 IO safe_mode 7 gpmc_d11 0 IO H H 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS gpio_47 4 IO safe_mode 7 gpmc_d12 0 IO H H 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS gpio_48 4 IO safe_mode 7 gpmc_d13 0 IO H H 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS gpio_49 4 IO safe_mode 7 gpmc_d14 0 IO H H 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS gpio_50 4 IO safe_mode 7 gpmc_d15 0 IO H H 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS gpio_51 4 IO K2 P1 R1 R2 T2 W1 Y1 AC3 AB4 AC4 AB6 AC6 AB7 AC7 safe_mode 7 G4 Y2 gpmc_ncs0 0 O 1 1 0 VDDS_ MEM No 4 NA LVCMOS H3 Y1 gpmc_ncs1 0 O H 1 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS gpio_52 4 IO H H 7 VDDS_ MEM Yes 4 PU/ PD LVCMOS H H 7 VDDS_ MEM Yes 4 PU/ PD LVCMOS H H 7 VDDS_ MEM Yes 4 PU/ PD LVCMOS H H 7 VDDS_ MEM Yes 4 PU/ PD PRODUCT PREVIEW BALL BOTTOM [1] LVCMOS safe_mode NA 7 gpmc_ncs2 0 O gpio_53 V8 4 IO safe_mode NA 7 gpmc_ncs3 0 O sys_ ndmareq0 U8 1 I IO gpio_54 T8 NA 4 safe_mode 7 gpmc_ncs4 0 O sys_ ndmareq1 1 I mcbsp4_ clkx IO 4 IO safe_mode NA IO 3 gpio_55 R8 2 gpt9_pwm_evt 7 gpmc_ncs5 0 O sys_ ndmareq2 1 I mcbsp4_dr 2 I gpt10_pwm_evt 3 IO Submit Documentation Feedback TERMINAL DESCRIPTION 15 OMAP3525-HiRel and OMAP3530-HiRel Applications Processors SPRS599 SPRS599 JUNE 2009 www.ti.com Table 2-1. Ball Characteristics (CBB Pkg.) (continued) BALL BOTTOM [1] BALL TOP [2] PIN NAME [3] MODE [4] TYPE [5] IO gpio_56 P8 NA 4 safe_mode gpmc_ncs6 0 O 1 mcbsp4_dx 2 BUFFER STRENGTH (mA) [11] PULL U/D TYPE [12] IO CELL [13] H H 7 VDDS_ MEM Yes 4 PU/ PD LVCMOS H H 7 VDDS_ MEM Yes 4 PU/ PD LVCMOS L 0 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS IO 7 gpmc_ncs7 0 O gpmc_io_dir 1 O mcbsp4_fsx 2 IO gpt8_pwm_evt 3 IO gpio_58 4 IO safe_mode 7 gpmc_clk 0 O gpio_59 PRODUCT PREVIEW HYS [10] IO 4 safe_mode W2 POWER [9] IO 3 gpio_57 T4 RESET REL. MODE [8] I gpt11_pwm_evt NA BALL RESET REL. STATE [7] 7 sys_ ndmareq3 N8 BALL RESET STATE [6] 4 IO safe_mode 7 F3 W1 gpmc_nadv_ale 0 O 0 0 0 VDDS_ MEM No 4 NA LVCMOS G2 V2 gpmc_noe 0 O 1 1 0 VDDS_ MEM No 4 NA LVCMOS F4 V1 gpmc_nwe 0 O 1 1 0 VDDS_ MEM No 4 NA LVCMOS G3 AC12 gpmc_nbe0_cle 0 O L 0 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS gpio_60 4 IO L L 7 VDDS_ MEM Yes 4 PU/ PD LVCMOS L 0 0 VDDS_ MEM Yes 4 PU/ PD LVCMOS safe_mode NA 7 gpmc_nbe1 0 O gpio_61 U3 4 IO safe_mode H1 AB10 7 gpmc_nwp 0 O gpio_62 4 IO safe_mode 7 M8 AB12 gpmc_wait0 0 I H H 0 VDDS_ MEM Yes NA PU/ PD LVCMOS L8 AC10 gpmc_wait1 0 I H H 7 VDDS_ MEM Yes 4 PU/ PD LVCMOS gpio_63 4 IO H H 7 VDDS_ MEM Yes 4 PU/ PD LVCMOS H H 7 VDDS_ MEM Yes 4 PU/ PD LVCMOS H H 7 VDDS Yes 8 PU/ PD LVCMOS H H 7 VDDS Yes 8 PU/ PD LVCMOS H H 7 VDDS Yes 8 PU/ PD LVCMOS L L 7 VDDS Yes 8 PU/ PD LVCMOS L L 7 VDDS Yes 8 PU/ PD LVDS/ CMOS safe_mode NA 7 gpmc_wait2 0 I gpio_64 K8 4 IO safe_mode NA 7 gpmc_wait3 0 I sys_ ndmareq1 J8 1 I IO gpio_65 NA IO 7 dss_hsync 0 O 4 IO 7 dss_vsync 0 O gpio_68 D27 O 4 safe_mode NA 0 gpio_67 D26 dss_pclk safe_mode NA 7 gpio_66 D28 4 safe_mode 4 IO safe_mode 16 NA 0 O 4 IO 7 dss_data0 0 IO uart1_cts AG22 7 safe_mode NA dss_acbias gpio_69 E27 2 I TERMINAL DESCRIPTION Submit Documentation Feedback OMAP3525-HiRel and OMAP3530-HiRel Applications Processors www.ti.com SPRS599 SPRS599 JUNE 2009 Table 2-1. Ball Characteristics (CBB Pkg.) (continued) BALL TOP [2] PIN NAME [3] MODE [4] TYPE [5] IO gpio_70 NA dss_data1 0 IO 2 0 IO 4 0 IO 4 0 IO 2 dss_data5 0 IO 2 dss_data6 0 IO 2 dss_data7 0 IO 2 dss_data8 0 IO 4 0 IO 4 0 IO 4 0 IO 4 0 IO 4 8 PU/ PD LVDS/ CMOS L L 7 VDDS Yes 8 PU/ PD LVDS/ CMOS L L 7 VDDS Yes 8 PU/ PD LVDS/ CMOS L L 7 VDDS Yes 8 PU/ PD LVCMOS L L 7 VDDS Yes 8 PU/ PD LVCMOS L L 7 VDDS Yes 8 PU/ PD LVCMOS L L 7 VDDS Yes 8 PU/ PD LVCMOS L L 7 VDDS Yes 8 PU/ PD LVDS/ CMOS L L 7 VDDS Yes 8 PU/ PD LVDS/ CMOS L L 7 VDDS Yes 8 PU/ PD LVDS/ CMOS L L 7 VDDS Yes 8 PU/ PD LVDS/ CMOS L L 7 VDDS Yes 8 PU/ PD LVDS/ CMOS L L 7 VDDS Yes 8 PU/ PD LVDS/ CMOS L L 7 VDDS Yes 8 PU/ PD LVCMOS IO 7 dss_data13 0 IO 4 IO safe_mode 7 dss_data14 0 IO gpio_84 4 IO safe_mode 7 dss_data15 0 IO gpio_85 4 IO safe_mode 7 dss_data16 0 IO gpio_86 NA Yes 7 dss_data12 gpio_83 G25 VDDS IO safe_mode NA 7 7 dss_data11 gpio_82 AA27 L IO safe_mode NA L 7 dss_data10 gpio_81 AA28 LVDS/ CMOS IO safe_mode NA PU/ PD 7 dss_data9 gpio_80 AB27 8 IO safe_mode NA Yes 7 gpio_79 AB28 VDDS IO 4 safe_mode NA 7 I gpio_78 AD27 L 7 gpio_77 NA L IO 4 safe_mode AD28 LVDS/ CMOS O uart1_rx NA PU/ PD 7 gpio_76 G26 8 IO 4 safe_mode NA Yes O uart1_tx F27 VDDS 7 gpio_75 NA 7 IO 4 safe_mode F28 L I uart3_tx_ irtx NA L 7 dss_data4 gpio_74 E26 IO CELL [13] IO safe_mode NA PULL U/D TYPE [12] 7 dss_data3 uart3_rx_ irrx AH24 BUFFER STRENGTH (mA) [11] IO safe_mode NA dss_data2 gpio_73 AG24 HYS [10] 7 safe_mode NA 4 gpio_72 AH23 POWER [9] IO gpio_71 NA RESET REL. MODE [8] O safe_mode AG23 BALL RESET REL. STATE [7] 7 uart1_rts AH22 4 safe_mode BALL RESET STATE [6] 4 IO Submit Documentation Feedback TERMINAL DESCRIPTION 17 PRODUCT PREVIEW BALL BOTTOM [1] OMAP3525-HiRel and OMAP3530-HiRel Applications Processors SPRS599 SPRS599 JUNE 2009 www.ti.com Table 2-1. Ball Characteristics (CBB Pkg.) (continued) BALL BOTTOM [1] BALL TOP [2] PIN NAME [3] MODE [4] TYPE [5] BALL RESET STATE [6] BALL RESET REL. STATE [7] RESET REL. MODE [8] POWER [9] HYS [10] BUFFER STRENGTH (mA) [11] PULL U/D TYPE [12] IO CELL [13] safe_mode 7 H27 NA dss_data17 gpio_87 0 IO L L 7 VDDS Yes 8 PU/ PD LVCMOS 4 IO L L 7 VDDS Yes 8 PU/ PD LVCMOS L L 7 VDDS Yes 8 PU/ PD LVCMOS H H 7 VDDS Yes 8 PU/ PD LVCMOS L L 7 VDDS Yes 8 PU/ PD LVCMOS L L 7 VDDS Yes 8 PU/ PD LVDS/ CMOS L L 7 VDDS Yes 8 PU/ PD LVDS/ CMOS safe_mode IO 2 IO 3 IO 4 IO safe_mode 7 IO 2 IO 3 IO gpio_89 4 IO safe_mode PRODUCT PREVIEW 0 dss_data1 7 0 O 2 IO dss_data2 3 IO gpio_90 4 IO safe_mode 7 0 O 2 IO dss_data3 3 IO gpio_91 4 IO safe_mode 7 0 O 2 O dss_data4 3 IO gpio_92 4 IO safe_mode 7 dss_data23 0 O dss_data5 NA dss_data22 mcspi3_cs1 AC28 NA dss_data21 mcspi3_cs0 AC27 NA dss_data20 mcspi3_ somi J26 NA dss_data19 mcspi3_ simo E28 NA 0 gpio_88 H25 7 dss_data0 NA dss_data18 mcspi3_clk H26 3 IO IO gpio_93 4 safe_mode 7 W28 NA tv_out2 0 O Z 0 0 VDDADAC NA (2) NA 10-bit DAC Y28 NA tv_out1 0 O Z 0 0 VDDADAC NA (2) NA 10-bit DAC Y27 NA tv_vfb1 0 AO Z NA 0 VDDADAC NA (2) NA 10-bit DAC W27 NA tv_vfb2 0 AO Z NA 0 VDDADAC NA (2) NA 10-bit DAC W26 NA tv_vref 0 AO Z NA 0 VDDADAC NA (2) NA 10-bit DAC A24 NA cam_hs 0 IO L L 7 VDDS Yes 4 PU/ PD LVCMOS gpio_94 4 IO safe_mode 7 cam_vs 0 IO L L 7 VDDS Yes 4 PU/ PD LVCMOS gpio_95 4 IO L L 7 VDDS Yes 4 PU/ PD LVCMOS L L 7 VDDS Yes 4 PU/ PD LVCMOS L L 7 VDDS Yes 4 PU/ PD LVCMOS A23 NA safe_mode 18 7 cam_pclk 0 I 4 IO 7 cam_fld 0 IO 2 IO gpio_98 (2) IO cam_global_reset NA O 4 safe_mode C23 0 gpio_97 NA 7 safe_mode C27 NA cam_ xclka gpio_96 C25 4 IO The drive strength is fixed regardless of the load. The driver is designed to drive 75 for video applications. TERMINAL DESCRIPTION Submit Documentation Feedback OMAP3525-HiRel and OMAP3530-HiRel Applications Processors www.ti.com SPRS599 SPRS599 JUNE 2009 Table 2-1. Ball Characteristics (CBB Pkg.) (continued) BALL TOP [2] AG17 NA safe_mode IO 7 cam_d6 0 I 4 IO 7 cam_d7 0 I 4 IO 7 cam_d8 0 I 4 IO 7 cam_d9 0 I 4 IO 7 cam_d10 0 I 4 IO safe_mode 7 cam_d11 0 I gpio_110 NA I 4 gpio_109 C26 0 safe_mode NA 7 cam_d5 gpio_108 B25 IO safe_mode NA I 4 gpio_107 L27 0 safe_mode NA 7 cam_d4 gpio_106 K27 IO safe_mode NA I 4 gpio_105 L28 0 safe_mode NA 7 cam_d3 gpio_104 K28 IO safe_mode NA I 4 gpio_103 A25 0 safe_mode NA 7 cam_d2 gpio_102 D24 I safe_mode NA I 4 gpio_101 C24 0 safe_mode NA 7 cam_d1 gpio_100 B24 7 cam_d0 gpio_99 NA MODE [4] safe_mode AH17 PIN NAME [3] TYPE [5] BALL RESET STATE [6] BALL RESET REL. STATE [7] RESET REL. MODE [8] POWER [9] HYS [10] BUFFER STRENGTH (mA) [11] PULL U/D TYPE [12] IO CELL [13] 0 I L L 7 VDDS Yes NA PU/PD LVDS/ CMOS 4 I L L 7 VDDS Yes NA PU/PD LVDS/ CMOS L L 7 VDDS Yes 4 PU/ PD LVCMOS L L 7 VDDS Yes 4 PU/ PD LVCMOS L L 7 VDDS Yes 4 PU/ PD LVCMOS L L 7 VDDS Yes 4 PU/ PD LVCMOS L L 7 VDDS Yes NA PU/PD LVDS/ CMOS PU/PD LVDS/ CMOS PU/PD LVDS/ CMOS PU/PD LVDS/ CMOS 4 IO NA NA VDDS Yes NA 8 L L 7 VDDS Yes NA 8 LVCMOS L L 7 VDDS Yes 4 PU/ PD LVCMOS L L 7 VDDS Yes 4 PU/ PD LVCMOS L L 7 VDDS Yes 4 PU/ PD LVCMOS L L 7 VDDS Yes 4 PU/ PD LVCMOS I L L 7 VDDS Yes NA PU/PD LVDS/ CMOS I L L 7 VDDS Yes NA PU/PD LVDS/ CMOS I L L 7 VDDS Yes NA PU/PD LVDS/ CMOS I L L 7 VDDS Yes NA PU/PD LVDS/ CMOS 7 0 O 4 IO 7 cam_wen 0 I 2 O IO 4 7 cam_ strobe 0 O 4 IO 7 gpio_112 4 7 gpio_113 4 7 gpio_114 4 safe_mode AH18 NA 7 PU/ PD cam_ xclkb safe_mode AG18 NA L 4 safe_mode AH19 L NA safe_mode NA 8 Yes gpio_126 AG19 NA VDDS gpio_167 NA Yes 7 safe_mode D25 VDDS L cam_ shutter NA 7 L safe_mode B23 L NA gpio_111 NA L NA safe_mode B26 8 7 gpio_115 4 Submit Documentation Feedback TERMINAL DESCRIPTION 19 PRODUCT PREVIEW BALL BOTTOM [1] OMAP3525-HiRel and OMAP3530-HiRel Applications Processors SPRS599 SPRS599 JUNE 2009 www.ti.com Table 2-1. Ball Characteristics (CBB Pkg.) (continued) BALL BOTTOM [1] BALL TOP [2] PIN NAME [3] MODE [4] TYPE [5] BALL RESET STATE [6] BALL RESET REL. STATE [7] RESET REL. MODE [8] POWER [9] HYS [10] BUFFER STRENGTH (mA) [11] PULL U/D TYPE [12] IO CELL [13] safe_mode 7 P21 NA mcbsp2_fsx gpio_116 0 IO L L 7 VDDS Yes 4 (3) PU/ PD LVCMOS 4 IO L L 7 VDDS Yes 4 (3) PU/ PD LVCMOS L L 7 VDDS Yes 4 (3) PU/ PD LVCMOS L L 7 VDDS Yes 4 (3) PU/ PD LVCMOS L L 7 VDDS_MMC1 Yes 8 PU/ PD (4) LVCMOS L L 7 VDDS_MMC1 Yes 8 PU/ PD (4) LVCMOS L L 7 VDDS_MMC1 Yes 8 PU/ PD (4) LVCMOS L L 7 VDDS_MMC1 Yes 8 PU/ PD (4) LVCMOS L L 7 VDDS_MMC1 Yes 8 PU/ PD (4) LVCMOS L L 7 VDDS_MMC1 Yes 8 PU/ PD (4) LVCMOS L L 7 VDDS_MMC1a No 8 PD (4) LVCMOS L L 7 VDDS_MMC1a No 8 PD (4) LVCMOS L L 7 VDDS_MMC1a No 8 PD (4) LVCMOS L L 7 VDDS_MMC1a No 8 PD (4) LVCMOS L L 7 VDDS Yes 4 PU/ PD LVCMOS H H 7 VDDS Yes 4 PU/ PD LVCMOS safe_mode 0 IO 4 IO 7 mcbsp2_dr 0 I gpio_118 NA 7 safe_mode R21 NA mcbsp2_ clkx gpio_117 N21 4 IO safe_mode PRODUCT PREVIEW 0 IO 4 IO 7 mmc1_clk 0 O gpio_120 NA 7 safe_mode N28 NA mcbsp2_dx gpio_119 M21 4 IO safe_mode NA 7 mmc1_cmd 0 IO gpio_121 M27 4 IO safe_mode NA 7 mmc1_dat0 0 IO gpio_122 N27 4 IO safe_mode NA 7 mmc1_dat1 0 IO gpio_123 N26 4 IO safe_mode NA 7 mmc1_dat2 0 IO gpio_124 N25 4 IO safe_mode NA 7 mmc1_dat3 0 IO gpio_125 P28 4 IO safe_mode NA 7 mmc1_dat4 0 IO gpio_126 P27 4 IO safe_mode NA 7 mmc1_dat5 0 IO gpio_127 P26 4 IO safe_mode NA 7 mmc1_dat6 0 IO gpio_128 R27 4 IO safe_mode 0 IO 4 IO 7 mmc2_clk 0 O mcspi3_clk NA 7 safe_mode AE2 NA mmc1_dat7 gpio_129 R25 1 IO IO gpio_130 AG5 7 20 0 IO 1 IO gpio_131 (4) mmc2_ cmd mcspi3_ simo (3) NA 4 safe_mode 4 IO The buffer strength of this IO cell is programmable (2, 4, 6, or 8 mA) according to the selected mode; the default value is described in the above table. The PU nominal drive strength of this IO cell is equal to 25 µA @ 1.8V and 41.6 µA @ 3.0V. The PD nominal drive strength of this IO cell is equal to 1 mA @ 1.8V and 1.66 mA @ 3.0V. TERMINAL DESCRIPTION Submit Documentation Feedback OMAP3525-HiRel and OMAP3530-HiRel Applications Processors www.ti.com SPRS599 SPRS599 JUNE 2009 Table 2-1. Ball Characteristics (CBB Pkg.) (continued) BALL BOTTOM [1] BALL TOP [2] PIN NAME [3] MODE [4] TYPE [5] BALL RESET STATE [6] BALL RESET REL. STATE [7] RESET REL. MODE [8] POWER [9] HYS [10] BUFFER STRENGTH (mA) [11] PULL U/D TYPE [12] IO CELL [13] safe_mode 7 AH5 NA mmc2_ dat0 mcspi3_ somi 0 IO H H 7 VDDS Yes 4 PU/ PD LVCMOS 1 IO IO H H 7 VDDS Yes 4 PU/ PD LVCMOS H H 7 VDDS Yes 4 PU/ PD LVCMOS H H 7 VDDS Yes 4 PU/ PD LVCMOS L L 7 VDDS Yes 4 PU/ PD LVCMOS L L 7 VDDS Yes 4 PU/ PD LVCMOS L L 7 VDDS Yes 4 PU/ PD LVCMOS L L 7 VDDS Yes 4 PU/ PD LVCMOS L L 7 VDDS Yes 4 PU/ PD LVCMOS L L 7 VDDS Yes 4 PU/ PD LVCMOS gpio_132 mmc2_ dat1 0 IO 4 IO safe_mode NA 7 mmc2_ dat2 0 IO mcspi3_cs1 AG4 1 O IO gpio_134 NA 7 mmc2_ dat3 0 IO mcspi3_cs0 AF4 4 safe_mode 1 IO IO gpio_135 AE4 7 0 IO 1 O mmc3_dat0 3 IO gpio_136 4 IO safe_mode 7 0 IO 1 O cam_global_reset 2 IO mmc3_dat1 3 IO gpio_137 4 IO hsusb3_tll_stp 5 IO mm3_rxdp 6 IO safe_mode NA mmc2_ dat5 mmc2_dir_dat1 AF3 NA mmc2_ dat4 mmc2_dir_dat0 AH3 NA 4 safe_mode 7 mmc2_ dat6 0 IO mmc2_dir_ cmd 1 O cam_ shutter 2 O mmc3_dat2 3 IO gpio_138 IO 5 IO safe_mode 7 0 IO 1 I mmc3_dat3 3 IO gpio_139 4 IO hsusb3_tll_nxt 5 IO mm3_rxdm 6 IO safe_mode 7 mcbsp3_dx 0 IO uart2_cts NA mmc2_ dat7 mmc2_ clkin AF6 NA 4 hsusb3_tll_dir AE3 1 I gpio_140 IO 5 IO safe_mode 7 mcbsp3_dr 0 I uart2_rts NA 4 hsusb3_tll_ data4 AE6 PRODUCT PREVIEW NA 7 gpio_133 AH4 4 safe_mode 1 O gpio_141 4 IO hsusb3_tll_ data5 5 IO safe_mode 7 Submit Documentation Feedback TERMINAL DESCRIPTION 21 OMAP3525-HiRel and OMAP3530-HiRel Applications Processors SPRS599 SPRS599 JUNE 2009 www.ti.com Table 2-1. Ball Characteristics (CBB Pkg.) (continued) BALL BOTTOM [1] BALL TOP [2] PIN NAME [3] MODE [4] TYPE [5] BALL RESET STATE [6] BALL RESET REL. STATE [7] RESET REL. MODE [8] POWER [9] HYS [10] BUFFER STRENGTH (mA) [11] PULL U/D TYPE [12] IO CELL [13] AF5 NA mcbsp3_ clkx 0 IO L L 7 VDDS Yes 4 PU/ PD LVCMOS uart2_tx 1 O L L 7 VDDS Yes 4 PU/ PD LVCMOS H H 7 VDDS Yes 4 PU/ PD LVCMOS H H 7 VDDS Yes 4 PU/ PD LVCMOS H H 7 VDDS Yes 4 PU/ PD LVCMOS H H 7 VDDS Yes 4 PU/ PD LVCMOS L L 7 VDDS Yes 4 PU/ PD LVCMOS L L 7 VDDS Yes 4 PU/ PD LVCMOS L L 7 VDDS Yes 4 PU/ PD LVCMOS L L 7 VDDS Yes 4 PU/ PD LVCMOS L L 7 VDDS Yes 4 PU/ PD LVCMOS L L 7 VDDS Yes 4 PU/ PD LVCMOS gpio_142 IO 7 mcbsp3_fsx 0 IO uart2_rx NA IO 5 safe_mode AE5 4 hsusb3_tll_ data6 1 I gpio_143 IO 7 I 1 IO 2 IO gpio_144 4 IO safe_mode PRODUCT PREVIEW 0 gpt9_pwm_evt 7 0 O 1 I gpt10_pwm_evt 2 IO gpio_145 4 IO safe_mode 7 0 O 1 IO gpt11_pwm _evt 2 IO gpio_146 4 IO safe_mode 7 0 I 1 IO gpt8_pwm_evt 2 IO gpio_147 4 IO safe_mode 7 0 O 4 IO 7 uart1_cts 0 I 4 IO hsusb3_tll_clk 5 O safe_mode 7 3 IO 4 IO 7 mcbsp4_ clkx 0 IO gpio_152 4 IO hsusb3_tll_ data1 5 IO mm3_txse0 6 IO safe_mode 7 mcbsp4_dr 0 I gpio_153 4 IO hsusb3_tll_ data0 5 IO mm3_rxrcv 22 IO safe_mode NA I 2 gpio_151 AD1 0 mcspi4_clk NA uart1_rx mcbsp1_ clkr AE1 NA 7 uart1_rts gpio_150 Y8 IO safe_mode NA O 4 gpio_149 W8 0 safe_mode NA uart1_tx gpio_148 AA9 NA uart2_rx mcbsp3_fsx AA8 NA uart2_tx mcbsp3_ clkx AD25 NA uart2_rts mcbsp3_dr AA25 NA uart2_cts mcbsp3_dx AB25 NA IO 5 safe_mode AB26 4 hsusb3_tll_ data7 6 IO TERMINAL DESCRIPTION Submit Documentation Feedback OMAP3525-HiRel and OMAP3530-HiRel Applications Processors www.ti.com SPRS599 SPRS599 JUNE 2009 Table 2-1. Ball Characteristics (CBB Pkg.) (continued) BALL TOP [2] PIN NAME [3] MODE [4] safe_mode 7 AD2 NA mcbsp4_dx gpio_154 POWER [9] HYS [10] BUFFER STRENGTH (mA) [11] PULL U/D TYPE [12] IO CELL [13] 0 IO L L 7 VDDS Yes 4 PU/ PD LVCMOS 4 IO 5 IO 6 IO 7 mcbsp4_fsx 0 IO L L 7 VDDS Yes 4 PU/ PD LVCMOS gpio_155 4 IO hsusb3_tll_ data3 5 IO mm3_txen_n 6 IO safe_mode 7 mcbsp1_ clkr 0 IO L L 7 VDDS Yes 4 PU/ PD LVCMOS mcspi4_clk NA RESET REL. MODE [8] safe_mode Y21 BALL RESET REL. STATE [7] mm3_txdat NA BALL RESET STATE [6] hsusb3_tll_ data2 AC1 TYPE [5] 1 IO IO L L 7 VDDS Yes 4 PU/ PD LVCMOS L L 7 VDDS Yes 4 PU/ PD LVCMOS L L 7 VDDS Yes 4 PU/ PD LVCMOS L L 7 VDDS Yes 4 PU/ PD LVCMOS L L 7 VDDS Yes 4 PU/ PD LVCMOS L L 7 VDDS Yes 4 PU/ PD LVCMOS H H 7 VDDS Yes 4 PU/ PD LVCMOS H H 7 VDDS Yes 4 PU/ PD LVCMOS H H 7 VDDS Yes 4 PU/ PD LVCMOS H H 7 VDDS Yes 4 PU/ PD LVCMOS gpio_156 AA21 NA 4 safe_mode 7 mcbsp1_fsr 0 IO cam_global_reset 2 IO IO gpio_157 7 0 IO 1 IO mcbsp3_dx 2 IO gpio_158 4 IO safe_mode NA mcbsp1_dx mcspi4_ simo U21 NA 4 safe_mode V21 7 mcbsp1_dr 0 I mcspi4_ somi 1 IO mcbsp3_dr 2 O gpio_159 4 IO safe_mode 4 IO 5 I 7 mcbsp1_fsx 0 IO 1 IO mcbsp3_fsx 2 IO gpio_161 4 IO safe_mode 7 mcbsp1_ clkx 0 IO mcbsp3_ clkx NA O mcspi4_cs0 W21 I 2 safe_mode NA 0 uart1_cts K26 7 gpio_160 NA mcbsp_clks cam_ shutter T21 2 IO IO gpio_162 7 uart3_cts_ rctx 0 IO gpio_163 NA 4 safe_mode H18 4 IO safe_mode NA 7 uart3_rts_ sd 0 O gpio_164 H19 4 IO safe_mode NA 7 uart3_rx_ irrx 0 I gpio_165 H20 4 IO safe_mode NA 7 uart3_tx_ irtx 0 O gpio_166 H21 PRODUCT PREVIEW BALL BOTTOM [1] 4 IO Submit Documentation Feedback TERMINAL DESCRIPTION 23 OMAP3525-HiRel and OMAP3530-HiRel Applications Processors SPRS599 SPRS599 JUNE 2009 www.ti.com Table 2-1. Ball Characteristics (CBB Pkg.) (continued) BALL BOTTOM [1] BALL TOP [2] PIN NAME [3] MODE [4] TYPE [5] BALL RESET STATE [6] BALL RESET REL. STATE [7] RESET REL. MODE [8] POWER [9] HYS [10] BUFFER STRENGTH (mA) [11] PULL U/D TYPE [12] IO CELL [13] safe_mode 7 T28 NA hsusb0_clk gpio_120 0 I L L 7 VDDS Yes 4 PU/ PD LVCMOS 4 IO H H 7 VDDS Yes 4 PU/ PD LVCMOS L L 7 VDDS Yes 4 PU/ PD LVCMOS L L 7 VDDS Yes 4 PU/ PD LVCMOS L L 7 VDDS Yes 4 PU/ PD LVCMOS L L 7 VDDS Yes 4 PU/ PD LVCMOS L L 7 VDDS Yes 4 PU/ PD LVCMOS L L 7 VDDS Yes 4 PU/ PD LVCMOS L L 7 VDDS Yes 4 PU/ PD LVCMOS L L 7 VDDS Yes 4 PU/ PD LVCMOS L L 7 VDDS Yes 4 PU/ PD LVCMOS L L 7 VDDS Yes 4 PU/ PD LVCMOS safe_mode NA 0 O 4 IO 7 hsusb0_dir 0 I gpio_122 R28 7 safe_mode NA hsusb0_stp gpio_121 T25 4 IO safe_mode NA PRODUCT PREVIEW 7 hsusb0_nxt 0 I gpio_124 T26 4 IO safe_mode NA 7 hsusb0_ data0 0 IO uart3_tx_ irtx T27 2 O IO gpio_125 NA 7 hsusb0_ data1 0 IO uart3_rx_ irrx U28 4 safe_mode 2 I IO gpio_130 NA 7 hsusb0_ data2 0 IO uart3_rts_ sd U27 4 safe_mode 2 O IO gpio_131 NA 7 hsusb0_ data3 0 IO uart3_cts_ rctx U26 4 safe_mode 2 IO IO gpio_169 NA 7 hsusb0_ data4 0 IO gpio_188 U25 4 safe_mode 4 IO safe_mode NA 7 hsusb0_ data5 0 IO gpio_189 V28 4 IO safe_mode NA 7 hsusb0_ data6 0 IO gpio_190 V27 4 IO safe_mode NA 7 hsusb0_ data7 0 IO gpio_191 V26 4 IO safe_mode 7 K21 NA i2c1_scl 0 IOD H H 0 VDDS Yes 4 PU/ PD Open Drain J21 NA i2c1_sda 0 IOD H H 0 VDDS Yes 4 PU/ PD Open Drain AF15 NA i2c2_scl 0 IOD H H 7 VDDS Yes 4 PU/ PD Open Drain gpio_168 4 IO safe_mode 7 i2c2_sda 0 IOD H H 7 VDDS Yes 4 PU/ PD Open Drain gpio_183 4 IO safe_mode 7 i2c3_scl 0 IOD H H 7 VDDS Yes 4 PU/ PD Open Drain gpio_184 4 IO safe_mode 7 i2c3_sda 0 IOD H H 7 VDDS Yes 4 PU/ PD Open Drain gpio_185 4 IO AE15 NA AF14 NA AG14 24 NA TERMINAL DESCRIPTION Submit Documentation Feedback OMAP3525-HiRel and OMAP3530-HiRel Applications Processors www.ti.com SPRS599 SPRS599 JUNE 2009 Table 2-1. Ball Characteristics (CBB Pkg.) (continued) BALL TOP [2] AD26 NA safe_mode O 7 hdq_sio 0 IOD 1 I i2c2_sccbe 2 O i2c3_sccbe 3 O gpio_170 4 IO safe_mode 7 mcspi1_clk 0 IO mmc2_dat4 NA IOD 1 sys_altclk AB3 0 safe_mode NA 7 i2c4_sda sys_ nvmode2 J25 7 i2c4_scl sys_ nvmode1 NA MODE [4] safe_mode AE26 PIN NAME [3] TYPE [5] BALL RESET STATE [6] BALL RESET REL. STATE [7] RESET REL. MODE [8] POWER [9] HYS [10] BUFFER STRENGTH (mA) [11] PULL U/D TYPE [12] IO CELL [13] 0 IOD H H 0 VDDS Yes 4 PU/ PD Open Drain 1 O H H 0 VDDS Yes 4 PU/ PD Open Drain H H 7 VDDS Yes 4 PU/ PD LVCMOS L L 7 VDDS Yes 4 (3) 1 IO PU/ PD LVCMOS IO L L 7 VDDS Yes 4 (3) PU/ PD LVCMOS L L 7 VDDS Yes 4 (3) PU/ PD LVCMOS H H 7 VDDS Yes 4 (3) PU/ PD LVCMOS L H 7 VDDS Yes 4 (3) PU/ PD LVCMOS L H 7 VDDS Yes 4 (3) PU/ PD LVCMOS H H 7 VDDS Yes 4 PU/ PD LVCMOS L L 7 VDDS Yes 4 PU/ PD LVCMOS L L 7 VDDS Yes 4 PU/ PD LVCMOS gpio_171 NA 7 mcspi1_ simo 0 IO mmc2_dat5 AB4 4 safe_mode 1 IO IO gpio_172 7 mcspi1_ somi 0 IO mmc2_dat6 NA 4 safe_mode AA4 1 IO IO gpio_173 7 mcspi1_cs0 0 IO mmc2_dat7 NA 4 safe_mode AC2 1 IO IO gpio_174 7 mcspi1_cs1 0 O mmc3_cmd NA 4 safe_mode AC3 3 IO IO gpio_175 7 mcspi1_cs2 0 O mmc3_clk NA 4 safe_mode AB1 3 O IO gpio_176 7 0 O 2 IO hsusb2_ data2 3 IO gpio_177 4 IO mm2_txdat 5 IO safe_mode NA mcspi1_cs3 hsusb2_tll_ data2 AA3 NA 4 safe_mode AB2 7 mcspi2_clk 0 IO hsusb2_tll_ data7 2 IO hsusb2_ data7 3 O gpio_178 4 IO safe_mode 7 0 IO 1 IO hsusb2_tll_ data4 2 IO hsusb2_ data4 3 I gpio_179 4 IO safe_mode NA mcspi2_ simo gpt9_pwm_evt Y2 PRODUCT PREVIEW BALL BOTTOM [1] 7 Submit Documentation Feedback TERMINAL DESCRIPTION 25 OMAP3525-HiRel and OMAP3530-HiRel Applications Processors SPRS599 SPRS599 JUNE 2009 www.ti.com Table 2-1. Ball Characteristics (CBB Pkg.) (continued) BALL BOTTOM [1] BALL TOP [2] Y3 NA PIN NAME [3] MODE [4] TYPE [5] BALL RESET STATE [6] BALL RESET REL. STATE [7] RESET REL. MODE [8] POWER [9] HYS [10] BUFFER STRENGTH (mA) [11] PULL U/D TYPE [12] IO CELL [13] L L 7 VDDS Yes 4 PU/ PD LVCMOS H H 7 VDDS Yes 4 PU/ PD LVCMOS L L 7 VDDS Yes 4 PU/ PD LVCMOS mcspi2_ somi 0 IO gpt10_pwm_evt 1 IO hsusb2_tll_ data5 2 IO hsusb2_ data5 3 O gpio_180 4 IO safe_mode 7 0 IO 1 IO hsusb2_tll_ data6 2 IO hsusb2_ data6 3 O gpio_181 NA mcspi2_cs0 gpt11_pwm_evt Y4 4 IO PRODUCT PREVIEW safe_mode 7 0 O 1 IO hsusb2_tll_ data3 2 IO hsusb2_ data3 3 IO gpio_182 4 IO mm2_txen_n 5 IO safe_mode NA mcspi2_cs1 gpt8_pwm_evt V3 7 AE25 NA sys_32k 0 I Z I NA VDDS Yes NA NA LVCMOS AE17 NA sys_xtalin 0 I Z I NA VDDS NA NA NA LVCMOS AF17 NA sys_xtalout 0 O Z O NA VDDS NA NA NA LVCMOS AF25 NA sys_clkreq 0 IO 0 1 0 VDDS Yes 8 PU/ PD LVCMOS gpio_1 4 IO safe_mode 7 sys_nirq 0 I H H 7 VDDS Yes 4 PU/ PD LVCMOS gpio_0 4 IO LVCMOS AF26 NA safe_mode 7 AH25 NA sys_ nrespwron 0 I Z I NA VDDS Yes NA NA AF24 NA sys_ nreswarm 0 IOD 0 1 (PU) 0 VDDS Yes 8 PU/ PD gpio_30 4 IO safe_mode 7 sys_boot0 0 I gpio_2 4 IO safe_mode 7 sys_boot1 0 I gpio_3 4 IO safe_mode 7 sys_boot2 0 I gpio_4 4 IO safe_mode 7 sys_boot3 0 I gpio_5 4 IO safe_mode 7 sys_boot4 0 I mmc2_dir_dat2 1 O IO AH26 NA AG26 AE14 AF18 AF19 NA NA NA NA gpio_6 AE21 NA 4 safe_mode sys_boot5 0 I 1 0 VDDS Yes 4 PU/ PD LVCMOS Z Z 0 VDDS Yes 4 PU/ PD LVCMOS Z Z 0 VDDS Yes 4 PU/ PD LVCMOS Z Z 0 VDDS Yes 4 PU/ PD LVCMOS Z Z 0 VDDS Yes 4 PU/ PD LVCMOS Z Z 0 VDDS Yes 4 PU/ PD LVCMOS Z Z 0 VDDS Yes 4 PU/ PD LVCMOS IO gpio_7 4 7 sys_boot6 0 I gpio_8 26 Z O safe_mode NA Z 7 mmc2_dir_dat3 AF21 LVCMOS Open Drain 4 IO TERMINAL DESCRIPTION Submit Documentation Feedback OMAP3525-HiRel and OMAP3530-HiRel Applications Processors www.ti.com SPRS599 SPRS599 JUNE 2009 Table 2-1. Ball Characteristics (CBB Pkg.) (continued) BALL BOTTOM [1] BALL TOP [2] PIN NAME [3] MODE [4] TYPE [5] BALL RESET STATE [6] BALL RESET REL. STATE [7] RESET REL. MODE [8] POWER [9] HYS [10] BUFFER STRENGTH (mA) [11] PULL U/D TYPE [12] IO CELL [13] safe_mode 7 AF22 NA sys_off_ mode gpio_9 0 O 0 L 7 VDDS Yes 8 PU/ PD LVCMOS 4 IO L L 7 VDDS Yes 8 PU/ PD LVCMOS L L 7 VDDS Yes 4 PU/ PD LVCMOS safe_mode NA 7 sys_clkout1 0 O gpio_10 AG25 4 IO safe_mode NA 7 sys_clkout2 0 O gpio_186 AE22 4 IO 7 NA sys_ ipmcsws 0 AI Z AI NA VDDS NA NA NA Analog A1 NA sys_ opmcsws 0 AO 0 AO NA VDDS No NA NA LVCMOS AA17 NA jtag_ntrst 0 I L L 0 VDDS Yes NA PU/ PD LVCMOS AA13 NA jtag_tck 0 I L L 0 VDDS Yes NA PU/ PD LVCMOS AA12 NA jtag_rtck 0 O L 0 0 VDDS Yes 8 PU/ PD LVCMOS AA18 NA jtag_tms_tmsc 0 IO H H 0 VDDS Yes 8 PU/ PD LVCMOS AA20 NA jtag_tdi 0 I H H 0 VDDS Yes NA PU/ PD LVCMOS AA19 NA jtag_tdo 0 O L Z 0 VDDS Yes 8 PU/ PD LVCMOS AA11 NA jtag_emu0 0 IO H H 0 VDDS Yes 8 PU/ PD LVCMOS gpio_11 4 IO safe_mode 7 jtag_emu1 0 IO H H 0 VDDS Yes 8 PU/ PD LVCMOS gpio_31 4 IO safe_mode 7 etk_clk 0 O H H 4 VDDS Yes 4 PU/ PD LVCMOS mcbsp5_ clkx 1 IO O H H 4 VDDS Yes 4 PU/ PD LVCMOS H H 4 VDDS Yes 4 PU/ PD LVCMOS H H 4 VDDS Yes 4 PU/ PD LVCMOS AA10 AF10 NA NA mmc3_clk 2 hsusb1_stp 3 O gpio_12 4 IO IO mm1_rxdp 0 O 2 IO 3 O gpio_13 4 IO hsusb1_tll_clk 6 O etk_d0 0 O mcspi3_ simo NA I etk_ctl hsusb1_clk AF11 6 mmc3_cmd NA 5 hsusb1_tll_stp AE10 1 IO mmc3_dat4 IO 3 IO gpio_14 4 IO mm1_rxrcv 5 IO hsusb1_tll_ data0 6 IO etk_d1 0 O mcspi3_ somi 1 IO hsusb1_ data1 3 IO gpio_15 4 IO mm1_txse0 5 IO hsusb1_tll_ data1 NA 2 hsusb1_ data0 AG12 PRODUCT PREVIEW safe_mode B1 6 IO Submit Documentation Feedback TERMINAL DESCRIPTION 27 OMAP3525-HiRel and OMAP3530-HiRel Applications Processors SPRS599 SPRS599 JUNE 2009 www.ti.com Table 2-1. Ball Characteristics (CBB Pkg.) (continued) BALL BOTTOM [1] BALL TOP [2] AH12 NA PIN NAME [3] MODE [4] TYPE [5] BALL RESET STATE [6] BALL RESET REL. STATE [7] RESET REL. MODE [8] POWER [9] HYS [10] BUFFER STRENGTH (mA) [11] PULL U/D TYPE [12] IO CELL [13] H H 4 VDDS Yes 4 PU/ PD LVCMOS H H 4 VDDS Yes 4 PU/ PD LVCMOS L L 4 VDDS Yes 4 PU/ PD LVCMOS L L 4 VDDS Yes 4 PU/ PD LVCMOS L L 4 VDDS Yes 4 PU/ PD LVCMOS L L 4 VDDS Yes 4 PU/ PD LVCMOS L L 4 VDDS Yes 4 PU/ PD LVCMOS L L 4 VDDS Yes 4 PU/ PD LVCMOS O 1 IO 3 IO gpio_16 4 IO mm1_txdat 5 IO hsusb1_tll_data2 6 IO etk_d3 0 O mcspi3_clk NA 0 hsusb1_ data2 AE13 etk_d2 mcspi3_cs0 1 IO IO 4 IO 6 IO etk_d4 0 O mcbsp5_dr NA IO 3 hsusb1_tll_ data7 AE11 2 gpio_17 PRODUCT PREVIEW mmc3_dat3 hsusb1_ data7 1 I mmc3_dat0 IO 4 IO hsusb1_tll_ data4 6 IO etk_d5 0 O mcbsp5_fsx NA IO 3 gpio_18 AH9 2 hsusb1_ data4 1 IO mmc3_dat1 IO 4 IO hsusb1_tll_ data5 6 IO etk_d6 0 O mcbsp5_dx NA IO 3 gpio_19 AF13 2 hsusb1_ data5 1 IO mmc3_dat2 IO 4 IO hsusb1_tll_ data6 6 IO etk_d7 0 O mcspi3_cs1 NA IO 3 gpio_20 AH14 2 hsusb1_ data6 1 O mmc3_dat7 IO etk_d8 0 O 1 O mmc3_dat6 2 IO hsusb1_dir 3 I gpio_22 4 IO hsusb1_tll_dir 6 O etk_d9 0 O sys_secure_indic ator 1 O mmc3_dat5 2 IO hsusb1_nxt 3 I gpio_23 4 IO mm1_rxdm 5 IO hsusb1_tll_nxt 28 IO 6 sys_drm_ msecure NA IO 5 hsusb1_tll_ data3 AG9 IO 4 mm1_txen_n NA IO 3 gpio_21 AF9 2 hsusb1_ data3 6 O TERMINAL DESCRIPTION Submit Documentation Feedback OMAP3525-HiRel and OMAP3530-HiRel Applications Processors www.ti.com SPRS599 SPRS599 JUNE 2009 Table 2-1. Ball Characteristics (CBB Pkg.) (continued) BALL TOP [2] AE7 NA PIN NAME [3] MODE [4] TYPE [5] BALL RESET STATE [6] BALL RESET REL. STATE [7] RESET REL. MODE [8] POWER [9] HYS [10] BUFFER STRENGTH (mA) [11] PULL U/D TYPE [12] IO CELL [13] L L 4 VDDS Yes 4 PU/ PD LVCMOS L L 4 VDDS Yes 4 PU/ PD LVCMOS L L 4 VDDS Yes 4 PU/ PD LVCMOS L L 4 VDDS Yes 4 PU/ PD LVCMOS L L 4 VDDS Yes 4 PU/ PD LVCMOS L L 4 VDDS Yes 4 PU/ PD LVCMOS O 2 I 3 O gpio_24 4 IO hsusb2_tll_clk 6 O etk_d11 0 O hsusb2_stp NA 0 hsusb2_clk AF7 etk_d10 uart1_rx 3 O gpio_25 IO 6 I etk_d12 0 O hsusb2_dir NA IO 5 hsusb2_tll_stp AG7 4 mm2_rxdp 3 I gpio_26 NA IO 6 O etk_d13 0 O hsusb2_nxt AH7 4 hsusb2_tll_dir 3 I gpio_27 IO 5 IO hsusb2_tll_nxt 6 O etk_d14 0 O hsusb2_ data0 NA 4 mm2_rxdm AG8 3 IO gpio_28 IO 5 IO hsusb2_tll_ data0 6 IO etk_d15 0 O hsusb2_ data1 NA 4 mm2_rxrcv AH8 PRODUCT PREVIEW BALL BOTTOM [1] 3 IO gpio_29 4 IO mm2_txse0 5 IO hsusb2_tll_ data1 6 IO Submit Documentation Feedback TERMINAL DESCRIPTION 29 OMAP3525-HiRel and OMAP3530-HiRel Applications Processors SPRS599 SPRS599 JUNE 2009 www.ti.com Table 2-2. Ball Characteristics (CBC Pkg.) BALL BOTTOM [1] BALL TOP [2] AE16 - PIN NAME [4] MODE [5] TYPE [6] BALL RESET STATE [7] BALL RESET REL. STATE [8] RESET REL. MODE [9] POWER [10] HYS [11] BUFFER STRENG TH (mA) [12] PULLUP /DOWN TYPE [13] IO CELL [14] L L 7 - Yes 4 PU100/ PU100/ PD100 PD100 LVDS/ CMOS L L 7 - Yes 4 PU100/ PU100/ PD100 PD100 LVDS/ CMOS L L 7 - Yes 4 PU100/ PU100/ PD100 PD100 LVDS/ CMOS L L 7 - Yes 4 PU100/ PU100/ PD100 PD100 LVDS/ CMOS L L 7 - Yes 4 PU100/ PU100/ PD100 PD100 LVDS/ CMOS L L 7 - Yes 4 PU100/ PU100/ PD100 PD100 LVDS/ CMOS 4 I 7 - - 0 IDS 4 I 7 - - 0 IDS 4 I 7 - - 0 IDS gpio_113 4 I safe_mode 7 - - 0 IDS gpio_115 PRODUCT PREVIEW IDS safe_mode - I 2 gpio_114 AE17 0 safe_mode - cam_d1 gpio_112 AD16 - safe_mode - I 7 gpio_100 AE18 4 - - IDS safe_mode AD17 I 2 gpio_99 - 0 - AE15 cam_d0 4 I safe_mode 7 - - G20 sdrc_a0 0 O 0 0 0 vdds_io No 4 (1) NA LVDS/ CMOS - K20 sdrc_a1 0 O 0 0 0 vdds_io No 4 (1) NA LVDS/ CMOS - J20 sdrc_a2 0 O 0 0 0 vdds_io No 4 (1) NA LVDS/ CMOS - J21 sdrc_a3 0 O 0 0 0 vdds_io No 4 (1) NA LVDS/ CMOS - U21 sdrc_a4 0 O 0 0 0 vdds_io No 4 (1) NA LVDS/ CMOS (1) NA LVDS/ CMOS - R20 sdrc_a5 0 O 0 0 0 vdds_io No 4 - M21 sdrc_a6 0 O 0 0 0 vdds_io No 4 (1) NA LVDS/ CMOS - M20 sdrc_a7 0 O 0 0 0 vdds_io No 4 (1) NA LVDS/ CMOS - N20 sdrc_a8 0 O 0 0 0 vdds_io No 4 (1) NA LVDS/ CMOS - K21 sdrc_a9 0 O 0 0 0 vdds_io No 4 (1) NA LVDS/ CMOS - Y16 sdrc_a10 0 O 0 0 0 vdds_io No 4 (1) NA LVDS/ CMOS - N21 sdrc_a11 0 O 0 0 0 vdds_io No 4 (1) NA LVDS/ CMOS - R21 sdrc_a12 0 O 0 0 0 vdds_io No 4 (1) NA LVDS/ CMOS - AA15 sdrc_a13 0 O 0 0 0 vdds_io No 4 (1) NA LVDS/ CMOS - Y12 sdrc_a14 0 O 0 0 0 vdds_io No 4 (1) NA LVDS/ CMOS - AA18 sdrc_ba0 0 O 0 0 0 vdds_io No 4 (1) NA LVDS/ CMOS - V20 sdrc_ba1 0 O 0 0 0 vdds_io No 4 (1) NA LVDS/ CMOS - Y15 sdrc_cke0 0 O H 1 7 vdds_io Yes 4 (1) safe_mode 7 PU100/ PU100/ PD100 PD100 LVDS/ CMOS sdrc_cke1 0 O H 1 7 vdds_io Yes 4 (1) safe_mode 7 PU100/ PU100/ PD100 PD100 LVDS/ CMOS - (1) 30 Y13 The drive strength is programmable vs the capacity load: load range = [2 pF to 6 pF] per default or [6 pF to 12 pF] according to the selected mode. TERMINAL DESCRIPTION Submit Documentation Feedback OMAP3525-HiRel and OMAP3530-HiRel Applications Processors www.ti.com SPRS599 SPRS599 JUNE 2009 Table 2-2. Ball Characteristics (CBC Pkg.) (continued) BALL TOP [2] - A12 - PIN NAME [4] MODE [5] TYPE [6] BALL RESET STATE [7] BALL RESET REL. STATE [8] RESET REL. MODE [9] POWER [10] HYS [11] BUFFER STRENG TH (mA) [12] PULLUP /DOWN TYPE [13] IO CELL [14] sdrc_clk 0 IO L 0 0 vdds_io Yes 4 (1) PU100/ PU100/ PD100 PD100 LVDS/ CMOS D1 sdrc_d0 0 IO L Z 0 vdds_io Yes 4 (1) PU100/ PU100/ PD100 PD100 LVDS/ CMOS - G1 sdrc_d1 0 IO L Z 0 vdds_io Yes 4 (1) PU100/ PU100/ PD100 PD100 LVDS/ CMOS - G2 sdrc_d2 0 IO L Z 0 vdds_io Yes 4 (1) PU100/ PU100/ PD100 PD100 LVDS/ CMOS - E1 sdrc_d3 0 IO L Z 0 vdds_io Yes 4 (1) PU100/ PU100/ PD100 PD100 LVDS/ CMOS - D2 sdrc_d4 0 IO L Z 0 vdds_io Yes 4 (1) PU100/ PU100/ PD100 PD100 LVDS/ CMOS - E2 sdrc_d5 0 IO L Z 0 vdds_io Yes 4 (1) PU100/ PU100/ PD100 PD100 LVDS/ CMOS - B3 sdrc_d6 0 IO L Z 0 vdds_io Yes 4 (1) PU100/ PU100/ PD100 PD100 LVDS/ CMOS - B4 sdrc_d7 0 IO L Z 0 vdds_io Yes 4 (1) PU100/ PU100/ PD100 PD100 LVDS/ CMOS - A10 sdrc_d8 0 IO L Z 0 vdds_io Yes 4 (1) PU100/ PU100/ PD100 PD100 LVDS/ CMOS - B11 sdrc_d9 0 IO L Z 0 vdds_io Yes 4 (1) PU100/ PU100/ PD100 PD100 LVDS/ CMOS - A11 sdrc_d10 0 IO L Z 0 vdds_io Yes 4 (1) PU100/ PU100/ PD100 PD100 LVDS/ CMOS - B12 sdrc_d11 0 IO L Z 0 vdds_io Yes 4 (1) PU100/ PU100/ PD100 PD100 LVDS/ CMOS - A16 sdrc_d12 0 IO L Z 0 vdds_io Yes 4 (1) PU100/ PU100/ PD100 PD100 LVDS/ CMOS - A17 sdrc_d13 0 IO L Z 0 vdds_io Yes 4 (1) PU100/ PU100/ PD100 PD100 LVDS/ CMOS - B17 sdrc_d14 0 IO L Z 0 vdds_io Yes 4 (1) PU100/ PU100/ PD100 PD100 LVDS/ CMOS - B18 sdrc_d15 0 IO L Z 0 vdds_io Yes 4 (1) PU100/ PU100/ PD100 PD100 LVDS/ CMOS - B7 sdrc_d16 0 IO L Z 0 vdds_io Yes 4 (1) PU100/ PU100/ PD100 PD100 LVDS/ CMOS - A5 sdrc_d17 0 IO L Z 0 vdds_io Yes 4 (1) PU100/ PU100/ PD100 PD100 LVDS/ CMOS - B6 sdrc_d18 0 IO L Z 0 vdds_io Yes 4 (1) PU100/ PU100/ PD100 PD100 LVDS/ CMOS (1) PU100/ PU100/ PD100 PD100 LVDS/ CMOS - A6 sdrc_d19 0 IO L Z 0 vdds_io Yes 4 - A8 sdrc_d20 0 IO L Z 0 vdds_io Yes 4 (1) PU100/ PU100/ PD100 PD100 LVDS/ CMOS - B9 sdrc_d21 0 IO L Z 0 vdds_io Yes 4 (1) PU100/ PU100/ PD100 PD100 LVDS/ CMOS - A9 sdrc_d22 0 IO L Z 0 vdds_io Yes 4 (1) PU100/ PU100/ PD100 PD100 LVDS/ CMOS - B10 sdrc_d23 0 IO L Z 0 vdds_io Yes 4 (1) PU100/ PU100/ PD100 PD100 LVDS/ CMOS - C21 sdrc_d24 0 IO L Z 0 vdds_io Yes 4 (1) PU100/ PU100/ PD100 PD100 LVDS/ CMOS - D20 sdrc_d25 0 IO L Z 0 vdds_io Yes 4 (1) PU100/ PU100/ PD100 PD100 LVDS/ CMOS - B19 sdrc_d26 0 IO L Z 0 vdds_io Yes 4 (1) PU100/ PU100/ PD100 PD100 LVDS/ CMOS - C20 sdrc_d27 0 IO L Z 0 vdds_io Yes 4 (1) PU100/ PU100/ PD100 PD100 LVDS/ CMOS - D21 sdrc_d28 0 IO L Z 0 vdds_io Yes 4 (1) PU100/ PU100/ PD100 PD100 LVDS/ CMOS - E20 sdrc_d29 0 IO L Z 0 vdds_io Yes 4 (1) PU100/ PU100/ PD100 PD100 LVDS/ CMOS - E21 sdrc_d30 0 IO L Z 0 vdds_io Yes 4 (1) PU100/ PU100/ PD100 PD100 LVDS/ CMOS Submit Documentation Feedback TERMINAL DESCRIPTION 31 PRODUCT PREVIEW BALL BOTTOM [1] OMAP3525-HiRel and OMAP3530-HiRel Applications Processors SPRS599 SPRS599 JUNE 2009 www.ti.com Table 2-2. Ball Characteristics (CBC Pkg.) (continued) BALL BOTTOM [1] BALL TOP [2] - G21 - TYPE [6] BALL RESET STATE [7] BALL RESET REL. STATE [8] RESET REL. MODE [9] POWER [10] HYS [11] BUFFER STRENG TH (mA) [12] PULLUP /DOWN TYPE [13] IO CELL [14] sdrc_d31 0 IO L Z 0 vdds_io Yes 4 (1) PU100/ PU100/ PD100 PD100 LVDS/ CMOS H1 sdrc_dm0 0 O 0 0 0 vdds_io No 4 (1) NA LVDS/ CMOS - A14 sdrc_dm1 0 O 0 0 0 vdds_io No 4 (1) NA LVDS/ CMOS - A4 sdrc_dm2 0 O 0 0 0 vdds_io No 4 (1) NA LVDS/ CMOS - A18 sdrc_dm3 0 O 0 0 0 vdds_io No 4 (1) NA LVDS/ CMOS - C2 sdrc_dqs0 0 IO L Z 0 vdds_io Yes 4 (1) PU100/ PU100/ PD100 PD100 LVDS/ CMOS - B15 sdrc_dqs1 0 IO L Z 0 vdds_io Yes 4 (1) PU100/ PU100/ PD100 PD100 LVDS/ CMOS - B8 sdrc_dqs2 0 IO L Z 0 vdds_io Yes 4 (1) PU100/ PU100/ PD100 PD100 LVDS/ CMOS - A19 sdrc_dqs3 0 IO L Z 0 vdds_io Yes 4 (1) PU100/ PU100/ PD100 PD100 LVDS/ CMOS - U20 sdrc_ncas 0 O 1 1 0 vdds_io No 4 (1) NA LVDS/ CMOS - B13 sdrc_nclk 0 O 1 1 0 vdds_io No 4 (1) NA LVDS/ CMOS - T21 sdrc_ncs0 0 O 1 1 0 vdds_io No 4 (1) NA LVDS/ CMOS - T20 sdrc_ncs1 0 O 1 1 0 vdds_io No 4 (1) NA LVDS/ CMOS - V21 sdrc_nras 0 O 1 1 0 vdds_io No 4 (1) NA LVDS/ CMOS - Y18 sdrc_nwe 0 O 1 1 0 vdds_io No 4 (1) NA LVDS/ CMOS AE21 - dss_data0 0 IO L L 7 - No 4 - 1 ODS PU100/ PU100/ PD100 PD100 LVDS/ CMOS uart1_cts 2 I gpio_70 4 IO safe_mode 7 - dss_data1 0 IO L L 7 - No 4 - 1 ODS PU100/ PU100/ PD100 PD100 LVDS/ CMOS uart1_rts 2 O gpio_71 4 IO safe_mode 7 - dss_data2 0 IO L L 7 - No 4 - 1 ODS PU100/ PU100/ PD100 PD100 LVDS/ CMOS gpio_72 4 IO safe_mode 7 - dss_data3 0 IO L L 7 - No 4 - 1 ODS PU100/ PU100/ PD100 PD100 LVDS/ CMOS gpio_73 4 IO safe_mode 7 - dss_data4 0 IO L L 7 - No 4 - 1 ODS PU100/ PU100/ PD100 PD100 LVDS/ CMOS uart3_rx_irrx 2 I gpio_74 4 IO safe_mode 7 - dss_data5 0 IO L L 7 - No 4 - 1 ODS PU100/ PU100/ PD100 PD100 LVDS/ CMOS uart3_tx_irtx 2 O gpio_75 4 IO safe_mode PRODUCT PREVIEW MODE [5] 7 - AE22 AE23 AE24 AD23 AD24 32 - - - - - PIN NAME [4] TERMINAL DESCRIPTION Submit Documentation Feedback OMAP3525-HiRel and OMAP3530-HiRel Applications Processors www.ti.com SPRS599 SPRS599 JUNE 2009 Table 2-2. Ball Characteristics (CBC Pkg.) (continued) BALL TOP [2] AC26 - PIN NAME [4] MODE [5] TYPE [6] BALL RESET STATE [7] BALL RESET REL. STATE [8] RESET REL. MODE [9] POWER [10] HYS [11] BUFFER STRENG TH (mA) [12] PULLUP /DOWN TYPE [13] IO CELL [14] L L 7 - NA 4 PU100/ PU100/ PD100 PD100 LVDS/ CMOS L L 7 - NA 4 PU100/ PU100/ PD100 PD100 LVDS/ CMOS L L 7 - NA 4 PU100/ PU100/ PD100 PD100 LVDS/ CMOS L L 7 - NA 4 PU100/ PU100/ PD100 PD100 LVDS/ CMOS L L 7 - NA 4 PU100/ PU100/ PD100 PD100 LVDS/ CMOS L L 7 - NA 4 PU100/ PU100/ PD100 PD100 LVDS/ CMOS H H 7 vdds_io Yes 4 PU100/ PU100/ PD100 PD100 LVCMOS L L 7 - NA 4 PU100/ PU100/ PD100 PD100 LVDS/ CMOS L L 7 - NA 4 PU100/ PU100/ PD100 PD100 LVDS/ CMOS H H 7 vdds_io Yes 4 PU100/ PU100/ PD100 PD100 LVCMOS L L 7 vdds_io Yes 4 (1) PU100/ PU100/ PD100 PD100 LVCMOS L L 7 vdds_io Yes 4 (1) PU100/ PU100/ PD100 PD100 LVCMOS L L 7 vdds_io Yes 4 (1) PU100/ PU100/ PD100 PD100 LVCMOS ODS 4 IO 7 - dss_data14 0 IO 1 ODS 4 IO 7 - dss_data15 0 IO 1 ODS 4 IO 7 - dss_data20 0 O 1 O 2 IO 3 IO 4 IO 7 - dss_data22 0 O - 1 ODS mcspi3_cs1 2 O dss_data4 3 IO gpio_92 4 IO safe_mode 7 - dss_data23 0 O - 1 ODS dss_data5 3 IO gpio_93 4 IO safe_mode 7 - dss_pclk 0 O gpio_66 4 IO hw_dbg12 5 O safe_mode 7 - gpmc_a1 0 O gpio_34 4 IO safe_mode 7 - gpmc_a2 0 O gpio_35 4 IO safe_mode 7 - gpmc_a3 0 O gpio_36 - 1 safe_mode H2 IO gpio_90 - 0 dss_data2 H1 - dss_data13 mcspi3_somi - IO 7 - J2 4 safe_mode - ODS gpio_85 G25 1 - - IO safe_mode AB25 0 gpio_84 - - dss_data12 - AC25 IO 7 safe_mode - 4 gpio_83 F25 ODS - - 1 safe_mode AB26 IO gpio_82 - 0 - AA26 - dss_data11 safe_mode - IO 7 gpio_81 Y25 4 - - ODS safe_mode AA25 IO 1 gpio_80 - 0 - AD26 dss_data10 4 IO Submit Documentation Feedback TERMINAL DESCRIPTION 33 PRODUCT PREVIEW BALL BOTTOM [1] OMAP3525-HiRel and OMAP3530-HiRel Applications Processors SPRS599 SPRS599 JUNE 2009 www.ti.com Table 2-2. Ball Characteristics (CBC Pkg.) (continued) BALL BOTTOM [1] BALL TOP [2] G2 - PIN NAME [4] MODE [5] TYPE [6] safe_mode 7 0 O 1 0 O 1 4 0 O gpio_59 4 L 7 vdds_io Yes 4 (1) PU100/ PU100/ PD100 PD100 LVCMOS H H 7 vdds_io Yes 4 (1) PU100/ PU100/ PD100 PD100 LVCMOS H H 7 vdds_io Yes 4 (1) PU100/ PU100/ PD100 PD100 LVCMOS H H 7 vdds_io Yes 4 (1) PU100/ PU100/ PD100 PD100 LVCMOS H H 7 vdds_io Yes 4 (1) PU100/ PU100/ PD100 PD100 LVCMOS H H 7 vdds_io Yes 4 (1) PU100/ PU100/ PD100 PD100 LVCMOS L 0 0 vdds_io Yes 4 (1) PU100/ PU100/ PD100 PD100 LVCMOS - gpmc_clk L IO 7 LVCMOS I safe_mode PU100/ PU100/ PD100 PD100 - gpmc_a10 4 (1) IO 7 Yes I 4 vdds_io - gpmc_a9 7 IO gpio_43 PRODUCT PREVIEW 4 sys_ndmareq3 L1 O L - 0 safe_mode N1 7 gpmc_a8 L IO gpio_42 - 4 sys_ndmareq2 D2 O IO CELL [14] - 0 safe_mode - 7 gpmc_a7 PULLUP /DOWN TYPE [13] IO gpio_41 D1 4 safe_mode - O BUFFER STRENG TH (mA) [12] - 0 gpio_40 E2 7 gpmc_a6 HYS [11] IO safe_mode - 4 gpio_39 E1 O POWER [10] - 0 safe_mode - 7 gpmc_a5 RESET REL. MODE [9] IO gpio_38 F2 4 safe_mode - O BALL RESET REL. STATE [8] - 0 gpio_37 F1 7 gpmc_a4 BALL RESET STATE [7] IO safe_mode 7 - AA2 U2 gpmc_d0 0 IO H H 0 vdds_io Yes 4 (1) PU100/ PU100/ PD100 PD100 LVCMOS AA1 U1 gpmc_d1 0 IO H H 0 vdds_io Yes 4 (1) PU100/ PU100/ PD100 PD100 LVCMOS AC2 V2 gpmc_d2 0 IO H H 0 vdds_io Yes 4 (1) PU100/ PU100/ PD100 PD100 LVCMOS AC1 V1 gpmc_d3 0 IO H H 0 vdds_io Yes 4 (1) PU100/ PU100/ PD100 PD100 LVCMOS AE5 AA3 gpmc_d4 0 IO H H 0 vdds_io Yes 4 (1) PU100/ PU100/ PD100 PD100 LVCMOS AD6 AA4 gpmc_d5 0 IO H H 0 vdds_io Yes 4 (1) PU100/ PU100/ PD100 PD100 LVCMOS AD5 Y3 gpmc_d6 0 IO H H 0 vdds_io Yes 4 (1) PU100/ PU100/ PD100 PD100 LVCMOS AC5 Y4 gpmc_d7 0 IO H H 0 vdds_io Yes 4 (1) PU100/ PU100/ PD100 PD100 LVCMOS (1) PU100/ PU100/ PD100 PD100 LVCMOS V1 IO 4 IO 7 - gpmc_d10 0 IO 4 IO 7 - gpmc_d11 0 IO gpio_47 4 IO safe_mode 34 - 0 safe_mode P2 7 gpmc_d9 gpio_46 U2 IO safe_mode N1 IO 4 gpio_45 T1 0 safe_mode T1 gpmc_d8 gpio_44 Y1 R1 7 - TERMINAL DESCRIPTION H H 0 vdds_io Yes 4 H H 0 vdds_io Yes 4 (1) PU100/ PU100/ PD100 PD100 LVCMOS H H 0 vdds_io Yes 4 (1) PU100/ PU100/ PD100 PD100 LVCMOS H H 0 vdds_io Yes 4 (1) PU100/ PU100/ PD100 PD100 LVCMOS Submit Documentation Feedback OMAP3525-HiRel and OMAP3530-HiRel Applications Processors www.ti.com SPRS599 SPRS599 JUNE 2009 Table 2-2. Ball Characteristics (CBC Pkg.) (continued) BALL TOP [2] U1 P1 POWER [10] HYS [11] BUFFER STRENG TH (mA) [12] PULLUP /DOWN TYPE [13] IO CELL [14] gpmc_d12 0 IO H H 0 vdds_io Yes 4 (1) IO PU100/ PU100/ PD100 PD100 LVCMOS 4 7 - gpmc_d13 0 IO H H 0 vdds_io Yes 4 (1) IO PU100/ PU100/ PD100 PD100 LVCMOS 4 7 - gpmc_d14 0 IO H H 0 vdds_io Yes 4 (1) IO PU100/ PU100/ PD100 PD100 LVCMOS 4 safe_mode 7 - gpmc_d15 0 IO H H 0 vdds_io Yes 4 (1) 4 IO PU100/ PU100/ PD100 PD100 LVCMOS gpio_51 K2 RESET REL. MODE [9] gpio_50 M2 BALL RESET REL. STATE [8] safe_mode J2 BALL RESET STATE [7] gpio_49 L2 TYPE [6] safe_mode M1 MODE [5] gpio_48 P1 PIN NAME [4] safe_mode 7 - AD10 AA9 gpmc_nadv_ale 0 O 0 0 0 vdds_io No 4 (1) NA LVCMOS K2 - gpmc_nbe0_cle 0 O L 0 0 vdds_io Yes 4 (1) LVCMOS gpio_60 4 IO PU100/ PU100/ PD100 PD100 safe_mode 7 - gpmc_nbe1 0 O L L 7 vdds_io Yes 4 (1) 4 IO PU100/ PU100/ PD100 PD100 LVCMOS gpio_61 J1 - safe_mode 7 - AD8 AA8 gpmc_ncs0 0 O 1 1 0 vdds_io No 4 (1) NA LVCMOS AD1 W1 gpmc_ncs1 0 O H 1 0 vdds_io Yes 4 (1) LVCMOS gpio_52 4 IO PU100/ PU100/ PD100 PD100 safe_mode 7 - gpmc_ncs2 0 O H H 7 vdds_io Yes 4 (1) 4 IO PU100/ PU100/ PD100 PD100 LVCMOS gpio_53 safe_mode 7 - gpmc_ncs3 0 O H H 7 vdds_io Yes 4 (1) 1 I PU100/ PU100/ PD100 PD100 LVCMOS sys_ndmareq0 gpio_54 4 IO safe_mode 7 - gpmc_ncs4 0 O H H 7 vdds_io Yes 4 (1) 1 I PU100/ PU100/ PD100 PD100 LVCMOS sys_ndmareq1 mcbsp4_clkx 2 IO gpt9_pwm_evt 3 IO gpio_55 4 IO safe_mode 7 - gpmc_ncs5 0 O H H 7 vdds_io Yes 4 (1) 1 I PU100/ PU100/ PD100 PD100 LVCMOS sys_ndmareq2 mcbsp4_dr 2 I gpt10_pwm_evt 3 IO gpio_56 4 IO safe_mode 7 - gpmc_ncs6 0 O H H 7 vdds_io Yes 4 (1) 1 I PU100/ PU100/ PD100 PD100 LVCMOS sys_ndmareq3 mcbsp4_dx 2 IO gpt11_pwm_evt 3 IO gpio_57 4 IO safe_mode 7 - gpmc_ncs7 0 O H H 7 vdds_io Yes 4 (1) 1 O PU100/ PU100/ PD100 PD100 LVCMOS gpmc_io_dir mcbsp4_fsx 2 IO gpt8_pwm_evt 3 IO gpio_58 4 IO A3 B6 B4 C4 B5 C5 - - - - - - Submit Documentation Feedback TERMINAL DESCRIPTION 35 PRODUCT PREVIEW BALL BOTTOM [1] OMAP3525-HiRel and OMAP3530-HiRel Applications Processors SPRS599 SPRS599 JUNE 2009 www.ti.com Table 2-2. Ball Characteristics (CBC Pkg.) (continued) BALL BOTTOM [1] BALL TOP [2] PIN NAME [4] MODE [5] TYPE [6] BALL RESET STATE [7] BALL RESET REL. STATE [8] RESET REL. MODE [9] POWER [10] HYS [11] BUFFER STRENG TH (mA) [12] PULLUP /DOWN TYPE [13] IO CELL [14] safe_mode 7 - N2 L2 gpmc_noe 0 O 1 1 0 vdds_io No 4 (1) M1 K1 gpmc_nwe NA LVCMOS 0 O 1 1 0 vdds_io No 4 (1) NA AC6 Y5 LVCMOS gpmc_nwp 0 O L 0 0 vdds_io Yes 4 (1) LVCMOS gpio_62 4 IO PU100/ PU100/ PD100 PD100 7 - Y10 gpmc_wait0 0 I H H 0 vdds_io Yes 4 (1) PU100/ PU100/ PD100 PD100 LVCMOS AC8 Y8 gpmc_wait1 0 I H H 7 vdds_io Yes 4 (1) 4 IO PU100/ PU100/ PD100 PD100 LVCMOS gpio_63 safe_mode 7 - gpmc_wait2 0 I H H 7 vdds_io Yes 4 (1) 4 IO PU100/ PU100/ PD100 PD100 LVCMOS gpio_64 safe_mode 7 - gpmc_wait3 0 I H H 7 vdds_io Yes 4 (1) 1 I PU100/ PU100/ PD100 PD100 LVCMOS sys_ndmareq1 gpio_65 4 IO safe_mode 7 - hsusb0_clk 0 I L L 7 vdds_io Yes 4 (2) 4 IO PU100/ PU100/ PD100 PD100 LVCMOS gpio_120 safe_mode 7 - hsusb0_data0 0 IO L L 7 vdds_io Yes 4 (2) 2 O PU100/ PU100/ PD100 PD100 LVCMOS uart3_tx_irtx gpio_125 4 IO safe_mode 7 - hsusb0_data1 0 IO L L 7 vdds_io Yes 4 (2) 2 I PU100/ PU100/ PD100 PD100 LVCMOS uart3_rx_irrx gpio_130 4 IO safe_mode 7 - hsusb0_data2 0 IO L L 7 vdds_io Yes 4 (2) 2 O PU100/ PU100/ PD100 PD100 LVCMOS uart3_rts_sd gpio_131 4 IO safe_mode 7 - hsusb0_data3 0 IO L L 7 vdds_io Yes 4 (2) 2 IO PU100/ PU100/ PD100 PD100 LVCMOS uart3_cts_rctx gpio_169 4 IO safe_mode 7 - hsusb0_data4 0 IO L L 7 vdds_io Yes 4 (2) 4 IO PU100/ PU100/ PD100 PD100 LVCMOS gpio_188 safe_mode 7 - hsusb0_data5 0 IO L L 7 vdds_io Yes 4 (2) 4 IO PU100/ PU100/ PD100 PD100 LVCMOS gpio_189 safe_mode 7 - hsusb0_data6 0 IO L L 7 vdds_io Yes 4 (2) 4 IO PU100/ PU100/ PD100 PD100 LVCMOS gpio_190 safe_mode 7 - hsusb0_data7 0 IO L L 7 vdds_io Yes 4 (2) 4 IO PU100/ PU100/ PD100 PD100 LVCMOS gpio_191 safe_mode 7 - hsusb0_dir 0 I L L 7 vdds_io Yes 4 (2) 4 IO PU100/ PU100/ PD100 PD100 LVCMOS gpio_122 safe_mode PRODUCT PREVIEW safe_mode AC11 7 - B3 C6 W19 V20 Y20 V18 W20 W17 Y18 Y19 Y17 V19 (2) 36 - - - - - - - - - - - - The capacity load range is [2 pf to 6 pF]. TERMINAL DESCRIPTION Submit Documentation Feedback OMAP3525-HiRel and OMAP3530-HiRel Applications Processors www.ti.com SPRS599 SPRS599 JUNE 2009 Table 2-2. Ball Characteristics (CBC Pkg.) (continued) BALL BOTTOM [1] BALL TOP [2] W18 - TYPE [6] BALL RESET STATE [7] BALL RESET REL. STATE [8] RESET REL. MODE [9] POWER [10] HYS [11] BUFFER STRENG TH (mA) [12] PULLUP /DOWN TYPE [13] IO CELL [14] hsusb0_nxt 0 I L L 7 vdds_io Yes 4 (2) IO PU100/ PU100/ PD100 PD100 LVCMOS 4 safe_mode 7 - hsusb0_stp 0 O H H 7 vdds_io Yes 4 (2) 4 IO PU100/ PU100/ PD100 PD100 LVCMOS gpio_121 - MODE [5] gpio_124 U20 PIN NAME [4] 7 - - jtag_ntrst 0 I L L 0 vdds_io Yes NA PU100/ PU100/ PD100 PD100 LVCMOS W13 - jtag_rtck 0 O L 0 0 vdds_io Yes 4 PU100/ PU100/ PD100 PD100 LVCMOS V14 - jtag_tck 0 I L L 0 vdds_io Yes NA PU100/ PU100/ PD100 PD100 LVCMOS U16 - jtag_tdi 0 I H H 0 vdds_io Yes NA PU100/ PU100/ PD100 PD100 LVCMOS Y13 - jtag_tdo 0 O L Z 0 vdds_io Yes 4 PU100/ PU100/ PD100 PD100 LVCMOS V15 - jtag_tms_tmsc 0 IO H H 0 vdds_io Yes 4 PU100/ PU100/ PD100 PD100 LVCMOS N19 - mmc1_clk 0 O L L 7 vdds_mmc1 Yes 8 1 O PU100/ PU100/ PD100 PD100 LVCMOS gpio_120 4 IO safe_mode 7 - mmc1_cmd 0 IO L L 7 vdds_mmc1 Yes 8 1 O PU100/ PU100/ PD100 PD100 LVCMOS gpio_121 4 IO safe_mode 7 - mmc1_dat0 0 IO L L 7 vdds_mmc1 Yes 8 1 IO PU100/ PU100/ PD100 PD100 LVCMOS gpio_122 4 IO safe_mode 7 - mmc1_dat1 0 IO L L 7 vdds_mmc1 Yes 8 1 IO PU100/ PU100/ PD100 PD100 LVCMOS gpio_123 4 IO safe_mode 7 - mmc1_dat2 0 IO L L 7 vdds_mmc1 Yes 8 1 IO PU100/ PU100/ PD100 PD100 LVCMOS gpio_124 4 IO safe_mode 7 - mmc1_dat3 0 IO L L 7 vdds_mmc1 Yes 8 1 IO PU100/ PU100/ PD100 PD100 LVCMOS gpio_125 4 IO safe_mode 7 - mmc1_dat4 0 IO L L 7 vdds_mmc1a No 8 PU/PD (3) LVCMOS - 2 IO gpio_126 4 IO safe_mode 7 - mmc1_dat5 0 IO L L 7 vdds_mmc1a No 8 PU/PD (3) LVCMOS - 2 O gpio_127 4 IO safe_mode 7 - mmc1_dat6 0 IO L L 7 vdds_mmc1a No 8 PU/PD (3) LVCMOS - 2 O gpio_128 4 IO safe_mode 7 - L18 M19 M18 K1