NS32381-15 NS32381-20 NS32381-25 NS32381-30 NS32381 NS32081 C1995 RRD-B30M115 - Datasheet Archive

 

NS32381-15 NS32381-20 NS32381-25 NS32381-30 Floating-Point Unit General Description The NS32381 is a second generation CMOS

 

April 1991 NS32381-15 NS32381-15 NS32381-20 NS32381-20 NS32381-25 NS32381-25 NS32381-30 NS32381-30 Floating-Point Unit General Description The NS32381 NS32381 is a second generation CMOS floating-point slave processor that is fully software compatible with its forerunner the NS32081 NS32081 FPU The NS32381 NS32381 FPU functions with all Series 32000 and Series 32000 EP CPUs in a tightly coupled slave configuration The performance of the NS32381 NS32381 has been increased over the NS32081 NS32081 by architecture improvements hardware enhancements and higher clock frequencies Key improvements include the addition of a 32-bit slave protocol an early done algorithm to increase CPU FPU parallelism an expanded register set an automatic power down feature expanded math hardware and additional instructions The NS32381 NS32381 FPU contains eight 64-bit data registers and a Floating-Point Status Register (FSR) The FPU executes 20 instructions and operates on both single and doubleprecision operands Three separate processors in the NS32381 NS32381 manipulate the mantissa sign and exponent The CPU and NS32381 NS32381 FPU form a tightly coupled computer cluster which appears to the user as a single processing unit The CPU and FPU communication is handled automatically and is user transparent The FPU is fabricated with National's advanced double-metal CMOS process Features Y Y Y Y Y Y Y Y Y Y Y Compatible with all Series 32000 and Series 32000 EP CPUs Selectable 16-bit or 32-bit Slave Protocol Compatible with IEEE Standard 754-1985 for binary floating point arithmetic Early done algorithm Single (32-bit) and double (64-bit) precision operations Eight on-chip (64-bit) data registers Automatic power down mode Full upward compatibility with existing 32000 software High speed double-metal CMOS design 68-pin PGA package 68-pin plastic package FPU Block Diagram TL EE 9157 ­ 1 FIGURE 1-1 Series 32000 and TRI-STATE are registered trademarks of National Semiconductor Corporation C1995 C1995 National Semiconductor Corporation TL EE 9157 RRD-B30M115 RRD-B30M115 Printed in U S A NS32381-15 NS32381-15 NS32381-20 NS32381-20 NS32381-25 NS32381-25 NS32381-30 NS32381-30 Floating-Point Unit PRELIMINARY Table of Contents 4 0 DEVICE SPECIFICATIONS 1 0 PRODUCT INTRODUCTION 4 1 Pin Descriptions 1 1 IEEE STD 754 Features Supported by the NS32381 NS32381 4 1 1 Supplies 4 1 2 Input Signals 4 1 3 Output Signals 4 1 4 Input Output Signals 1 2 Operand Formats 1 2 1 Normalized Numbers 1 2 2 Zero 1 2 3 Reserved Operands 1 2 4 Integers 1 2 5 Memory Representations 4 2 Absolute Maximum Ratings 4 3 Electrical Characteristics 4 4 Switching Characteristics 2 0 ARCHITECTURAL DESCRIPTION 4 4 1 Definitions 4 4 2 Timing Tables 4 4 2 1 Output Signal Propagation Delays for all CPUs 4 4 2 2 Output Signal Propagation Delays for the NS32008 NS32008 NS32016 NS32016 NS32032 NS32032 CPUs 4 4 2 3 Output Signal Propagation Delays for the 32-Bit Slave Protocol NS32332 NS32332 CPU 4 4 2 4 Output Signal Propagation Delays for the 32-Bit Slave Protocol NS32532 NS32532 CPU 4 4 2 5 Input Signal Requirements for all CPUs 4 4 2 6 Input Signal Requirements for the NS32008 NS32008 NS32016 NS32016 NS32032 NS32032 CPUs 4 4 2 7 Input Signal Requirements for the 32-Bit Slave Protocol NS32332 NS32332 CPU 4 4 2 8 Input Signal Requirements for the 32-Bit Slave Protocol NS32532 NS32532 CPU 4 4 2 9 Clocking Requirements for all CPUs 2 1 Programming Model 2 1 1 Floating-Point Registers 2 1 2 Floating-Point Status Register (FSR) 2 1 2 1 FSR Mode Control Fields 2 1 2 2 FSR Status Fields 2 1 2 3 FSR Software Fields (SWF) 2 2 Instruction Set 2 3 Exceptions 3 0 FUNCTIONAL DESCRIPTION 3 1 Power and Grounding 3 2 Automatic Power Down Mode 3 3 Clocking 3 4 Resetting 3 5 Bus Operation 3 5 1 Bus Cycles 3 5 2 Operand Transfer Sequences APPENDIX A NS32381 NS32381 PERFORMANCE ANALYSIS 3 6 Instruction Protocols 3 6 1 General Protocol Sequence 3 6 2 Early Done Algorithm 3 6 3 Floating-Point Protocols 2 List of Illustrations FPU Block Diagram 1-1 Floating-Point Operand Formats 1-2 Integer Format Register Set The Floating-Point Status Register Floating-Point Instruction Formats Recommended Supply Connections Power-On Reset Requirements General Reset Timing System Connection Diagram with the NS32532 NS32532 CPU System Connection Diagram with the NS32332 NS32332 CPU System Connection Diagram with the NS32008 NS32008 NS32016 NS32016 or NS32032 NS32032 CPU System Connection Diagram with the NS32CG16 NS32CG16 CPU Slave Processor Read Cycle (NS32008 NS32008 NS32016 NS32016 NS32032 NS32032 and NS32332 NS32332 CPUs) Slave Processor Read Cycle (NS32532 NS32532 CPU) Slave Processor Write Cycle (NS32008 NS32008 NS32016 NS32016 NS32032 NS32032 and NS32332 NS32332 CPUs) Slave Processor Write Cycle (NS32532 NS32532 CPU) ID and Opcode Format 16-Bit Slave Protocol ID and Opcode Format 32-Bit Slave Protocol FPU Status Word Format 16-Bit General Slave Instruction Protocol FPU Actions 32-Bit General Slave Instruction Protocol FPU Actions 68-Pin PGA Package 68-Pin PLCC Package Timing Specification Standard (Signal Valid After Clock Edge) Timing Specification Standard (Signal Valid Before Clock Edge) Clock Timing Power-On Reset Non-Power-On Reset Read Cycle from FPU (NS32008 NS32008 NS32016 NS32016 NS32032 NS32032 CPUs) Write Cycle to FPU (NS32008 NS32008 NS32016 NS32016 NS32032 NS32032 CPUs) Read Cycle from FPU (NS32332 NS32332 CPU) Write Cycle to FPU (NS32332 NS32332 CPU) SDN332 SDN332 Timing (NS32332 NS32332 CPU) SDN332 SDN332 (TRAP) Timing (NS32332 NS32332 CPU) Read Cycle from FPU (NS32532 NS32532 CPU) Write Cycle from FPU (NS32532 NS32532 CPU) SDN532 SDN532 Timing (NS32532 NS32532 CPU) FSSR Timing (NS32532 NS32532 CPU) SPC Pulse from FPU 3 1-3 2-1 2-2 2-3 3-1 3-2 3-3 3-4a 3-4b 3-4c 3-4d 3-5 3-6 3-7 3-8 3-9 3-10 3-11 3-12 3-13 4-1 4-2 4-3 4-4 4-5 4-6 4-7 4-8 4-9 4-10 4-11 4-12 4-13 4-14 4-15 4-16 4-17 4-18 List of Tables Sample F Fields 1-1 Sample E Fields 1-2 Normalized Number Ranges Integer Fields 16-Bit General Slave Instruction Protocol 32-Bit General Slave Instruction Protocol Floating-Point Instruction Protocols 1-4 3-1 3-2 3-3 1-3 4 1 0 Product Introduction tracted from the E field value in order to obtain the true exponent The bias value is 011 112 which is either 127 (single precision) or 1023 (double precision) Thus the true exponent can be either positive or negative as shown in Table 1-2 The NS32381 NS32381 Floating-Point Unit (FPU) provides high speed floating-point operations for the Series 32000 family and is fabricated using National high-speed CMOS technology It operates as a slave processor for transparent expansion of the Series 32000 basic instruction set The FPU can also be used with other microprocessors as a peripheral device by using additional TTL and CMOS interface logic The NS32381 NS32381 is compatible with the IEEE Floating-Point Formats TABLE 1-2 Sample E Fields E Field F Field Represented Value 011 110 100 0 1 5 c 2b1 e 0 75 011 111 100 0 1 5 c 20 e 1 50 100 000 100 0 1 5 c 21 e 3 00 Two values of the E field are not exponents 11 11 signals a reserved operand (Section 1 2 3) 00 00 represents the number zero if the F field is also all zeroes otherwise it signals a reserved operand The S bit indicates the sign of the operand It is 0 for positive and 1 for negative Floating-point numbers are in signmagnitude form that is only the S bit is complemented in order to change the sign of the represented number 1 1 IEEE STD 754 FEATURES SUPPORTED BY THE NS32381 NS32381 a) Basic floating-point number formats b) Add subtract multiply divide and compare operations c) Conversions between different floating-point formats d) Conversions between floating-point and integer formats e) Round floating-point number to integer (round to nearest round toward negative infinity and round toward zero in double or single-precision) f) Exception signaling and handling (invalid operation divide by zero overflow underflow and inexact) 1 2 1 Normalized Numbers Normalized numbers are numbers which can be expressed as floating-point operands as described above where the E field is neither all zeroes nor all ones The value of a Normalized number can be derived by the formula ( b1)S c 2(E-Bias) c (1 a F) 1 2 OPERAND FORMATS The NS32381 NS32381 FPU operates on two floating-point data types single precision (32 bits) and double precision (64 bits) Floating-point instruction mnemonics use the suffix F (Floating) to select the single precision data type and the suffix L (Long Floating) to select the double precision data type A floating-point number is divided into three fields as shown in Figure 1-2 The F field is the fractional portion of the represented number In Normalized numbers (Section 1 2 1) the binary point is assumed to be immediately to the left of the most significant bit of the F field with an implied 1 bit to the left of the binary point Thus the F field represents values in the range 10 s x k 20 The range of Normalized numbers is given in Table 1-3 1 2 2 Zero There are two representations for zero positive and negative Positive zero has all-zero F and E fields and the S bit is zero Negative zero also has all-zero F and E fields but its S bit is one 1 2 3 Reserved Operands The IEEE Standard for Binary Floating-Point Arithmetic provides for certain exceptional forms of floating-point operands The NS32381 NS32381 FPU treats these forms as reserved operands The reserved operands are Positive and negative infinity Not-a-Number (NaN) values Denormalized numbers Both Infinity and NaN values have all ones in their E fields Denormalized numbers have all zeroes in their E fields and non-zero values in their F fields The NS32381 NS32381 FPU causes an Invalid Operation trap (Section 2 1 2 2) if it receives a reserved operand unless the operation is simply a move (without conversion) The FPU does not generate reserved operands as results TABLE 1-1 Sample F Fields F Field 000 0 010 0 100 0 110 0 Binary Value 1 000 0 1 010 0 1 100 0 1 110 0 Decimal Value 1 000 0 1 250 0 1 500 0 1 750 0 u Implied Bit The E field contains an unsigned number that gives the binary exponent of the represented number The value in the E field is biased that is a constant bias value must be sub- Single Precision 23 22 31 30 S E F 1 8 0 23 Double Precision 63 62 52 51 S E 1 11 0 F 52 FIGURE 1-2 Floating-Point Operand Formats 5 1 0 Product Introduction (Continued) TABLE 1-3 Normalized Number Ranges Single Precision 2127 c (2 b 2b23) e 3 40282346 c 1038 Double Precision 21023 c (2 b 2b52) e 1 7976931348623157 c 10308 Least Positive 2b126 e 1 17549436 c 10 b 38 2b1022 e 2 2250738585072014 c 10 b 308 Least Negative b (2 b 126) e b 1 17549436 c 10 b 38 b (2 b 1022) e b 2 2250738585072014 c 10 b 308 Most Negative b 2127 c (2 b 2 b 23) e b 3 40282346 c 1038 b 21023 c (2 b 2 b 52) e b 1 7976931348623157 c 10308 Most Positive Note The values given are extended one full digit beyond their represented accuracy to help in generating rounding and conversion algorithms address The only exception to this rule is the Immediate addressing mode where the operand is held (within the instruction format) with the most significant byte at the lowest address 1 2 4 Integers In addition to performing floating-point arithmetic the NS32381 NS32381 FPU performs conversions between integer and floating-point data types Integers are accepted or generated by the FPU as two's complement values of byte (8 bits) word (16 bits) or double word (32 bits) length See Figure 1-3 for the Integer Format and Table 1-4 for the Integer Fields nb1 n-2 S 2 0 Architectural Description 2 1 PROGRAMMING MODEL The Series 32000 architecture includes nine registers that are implemented on the NS32381 NS32381 Floating-Point Unit (FPU) 0 2 1 1 Floating-Point Registers There are eight registers (L0 ­ L7) on the NS32381 NS32381 FPU for providing high-speed access to floating-point operands Each is 64 bits long A floating-point register is referenced whenever a floating-point instruction uses the Register addressing mode (Section 2 2 2) for a floating-point operand All other Register mode usages (i e integer operands) refer to the General Purpose Registers (R0 ­ R7) of the CPU and the FPU transfers the operand as if it were in memory I FIGURE 1-3 Integer Format TABLE 1-4 Integer Fields S Value Name 0 I Positive Integer 1 I b 2n Negative Integer Note These registers are all upward compatible with the 32-bit NS32081 NS32081 registers (F0­F7) such that when the Register addressing mode is specified for a double precision (64-bit) operand a pair of 32-bit registers holds the operand The programmer specifies the even register of the pair which contains the least significant half of the operand and the next consecutive register contains the most significant half Note n represents the number of bits in the word 8 for byte 16 for word and 32 for double-word 1 2 5 Memory Representations The NS32381 NS32381 FPU does not directly access memory However it is cooperatively involved in the execution of a set of two-address instructions with its Series 32000 Family CPU The CPU determines the representation of operands in memory In the Series 32000 family of CPUs operands are stored in memory with the least significant byte at the lowest byte 2 1 2 Floating-Point Status Register (FSR) The Floating-Point Status Register (FSR) selects operating modes and records any exceptional conditions encountered during execution of a floating-point operation Figure 2-2 shows the format of the FSR TL EE 9157 ­ 36 FIGURE 2-1 Register Set TL EE 9157 ­ 37 FIGURE 2-2 The Floating-Point Status Register 6 2 0 Architectural Description (Continued) 010 Overflow A result (either floating-point or integer) of a floating-point instruction is too great in magnitude to be held in the format of the destination operand Note that rounding as well as calculations can cause this condition 011 Divide by zero An attempt has been made to divide a non-zero floating-point number by zero Dividing zero by zero is considered an Invalid Operation instead (below) 100 Illegal Instruction Any instruction forms not included in the NS32381 NS32381 Instruction Set are detected by the FPU as being illegal 101 Invalid Operation One of the floating-point operands of a floating-point instruction is a Reserved operand or an attempt has been made to divide zero by zero using the DIVf instruction 110 Inexact Result The result (either floating-point or integer) of a floating-point instruction cannot be represented exactly in the format of the destination operand and a rounding step must alter it to fit This condition is always reported in the TT field and IF bit unless any other exceptional condition has occurred in the same instruction In this case the TT field always contains the code for the other exception and the IF bit is not altered A trap is caused by this condition only if the IEN bit is set otherwise the result is rounded and delivered and no trap occurs 111 (Reserved for future use ) Underflow Flag (UF) Bit 4 This bit is set by the FPU whenever a result is too small in absolute value to be represented as a normalized number Its function is not affected by the state of the UEN bit The UF bit is cleared only by writing a zero into it with the Load FSR instruction or by a hardware reset Inexact Result Flag (IF) Bit 6 This bit is set by the FPU whenever the result of an operation must be rounded to fit within the destination format The IF bit is set only if no other error has occurred It is cleared only by writing a zero into it with the Load FSR instruction or by a hardware reset Register Modify Bit (RMB) Bit 16 This bit is set by the FPU whenever writing to a floating point data register The RMB bit is cleared only by writing a zero with the LFSR instruction or by a hardware reset This bit can be used in context switching to determine whether the FPU registers should be saved 2 1 2 1 FSR Mode Control Fields The FSR mode control fields select FPU operation modes The meanings of the FSR mode control bits are given below Rounding Mode (RM) Bits 7 and 8 This field selects the rounding method Floating-point results are rounded whenever they cannot be exactly represented The rounding modes are 00 Round to nearest value The value which is nearest to the exact result is returned If the result is exactly halfway between the two nearest values the even value (LSB e 0) is returned 01 Round toward zero The nearest value which is closer to zero or equal to the exact result is returned 10 Round toward positive infinity The nearest value which is greater than or equal to the exact result is returned 11 Round toward negative infinity The nearest value which is less than or equal to the exact result is returned Underflow Trap Enable (UEN) Bit 3 If this bit is set the FPU requests a trap whenever a result is too small in absolute value to be represented as a normalized number If it is not set any underflow condition returns a result of exactly zero Inexact Result Trap Enable (IEN) Bit 5 If this bit is set the FPU requests a trap whenever the result of an operation cannot be represented exactly in the operand format of the destination If it is not set the result is rounded according to the selected rounding mode 2 1 2 2 FSR Status Fields The FSR Status Fields record exceptional conditions encountered during floating-point data processing The meanings of the FSR status bits are given below Trap Type (TT) bits 0-2 This 3-bit field records any exceptional condition detected by a floating-point instruction The TT field is loaded with zero whenever any floating-point instruction except LFSR or SFSR completes without encountering an exceptional condition It is also set to zero by a hardware reset or by writing zero into it with the Load FSR (LFSR) instruction Underflow and Inexact Result are always reported in the TT field regardless of the settings of the UEN and IEN bits 000 No exceptional condition occurred 001 Underflow A non-zero floating-point result is too small in magnitude to be represented as a normalized floating-point number in the format of the destination operand This condition is always reported in the TT field and UF bit but causes a trap only if the UEN bit is set If the UEN bit is not set a result of Positive Zero is produced and no trap occurs 2 1 2 3 FSR Software Field (SWF) Bits 9-15 of the FSR hold and display any information written to them (using the LFSR and SFSR instructions) but are not otherwise used by FPU hardware They are reserved for use with NSC floating-point extension software 7 2 0 Architectural Description (Continued) An operand designation (gen1 gen2) indicates a choice of addressing mode expressions This choice affects the binary pattern in the corresponding gen1 or gen2 field of the instruction format Refer to Table 2-1 for the options available and their patterns Further details of the exact operations performed by each instruction are found in the Series 32000 Instruction Set Reference Manual 2 2 INSTRUCTION SET This section describes the floating-point instructions executed by the FPU in conjunction with the CPU These instructions form a subset of the Series 32000 instruction set and take 9 11 and 12 encoding formats A list of all the Series 32000 instructions as well as details on their formats and addressing modes can be found in the appropriate CPU data sheets Certain notations in the following instruction description tables serve to relate the assembly language form of each instruction to its binary format in Figure 2-3 Movement and Conversion The following instructions move the gen1 operand to the gen2 operand leaving the gen1 operand intact Format 9 Format Op Instruction 11 0001 MOVf gen1 gen2 9 010 MOVLF gen1 gen2 9 011 MOVFL gen1 gen2 9 000 MOVif gen1 gen2 9 100 ROUNDfi gen1 gen2 9 101 TRUNCfi gen1 gen2 9 111 FLOORfi gen1 gen2 TL EE 9157­5 Format 11 TL EE 9157­6 Format 12 TL EE 9157­7 FIGURE 2-3 Floating-Point Instruction Formats The Format column indicates which of the three formats in Figure 2-3 represents each instruction The Op column indicates the binary pattern for the field called ``op'' in the applicable format The Instruction column gives the form of each instruction as it appears in assembly language The form consists of an instruction mnemonic in upper case with one or more suffixes (i or f) indicating data types followed by a list of operands (gen1 gen2) An i suffix on an instruction mnemonic indicates a choice of integer data types This choice affects the binary pattern in the i field of the corresponding instruction format as follows Description Move without conversion Move converting from double precision to single precision Move converting from single precision to double precision Move converting from any integer type to any floating-point type Move converting from floatingpoint to the nearest integer Move converting from floatingpoint to the nearest integer closer to zero Move converting from floatingpoint to the largest integer less than or equal to its value Note The MOVLF instruction f bit must be 1 and the i field must be 10 The MOVFL instruction f bit must be 0 and the i field must be 11 Suffix i B W D Data Type Byte Word Double Word i Field 00 01 11 Arithmetic Operations The following instructions perform floating-point arithmetic operations on the gen1 and gen2 operands leaving the result in the gen2 operand An f suffix on an instruction mnemonic indicates a choice of floating-point data types This choice affects the setting of the f bit of the corresponding instruction format as follows Suffix f F L Data Type Single Precision Double Precision (Long) Note POLY and DOT use the additional third implied operand POLY and DOT put their result to LO FO register and not to GEN2 Format 11 11 8 Op 0000 0100 Instruction ADDf gen1 gen2 SUBf gen1 gen2 11 f Bit 1 0 1100 MULf gen1 gen2 Description Add gen1 to gen2 Subtract gen1 from gen2 Multiply gen2 by gen1 2 0 Architectural Description (Continued) Rounding Format Op Instruction Description 11 1000 DIVf gen1 gen2 Divide gen2 by gen1 11 0101 NEGf gen1 gen2 Move negative of gen1 to gen2 11 1101 ABSf gen1 gen2 Move absolute value of gen1 to gen2 (N) 12 0100 SCALBf gen1 gen2 Move gen2 2gen1 to gen2 for integral values of gen1 without computing 2gen1 (N) 12 (N) 12 (N) 12 The FPU supports all IEEE rounding options Round toward nearest value or even significant if a tie Round toward zero Round toward positive infinity and Round toward negative infinity 2 3 EXCEPTIONS The FPU supports five types of exceptions Invalid operation Division by zero Overflow Underflow and Inexact Result When an exception occurs the FPU may or may not generate a trap depending upon the bit setting in the FSR Register The user can disable the Inexact Result and the Underflow traps If an undefined Floating-Point instruction is passed to the FPU an Illegal Instruction trap will occur The user can't disable trap on Illegal Instruction Upon detecting an exceptional condition in executing a floating-point instruction the FPU requests a TRAP by pulsing the SPC line for one clock cycle pulsing the SDN332 SDN332 line for two and a half clock cycles and pulsing the FSSR line for one clock cycle (The user will connect the correct lines according to the CPU being used) In addition the FPU sets the Q bit in the status word register The CPU responds by reading the status word register (refer to Section 3 6 1 for its format) while applying status code 1110 on the status lines A trapped instruction returns no result (even if the destination is FPU register) and does not affect the CPU PSR The FPU records exceptional cause in the trap type (TT) field of the FSR If an illegal opcode is detected the FPU sets the TS bit in the slave processor status word register indicating a trap (UND) 0101 LOGBf gen1 gen2 Move the unbiased exponent of gen1 to gen2 0011 DOTf gen1 gen2 Move (gen1 gen2) a L0 to L0 ( ) 0010 POLYf gen1 gen2 Move (L0 gen1) a gen2 to L0 ( ) Notes (N) Indicates NEW instruction ( )The third impled operand used by these instructions can be either F0 or L0 depending on whether `floating' or `long' data type is specified in the opcode Comparison The Compare instruction compares two floating-point values sending the result to the CPU PSR Z and N bits for use as condition codes See Figure 3-11 The Z bit is set if the gen1 and gen2 operands are equal it is cleared otherwise The N bit is set if the gen1 operand is greater than the gen2 operand it is cleared otherwise The CPU PSR L bit is unconditionally cleared Positive and negative zero are considered equal Format 11 Op 0010 Instruction CMPf gen1 gen2 3 0 Functional Description 3 1 POWER AND GROUNDING The NS32381 NS32381 requires a single 5V power supply applied on the VCC pins These pins should be connected together by a power (VCC) plane on the printed circuit board See Figure 3-1 Description Compare gen1 to gen2 The grounding connections are made on the GND pins These pins should be connected together by a ground (GND) plane on the printed circuit board See Figure 3-1 Floating-Point Status Register Access The following instructions load and store the FSR as a 32bit integer Format 9 9 Op 001 110 Instruction LFSR gen1 SFSR gen2 Description Load FSR Store FSR Note All instructions support all of the Series 32000 family data formats and addressing modes TL EE 9157 ­ 8 PGA Package TL EE 9157 ­ 43 PLCC Package FIGURE 3-1 Recommended Supply Connections 9 3 0 Functional Description (Continued) TL EE 9157 ­ 9 FIGURE 3-2 Power-On Reset Requirements either one byte (8 bits) one word (16 bits) or one double word (32 bits) to or from the FPU During all bus cycles the SPC line is driven by the CPU as an active low data strobe and the FPU monitors pins ST0 ­ ST3 to keep track of the sequence (protocol) established for the instruction being executed This is necessary in a virtual memory environment allowing the FPU to retry an aborted instruction 3 2 AUTOMATIC POWER DOWN MODE The NS32381 NS32381 supports a power down mode in which the device consumes only 20% of its original power at 30 MHz The NS32381 NS32381 enters the power down mode (internal clocks are stopped with phase two high) if it does not receive an SPC pulse from the CPU within 256 clocks The FPU exits the power down mode and returns to normal operation after it receives an SPC from the CPU There is no extra delay caused by the FPU being in the power down mode 3 5 1 Bus Cycles A bus cycle is initiated by the CPU which asserts the proper status on (ST0 ­ ST3) and pulses SPC low The status lines are sampled by the FPU on the leading (falling) edge of the SPC pulse except for the 32532 CPU When used with the 32532 CPU the status lines are sampled on the rising edge of CLK in the T2 state If the transfer is from the FPU (a slave processor read cycle) the FPU asserts data on the data bus for the duration of the SPC pulse If the transfer is to the FPU (a slave processor write cycle) the FPU latches data from the data bus on the trailing (rising) edge of the SPC pulse Figures 3-5 3-6 3-7 and 3-8 illustrate these sequences The direction of the transfer and the role of the bidirectional SPC line are determined by the instruction protocol being performed SPC is always driven by the CPU during slave processor bus cycles Protocol sequences for each instruction are given in Section 3 6 3 3 CLOCKING The NS32381 NS32381 FPU requires a single-phase TTL clock input on its CLK pin Different Clock sources can be used to provide the CLK signal depending on the application For example it can come from the BCLK of the NS32532 NS32532 CPU It can also come from the CTTL pin of the NS32C201 NS32C201 Timing Control Unit if it is required 3 4 RESETTING The RST pin serves as a reset for on-chip logic The FPU may be reset at any time by pulling the RST pin low for at least 64 clock cycles Upon detecting a reset the FPU terminates instruction processing resets its internal logic and clears the FSR to all zeroes On application of power RST must be held low for at least 30 ms after VCC is stable This ensures that all on-chip voltages are completely stable before operation See Figures 3-2 and 3-3 3 5 2 Operand Transfer Sequences An operand is transferred in one or more bus cycles For the 16-Bit Slave Protocol a 1-byte operand is transferred on the least significant byte of the data bus (D0 ­ D7) A 2-byte operand is transferred on the entire bus A 4-byte or 8-byte operand is transferred in consecutive bus cycles least significant word first For the 32-Bit Slave Protocol a 4-byte operand is transferred on the entire data bus in a single bus cycle and an 8-byte operand is transferred in two consecutive bus cycles with the most significant byte transferred on data bits (D0 ­ D7) The complete operand transfer of bytes B0 ­ B7 where B0 is the least significant byte would appear on the data bus as B4 B5 B6 B7 followed by B0 B1 B2 B3 in the second bus cycle TL EE 9157­10 FIGURE 3-3 General Reset Timing 3 5 BUS OPERATION Instructions and operands are passed to the NS32381 NS32381 FPU with slave processor bus cycles Each bus cycle transfers 10 3 0 Functional Description (Continued) TL EE 9157 ­ 38 FIGURE 3-4a System Connection Diagram with the NS32532 NS32532 NS32GX32 NS32GX32 or NS32GX320 NS32GX320 CPU TL EE 9157 ­ 39 FIGURE 3-4b System Connection Diagram with the NS32332 NS32332 CPU 11 3 0 Functional Description (Continued) TL EE 9157 ­ 40 FIGURE 3-4c System Connection Diagram with the NS32008 NS32008 NS32016 NS32016 or NS32032 NS32032 CPU TL EE 9157 ­ 41 FIGURE 3-4d System Connection Diagram with the NS32CG16 NS32CG16 NS32FX16 NS32FX16 or NS32CG160 NS32CG160 CPU 12 3 0 Functional Description (Continued) TL EE 9157 ­ 12 Note 1 FPU samples CPU status here FIGURE 3-5 Slave Processor Read Cycle (NS32008 NS32008 NS32016 NS32016 NS32032 NS32032 NS32CG16 NS32CG16 NS32FX16 NS32FX16 NS32CG160 NS32CG160 and NS32332 NS32332 CPUs) TL EE 9157 ­ 13 Note 1 FPU samples CPU status here FIGURE 3-6 Slave Processor Read Cycle (NS32532 NS32532 NS32GX32 NS32GX32 and NSGX320 NSGX320 CPU) 13 3 0 Functional Description (Continued) TL EE 9157 ­ 14 Note 1 FPU samples CPU status here Note 2 FPU samples data bus here FIGURE 3-7 Slave Processor Write Cycle (NS32008 NS32008 NS32016 NS32016 NS32032 NS32032 NS32CG16 NS32CG16 NS32FX16 NS32FX16 NS32CG160 NS32CG160 and NS32332 NS32332 CPU) TL EE 9157 ­ 15 Note 1 FPU samples CPU status here Note 2 FPU samples data bus here FIGURE 3-8 Slave Processor Write Cycle (NS32532 NS32532 NS32GX32 NS32GX32 and NS32GX320 NS32GX320 CPU) 14 3 0 Functional Description (Continued) 3 6 INSTRUCTION PROTOCOLS 2) It specifies which Slave Processor will execute it 3 6 1 General Protocol Sequences 3) It determines the format of the following Operation Word of the instruction Upon receiving a slave processor instruction the CPU initiates a sequence outlined in either Table 3-1 or 3-2 depending on the PS0 and PS1 to allow for the 16-bit or 32-bit slave protocol The NS32008 NS32008 NS32016 NS32016 NS32C016 NS32C016 NS32032 NS32032 NS32C032 NS32C032 NS32CG16 NS32CG16 NS32FX16 NS32FX16 and NS32CG160 NS32CG160 all communicate with the NS32381 NS32381 using the 16-bit Slave Protocol The NS32332 NS32332 NS32532 NS32532 NS32GX32 NS32GX32 and NS32GX320 NS32GX320 CPUs communicate with the NS32381 NS32381 using a 32-bit Slave Protocol a different version is provided for each CPU The NS32381 NS32381 supports both the 16-bit and 32-bit General Slave protocol sequences See Tables 3-1 3-2 and Figures 3-12 3-13 respectively Slave Processor instructions have a three-byte Basic Instruction field consisting of an ID byte followed by an Operation Word See Figure 3-9 for the ID and Opcode format 16-bit Slave Protocol and Figure 3-10 for the ID and Opcode Format 32-bit Slave Protocol The ID Byte has three functions 1) It identifies the instruction to the CPU as being a Slave Processor instruction TABLE 3-1 16-Bit General Slave Instruction Protocol Step Status 1 2 3 4 5 6 7 ID (1111) OP (1101) OP (1101) ST (1110) OP (1101) Action CPU sends ID Byte CPU sends Operation Word CPU sends required operands (if any) Slaves starts execution (CPU prefetches) Slave pulses SPC low CPU Reads Status Word CPU Reads Result (if destination is memory and if no TRAP occurred) TABLE 3-2 32-Bit General Slave Instruction Protocol Step Status Action 1 2 3 4 5 ID (1111) OP (1101) 6 OP (1101) CPU sends ID and Operation Word CPU sends required operands (if any) Slaves starts execution (CPU prefetches) Slave signals DONE or TRAP or CMPf CPU Reads Status Word (If TRAP was signaled or a CMPf instruction was executed) CPU Reads Result (if destination is memory and if no TRAP occurred) ST (1110) TABLE 3-3 Floating-Point Instruction Protocols Mnemonic ADDf SUBf MULf DIVf MOVf ABSf NEGf CMPf FLOORfi TRUNCfi ROUNDfi MOVFL MOVLF MOVif LFSR SFSR SCALBf LOGBf DOTf POLYf Operand 1 Class Operand 2 Class Operand 1 Issued Operand 2 Issued Returned Value Type and Destination PSR Bits Affected read f read f read f read f read f read f read f read f read f read f read f read F read L read i read D N A read f read f read f read f rmw f rmw f rmw f rmw f write f write f write f read f write i write i write i write L write F write f N A write D rmw f write f read f read f f f f f f f f f f f f F L i D N A f f f f f f f f f to Op 2 f to Op 2 f to Op 2 f to Op 2 f to Op 2 f to Op 2 f to Op 2 N A i to Op 2 i to Op 2 i to Op 2 L to Op 2 F to Op 2 f to Op 2 N A D to Op 2 f to Op 2 f to Op 2 f to F0 L0 f to F0 L0 none none none none none none none NZL none none none none none none none none none none none none N A N A N A f N A N A N A N A N A N A N A N A f N A f f D e Double Word i e Integer size (B W D) specified in mnemonic f e Floating-Point type (F L) specified in mnemonic N A e Not Applicable to this instruction The ``returned value'' can go to either F0 or L0 depending on the ``f'' bit in the opcode i e whether ``floating'' or ``long'' data type is used 15 3 0 Functional Description (Continued) 7 For the 32-bit Slave Protocol upon completion of the instruction the FPU will signal the CPU by pulsing either SDNXXX or FSSR (Force Slave Status Read) A half clock cycle SDN332 SDN332 pulse with a NS32332 NS32332 CPU or a one clock cycle SDN532 SDN532 pulse with a NS32532 NS32532 NS32GX32 NS32GX32 or NS32GX320 NS32GX320 CPU indicates a valid completion of the instruction and that there is no need for the CPU to read its Status Word Register But if there is a need for the CPU to read FPU's Status Word Register a two and a half clock cycle SDN332 SDN332 (from NS32332 NS32332) or a one clock cycle FSSR pulse (from NS32532 NS32532 NS32GX32 NS32GX32 or NS32GX320 NS32GX320) will be issued instead In all cases for both the 16-Bit and 32-Bit Slave Protocols the CPU will use SPC to read the Status Word from the FPU while applying status code (1110) This word has the format shown in Figure 3-11 If the Q bit (``Quit'' Bit 0) is set this indicates that an error (TRAP) has been detected by the FPU The CPU will not continue the protocol but will immediately trap through the Slave vector in the Interrupt Table If the instruction being performed is CMPf (Section 2 2 3) and the Q bit is not set the CPU loads Processor Status Register (PSR) bits N Z and L from the corresponding bits in the FPU Status Word The FPU always sets the L bit to zero The last step will be for the CPU to read the result provided there are no errors and the result's destination is either in memory or in a CPU register Here again the CPU uses SPC to read the result from the FPU and transfer it to its destination These Read cycles from the FPU are performed by the CPU while applying Status Code 1101 (Transfer Slave Operand) 0 ID Byte 15 7 OPCODE (low) 0 OPCODE (high) Byte 1 Byte 0 Operation Word FIGURE 3-9 ID and OPCODE Format 16-Bit Slave Protocol 31 23 ID 15 7 0 OPCODE (low) OPCODE (high) XXXXXXXX Byte 3 Byte 2 Byte 1 Byte 0 FIGURE 3-10 ID and OPCODE Format 32-Bit Slave Protocol For the 16-bit Slave Protocol the CPU applies Status Code 1111 (Broadcast ID) and sends the ID Byte on the least significant half of the Data Bus (D0­D7) The CPU next sends the Operation Word while applying Status Code 1101 (Transfer Slave Operand) The Operation Word is swapped on the Data Bus that is bits 0­7 appear on pins D8­D15 and bits 8 ­ 15 appear on pins D0­D7 For the 32-bit Slave Protocol the CPU applies Status Code 1111 and sends the ID Byte (different ID for each format) in byte 3 (D24 ­ D31) and the Operation Word in bytes 1 and 2 in a single double word transfer The Operation Word is swapped such that OPCODE low appears on byte 2 (D16­ D23) and OPCODE high appears on byte 1 (D8­D15) Byte 0 (D0 ­ D7) is not used All Slave Processors input and decode the data from these transfers The Slave Processor selected by the ID Byte is activated and from this point on the CPU is communicating with it only If any other slave protocol is in progress (e g an aborted Slave instruction) this transfer cancels it Both the CPU and FPU are aware of the number and size of the operands at this point Using the Addressing Mode fields within the Operation Word the CPU starts fetching operands and issuing them to the FPU To do so it references any Addressing Mode extensions appended to the FPU instruction Since the CPU is solely responsible for memory accesses these extensions are not sent to the Slave Processor The Status Code applied is 1101 (Transfer Slave Processor Operand) After the CPU has issued the last operand the FPU starts the actual execution of the instruction A one clock cycle SPC pulse is used to indicate the completion of the instruction and for the CPU to continue with the 16-Bit Slave Protocol by reading the FPU's Status Word Register 31 15 ZERO Bit (0) (2) (6) (7) (15) 16 TS 7 ZERO 0 NZ0 0 0 L 0Q Description Set to ``1'' if an FPU TRAP (error) occurred Cleared to `0'' by a valid CMPf L Cleared to ``0'' by the FPU Z Set to ``1'' if the second operand is equal to the first operand Otherwise it is cleared to ``0'' N Set to ``1'' if the second operand is less than the first operand Otherwise it is cleared to ``0'' TS Set to ``1'' if the TRAP is (UND) and cleared to ``0'' if the TRAP is (FPU) FIGURE 3-11 FPU Status Word Format Q 3 0 Functional Description (Continued) TL EE 9157 ­ 16 FIGURE 3-12 16-Bit General Slave Instruction Protocol FPU Actions TL EE 9157 ­ 17 FIGURE 3-13 32-Bit General Slave Instruction Protocol FPU Actions 17 4 1 2 Input Signals 3 0 Functional Description (Continued) CLK 3 6 2 Early Done Algorithm The NS32381 NS32381 has the ability to modify the General Slave protocol sequences and to boost the performance of the FPU by 20% to 40% This is called the Early Done Algorithm Early Done is defined by the fact that the destination of an instruction is an FPU register and that the instruction and range of operands cannot generate a TRAP When these conditions are met the FPU will send a SDNXXX or SPC pulse after receiving all of the operands from the CPU and before executing the instruction Hence this becomes an early done as compared to the General Slave Protocols In the case of the 16-bit Slave Protocol in which the CPU always reads the slave status word the FPU will force all zeroes to be read The CPU can then send the next instruction to the FPU and save the general protocol overhead The FPU will start the new instruction immediately after finishing the previous instruction SFSR CMPF and CMPL do not generate an Early Done DDIN ST0 ­ ST3 Note The NS32332 NS32332 generates four status lines and the NS32532 NS32532 generates five The user should connect the status lines as shown below NS32381 NS32381 3 6 3 Floating-Point Protocols Table 3-3 gives the protocols followed for each floatingpoint instruction The instructions are referenced by their mnemonics For the bit encodings of each instruction see section 2 2 3 The Operand Class columns give the Access Classes for each general operand defining how the addressing modes are interpreted by the CPU (see Series 32000 Instruction Set Reference Manual) The Operand Issued columns show the sizes of the operands issued to the Floating-Point Unit by the CPU ``D'' indicates a 32-bit Double Word ``i'' indicates that the instruction specifies an integer size for the operand (B e Byte W e Word D e Double Word) ``f'' indicates that the instruction specifies a floating-point size for the operand (F e 32-bit Standard Floating L e 64-bit Long Floating) The Returned Value Type and Destination column gives the size of any returned value and where the CPU places it The PSR Bits Affected column indicates which PSR bits if any are updated from the FPU Status Word (Figure 3-11 ) Any operand indicated as being of type ``f'' will not cause a transfer if the Register addressing mode is specified because the Floating-Point Registers are physically on the Floating-Point Unit and are therefore available without CPU assistance RST NOE PS0 PS1 NS32332 NS32332 NS32532 NS32532 NS32GX32 NS32GX32 NS32GX320 NS32GX320 ST0 ST0 ST0 ST1 ST1 ST1 ST2 ST2 ST2 ST3 ST3 ST4 Reset Active low Resets the last operation and clears the FSR register New Opcode Enable Active high This signal enables the new opcodes available in the NS32381 NS32381 Protocol Select Selects the slave protocol to be used PS0 is the least significant and rightmost bit 00 Selects 16-bit protocol 01 Selects 32-bit protocol for NS32332 NS32332 10 Reserved 11 Selects 32-bit protocol for NS32532 NS32532 NS32GX32 NS32GX32 NS32GX320 NS32GX320 4 1 3 Output Signals SDN332 SDN332 Slave Done 332 Active low This signal is for use with the NS32332 NS32332 CPU only If held active for a half clock cycle and released this pin indicates the successful completion of a floatingpoint instruction by the FPU Holding this pin active for two and a half clock cycles indicates TRAP or that the CMPf instruction has been executed SDN532 SDN532 Slave Done 532 Active low This signal is for use with the NS32532 NS32532 NS32GX32 NS32GX32 NS32GX320 NS32GX320 CPUs only When active it indicates successful completion of a floating-point instruction by the FPU FSSR Force Slave Status Read Active low This signal is for use with the NS32532 NS32532 NS32GX32 NS32GX32 NS32GX320 NS32GX320 CPUs only When active it indicates TRAP or that the CMPf instruction has been executed 4 0 Device Specifications 4 1 PIN DESCRIPTIONS 4 1 1 Supplies The following is a brief description of all NS32381 NS32381 pins VCC Power a 5V positive supply GND Clock TTL-level clock signal Data Direction In Active low Status signal indicating the direction of data transfers during a bus cycle Status Bus cycle status code from CPU ST0 is the least significant and rightmost bit 1100 Reserved 1101 Transferring Operation Word or Operand 1110 Reading Status Word 1111 Broadcasting Slave ID Ground Ground reference for both on-chip logic and drivers connected to output pins 4 1 4 Input Output Signals D0 ­ D31 Data Bus These are the 32 signal lines which carry data between the NS32381 NS32381 and the CPU SPC Slave Processor Control Active low This is the data strobe signal for slave transfers For the 32-bit protocol SPC is only an input signal For the 16-bit Slave Protocol the upper sixteen data input signals (D16­ D31) and DDIN should be left floating 18 4 0 Device Specifications (Continued) Connection Diagrams TL EE 9157 ­ 18 Bottom View Order Number NS32381 NS32381 See NS Package Number U68D FIGURE 4-1 68-Pin PGA Package NS32381 NS32381 Pinout Descriptions Desc Pin Desc Pin VCC D1 D0 PS1 (Note 1) GND GND CLK RST Reserved (Note 2) Reserved (Note 2) D2 D17 D16 PS0 (Note 1) GND NOE (Note 1) Reserved (Note 3) Reserved (Note 2) VCC D15 D18 D3 D31 D14 D19 VCC D30 VCC D4 D20 D13 D29 Reserved (Note 3) D5 A2 A3 A4 A5 A6 A7 A8 A9 A10 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 C1 C2 C10 C11 D1 D2 D10 D11 E1 E2 E10 E11 F1 F2 D28 GND GND D21 D12 D27 D6 D22 D11 SDN332 SDN332 D7 D23 SPC SDN532 SDN532 VCC D8 GND D26 GND VCC Reserved (Note 3) ST0 ST1 Reserved (Note 3) GND D24 D25 D9 D10 DDIN VCC ST2 ST3 FSSR F10 F11 G1 G2 G10 G11 H1 H2 H10 H11 J1 J2 J10 J11 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 L2 L3 L4 L5 L6 L7 L8 L9 L10 Note 1 CMOS input never float Note 2 Pin should be grounded Note 3 Pin should be left floating 19 4 0 Device Specifications (Continued) Connection Diagrams (Continued) TL EE 9157 ­ 42 Bottom View Order Number NS32381V-15 NS32381V-15 NS32381V-20 NS32381V-20 NS32381V-25 NS32381V-25 or NS32381V-30 NS32381V-30 See NS Package Number V68 FIGURE 4-2 68-Pin PLCC Package Note 1 All these pins should be left open Note 2 All these pins should be grounded 20 4 0 Device Specifications (Continued) All Input or Output Voltages with Respect to GND 4 2 ABSOLUTE MAXIMUM RATINGS If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Maximum Case Temperature 95 C Storage Temperature b 0 5V to a 7 0V ESD Rating 2000V (in human body model) Note Absolute maximum ratings indicate limits beyond which permanent damage may occur Continuous operation at these limits is not intended operation should be limited to those conditions specified under Electrical Characteristics b 65 C to a 150 C 4 3 ELECTRICAL CHARACTERISTICS TA e 0 C to 70 C VCC e 5V g 5% GND e 0V Max Units VIH Symbol High Level Input Voltage Parameter Conditions Min 20 Typ VCC a 0 5 V VIL Low Level Input Voltage b0 5 08 VOH High Level Output Voltage IOH e b400 mA VOL Low Level Output Voltage IOL e 4 mA II Input Load Current 0 s VIN s VCC VIH V 24 V 04 V b 10 0 10 0 mA High Level Input Voltage for PS0 PS1 NOE 35 VCC a 0 5 V VIL Low Level Input Voltage for PS0 PS1 NOE b0 5 15 V II Input Load Current for PS0 PS1 NOE 0 s VIN s VCC b 100 100 mA IL Leakage Current (Output and I O Pins in TRI-STATE Input Mode) 0 4 s VOUT s 2 4V b 20 0 20 0 mA ICC Active Supply Current IOUT e 0 TA e 25 C VCC e 5V 300 mA ICC Power Down Current IOUT e 0 TA e 25 C VCC e 5V 60 mA Except PS0 PS1 NOE and Reserved pins Note PS0 PS1 NOE pins have to be connected to either GND or VCC (possible via resistor) as it is shown in Figure 3-4a 3-4b 3-4c and 3-4d ABBREVIATIONS LE Leading Edge TE Trailing Edge 4 4 SWITCHING CHARACTERISTICS 4 4 1 Definitions All the Timing Specifications given in this section refer to 0 8V and 2 0V on all the input and output signals as illustrated in Figures 4 3 and 4 4 unless specifically stated otherwise RE FE Rising Edge Falling Edge TL EE 9157 ­ 20 FIGURE 4-4 Timing Specification Standard (Signal Valid before Clock Edge) TL EE 9157 ­ 19 FIGURE 4-3 Timing Specification Standard (Signal Valid after Clock Edge) 21 4 0 Device Specifications (Continued) 4 4 2 Timing Tables 4 4 2 1 Output Signal Propagation Delays for all CPUs (16-Bit Slave Protocol) Maximum times assume capacitive loading of 100 pF at 15 MHz and 50 pF at 20 MHz and 25 MHz Symbol Figure Reference Conditions Description NS32381-15 NS32381-15 Min NS32381-20 NS32381-20 Max Min NS32381-25 NS32381-25 Max Min Units Max tSPCFw 4-18 SPC Pulse Width from FPU At 0 8V (Both Edges) tSPCFa 4-18 SPC Output Active After CLK R E 17 17 15 ns tSPCFia 4-18 SPC Output Inactive After CLK R E 38 33 25 ns tSPCFf(1) 4-18 SPC Output Floating After CLK F E 35 30 25 ns tCLKpb10 tCLKp a 10 tCLKpb10 tCLKp a 10 tCLKpb10 tCLKp a 10 ns 4 4 2 2 Output Signal Propagation Delays for the NS32008 NS32008 NS32016 NS32016 NS32032 NS32032 NS32CG16 NS32CG16 NS32FX16 NS32FX16 NS32CG160 NS32CG160 CPUs Maximum times assumes capacitive loading of 100 pF at 15 MHz and 50 pF at 20 MHz and 25 MHz Symbol Figure Description Reference Conditions NS32381-15 NS32381-15 NS32381-20 NS32381-20 NS32381-25 NS32381-25 Min Min Min Max Max Units Max tDv 4-8 Data Valid (D0­D15) After SPC L E 30 23 18 ns tDf(1) 4-8 D0­D15 Floating After SPC T E 30 30 30 ns 4 4 2 3 Output Signal Propagation Delays for the 32-Bit Slave Protocol NS32332 NS32332 CPU Maximum times assume capacitive loading of 100 pF unless otherwise specified Symbol Figure Description NS32381-15 NS32381-15 Reference Conditions tDv 4-10 Data Valid 4-10 Data Hold After SPC T E tDf(1) 4-10 Data Floating After SPC T E tSDNa 4-12 13 Slave Done Active After CLK F E tSDNh 4-13 Slave Done Hold After CLK R E tSDNw 4-12 Slave Done Pulse Width At 0 8V (Both Edges) tSDNf(1) 4-12 13 Slave Done Floating 4-13 Slave Done (TRAP) Pulse Width At 0 8V (Both Edges) 25 8 Note 1 Guaranteed by characterization Due to tester conditions this parameter is not 100% tested 22 ns ns 30 3 ns 28 tCLKpb15 ns 33 ns tCLKp a 10 After CLK R E tSTRPw Units Max After SPC L E 75 pF Cap Loading tDh Min 30 2 tCLKpb10 2 tCLKp a 10 ns ns ns 4 0 Device Specifications (Continued) 4 4 2 4 Output Signal Propagation Delays for the 32-Bit Slave Protocol NS32532 NS32532 CPU Maximum times assume capacitive loading of 50 pF Symbol Figure NS32381-20 NS32381-20 NS32381-25 NS32381-25 NS32381-30 NS32381-30 Min Reference Conditions Description Min Min Units Max tDv 4-14 Data Valid After SPC L E 35 tDh 4-14 Data Hold After CLK R E tDf(1) 4-14 Data Floating After SPC T E 30 tSDa 4-16 Slave Done Active After CLK R E 35 tSDh 4-16 Slave Done Hold After CLK R E tSDf(1) 4-16 Slave Done Floating After CLK R E tFSSRa 4-17 Forced Slave Status Read Active After CLK R E tFSSRh 4-17 Forced Slave Status Read Hold After CLK R E tFSSRf(1) 4-17 Forced Slave Status Read Floating After CLK R E Max 35 35 ns 30 30 ns 25 3 20 ns 3 2 Max 33 3 20 ns 30 30 30 ns 35 2 2 25 20 ns 20 ns 30 ns 33 25 ns 2 25 30 2 2 30 4 4 2 5 Input Signal Requirements with all CPUs Symbol Figure NS32381-15 NS32381-15 Reference Conditions Description Min NS32381-20 NS32381-20 Max Min Max NS32381-25 NS32381-25 Min Max NS32381-30 NS32381-30 Min Units Max tPWR 4-6 Power-On Reset Duration After CLK R E 30 30 30 30 ms tRSTw 4-7 Reset Pulse Width At 0 8V (Both Edges) 64 64 64 64 tCLKp tRSTs 4-7 Reset Setup Time Before CLK R E 10 14 12 11 ns tRSTh 4-7 Reset Hold After CLK R E 0 0 0 0 ns 4 4 2 6 Input Signal Requirements with the NS32008 NS32008 NS32016 NS32016 NS32032 NS32032 NS32CG16 NS32CG16 NS32FX16 NS32FX16 NS32CG160 NS32CG160 CPUs Symbol Figure Description Reference Conditions NS32381-15 NS32381-15 NS32381-20 NS32381-20 NS32381-25 NS32381-25 Min Min Min Max Max Units Max tSs 4-8 Status (ST0­ST1) Setup Before SPC L E 20 20 15 ns tSh 4-8 Status (ST0­ST1) Hold After SPC L E 20 20 20 ns tDs 4-9 Data Setup (D0­D15) Before SPC T E 25 20 15 ns tDh 4-9 Data Hold (D0­D15) After SPC T E 20 20 15 ns tSPCw 4-8 SPC Pulse Width from CPU At 0 8V (Both Edges) 35 35 28 ns Note 1 Guaranteed by characterization Due to tester conditions this parameter is not 100% tested 23 4 0 Device Specifications (Continued) 4 4 2 7 Input Signal Requirements with the 32-Bit Slave Protocol NS32332 NS32332 CPU Symbol Figure NS32381-15 NS32381-15 Reference Conditions Description Min Units Max tSTs 4-11 Status Setup Before SPC L E 20 ns tSTh 4-11 Status Hold After SPC L E 20 ns tDs 4-11 Data Setup Before SPC T E 20 ns tDh 4-11 Data Hold After SPC T E 20 ns tSPCw 4-11 SPC Pulse Width At 0 8V (Both Edges) 35 ns 4 4 2 8 Input Signal Requirements with the 32-Bit Slave Protocol NS32532 NS32532 CPU Symbol Figure NS32381-20 NS32381-20 NS32381-25 NS32381-25 NS32381-30 NS32381-30 Min Reference Conditions Description Min Min Max Max Units Max tSTs 4-15 Status Setup Before CLK (T2) R E 25 25 23 tSTh 4-15 Status Hold After CLK (T2) R E 20 10 10 ns tDDINs 4-15 Data Direction In Setup Before SPC L E 0 0 0 ns tDDINh 4-15 Data Direction In Hold After SPC T E 10 10 10 ns tDs 4-15 Data Setup Before SPC T E 6 6 4 ns tDh ns 4-15 Data Hold After SPC T E 20 15 15 ns tSPCs 4-14 15 SPC Setup Before CLK R E 25 23 20 ns tSPCh 4-14 15 SPC Hold After CLK R E 0 0 0 ns 4 4 2 9 Clocking Requirements with all CPUs Symbol Figure Description Reference Conditions NS32381-15 NS32381-15 NS32381-20 NS32381-20 NS32381-25 NS32381-25 NS32381-30 NS32381-30 Units Min Max Min Max Min Max Min Max tCLKh 4-5 Clock High Time At 2 0 V (Both Edges) 0 5 tCLKp b8 3 0 5 tCLKp b5 0 5 tCLKp b5 0 5 tCLKp b 3 65 ns tCLKl 4-5 Clock Low Time At 0 8V (Both Edges) 0 5 tCLKp b8 3 0 5 tCLKp b5 0 5 tCLKp b4 0 5 tCLKp b 3 65 ns tCTr(1) 4-5 Clock Rise Time Between 0 8V and 2 0V 7 5 4 3 ns tCTd(1) 4-5 Clock Fall Time Between 2 0V and 0 8V 7 5 4 3 ns tCLKp 4-5 Clock Period 1000 ns CLK R E to Next CLK R E (Note 2) 66 1000 50 1000 40 1000 33 3 Note 1 Guaranteed by characterization Due to tester conditions this parameter is not 100% tested Note 2 The 1 MHz clock frequency is allowed for power-down mode only Floating-point instructions can be executed only after the clock frequency has been brought back to normal operating frequency 24 4 0 Device Specifications (Continued) 4 4 3 Timing Diagrams TL EE 9157 ­ 21 FIGURE 4-5 Clock Timing TL EE 9157 ­ 22 FIGURE 4-6 Power-On Reset TL EE 9157 ­ 24 FIGURE 4-7 Non-Power-On Reset Note The rising edge of RST must occur while CLK is high as shown TL EE 9157 ­ 25 FIGURE 4-8 Read Cycle from FPU (NS32008 NS32008 NS32016 NS32016 NS32032 NS32032 NS32CG16 NS32CG16 NS32FX16 NS32FX16 NS32CG160 NS32CG160 CPUs) 25 4 0 Device Specifications (Continued) TL EE 9157 ­ 26 FIGURE 4-9 Write Cycle to FPU (NS32008 NS32008 NS32016 NS32016 NS32032 NS32032 NS32CG16 NS32CG16 NS32FX16 NS32FX16 NS32CG160 NS32CG160 CPUs) TL EE 9157 ­ 27 FIGURE 4-10 Read Cycle from FPU (NS32332 NS32332 CPU) TL EE 9157 ­ 28 FIGURE 4-11 Write Cycle to FPU (NS32332 NS32332 CPU) 26 4 0 Device Specifications (Continued) TL EE 9157 ­ 29 FIGURE 4-12 SDN332 SDN332 Timing (NS32332 NS32332 CPU) TL EE 9157 ­ 30 FIGURE 4-13 SDN332 SDN332 (TRAP) Timing (NS32332 NS32332 CPU) TL EE 9157 ­ 31 FIGURE 4-14 Read Cycle from FPU (NS32532 NS32532 NS32GX32 NS32GX32 NS32GX320 NS32GX320 CPU) 27 4 0 Device Specifications (Continued) TL EE 9157 ­ 32 FIGURE 4-15 Write Cycle to FPU (NS32532 NS32532 NS32GX32 NS32GX32 NS32GX320 NS32GX320 CPU) TL EE 9157 ­ 33 FIGURE 4-16 SDN532 SDN532 Timing (NS32532 NS32532 NS32GX32 NS32GX32 NS32GX320 NS32GX320 CPU) TL EE 9157 ­ 34 FIGURE 4-17 FSSR Timing (NS32532 NS32532 NS32GX32 NS32GX32 NS32GX320 NS32GX320 CPU) TL EE 9157 ­ 35 FIGURE 4-18 SPC Pulse from FPU 28 Appendix A The following instructions do not generate an early done In this case EXT is the time from the last data sent to the FPU until the normal DONE is issued (FPU Pipe is empty) NS32381 NS32381 PERFORMANCE ANALYSIS The following performance numbers were taken from simulations using the 381 SIMPLE model The timing terms have been designed to provide performance numbers which are CPU independent Numbers were obtained from SIMPLE simulations taking the average execution times using `typical' operands Listed below are definitions of the timing terms EXT (EXecution Time) This is the time from the last data sent to the FPU until the early DONE is issued (FPU Pipe is empty) EDD (Early Done Delta) This is the time from when the early DONE is issued until the execution of the next instruction may start Provided that the CPU can transfer the ID OPCODE and any operands to the FPU during the EDD time the average system execution time for an instruction (keeping the FPU pipe filled) is EXT a EDD The system execution time for a single FPU instruction with FPU register destination and early done is EXT plus the protocol time (FPU pipe is initially empty) Instruction EXT EDD 5 8 5 5 6 8 5 45 9 6 11 11 31 31 any reg any reg 11 11 31 31 42 42 MULF any reg MULL any reg 11 11 20 27 31 38 DIVF DIVL any reg any reg 11 11 45 59 56 70 POLYF any any POLYL any any 15 15 46 53 61 68 DOTF any any DOTL any any 15 15 46 53 17 17 any any any any 9 9 any any 49 LOGBf 42 42 SUBF SUBL any any any any SCALBf 15 ADDF any reg ADDL any reg 46 46 46 ABSf NEGf 50 MOVFL any reg 18 CMPF CMPL 11 13 MOVif any reg 7 any any ROUNDfi any mem FLOORfi any mem TRUNCfi any mem 13 MOVF any reg MOVL any reg 61 68 LFSR EXT reg mem any any 36 MOVLF Total any reg Instruction SFSR Measured in the number of clock cycles 29 30 Physical Dimensions inches (millimeters) Pin Grid Array (U) Order Number NS32381U NS32381U NS Package Number U68D 31 NS32381-15 NS32381-15 NS32381-20 NS32381-20 NS32381-25 NS32381-25 NS32381-30 NS32381-30 Floating-Point Unit Physical Dimensions inches (millimeters) Plastic Leaded Chip Carrier (V) Order Number NS32381V NS32381V NS Package Number V68A LIFE SUPPORT POLICY NATIONAL'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or systems which (a) are intended for surgical implant into the body or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user National Semiconductor Corporation 1111 West Bardin Road Arlington TX 76017 Tel 1(800) 272-9959 Fax 1(800) 737-7018 2 A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness National Semiconductor Europe Fax (a49) 0-180-530 85 86 Email cnjwge tevm2 nsc com Deutsch Tel (a49) 0-180-530 85 85 English Tel (a49) 0-180-532 78 32 Fran ais Tel (a49) 0-180-532 93 58 Italiano Tel (a49) 0-180-534 16 80 National Semiconductor Hong Kong Ltd 13th Floor Straight Block Ocean Centre 5 Canton Rd Tsimshatsui Kowloon Hong Kong Tel (852) 2737-1600 Fax (852) 2736-9960 National Semiconductor Japan Ltd Tel 81-043-299-2309 Fax 81-043-299-2408 National does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications