NM25C04 NM93C66 AN-1012 C1995 RRD-B30M115 MC68HC11 68HC11 25C04 0123H D8-D15 - Datasheet Archive

 

The SPI (Serial Peripheral Interface) provides a simple eight bit serial port useful in communicating with external devices Prior

 

INTRODUCTION The SPI (Serial Peripheral Interface) provides a simple eight bit serial port useful in communicating with external devices Prior to the SPI EEPROMs introduction engineers used the standard MICROWIRE EEPROMs to interface with the SPI port MICROWIRE's diverse densities and data protection options offered highly versatile solutions Recently several manufacturers have developed serial EEPROMs that are now specifically designed to interface with this port Due to SPI's faster clock speed and interface compatibility this EEPROM device is increasing in popularity The following application note will compare these two EEPROMs and where the advantages exist in each family To perform this comparison a 4 kbit SPI and a 4 kbit MICROWIRE EEPROM are interfaced to the SPI port of a HC11 The NM25C04 NM25C04 SPI is a 512 by 8-bit serial EEPROM while the NM93C66 NM93C66 MICROWIRE is a 256 by 16-bit HARDWARE INTERFACE HC11 microcontroller's can be configured in one of two modes when utilizing the SPI port The ``master'' mode sets the microcontroller to orchestrate data transfer to the peripheral device The ``slave'' mode allows the peripheral device to command the HC11 In this application the HC11 is set as the ``master'' to control the data transfers to and from the serial EEPROMs Figure 1 and Figure 2 shows the typical SPI and MICROWIRE connection to a HC11 SPI port The HC11 SPI port has three lines that control data transfer and one extra general purpose I O line to control the peripheral device's chip select The MOSI (Master Out Slave In) line is used as data out MISO (Master In Slave Out) line is the data input and the SCK generates the serial clock The general purpose PD5 line controls the EEPROMs chip select Both the SPI and the MICROWIRE devices are configurable as a four wire interface Thus neither of the EEPROMs offer a connection advantage DATA TRANSFER The new SPI EEPROMs are specifically designed to interface with the SPI port Furthermore it operates at 2 1 MHz versus MICROWIRE's 1 MHz clock The SPI communication protocol is broken down into byte size sequences containing instruction address and data transfer information National Semiconductor Application Note 1012 Dovell Bonnett September 1995 TL D 12513 ­ 2 FIGURE 2 NM93C66 NM93C66 to HC11 Connections Address transfers are dependent on the memory density Standard MICROWIRE is organized in 16-bit words To provide the SPI byte size data transfer protocol three to five bits of additional instructions are required Furthermore a design consideration is required when interfacing a MICROWIRE device to the SPI port Data is valid relative to the clock signal Data is written to the EEPROM on the rising edge of the clock When reading from a MICROWIRE device data is valid on the falling edge Development of SPI compatibility is easily accomplished once the design issues are understood Non-byte wide instruction and address issues can be dealt with by shifting in leading 0's before the required start bit The leading 0's will not be recognized and can be used to fill out an instruction to byte length The MICROWIRE word wide architecture can be made to appear byte accessible with clever software The clock polarity issues can be handled by changing the configuration of the SPI port when receiving or transmitting data Both devices were driven with a 1 MHz clock from the SPI port Communications between the HC11 and the serial EEPROMs took roughly the same amount of time SOFTWARE COMPARISON Two software programs are included that demonstrate the interfacing difference between the HC11 microcontroller to a NM93C66 NM93C66 and a NM25C04 NM25C04 The MICROWIRE data transferring differences as described in the previous section only required an additional 38 bytes of program space The standard MICROWIRE family is organized in a 16-bit (word wide) manner SPI is an 8-bit (byte wide) structure Therefore the additional software overhead that is required for converting a word organization into a byte organization However there are devices available at National that offers the designer the option of either a x8 or x16 mode The data size selection is determined by the ORG pin found on the NM93CxxA family By setting the ORG pin low the SPI and MICROWIRE devices are comparable in the amount of required programming space AN-1012 AN-1012 TL D 12513 ­ 1 FIGURE 1 NM25C04 NM25C04 to HC11 Connections MICROWIRETM is a trademark of National Semiconductor Corporation SPITM is a trademark of Motorola C1995 C1995 National Semiconductor Corporation TL D 12513 SPI Versus MICROWIRE EEPROM Comparison SPI TM Versus MICROWIRE TM EEPROM Comparison RRD-B30M115 RRD-B30M115 Printed in U S A CONCLUSION When considering availability and price per bit both families of EEPROMs are quite competitive This application note has shown that both the SPI and MICROWIRE families of devices can be effectively interfaced to the HC11 MICROWIRE performance compares favorably with the newer SPI EEPROMs A few extra bytes of software is the most significant disadvantage when using word wide MICROWIRE mode In applications where the extra software storage space is available this becomes a non-issue 2 * * This code was developed to demonstrate how the NM25C04 NM25C04 serial EEPROM * can be interfaced to the MC68HC11 MC68HC11 microcontroller * write operations have been developed Basic read and The software demonstrates the * * * * following commands * * * * READ Read a byte * * WREN Enable write operations * * WRDI Disable write operations * * WRITE Program a byte * * * * The SPI port in Port D is used to interface the NM25C04 NM25C04 to the * * 68HC11 68HC11 The SPI port provides the clock (SCK) data out (MOSI) and * * the data in (MISO) lines The 25C04 25C04 CS line is driven by a general * * purpose Port D I O line * * * * The mainline was used to test the functionality of the subroutines * * The subroutines can be copied directly into a customer's program and * * be expected to operate as described The final mainline only * * performs a write enable write write disable and finally a read * * * * ADDRESS LOCATION EQUATES * * DDRD PORTD SPCR SPSR SPDR EQU EQU EQU EQU EQU $09 $08 $28 $29 $2A port D direction register 4 $1009 port D data register 4 $1008 SPI control register SPI status register SPI data register * * BIT POSITION EQUATES * * * * CSBIT EQU $20 CS position in port D 4 bit 5 * * VARIABLE ADDRESS EQUATES * * HIADD LOADD DATVAL EQU EQU EQU $0180 $0181 $0182 high order page pointer low order page pointer data transfer register * * RESET VECTOR * * * * ORG $FFFE reset vector to $E000 FDB $E000 3 * * PROGRAM STARTING LOCATION * * BEGIN ORG LDS LDX LDAA STAA LDAA STAA LDAA STAA LDAA $E000 $01FF $1000 $EF PORTD X $3F DDRD X $54 SPCR X SPSR X program execution begins at $E000 initialize stack pointer initialize `address index register` initialize I O ports (CS 4 1 SCK 4 0) SPI bits set to outputs initialize SPI port CPOL 4 0 reset SPIF bit CPHA 4 1 * * MAINLINE * * JSR WREN enable write operations LDAA $01 STAA HIADD LDAA $23 STAA LOADD address 4 123H LDAA $96 STAA DATVAL data 4 96H JSR WRITE write data 96H into address 0123H 0123H JSR WRDI disable writes LDAA $01 STAA HIADD LDAA $23 STAA LOADD address 4 123H JSR READ read address 123H LOOP BRA LOOP wait until reset loop * * NM25C04 NM25C04 FUNCTIONAL ROUTINES * * * * WRITE performs a byte write operation into the 25C04 25C04 The routine * * expects the address to modify to be specified in the HIADD and LOADD * * variables The new data value is specified in the DATVAL variable * * The 25C04 25C04 must be in the write enabled state for this function to be * * executed successfully * * 4 WRITE BCLR PORTD LDAA HIADD X CSBIT enable device ASLA move high order address to ASLA proper bit location ASLA ORAA JSR LDAA JSR LDAA JSR BSET JSR RTS $02 SENDB LOADD SENDB DATVAL SENDB PORTD X BUSY OR in WRITE instruction send WRITE instruction send in low order address CSBIT send in data value disable device wait until write has completed * * READ performs a byte read operation from the NM25C04 NM25C04 The routine * * expects the address to read to be specified in the HIADD and LOADD * * variables The data in the specified address is returned in the * * DATVAL variable * * READ JSR BCLR LDAA ASLA ASLA ASLA ORAA JSR LDAA JSR SENDB STAA BSET PORTD HIADD X CSBIT enable device move high order address to proper bit location $03 SENDB LOADD SENDB OR in READ instruction send READ instruction send in low order address read byte from NM25C04 NM25C04 DATVAL PORTD X CSBIT disable device * * WREN enables the NM25C04 NM25C04 to perform a write operation This * * function along with the WRDI (write disable) function helps to * * prevent against inadvertant data changes * * WREN BCLR LDAA JSR BSET RTS PORTD $06 SENDB PORTD X CSBIT enable device X CSBIT send EWEN instruction disable device * * WRDI disables the NM25C04 NM25C04 from further write operations This * * function prevents against inadvertant data changes * * 5 WRDI BCLR PORTD LDAA $04 JSR X CSBIT PORTD CSBIT SENDB BSET X enable device send EWDS instruction disable device RTS * * BUSY is used to pause until a write operation has completed * * BUSY BCLR LDAA JSR JSR BSET ANDA BNE RTS PORTD $05 SENDB SENDB PORTD $01 BUSY X CSBIT send `read status reg` instruction read status register X CSBIT loop until RDY bit in status is low * * SENDB is used to send a byte to the NM25C04 NM25C04 and also read the data * * that has been returned to the 68HC11 68HC11 * * SENDB PAUSE STAA BRCLR LDAA RTS SPDR SPSR SPDR X X X $80 PAUSE send byte in A register wait until byte has been sent read byte into a register * * This code was developed to demostrate how the NM93C66 NM93C66 serial EEPROM * * can be interfaced to the MC68HC11 MC68HC11 microcontroller SPI port The * * software includes several subroutines that perform various interface * * functions The internal architecture of the NM93C66 NM93C66 is configured * * with word wide data registers This applications code demonstrates * * storage of data in a byte wide manner Odd byte addresses are stored * * in the D8-D15 D8-D15 bits of each word and even address data is stored in * * the D0-D7 bits The software demonstrates the following commands * * * * READ Read a byte * * WEN Enable write and erase operations * * WDS Disable write and erase operations * * WRITE Program a byte * * * * The 68HC11 68HC11 interfaces to the NM93C66A NM93C66A by using 3 lines from the SPI * * port and a general purpose I O port bit The 68HC11 68HC11 SCK MOSI and * * MISO pins are used to drive the NM93C66 NM93C66 SK DI and DO pins * * respectively Port D bit 5 is used to drive the CS line of the * * NM93C66 NM93C66 * * * * The mainline was used to test the functionality of the subroutines * * The subroutines can be copied directly into a customer's program and * * be expected to operate as described The final mainline only * * performs a write enable write write disable and finally a read * * 6 * * ADDRESS LOCATION EQUATES * * DDRD PORTD SPCR SPSR SPDR EQU EQU EQU EQU EQU $09 $08 $28 $29 $2A port D direction register 4 $1009 port D data register 4 $1008 SPI control register SPI status register SPI data register * * BIT POSITION EQUATES * * * * CSBIT EQU $20 CS position in port D 4 bit 5 * * VARIABLE ADDRESS EQUATES * * HIADD LOADD DATVAL TEMP EQU EQU EQU EQU $0180 $0181 $0182 $0183 high order page pointer low order page pointer data transfer register temporary `scratch` register * * RESET VECTOR * * * * ORG FDB $FFFE $E000 reset vector to $E000 * * PROGRAM STARTING LOCATION * * ORG LDS LDX $E000 $01FF $1000 program execution begins at $E000 initialize stack pointer initialize `address index register` LDAA STAA LDAA STAA LDAA STAA LDAA BEGIN $CF PORTD X $3F DDRD X $50 SPCR X SPSR X initialize I O ports (CS 4 0 SCK 4 0) SPI bits set to outputs initialize SPI port reset SPIF bit * * MAINLINE * * 7 JSR WREN LDAA STAA HIADD LDAA LOOP enable write operation $01 $23 STAA LDAA STAA JSR JSR LDAA STAA LDAA STAA JSR BRA LOADD $96 DATVAL WRITE WDS $01 HIADD $23 LOADD READ LOOP write data 96H into address 0123H 0123H disable writes read address 123H wait until reset loop * * 98C66 98C66 FUNCTIONAL ROUTINES * * * * WRITE performs a byte write operation into the 93C66 93C66 The routine * * expects the address to modify to be specified in the HIADD and LOADD * * variables The new data value is specified in the DATVAL variable * * The 93C66 93C66 must be in the write enabled state for this function to be * * executed successfully Each word in the NM93C66 NM93C66 contains 2 bytes with * * the high order byte used for `odd` addresses and the low order byte used * * for `even` addresses The word addresses to be accessed is determined by * * dividing the byte address specified in HIADD and LOADD by two The data * * to be written is determined by reading the specified word address and * * mapping in the new byte value into the specified high or low order byte * * 8 WRITE LDAA DATVAL save the data value HIADD save the address PSHA LDAA PSHA NOFLIP LDAA PSHA EORA STAA JSR PULA STAA PULA STAA PULA STAA ROR ROR BCC PSHA LDAA STAA PULA STAA BSET LDAA JSR LDAA JSR LDAA JSR LDAA JSR BCLR JSR RTS LOADD $01 LOADD READ determine the byte address in the word that will not be modified read the valid byte LOADD retrieve address to modify HIADD TEMP HIADD LOADD NOFLIP retrieve new data value calculate word address DATVAL TEMP DATVAL PORTD X $05 SENDB LOADD SENDB DATVAL SENDB TEMP SENDB PORTD X BUSY CSBIT if carry 4 0 then we are set save new data value transfer valid byte in word into TEMP store new data byte value into DATVAL enable device send WRITE instruction send word address to modify send high order data byte CSBIT send low order data byte disable device wait until write has completed * * READ performs a byte read operation from the 93C66 93C66 The routine * * expects the address to read to be specified in the HIADD and LOADD * * variables The data in the specified address is returned in the * * DATVAL variable Each word in the NM93C66 NM93C66 contains 2 bytes with the * * high order byte used for `odd` addresses and the low order byte used * * for `even` addresses The word address to be accessed is determined * * by dividing the byte address specified in HIADD and LOADD by two * * 9 READ BSET PORTD LDAA $06 JSR SENDB ROR X CSBIT enable device HIADD send READ instruction ROR LOADD LDAA LOADD JSR SENDB send address LDAA $54 STAA SPCR X sample on falling edge when reading JSR SENDB read data value BCS DONER JSR SENDB DONER STAA DATVAL BCLR PORTD X CSBIT disable device LDAA $50 STAA SPCR X data valid on rising edge RTS * * WEN enables the 93C66 93C66 to perform a write operation This function * * along with the WDS (write disable) function helps to prevent against * * inadvertant data changes * * WEN BSET PORTD X CSBIT enable device LDAA $04 JSR SENDB send WEN instruction LDAA $C0 JSR SENDB send instruction 0 dummy address BCLR PORTD X CSBIT disable device RTS * * WDS disables the 93C66 93C66 from further write operations This * * function prevents against inadvertant data changes * * WDS BSET PORTD X CSBIT enable device LDAA $04 JSR SENDB send WDS instruction LDAA $00 JSR SENDB send instruction 0 dummy address BCLR PORTD X CSBIT disable device RTS * * SUPPORT ROUTINES * * 10 * * BUSY is used to pause until a write or erase operation has completed * * BUSY TWC BSET BRCLR BCLR RTS PORTD PORTD PORTD X X X CSBIT $04 CSBIT enable device TWC wait until write cycle has finished disable device * * SENDB is used to send a byte to the NM93C66 NM93C66 and also read the data * * that has been returned to the 68HC11 68HC11 * * SENDB PAUSE STAA BRCLR LDAA RTS SPDR SPSR SPDR X X X $80 PAUSE send byte in A register wait until byte has been sent read byte in A register 11 SPI Versus MICROWIRE EEPROM Comparison LIFE SUPPORT POLICY NATIONAL'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS 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