NJW1321 NJW1321FP1 QFP48 NJW1320

WIDE BAND VIDEO SWITCH WITH I2C BUS GENERAL DESCRIPTION The NJW1321 is a Wide Band Video Switch with I2C BUS. The NJW1321

NJW1321 NJW1321 WIDE BAND VIDEO SWITCH WITH I2C BUS GENERAL DESCRIPTION The NJW1321 NJW1321 is a Wide Band Video Switch with I2C BUS. The NJW1321 NJW1321 includes switch of 4-input 2-output and 6dB amplifier. It is suitable for RGB or Y, Pb, and Pr signal because frequency range is 100MHz. The NJW1321 NJW1321 includes external logic control terminals and external logic discernment terminals. The NJW1321 NJW1321 is suitable for PTV, DTV, PDP and other high quality AV systems. FEATURES Operating Voltage I2C BUS Interface 4-input 2-output 3-Circuits Wide frequency range PACKAGE OUTLINE NJW1321FP1 NJW1321FP1 +9.0V 0dB at 100MHz typ. -3dB at 300MHz typ. Internal 6dB amplifier (Selectable Bypass or 6dB) External logic discernment terminal External logic control terminal Selectable slave address Power Save Circuit Bi-CMOS Technology Package Outline QFP48 QFP48 BLOCK DIAGRAM Y/R IN1 6dB Y/R OUT1 6dB Y/R OUT2 6dB Pb/G OUT1 6dB Pb/G OUT2 6dB Pr/B OUT1 6dB Y/R IN2 Pr/B OUT2 Y/R IN3 Y/R IN4 Pb/G IN1 Pb/G IN2 Pb/G IN3 Pb/G IN4 Pr/B IN1 Pr/B IN2 Pr/B IN3 Pr/B IN4 PORT 0 ADDRESS PORT 1 SDA PORT 2 SCL I2C BUS PORT 3 GND VREF AUX 0 AUX 1 V+ BIAS AUX 2 AUX 3 DGND Ver.7 -1- NJW1321 NJW1321 Pb IN4 V+ Y IN4 V+ Y OUT1 GND Pb OUT1 GND Pr OUT1 AUX3 AUX2 Y OUT2 AUX1 AUX0 PIN CONFIGURATION 38 24 48 15 1 14 Pb IN2 GND Pr IN2 GND Y IN1 V+ Pb IN1 V+ Pr IN1 GND PORT3 PORT2 ADR 39 V+ GND Pr IN4 V+ Y IN3 GND Pb IN3 V+ Pr IN3 GND Y IN2 25 1. V+ 25. AUX0 37. V+ 2. Pb IN2 14. ADR 26. AUX1 38. Pb IN4 3. GND 15. SCL 27. Y OUT2 39. GND 4. Pr IN2 16. SDA 28. AUX2 40. Pr IN4 5. GND 17. GND 29. AUX3 41. V+ 6. Y IN1 18. DGND 30. Pr OUT1 42. Y IN3 7. V+ 19. VREG 31. GND 43. GND 8. Pb IN1 20. V+ 32. Pb OUT1 44. Pb IN3 9. V+ 21. Pr OUT2 33. GND 45. V+ 10. Pr IN1 22. PORT1 34. Y OUT1 46. Pr IN3 11. GND 23. PORT 0 35. V+ 47. GND 12. PORT3 -2- 13. PORT2 24. Pb OUT2 36. Y IN4 48. Y IN2 Pb OUT2 PORT0 PORT1 Pr OUT2 V+ VREF DGND GND SDA SCL NJW1321 NJW1321 ABSOLUTE MAXIMUM RATINGS (Ta=25°C) PARAMETER SYMBOL RATINGS UNIT Supply Voltage V+ 12.0 V Power Dissipation PD 1875(note) mW Topr -40 to +75 Operating Temperature Range °C Tstg -40 to +150 Storage Temperature Range °C (Note) At on a board of EIA/JEDEC specification. (76.2 × 114.3 × 1.6mm Two layers, FR-4) RECOMMENDED OPEARATING CONDITION (Ta=25°C) PARAMETER Operating Voltage SYMBOL Vopr TEST CONDITION MIN. 8.5 TYP. 9.0 MAX. 9.5 UNIT V ELECTRICAL CHARACTERISTICS (V+=9.0V, RL=10K, Ta=25°C) VIDEO PARAMETER SYMBOL TEST CONDITION MIN. TYP. MAX. UNIT - 85 100 Maximum Output Voltage Icc Vom 2.0 2.5 - mA Vp-p Voltage Gain 1 Gv1 6.0 6.4 6.8 dB Voltage Gain 2 Gv2 -0.5 0.0 0.5 dB - 0 - dB - 0 - dB - -3.0 - dB - -3.0 - dB - -60 -50 dB Operating Current Frequency Characteristic 1 Frequency Characteristic 2 Frequency Characteristic 3 Frequency Characteristic 4 Cross talk 1 CTB1 No signal f=100kHz, THD=1% 6dB Mode Vin=100kHz, 1.0Vp-p Sin signal Bypass Mode Vin=100kHz, 1.0Vp-p Sin signal 6dB Mode Vin=100MHz / 100kHz, 1.0Vp-p Sin signal Bypass Mode Vin=100MHz / 100kHz, 1.0Vp-p Sin signal 6dB Mode Vin=300MHz / 100kHz, 1.0Vp-p Sin signal Bypass Mode Vin=300MHz / 100kHz, 1.0Vp-p Sin signal Vin=4.43MHz,1.0Vp-p Sin signal Cross talk 2 CTB2 Vin=50MHz,1.0Vp-p Sin signal - -40 - dB Gf1 Gf2 Gf3 Gf4 Differential Gain DG Vin=1.0Vp-p 10step Video signal - 0.3 - % Differential Phase DP Vin=1.0Vp-p 10step Video signal - 0.3 - deg S/N SNv Vin=1.0Vp-p,100% White Video Signal - 65 - dB MIN. TYP. MAX. UNIT PORT, AUX PARAMETER SYMBOL TEST CONDITION PORT Input Voltage H VPTH 3.5 - 5.5 V PORT Input Voltage M VPTM 1.4 - 2.4 V PORY Input Voltage L VPTL 0 - 0.8 V AUX Output Voltage H VAUXH 3.5 - 5.5 V AUX Output Voltage M AUX Output Voltage L ADR Input Voltage H VAUXM VAUXL VADRH 1.4 0 3.5 - 2.4 0.8 5.0 V V V ADR Input Voltage L VADRL 0 - 1.0 V -3- NJW1321 NJW1321 TIMING ON THE I2C BUS (SDA,SCL) SDA tf tr tf tHD:ST A tBUF tr tSP tSU:DAT SCL tHD:STA S tLOW tSU:STA tHD:DAT tSU:ST O tHIGH Sr P CHARACTERISTICS OF I/O STAGES FOR I2C BUS (SDA,SCL) I2C BUS Load Conditions STANDARD MODE: Pull up resistance 4k (Connected to +5V), Load capacitance 200pF (Connected to GND) PARAMETER SYMBOL Standard mode MIN. TYP. UNIT MAX. Low Level Input Voltage VIL 0.0 - 1.5 V High Level Input Voltage VIH 2.7 - 5.5 V Low level output voltage (3mA at SDA pin) VOL 0 - 0.4 V Ii -10 - 10 µA Input current each I/O pin with an input voltage between 0.1VDD and 0.9VDDmax -4- S NJW1321 NJW1321 CHARACTERISTICS OF BUS LINES (SDA,SCL) FOR I2C-BUS DEVICES PARAMETER Standard mode SYMBOL UNIT MIN. TYP. MAX. fSCL - - 100 kHz tHD:STA 4.0 - - µs Low period of the SCL clock tLOW 4.7 - - µs High period of the SCL clock tHIGH 4.0 - - µs tSU:STA 4.7 - - µs tHD:DAT 0 - - µs tSU:DAT 250 - - ns Rise time of both SDA and SCL signals tr - - 1000 ns Fall time of both SDA and SCL signals tf - - 300 ns tSU:STO 4.0 - - µs Bus free time between a STOP and START condition tBUF 4.7 - - µs Capacitive load for each bus line Cb - - 400 pF Noise margin at the Low level VnL 0.5 - - V Noise margin at the High level VnH 1 - - V SCL clock frequency Hold time (repeated) START condition. Set-up time for a repeated START condition Data hold time NOTE) Data set-up time Set-up time for STOP condition Cb ; total capacitance of one bus line in pF. NOTE). Data hold time : tHD:DAT Please hold the Data Hold Time (tHD:DAT) to 300ns or more to avoid status of unstable at SCL falling edge. The SDA block in the NJW1321 NJW1321 does not hold data. Add external data-delay-circuit of the SDA terminal, in case of not providing a hold time of at least 300nsec for the SDA in the master device. The time-consists of the data-delay-circuit of the SDA terminal are as follows. (a) Low level (b) High level High level: TLH RP*CD Low level: THL RD*CD In addition, Schottky barrier diode (SBD) influences a Low level at the Acknowledge. Therefore choose the low forward voltage (Vf) as much as possible. VDD RP RP SCL MASTER SBD SDA RD NJW1321 NJW1321 CD -5- NJW1321 NJW1321 EQUIVALENT CIRCUIT PIN No. NAME 6 8 10 48 2 4 42 44 46 36 38 40 Y IN1 Pb IN1 Pr IN1 Y IN2 Pb IN2 Pr IN2 Y IN3 Pb IN3 Pr IN3 Y IN4 Pb IN4 Pr IN4 FUNCTION INSIDE EQUIVALENT CIRCUIT V+ V+ V+ 150k Y,Pb,Pr Input RGB Input 100 V+ 34 32 30 27 24 21 Y OUT1 Pb OUT1 Pr OUT1 Y OUT2 Pb OUT2 Pr OUT2 VOLTAGE 4.4V V+ Y,Pb,Pr Output RGB Output 3.7V 50 V+ 23 22 13 12 PORT0 PORT1 PORT2 PORT3 V+ Logic input terminal 66 100k V+ V+ V+ 1k 25 26 28 29 -6- AUX0 AUX1 AUX2 AUX3 Auxiliary 3 values voltage output terminal 66 0V 1.9V 5.0V NJW1321 NJW1321 PIN No. NAME FUNCTION INSIDE EQUIVALENT CIRCUIT V+ 14 ADR V+ VOLTAGE VREF Slave address setting terminal 66 15 16 SCL SDA I2C clock terminal I2C data terminal V+ 19 VREF Reference voltage terminal - 4k V+ V+ 66 4.8V 48k 1 7 9 20 35 37 41 45 V+ Supply voltage terminal - 3 5 11 17 31 33 39 43 47 GND Ground terminal - 18 DGND Ground terminal - -7- NJW1321 NJW1321 DEFINITION OF I2C REGISTER I2C BUS FORMAT MSB S LSB Slave Address 1bit MSB LSB A Data 1bit 8bit 8bit MSB A LSB Data A 8bit 1bit 1bit P 1bit S: Starting Term A: Acknowledge Bit P: Ending Term SLAVE ADDRESS R/W: Set the Write Mode or Read Mode. ADR : Set the Slave Address by "ADR" terminal. Slave Address Hex MSB 1 LSB 0 0 - 0 0 0 ADR R/W - R/W = 0 : Write Mode, ADR = 0/1 - 1 0 0 1 0 1 0 0 94(h) 1 0 0 1 0 1 1 0 96(h) R/W = 1 : Read Mode, ADR = 0/1 - 1 0 0 1 0 1 0 1 95(h) 1 0 0 1 0 1 1 1 97(h) CONTROL REGISTER TABLE < Write Mode > No. Data1 BIT D7 D6 PS1 D4 PS2 Data2 D5 D3 D2 OUT1 AUX0 D1 D0 OUT2 AUX1 AUX2 AUX3 < Read Mode > No. BIT D7 D6 D4 D5 PORT0 Data D3 PORT1 D2 D1 PORT2 D0 PORT3 CONTROL REGISTER DEFAULT VALUE Control register default value is all "0". No. Data1 Data2 -8- BIT D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NJW1321 NJW1321 INSTRUCTION CODE POWER SAVE, OUTPUT SETTING No. Data1 BIT D7 D6 PS1 D4 D5 PS2 D3 D2 OUT1 D1 D0 OUT2 ·PS1, PS2: Power Save Setting Power Save OUT1 ON OUT2 ON OUT1 ON OUT2 OFF OUT1 OFF OUT2 ON OUT1 OFF OUT2 OFF D7 0 0 1 1 D6 0 1 0 1 ON: Power Save OFF, OFF: Power Save ON (Mute) ·OUT1: Output 1 Setting YIN1 YIN2 YIN3 YIN4 Output 1 PbIN1 PbIN2 PbIN3 PbIN4 PrIN1 PrIN2 PrIN3 PrIN4 D5 0 0 1 1 D4 0 1 0 1 Gain 6dB 0dB D3 0 1 D2 0 0 1 1 D1 0 1 0 1 Gain 6dB 0dB D0 0 1 ·OUT2: Output 2 Setting YIN1 YIN2 YIN3 YIN4 Output 2 PbIN1 PbIN2 PbIN3 PbIN4 PrIN1 PrIN2 PrIN3 PrIN4 -9- NJW1321 NJW1321 AUX: AUXILIARY SETTING No. BIT D7 Data2 D6 D4 D5 AUX0 D3 AUX1 AUX0 L M H D7 0 0 1 D5 0 0 1 D3 0 0 1 D1 0 0 1 AUX3 D2 0 1 1 AUX3 L M H AUX2 D0 D4 0 1 1 AUX2 L M H D1 D6 0 1 1 AUX1 L M H D2 D0 0 1 1 PORT: PORT SETTING No. Data BIT D7 D6 PORT0 PORT1 PORT0 OPEN L M H D7 0 0 0 1 D6 0 0 1 1 PORT1 OPEN L M H D5 0 0 0 1 D4 0 0 1 1 PORT2 OPEN L M H D3 0 0 0 1 D2 0 0 1 1 PORT3 OPEN L M H - 10 - D4 D5 D1 0 0 0 1 D0 0 0 1 1 D3 D2 PORT2 D1 D0 PORT3 NJW1321 NJW1321 TEST CIRCUIT Pb IN4 Y IN4 50/75 1µF + 0.1µF 38 39 Pr OUT1 AUX3 AUX2 Y OUT2 AUX1 10k 50/75 1µF + Pb OUT1 Y OUT1 10µF + 10k 10k 0.1µF 10µF + 0.1µF 10k 10µF + 0.1µF 10k 10k AUX0 10k 10k 10µF + 0.1µF 0.1µF 37 36 35 34 33 32 31 30 29 28 27 26 25 24 + 10µF 0.1µF Pr IN4 10k + Y IN3 50/75 40 23 PORT0 41 50/75 22 PORT1 42 21 0.1µF 1µF + + NJW1320 NJW1320 NJW1321 NJW1321 1µF + 10µF 0.1µF 0.1µF 43 Pb IN3 + 50/75 Y IN2 44 19 18 46 17 47 Pr IN3 16 SDA 15 14 SCL 1µF 0.1µF 1µF + 0.1µF 1µF + 48 1 50/75 Pr OUT2 10k 20 45 50/75 Pb OUT2 1µF 2 3 4 5 6 7 8 9 10 11 12 13 0.1µF + + 1µF 0.1µF Pb IN2 V+ 50/75 + 1µF 0.1µF Pr IN2 50/75 + + 1µF 0.1µF Y IN1 50/75 1µF 1µF 0.1µF 0.1µF Pb IN1 50/75 PORT3 PORT2 ADR Pr IN1 50/75 + 100µF 0.1µF - 11 - NJW1321 NJW1321 APPLICATION CIRCUIT Pb IN4 Y IN4 75 Pb OUT1 Y OUT1 Pr OUT1 AUX3 AUX2 Y OUT2 AUX1 75 10k 1µF + 1µF + 0.1µF 38 39 AUX0 10µF + 10µF + 0.1µF 0.1µF 10k 10k 10k 10µF + 0.1µF 10µF + 0.1µF 0.1µF 37 36 35 34 33 32 31 30 29 28 27 26 25 24 + 10µF 0.1µF Pr IN4 + Y IN3 75 40 23 PORT0 41 75 22 PORT1 42 21 0.1µF 1µF + + 0.1µF NJW1320 NJW1320 NJW1321 NJW1321 1µF + 10µF 0.1µF 43 Pb IN3 + 75 Y IN2 75 44 19 18 46 17 47 Pr IN3 Pr OUT2 20 45 75 Pb OUT2 1µF 16 SDA 15 14 SCL 1µF 0.1µF 1µF + 0.1µF 1µF + 48 1 2 3 4 5 6 7 8 9 10 11 12 13 0.1µF + 1µF Pb IN2 + 0.1µF 75 1µF Pr IN2 + 0.1µF 75 1µF Y IN1 + + 0.1µF 75 1µF Pb IN1 1µF 0.1µF 75 Pr IN1 0.1µF PORT3 PORT2 ADR 75 V+ + 100µF 0.1µF UNUSED PIN CONNECTION Function Pin No. Video signal input 2, 4, 6, 8, 10, 36, 38, 40, 42, 44, 46, 48 Video signal output 21, 24, 27, 30, 32, 34 PORT 12, 13, 22, 23 AUX 25, 26, 28, 29 - 12 - Pin connection Connect to GND with capacitor of 0.1uF OPEN OPEN OPEN NJW1321 NJW1321 TYPICAL CHARACTERISTICS Voltege Gain vs. Frequency 10 0 Gv[dB] -10 -20 -30 0dB 6dB -40 106 107 108 Frequency[Hz] NOTE Please all connect V+ terminal and GND terminal. When the power supply voltage is not impressing, please do not impress voltage to the ADR terminal. [CAUTION] The specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. The application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights. - 13 -