NB4N111K QFN32 488AM AND8002/D NB4N111K/D EIA/JESD78 AND8003/D NB4N111KMNG

3.3V Differential In 1:10 Differential Fanout Clock Driver with HCSL Level Output http://onsemi.com Description The NB4N111K is a

NB4N111K NB4N111K 3.3V Differential In 1:10 Differential Fanout Clock Driver with HCSL Level Output http://onsemi.com Description The NB4N111K NB4N111K is a differential input clock 1 to 10 HCSL fanout buffer, optimized for ultra low propagation delay variation. The NB4N111K NB4N111K is designed with HCSL clock distribution for FBDIMM applications in mind. Inputs can accept differential LVPECL, CML, or LVDS levels. Single-ended LVPECL, CML, LVCMOS or LVTTL levels are accepted with the proper VREFAC supply (see Figures 5, 10, 11, 12, and 13). Clock input pins incorporate an internal 50 W on die termination resistors. Outputs can interface with LVDS with proper termination (See Figure 15). The NB4N111K NB4N111K specifically guarantees low outputtooutput skews. Optimal design, layout, and processing minimize skew within a device and from device to device. System designers can take advantage of the NB4N111K NB4N111K's performance to distribute low skew clocks across the backplane or the motherboard. 1 32 1 NB4N 111K AWLYYWWG A WL YY WW G · Typical Input Clock Frequencies: 100, 133, 166, 200, 266, 333, and 400 MHz · · · · Differential Pair 2 kV QFN32 QFN32 Flammability Rating Oxygen Index: 28 to 34 Level 1 UL 94 V-0 @ 0.125 in Transistor Count 622 Meets or exceeds JEDEC Spec EIA/JESD78 EIA/JESD78 IC Latchup Test 2. For additional information, see Application Note AND8003/D AND8003/D. Table 3. MAXIMUM RATINGS (Note 3) Parameter Symbol Condition 1 Condition 2 Rating Unit VCC Positive Power Supply GND = 0 V 6.0 V VI Positive Input GND = 0 V GND - 0.3 v VI v VCC V VINPP Differential Input Voltage IOUT Output Current Continuous Surge TA Operating Temperature Range QFN32 QFN32 Tstg Storage Temperature Range qJA Thermal Resistance (Junction-to-Ambient) (Note 3) 0 lfpm 500 lfpm QFN32 QFN32 QFN32 QFN32 qJC Thermal Resistance (Junction-to-Case) 2S2P (Note 4) QFN32 QFN32 Tsol Wave Solder |CLK - CLK| VCC V 50 100 mA mA °C °C 31 27 °C/W °C/W 12 °C/W 265 Pb-Free -40 to +70 -65 to +150 °C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 3. JEDEC standard 51-6, multilayer board - 2S2P (2 signal, 2 power). 4. JEDEC standard multilayer board - 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad. http://onsemi.com 3 NB4N111K NB4N111K Table 4. DC CHARACTERISTICS (VCC = 3.0 V to 3.6 V, TA = -40°C to +70°C Note 5) Symbol Characteristic IGND ICC Unit 120 mA 300 Input LOW Current CLKx, CLKx Max 98 mA 150 mA Input HIGH Current CLKx, CLKx IIL Typ 70 Power Supply Current (All Outputs Loaded) IIH Min GND Supply Current (All Outputs Loaded) 2.0 -150 -2.0 mA DIFFERENTIAL INPUT DRIVEN SINGLE-ENDED (Figures 5 and 7) Vth Input Threshold Reference Voltage Range (Note 6) 1050 VCC - 150 mV VIH Single-Ended Input HIGH Voltage Vth + 150 VCC mV VIL Single-Ended Input LOW Voltage GND Vth - 150 mV DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (Figures 6 and 8) VIHD Differential Input HIGH Voltage 1200 VCC mV VILD Differential Input LOW Voltage GND VCC - 75 mV VID Differential Input Voltage (VIHD - VILD) 75 2400 mV VCMR Input Common Mode Range 1163 VCC - 75 HCSL OUTPUTS (Figure 4) VOH Output HIGH Voltage 600 740 900 mV VOL Output LOW Voltage -150 0 150 mV NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 5. Input parameters vary 1:1 with VCC. Measurements taken with all outputs loaded 50 W to GND, see Figure 9. 6. Vth is applied to the complementary input when operating in single ended mode. http://onsemi.com 4 NB4N111K NB4N111K Table 5. AC CHARACTERISTICS VCC = 3.0 V to 3.6 V, GND = 0 V; -40°C to +70°C (Note 7) Symbol Characteristic Typ Max Unit 725 1000 mV 800 1100 ps Propagation Delay Variations Variation Per Each Diff Pair CLK/CLK to Qx/Qx (Note 8) (See Figure 3) 100 ps tSKEW Duty Cycle Skew (Note 9) Within-Device Skew Device-to-Device Skew (Note 10) 20 100 150 ps ps ps tJITTER RMS Random Clock Jitter (Note 11) 1 ps Vcross Absolute Crossing Magnitude Voltage 550 mV DVcross Variation in Magnitude of Vcross 150 mV tr, tf Absolute Magnitude in Output Risetime and Falltime (From 175 mV to 525 mV) Qx, Qx 700 ps Dtr, Dtf Variation in Magnitude of Risetime and Falltime (Single-Ended) (See Figure 4) Qx, Qx 125 ps VOUTPP tPLH, tPHL Propagation Delay to (See Figure 3) DtPLH, DtPHL Min Output Voltage Amplitude (@ VINPPmin) fin = 400 MHz CLK/CLK to Qx/Qx 550 fin = 400 MHz 250 175 340 NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 7. Measured by forcing VINPP (MIN) from a 50% duty cycle clock source. Measurements taken with all outputs loaded 50 W to GND, see Figure 9. Typical gain is 20 dB. 8. Measured from the input pair crosspoint to each single output pair crosspoint across temp and voltage ranges. 9. Duty cycle skew is measured between differential outputs using the deviations of the sum of Tpw- and Tpw+. 10. Skew is measured between outputs under identical transition @ 400 MHz. 11. Additive RMS jitter with 50% duty cycle clock signal using phase noise integrated from 12 KHz to 33 MHz CLK VINPP = VIH(CLK) - VIL(CLK) = VIH(CLK) - VIL(CLK) CLK tPLH tPHL Q VOUTPP = VOH(Q) - VOL(Q) = VOH(Q) - VOL(Q) Q DtPHL DtPLH Figure 3. AC Reference Measurement http://onsemi.com 5 NB4N111K NB4N111K 525 mV DVCROSS VCROSS 175 mV tr tf Figure 4. HCSL Output Parameter Characteristics CLK CLK CLK CLK Vth Vth Figure 5. Differential Input Driven Single-Ended (Vth = VREFAC) VCC Vthmax Figure 6. Differential Inputs Driven Differentially VCC VCMmax VIHmax VILmax Vth Vthmin GND VIH Vth VIL VCMR VIHDmax VILDmax VID = VIHD - VILD VIHDtyp VILDtyp VIHmin VCMmin VILmin GND Figure 7. Vth Diagram VIHDmin VILDmin Figure 8. VCMR Diagram http://onsemi.com 6 NB4N111K NB4N111K Qx Z0 = 50 W RS1B Receiver HCSL Driver RS2B Z0 = 50 W Qx CL1C 2 pF IREFA CL2C 2 pF RL1 50 RL2 50 A. Connect IREF pin to GND. B. RS1, RS2: 0 W for Test and Evaluation. Select to Minimizing Ringing. C. CL1, CL2: Receiver Input Simulation Load Capacitance Only. Figure 9. Typical Termination Configuration for Output Driver and Device Evaluation CLx for Test Only (Representing Receiver Input Loading); Not Added to Application VCC = 3.3 V VCC = 3.3 V Z0 = 50 W LVPECL Driver VCC = 3.3 V Z0 = 50 W NB4N111K NB4N111K D 50 W* VTCLK LVDS Driver VTCLK Z0 = 50 W 50 W* D NB4N111K NB4N111K D 50 W* VTCLK VTCLK Z0 = 50 W VTCLK = VTCLK = VCC - 2.0 V GND VCC = 3.3 V 50 W* D VTCLK = VTCLK GND GND GND *RTIN, Internal Input Termination Resistor *RTIN, Internal Input Termination Resistor Figure 10. LVPECL Interface Figure 11. LVDS Interface http://onsemi.com 7 NB4N111K NB4N111K VCC VCC Z0 = 50 W VCC VCC NB4N111K NB4N111K D 50 W* Z0 = 50 W VTCLK CML Driver LVCMOS/ LVTTL Driver VTCLK Z0 = 50 W VCC 50 W* D VTCLK VTCLK 50 W* D Vth VTCLK = OPEN VTCLK = OPEN D = Vth VTCLK = VTCLK = VCC GND NB4N111K NB4N111K D 50 W* GND GND *RTIN, Internal Input Termination Resistor *RTIN, Internal Input Termination Resistor Figure 12. Standard 50 W Load CML Interface Figure 13. LVCMOS/LVTTL Interface VCC VDR INTQb INTQ Q Qb Figure 14. HCSL Output Structure HCSL Driver Qx Zo = 50 W 100 W Qx GND 100 W Zo = 50 W RL = 150 W RL = 150 W Figure 15. HCSL Interface Termination to LVDS http://onsemi.com 8 LVDS Receive NB4N111K NB4N111K ORDERING INFORMATION Package Shipping NB4N111KMNG NB4N111KMNG QFN32 QFN32 (Pb-Free) 79 Units / Rail NB4N111KMNR4G NB4N111KMNR4G QFN32 QFN32 (Pb-Free) 1000 / Tape & Reel Device For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D BRD8011/D. http://onsemi.com 9 NB4N111K NB4N111K PACKAGE DIMENSIONS QFN32 QFN32 5x5, 0.5P CASE 488AM-01 488AM-01 ISSUE O A B D 2X ÉÉ ÉÉ PIN ONE LOCATION 0.15 C 2X NOTES: 1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM TERMINAL 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. E DIM A A1 A3 b D D2 E E2 e K L TOP VIEW 0.15 C (A3) 0.10 C A 32 X 0.08 C C L 32 X 9 D2 SEATING PLANE A1 SIDE VIEW SOLDERING FOOTPRINT* 5.30 EXPOSED PAD 16 K 3.20 32 X 17 MILLIMETERS MIN NOM MAX 0.800 0.900 1.000 0.000 0.025 0.050 0.200 REF 0.180 0.250 0.300 5.00 BSC 2.950 3.100 3.250 5.00 BSC 2.950 3.100 3.250 0.500 BSC 0.200 - - 0.300 0.400 0.500 8 32 X 0.63 E2 1 3.20 24 32 25 32 X b 0.10 C A B 5.30 e 32 X 0.05 C 0.28 BOTTOM VIEW 28 X 0.50 PITCH *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. The products described herein (NB4N111k), may be covered by U.S. patents including 6,362,644. There may be other patents pending. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5773-3850 http://onsemi.com 10 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative NB4N111K/D NB4N111K/D