N04S1833F1A N04S3233F1A N04S3633F1A N04S36 N04S32 N04S18 N04S3633F1AQ-11C - Datasheet Archive

 

N04S3233F1A N04S3633F1A NanoAmp Solutions, Inc. 1982 Zanker Road, San Jose, CA 95112 ph: 408-573-8878, FAX: 408-573-8877

 

N04S1833F1A N04S1833F1A N04S3233F1A N04S3233F1A N04S3633F1A N04S3633F1A NanoAmp Solutions, Inc. 1982 Zanker Road, San Jose, CA 95112 ph: 408-573-8878, FAX: 408-573-8877 www.nanoamp.com 4Mb High Speed Synchronous Flow-Thru SRAMs Features · · · · · · · · · · DSPstorage and networking memory. High performance flow-thru operation Cycle times up to 117MHz Access times as fast as 7.5nS Fully synchronous operation Power supply 3.3V +10% and -5% or Separate I/O power supply of 3.3V or 2.5V Individual byte write operation Three chip enable signals Simple depth expansion ZZ mode for low power sleep mode Mode pin for setting interleave or linear burst mode of operation JEDEC standard 100-pin TQFP and 119-ball PBGA packages Functional Description The N04S3633F1A N04S3633F1A, N04S3233F1A N04S3233F1A and N04S1833F1A N04S1833F1A are 4Mb high performance synchronous SRAMs that are part of a family of options for those demanding high performance. The memory devices contain 4Mb of memory cells organized as 131,072 x 36 (N04S3633F1A N04S3633F1A) 131,072 x 32 (N04S3233F1A N04S3233F1A) and 262,144 x 18 (N04S1833F1A N04S1833F1A). The devices operate in a synchronous manner with control signals, addresses and data inputs synchronized and captured at the rising edge of clock for ease of use. An asynchronous OE is available for disabling the outputs at any time. An asynchronous ZZ signal can be used to put the device into sleep mode with all data retained. The devices are fabricated using NanoAmp's advanced CMOS process and high-speed/ ultra low-power circuit technology. Flow-Thru Performance and Power SORT (MHz) 100 tCYCLE 10.0 Unit 117 8.5 nS tACCESS 8.0 7.5 nS Icc 325 350 mA Isb 10 10 mA Options · Organization 128K x 36 128K x 32 256K x 18 · Package 100-pin TQFP 119-ball PBGA · Speed 100MHz 117MHz N04S36 N04S36 N04S32 N04S32 N04S18 N04S18 Q G 10 11 Part number example: N04S3633F1AQ-11C N04S3633F1AQ-11C These 4Mb devices are the type of SRAMs originally developed as L2 cache memories for high performance CPUs. They now can be used in applications ranging from processor caches, FTRAM is a trademark of NanoAmp Solutions, Inc. NoBL is a trademark of Cycpress Semiconductor Corpopation ZBT is a trademark of Integrated Device Technology NtRAM is a trademark of Samsung Electronics Corporation Stock No. 23199-A 11/02 This is an advance datasheet and subject to change without notice. 1 N04S1833F1A N04S1833F1A N04S3233F1A N04S3233F1A N04S3633F1A N04S3633F1A NanoAmp Solutions A A CE1 CE2 BWd BWc BWb BWa CE3 VDD VSS CLK GW BW OE ADSC ADSP ADV A A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 (128K x 32) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 NC DQb DQb VDDQ VSS DQb DQb DQb DQb VSS VDDQ DQb DQb VSS NC VDD ZZ DQa DQa VDDQ VSS DQa DQa DQa DQa VSS VDDQ DQa DQa NC LBO A A A A A1 A0 DNU DNU VSS VDD DNU DNU A A A A A A A NC DQc DQc VDDQ VSS DQc DQc DQc DQc VSS VDDQ DQc DQc NC VDD NC VSS DQd DQd VDDQ VSS DQd DQd DQd DQd VSS VDDQ DQd DQd NC A NC NC VDDQ VSS NC DQaP DQa DQa VSS VDDQ DQa DQa VSS NC VDD ZZ DQa DQa VDDQ VSS DQa DQa NC NC VSS VDDQ NC NC NC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 (256K x 18) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 LBO A A A A A1 A0 DNU DNU VSS VDD DNU DNU A A A A A A A NC NC NC VDDQ VSS NC NC DQb DQb VSS VDDQ DQb DQb NC VDD NC VSS DQb DQb VDDQ VSS DQb DQb DQbP NC VSS VDDQ NC NC NC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 A A CE1 CE2 NC NC BWb BWa CE3 VDD VSS CLK GW BW OE ADSC ADSP ADV A A 100-Pin TQFP Packages Stock No. 23199-A 11/02 This is an advance datasheet and subject to change without notice. 2 N04S1833F1A N04S1833F1A N04S3233F1A N04S3233F1A N04S3633F1A N04S3633F1A NanoAmp Solutions (128K x 36) 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 DQbP DQb DQb VDDQ VSS DQb DQb DQb DQb VSS VDDQ DQb DQb VSS NC VDD ZZ DQa DQa VDDQ VSS DQa DQa DQa DQa VSS VDDQ DQa DQa DQaP LBO A A A A A1 A0 DNU DNU VSS VDD DNU DNU A A A A A A A DQcP DQc DQc VDDQ VSS DQc DQc DQc DQc VSS VDDQ DQc DQc NC VDD NC VSS DQd DQd VDDQ VSS DQd DQd DQd DQd VSS VDDQ DQd DQd DQdP 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 A A CE1 CE2 BWd BWc BWb BWa CE3 VDD VSS CLK GW BW OE ADSC ADSP ADV A A 100-Pin TQFP Packages Stock No. 23199-A 11/02 This is an advance datasheet and subject to change without notice. 3 N04S1833F1A N04S1833F1A N04S3233F1A N04S3233F1A N04S3633F1A N04S3633F1A NanoAmp Solutions 119-Ball PBGA Packages 256K x 18 1 A 2 3 4 5 6 7 VDDQ A A ADSP A A VDDQ B NC CE2 A ADSC A CE3 NC C NC A A VDD A A NC D DQb NC VSS NC VSS DQaP NC E NC DQb VSS CE1 VSS NC DQa F VDDQ NC VSS OE VSS DQa VDDQ G NC DQb BWb ADV VSS NC DQa H DQb NC VSS GW VSS DQa NC J VDDQ VDD NC VDD NC VDD VDDQ K NC DQb VSS CLK VSS NC DQa L DQb NC VSS NC BWa DQa NC M VDDQ DQb VSS BW VSS NC VDDQ N DQb NC VSS A1 VSS DQa NC P NC DQbP VSS A0 VSS NC DQa NC R NC A LBO VDD VSS A T NC A A NC A A ZZ U VDDQ NC NC NC NC NC VDDQ 128K x 32 1 2 3 4 5 6 7 VDDQ A VDDQ A A ADSP A A B NC CE2 A ADSC A CE3 NC C NC A A VDD A A NC D DQc NC VSS NC VSS NC DQb E DQc DQc VSS CE1 VSS DQb DQb F VDDQ DQc VSS OE VSS DQb VDDQ G DQc DQc BWc ADV BWb DQb DQb H DQc DQc VSS GW VSS DQb DQb J VDDQ VDD NC VDD NC VDD VDDQ K DQd DQd VSS CLK VSS DQa DQa L DQd DQd BWd NC BWa DQa DQa M VDDQ DQd VSS BW VSS DQa VDDQ N DQd DQd VSS A1 VSS DQa DQa P DQd NC VSS A0 VSS NC DQa R NC A LBO VDD NC A NC T NC NC A A A NC ZZ U VDDQ NC NC NC NC NC VDDQ 7 x 17 Ball BGA with 1.27 mm Ball Pitch Stock No. 23199-A 11/02 This is an advance datasheet and subject to change without notice. 4 N04S1833F1A N04S1833F1A N04S3233F1A N04S3233F1A N04S3633F1A N04S3633F1A NanoAmp Solutions 119-Ball PBGA Packages 128K x 36 1 A 2 3 4 5 6 7 VDDQ A A ADSP A A VDDQ B NC CE2 A ADSC A CE3 NC C NC A A VDD A A NC D DQc DQcP VSS NC VSS DQbP DQb E DQc DQc VSS CE1 VSS DQb DQb F DQc VSS OE VSS DQb VDDQ DQc DQc BWc ADV BWb DQb DQb H DQc DQc VSS GW VSS DQb DQb J VDDQ VDD NC VDD NC VDD VDDQ K DQd DQd VSS CLK VSS DQa DQa L DQd DQd BWd NC BWa DQa DQa M VDDQ DQd VSS BW VSS DQa VDDQ N DQd DQd VSS A1 VSS DQa DQa P DQd DQdP VSS A0 VSS DQaP DQa R NC A LBO VDD NC A NC T NC NC A A A NC ZZ U Stock No. 23199-A 11/02 VDDQ G VDDQ TMS TDI TCK TDO NC VDDQ This is an advance datasheet and subject to change without notice. 5 N04S1833F1A N04S1833F1A N04S3233F1A N04S3233F1A N04S3633F1A N04S3633F1A NanoAmp Solutions Pin Descriptions Signal Type POWER A0, A1 Synch Input Address inputs sampled at the rising edge of CLK. Least significant address bits are used to set the internal burst counter (if used). Ax Synch Input Address inputs 2 through 16/17, sampled at the rising edge of CLK. LBO Synch Input Linear burst order, active low, used for setting the address order of the burst counter. A low selects linear burst order while a high selects interleave burst order and if floating, this input will default to a high (interleave order) This should not be changed while operating the SRAM. ADV Synch Input Advance, sampled at the rising edge of clock. When asserted low, automatically increments the internal burst counter. ADSP Synch Input Address strobe from processor, sampled at the rising edge of clock. When asserted low, all addresses are captured. ADSP is ignored if CE1 is high. ADSC Synch Input Address strobe from controller, sampled at the rising edge of clock. When asserted low, all addresses are captured. BWa BWb BWc BWd Synch Input Byte writes, active low, sampled at the rising edge of CLK if WE is low for a write cycle. BWa controls byte a (DQa) inputs, BWb controls byte b (DQb) inputs, BWc controls byte c (DQc) inputs and BWd controls byte d (DQd) inputs. For x18 devices, only BWa and BWb apply. BW Synch Input Byte write enable, active low, sampled at the rising edge of CLK. A low state initiates a byte write. GW Synch Input Global write enable, active low, sampled at the rising edge of CLK. A low state writes to all bytes regardless of BWx and BW. CLK Clock Input Clock CE1 Synch Input Chip enable 1, active low, sampled on the rising edge of CLK. Used with CE2 and CE3 and to select the device. If inactive, ADSP is ignored. CE2 Synch Input Chip enable 2, active high, sampled on the rising edge of CLK. Used with CE1 and CE3 and to select the device. CE3 Synch Input Chip enable 3, active low, sampled on the rising edge of CLK. Used with CE2 and CE1 and to select the device. OE Asynch Input Output enable, asynchronous active low, tri-states the output buffers when high and enables the output buffers when low. ZZ Asynch Input Sleep mode, asynchronous active high, puts the device in a low power sleep mode that retains all data while high. Defaults to an inactive low state. DQa DQb DQc DQd Synch Input/ Output During a write cycle, the data lines are synchronous inputs that are sampled at the rising edge of CLK to specify data to be written to the memory array. During a read cycle, the data lines are driven out with data from the SRAM array. DQ(a, b, c, d) refer to the bytes a, b, c, d. For x18 devices, only DQa and DQb apply. VDD Power Supply Supplies power to the device core. VDDQ I/O Power Supply Supplies power to the I/O section of the device. VSS Ground supply Ground NC - No connect Stock No. 23199-A 11/02 This is an advance datasheet and subject to change without notice. 6 N04S1833F1A N04S1833F1A N04S3233F1A N04S3233F1A N04S3633F1A N04S3633F1A NanoAmp Solutions Functional Truth Table 1, 5, 7 Operation Address CE1 CE2 CE3 DESELECT NA H X DESELECT NA L L DESELECT NA L X H DESELECT NA L L X DESELECT NA L X READ, begin burst Ext L H READ, begin burst Ext L READ, continue burst Int X READ, continue burst Int READ, suspend burst READ, suspend burst ADSC W2 OE ZZ CLK3 DQ6 ADV ADSP Notes X X X L X X L L-H High-Z X X L X X X L L-H High-Z X L X X X L L-H High-Z X X L X X L L-H High-Z H X X L X X L L-H High-Z L X L X X L L L-H Data-out H L X H L H L L L-H Data-out X X L H H H L L L-H Data-out 4, 7 H X X L X H H L L L-H Data-out 4, 7 Current X X X H H H H L L L-H Data-out Current H X X H X H H L L L-H Data-out WRITE, begin burst Ext L H L X H L L X L L-H Data-in WRITE, continue burst Int X X X L H H L X L L-H Data-in 4, 7 WRITE, continue burst Int H X X L X H L X L L-H Data-in 4, 7 WRITE, suspend burst Current X X X H H H L X L L-H Data-in WRITE suspend burst Current H X X H X H L X L L-H Data-in NA X X X X X X X X H X High-Z Deep Sleep Notes: 1. X = don't care; H = logic HIGH; L = logic LOW. 2. W = L means write cycle per Write Truth Table below. W = H means read cycle. 3. L-H refers to the CLK edge transitioning from a low to a high state. 4. All continue burst cycles use the same control inputs. The type of cycle is chosen in the first cycle prior to the continue cycle. 5. All inputs except OE and ZZ must meet set-up and hold times. 6. All outputs will remain in high-Z during power-up. 7. A 2-bit burst counter is included which is incremented for all continue burst cycles. The address wraps around every fourth burst cycle. Write Truth Table 1, 2 Function READ BW Ba Bb Bc Bd H READ GW H X X X X H L H H H H 3 H L L H H H WRITE byte b 3 H L H L H H WRITE byte c 3 H L H H L H WRITE byte d 3 H L H H H L WRITE all bytes H L L L L L WRITE all bytes L X X X X X WRITE byte a Notes: 1. This represents the x36 device. For the x18 device, only BWa and BWb are used. 2. X = don't care; H = logic HIGH; L = logic LOW. 3. Multiple bytes may be exercised during a cycle. Stock No. 23199-A 11/02 This is an advance datasheet and subject to change without notice. 7 N04S1833F1A N04S1833F1A N04S3233F1A N04S3233F1A N04S3633F1A N04S3633F1A NanoAmp Solutions Burst Order Tables Interleave Starting digits Starting digits Starting digits Starting digits LBO = High A1 A1 A1 A1 First address A0 A0 A0 A0 0 0 0 1 1 0 1 1 Second address 0 1 0 0 1 1 1 0 Third address 1 0 1 1 0 0 0 1 Fourth address 1 1 1 0 0 1 0 0 Linear Starting digits First address Starting digits Starting digits A1 LBO = Low Starting digits A1 A1 A1 A0 A0 A0 A0 0 0 0 1 1 0 1 1 Second address 0 1 1 0 1 1 0 0 Third address 1 0 1 1 0 0 0 1 Fourth address 1 1 0 0 0 1 1 0 Note: At the end of a burst of four, the burst counter wraps to the starting address and continues. Stock No. 23199-A 11/02 This is an advance datasheet and subject to change without notice. 8 N04S1833F1A N04S1833F1A N04S3233F1A N04S3233F1A N04S3633F1A N04S3633F1A NanoAmp Solutions Functional Block Diagram LBO A0 A16(17) A0-A1 17(18) ADV ADSP ADSC CLK Address Register Control Logic CE1 CE2 CE3 BW GW Bx Burst Logic A'0-A'1 128K x 36 (256K x 18) Memory Array 17(18) 15(16) K 36/32(18) K C o n t r o l R e g i s t e r Data-in Register Write Control Logic 36/32(18) OE ZZ DQ0 DQ35/31 DQ35/31(17) Stock No. 23199-A 11/02 36/32(18) This is an advance datasheet and subject to change without notice. Output Buffers 9 N04S1833F1A N04S1833F1A N04S3233F1A N04S3233F1A N04S3633F1A N04S3633F1A NanoAmp Solutions Read and Write State Diagram D B Deselect W R R D D R Begin Read Begin Write W W B R B B D Burst Read D W R W Burst Write B Key: State diagram shows current state and transitions to possible next states. D = Deselect R = Read W = Write B = Burst (read, write or deselect) Stock No. 23199-A 11/02 This is an advance datasheet and subject to change without notice. 10 N04S1833F1A N04S1833F1A N04S3233F1A N04S3233F1A N04S3633F1A N04S3633F1A NanoAmp Solutions Functional Operation The N04S1833F1A N04S1833F1A and N04S3633F1A N04S3633F1A are developed for high performance applications such as level 2 caches, DSP main storage and networking memory. Devices are available for both pipeline and flow-through modes of operation depending on the particular system needs. All inputs except OE, LBO and ZZ are synchronized and registered by the rising edges of the clock (CLK). Three chip enables are available for depth expansion with CE1 and CE3 being active low and CE2 active high. The address inputs are latched and used as the location in memory to start a memory cycle . Output enable (OE), linear burst mode (LBO) and sleep mode (ZZ) are asynchronous signals that control other aspects of the device. OE is used to disable the output buffers at any time. LBO is either tied high for interleave burst order or low for linear burst order. ZZ is used to put the device in a low power sleep mode, while all data is retained in the SRAM memory array. For a burst cycle to start, all three chip enables must be active. Read operations are started with CE1, CE3 and ADSP being asserted low at the rising edge of CLK along with CE2 being asserted high. ADSC can also be used to initiate the read cycle. In this case, CE1, CE3 and ADSC are asserted low at the rising edge of CLK along with CE2 and ADSP being asserted high and the write controls (GW, BW, Bx) in a read operation configuration. If OE is active low, data will be present at the data outputs at tCQ the clock rises. The BW and Bx must be setup active low for whichever bytes will be written too. Burst Operation Burst cycles are continued with ADV being asserted low at the rising edge of CLK while ADSP and ADSC are high. In this operation, the internal burst counter is incremented and an internal address is used to access the SRAM array. The burst counter is a four bit counter and can be incremented in two orders, interleave and linear. The burst counter wraps around after four addresses and continues to operate as long as burst commands are valid and valid CLK cycles are performed. .Sleep Mode Sleep mode is a low power mode that allows the device to continue to retain data in a power down mode. ZZ is asserted high to enter sleep mode and after two clock cycles, the operating current will be reduced to ISL. Since ZZ is an asynchronous operation, sleep mode should not be started until all operations are completed. ZZ should be asserted low for normal operation. The input will default to a low if left floating. Write Operation Write operations are started with CE1, CE3 and ADSC being asserted low at the rising edge of CLK along with CE2 and ADSP being asserted high and the write controls (GW, BW, Bx) in a write operation configuration. Address and data-in must be setup at this first clock edge. Another way to start a write operation is with ADSP. In this case, CE1, CE3 and ADSP must be asserted low at the rising edge of CLK along with CE2 and ADSC being asserted high. Here, the write controls do not matter until the next clock edge. At the following rising edge of CLK, write controls must be active, ADV must be asserted high and the data-in must be setup. For write controls, GW asserted low will write to all bytes regardless of the byte write control inputs. If GW is high, then BW and Bx will control which bytes of data get written to the SRAM. For a write cycle, all the necessary control signals must be setup at the rising edge of CLK as stated above. Stock No. 23199-A 11/02 This is an advance datasheet and subject to change without notice. 11 N04S1833F1A N04S1833F1A N04S3233F1A N04S3233F1A N04S3633F1A N04S3633F1A NanoAmp Solutions Absolute Maximum Ratings Symbol Description Value Unit VDD Voltage on any VDD pin wrt Ground -0.5 to 4.6 V VIN1 Voltage on any input pin -0.5 to VDDQ +0.5V V VI/O1 Voltage on any DQ pin -0.5 to VDDQ +0.5V V TBIAS Temperature under bias -55 to 125 o TSTOR Storage temperature -65 to150 oC IOUT Current into output circuit 20 mA ESD Static Discharge Voltage > 1500 V ILatch Latch-Up Current > 200 mA C .1) Minimum voltage must not exceed -2V for pulse widths of < 20% tCYC. Pin Capacitance1 Item Symbol Input Capacitance Cin Clock Capacitance Cclk Input/Output Cpacitance Ci/o Conditions 25oC, Ta = VDD = Typ, f = 1MHz Max Unit 4 pF 4 pF 4 pF 1) Not 100% tested. Stock No. 23199-A 11/02 This is an advance datasheet and subject to change without notice. 12 N04S1833F1A N04S1833F1A N04S3233F1A N04S3233F1A N04S3633F1A N04S3633F1A NanoAmp Solutions Operating Conditions and DC Characteristics 1 Over the operating range. All voltages referenced to ground (Vss). Min Typ4 Max Unit VDD 3.135 3.3 3.6 V I/O Supply Voltage VDDQ 2.375 2.5 VDD V Input High Voltage VIH V Iteml Conditions Supply Voltage 2.0 VDD + 0.3 w/ 2.5V VDDQ 1.7 VDD + 0.3 w/ 3.3V VDDQ ­0.3 0.8 w/ 2.5V VDDQ ­0.3 0.7 w/ 3.3V VDDQ, IOH = -4.0mA 2.4 w/ 2.5V VDDQ, IOH = -2.0mA Input Low Voltage w/ 3.3V VDDQ 2.0 VIL Output High Voltage5 VOH Output Low Voltage Operating Current2, 3 VOL V IDD w/ 3.3V VDDQ, IOL = 8.0mA 0.4 w/ 2.5V VDDQ, IOL = 2.0mA 5 V 0.7 Device selected; All inputs < VIL or > VIH; Frequency = 1/Tcyc (MIN); Outputs open - 10 325 - 11 V 350 mA Deselect Current Standby (CMOS)3 ISB1 Device deselected; All inputs static and < 0.3V or > VDDQ-0.3, Frequency = 0 All 10 mA Device Current Standby (TTL)3 ISB2 Device deselected; All inputs static and < VIL or > VIH, Frequency = 0 All 30 mA Deselect Current Clock running (CMOS)3 ISB3 Device deselected; All inputs < 0.3V or > VDD0.3;Frequency = 1/Tcyc - 10 85 mA - 11 95 Deselect Current Clock running (TTL)3 ISB4 Device deselected; All inputs static and < VIL or > VIH, Frequency = 1/Tcyc - 10 110 - 11 125 mA 1) Currents are specified for VDD = VDD max. 2) Does not include output currents. 3) Device selected refers to a device in the active mode. Device deselected refers to a device as defined in the truth table. 4) Typical values measured at VDD TYP and 25oC. 5) Output load B used. Stock No. 23199-A 11/02 This is an advance datasheet and subject to change without notice. 13 N04S1833F1A N04S1833F1A N04S3233F1A N04S3233F1A N04S3633F1A N04S3633F1A NanoAmp Solutions Leakage Currents Item Symbol Conditions Min Max Units Notes ILI1 0V < VIN < VDD -5.0 5.0 µA 1 -30.0 30.0 ILO Outputs disabled 0V < VIN < VDDQ -5.0 5.0 Input Leakage Current Input Leakage Current of LBO and ZZ pins Output Leakage Current µA 1. LBO and ZZ inputs: ILI = +/- 30µA due to internal resistors for floating conditions. AC Test Conditions Item Value Input Pulse Level 0V to 2.5V Input Rise and Fall Time 1.0V/nS (10% to 90%) Input Timing Reference Level VDD/2 Output Timing Reference Level VDDQ/2 Output Load See diagram below VDDQ 50 R2 VLOAD DQ Z0 = 50 DQ 30 pF * 5 pF R1 Output Load A Output Load B * Includes Jig Capacitance AC Output Load VCCQ Component 3.3V Unit 2.5V VLOAD 1.5 1.25 V R1 351 1538 R2 317 1667 Stock No. 23199-A 11/02 This is an advance datasheet and subject to change without notice. 14 N04S1833F1A N04S1833F1A N04S3233F1A N04S3233F1A N04S3633F1A N04S3633F1A NanoAmp Solutions AC Timing Characteristics -11 Parameter Symbol Min -10 Max Min Max Unit CLOCK TIMINGS Clock Cycle Time tCYC 8.5 10 nS Clock High Pulse Width tCH 3.0 4.0 nS Clock Low Pulse Width tCL 3.0 4.0 nS Clock Frequency FMAX 117 100 MHz Clock high to output valid tCQ 7.5 8.0 nS Output hold from clock high tOH 2.0 2.0 nS Clock to output in low-Z1 tCLZ 0 0 nS Clock to output in high-Z1 tCHZ 3.5 3.5 nS OE low to output valid ttOE 3.5 3.5 nS OE low to output in low-Z1 tOLZ OE high to output in high-Z1 tOHZ OUTPUT TIMINGS 0 0 3.5 nS 3.5 nS SETUP AND HOLD TIMES Setup Time tS 2.0 2.0 nS Hold Time tH 0.5 0.5 nS 1) tCLZ, tCHZ, tOLZ, tOHZ are specified with output load B. Stock No. 23199-A 11/02 This is an advance datasheet and subject to change without notice. 15 Stock No. 23199-A 11/02 This is an advance datasheet and subject to change without notice. DQ OE CE2, CE3 CE1 ADDRESS WRITE ADV ADSC ADSP CLK tH tOLZ tS tH tH Q(A1) tOE tS tS tOHZ tCYC tS tH A2 tCH tCQ tH Q(A2) tS tCL Q(A2+1) tOH Q(A2+2) Q(A2+3) A3 Q(A3) Q(A3+1) Q(A3+2) Notes: 1. Q(A1) represents the first data accessed from address A1 in the SRAM and Q(A2) represents the first data accessed from address A2. Q(A2+1) represents the second bit accessed within the burst of address A2. 2. CE2, CE3 = L means active, CE3 = L and CE2 = H. CE2, CE3 = H means inactive, CE3 = H or CE2 = L. 3. WRITE = L means write cycle defined by Writh Truth Table. WRITE = H means read cycle. tH tH A1 tS tS Undefined Don't Care Q(A3+3) tCHZ NanoAmp Solutions N04S1833F1A N04S1833F1A N04S3233F1A N04S3233F1A N04S3633F1A N04S3633F1A Timing Waveforms for READ Cycles 16 Stock No. 23199-A 11/02 This is an advance datasheet and subject to change without notice. DQ OE CE2, CE3 CE1 ADDRESS WRITE ADV ADSC ADSP CLK tH tS tH tH D(A1) tS tS tS tCYC tS tH A2 tCH tH tH D(A2) tS tCL D(A2+1) D(A2+2) D(A2+3) D(A3 A3 Notes: 1. D(A1) represents the data to be written to address A1 in the SRAM and D(A2) represents the data to be written to address A2. D(A2+1) represents the second bit to be written to address A2+1 during the burst. 2. CE2, CE3 = L means active, CE3 = L and CE2 = H. CE2, CE3 = H means inactive, CE3 = H or CE2 = L. tH tH A1 tS tS Undefined Don't Care NanoAmp Solutions N04S1833F1A N04S1833F1A N04S3233F1A N04S3233F1A N04S3633F1A N04S3633F1A Timing Waveforms for WRITE Cycles 17 Stock No. 23199-A 11/02 This is an advance datasheet and subject to change without notice. DQ OE CE2, CE3 CE1 ADDRESS WRITE ADV ADSC ADSP CLK tH tOLZ tS tH tH Q(A1) tOE tS tS tOHZ tCYC tS tH A2 tCH tH D(A2) tS tCL A3 tCQ Q(A3) tOH Q(A3+1) Q(A3+2) Q(A3+3 Notes: 1. Q(A1) represents the data accessed from address A1 in the SRAM. D(A2) represents data written to address A2 in the SRAM. 2. CE2, CE3 = L means active, CE3 = L and CE2 = H. CE2, CE3 = H means inactive, CE3 = H or CE2 = L. 3. WRITE = L means write cycle from Write Truth Table. tH tH A1 tS tS Undefined Don't Care NanoAmp Solutions N04S1833F1A N04S1833F1A N04S3233F1A N04S3233F1A N04S3633F1A N04S3633F1A Timing Waveforms for Combined READ/WRITE Cycles 18 N04S1833F1A N04S1833F1A N04S3233F1A N04S3233F1A N04S3633F1A N04S3633F1A NanoAmp Solutions Timing Waveforms Sleep Mode CLK tZZ tRZZ ZZ tZZI Normal operations tRZZI Other Inputs Deselect Read or Deselect High-Z DQ ISL ICC Don't Care Sleep Mode Characteristics Item Symbol Conditions ZZ active to input ignored tZZ ZZ > VDD - 0.2V ZZ inactive to input sampled tRZZ ZZ < 0.2V ZZ active to sleep current tZZI ZZ > VDD - 0.2V ZZ inactive to exit sleep current tRZZI ZZ < 0.2V Sleep mode power supply current Stock No. 23199-A 11/02 Min Max Units 2 cycles 2 cycles 2 2 ISL This is an advance datasheet and subject to change without notice. Notes cycles cycles 20 mA 19 N04S1833F1A N04S1833F1A N04S3233F1A N04S3233F1A N04S3633F1A N04S3633F1A NanoAmp Solutions 100-Pin TQFP Package Dimensions E A A1 Pin 1 B1 B C D F H G All dimensions in mm Min Nom Max A Symbol Overall Width Description 15.80 16.00 16.20 A1 Width 13.90 14.00 14.10 B Overall Length 21.80 22.00 22.20 B1 Length 19.90 20.00 20.10 C Pin Pitch D Lead Width 0.22 0.30 0.38 E Package Height 1.35 1.40 1.45 F Standoff 0.05 G Lead Extension H Lead Bend Length Stock No. 23199-A 11/02 Notes 0.65 0.15 1.00 0.45 0.60 0.75 This is an advance datasheet and subject to change without notice. 20 N04S1833F1A N04S1833F1A N04S3233F1A N04S3233F1A N04S3633F1A N04S3633F1A NanoAmp Solutions 119-Ball BGA Package Dimensions E A D Pin A1 E B TOP VIEW BOTTOM VIEW C F SIDE VIEW All Dimensions in mm Symbol Description Min Nom Max A Package Width 13.80 14.00 14.20 B Package Length 21.80 22.00 22.20 C Package Height D Ball Width 0.75 0.80 E Ball Pitch F Ball Height Stock No. 23199-A 11/02 2.40 0.70 1.27 0.60 0.65 0.70 This is an advance datasheet and subject to change without notice. 21 N04S1833F1A N04S1833F1A N04S3233F1A N04S3233F1A N04S3633F1A N04S3633F1A NanoAmp Solutions Ordering Information N04SXX N04SXX 33 F1AX-XX X C = Commercial, 0°C to 70°C Temperature I = Industrial, -40°C to 85°C Performance Package Type I/O Width 10 = 100 MHz 11 = 117 MHz Q = 100-pin TQFP G = 119-ball PBGA 18 = x18 32 = x32 36 = x36 Note: Add -T&R following the part number for Tape and Reel. Orders will be considered in tray if not noted. Revision History Revision # A Date Change Description November 2002 Stock No. 23199-A 11/02 Initial Release This is an advance datasheet and subject to change without notice. 22