N04N1833F1A N04N3633F1A N04N1825F1A N04N36 N04N18 N04N3633F1AQ-11C N04NXX - Datasheet Archive

 

N04N3633F1A Advance Information NanoAmp Solutions, Inc. 1982 Zanker Road, San Jose, CA 95112 ph: 408-573-8878, FAX: 408-573-8877

 

N04N1833F1A N04N1833F1A N04N3633F1A N04N3633F1A Advance Information NanoAmp Solutions, Inc. 1982 Zanker Road, San Jose, CA 95112 ph: 408-573-8878, FAX: 408-573-8877 www.nanoamp.com 4Mb High Speed Synchronous Flow-Thru SRAMs with Fast bus Turnaround FTRAMTM Architecture Features · · · · · · · · · · · the SRAM. High performance flow-thru operation Cycle times up to 117MHz Access times as fast as 7.5nS Fully compatible with other bus latencyfree SRAMs Fully synchronous operation 3.3 V power supply Separate I/O power supply of 3.3V Individual byte write operation Three chip enable signals Simple depth expansion Mode pin for setting interleave or linear burst mode of operation JTAG Boundary Scan (BGA only) JEDEC standard 100-pin TQFP and 119-ball PBGA packages Functional Description The N04N3633F1A N04N3633F1A and N04N1825F1A N04N1825F1A are 4Mb high performance synchronous SRAMs that are part of a family of devices for those demanding high performance. The FTRAM family of devices is designed to operate without the need of NOP or deselect clock cycles when transitioning from read to write cycles and thereby allowing the use of all available bandwidth. These high-speed devices are fully compatible with other no bus turn-around SRAMs such as NoBLTM, ZBTTM and NtRAMTM devices. Flow-Thru Performance and Power SORT (MHz) Unit 40 50 66 100 117 tCYCLE 25.0 20.0 15.0 10.0 8.5 nS tACCESS 14.0 12.0 11.0 8.5 7.5 nS Icc 175 200 250 350 375 mA Isb 5 5 5 5 5 mA Options · Organization 128Kb x 36 256Kb x 18 · Package 100-pin TQFP 119-ball PBGA · Speed 40MHz 50MHz 66MHz 100MHz 117MHz N04N36 N04N36 N04N18 N04N18 Q G 04 05 66 10 11 Part number example: N04N3633F1AQ-11C N04N3633F1AQ-11C The memory devices contain 4Mb of memory cells organized as 131,072 x 36 (N04N3633F1A N04N3633F1A) and 262,144 x 18 (N04N1833F1A N04N1833F1A). The devices operate in a synchronous manner with control signals, addresses and data inputs synchronized and captured at the rising edge of clock for ease of use. An asynchronous OE is available for disabling the outputs at any time. The devices are fabricated using NanoAmp's advanced CMOS process and highspeed/ultra low-power circuit technology. The N04N3633F1A N04N3633F1A and N04N1833F1A N04N1833F1A are ideal for networking and communication systems where high-density, high-performance memory elements are required. The architecture allows the data bus to be fully utilized when moving data into and out of FTRAM is a trademark of NanoAmp Solutions, Inc. NoBL is a trademark of Cycpress Semiconductor Corpopation ZBT is a trademark of Integrated Device Technology NtRAM is a trademark of Samsung Electronics Corporation Stock No. 23197-A 11/02 This is an advance datasheet and subject to change without notice. 1 N04N1833F1A N04N1833F1A N04N3633F1A N04N3633F1A Advance Information NanoAmp Solutions A A CE1 CE2 BWd BWc BWb BWa CE3 VDD VSS CLK WE CEN OE ADV NC NC A A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 (128K x 36) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 DQbP DQb DQb VDDQ VSS DQb DQb DQb DQb VSS VDDQ DQb DQb VSS VSS VDD VSS DQa DQa VDDQ VSS DQa DQa DQa DQa VSS VDDQ DQa DQa DQaP LBO A A A A A1 A0 DNU DNU VSS VDD DNU DNU A A A A A A A DQcP DQc DQc VDDQ VSS DQc DQc DQc DQc VSS VDDQ DQc DQc VSS VDD VDD VSS DQd DQd VDDQ VSS DQd DQd DQd DQd VSS VDDQ DQd DQd DQdP A NC NC VDDQ VSS NC DQaP DQa DQa VSS VDDQ DQa DQa VSS VSS VDD VSS DQa DQa VDDQ VSS DQa DQa NC NC VSS VDDQ NC NC NC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 (256K x 18) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 LBO A A A A A1 A0 DNU DNU VSS VDD DNU DNU A A A A A A A NC NC NC VDDQ VSS NC NC DQb DQb VSS VDDQ DQb DQb VSS VDD VDD VSS DQb DQb VDDQ VSS DQb DQb DQbP NC VSS VDDQ NC NC NC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 A A CE1 CE2 NC NC BWb BWa CE3 VDD VSS CLK WE CEN OE ADV NC NC A A 100-Pin TQFP Packages Stock No. 23197-A 11/02 This is an advance datasheet and subject to change without notice. 2 N04N1833F1A N04N1833F1A N04N3633F1A N04N3633F1A Advance Information NanoAmp Solutions 119-Ball PBGA Packages 256K x 18 1 A 2 3 4 5 6 7 VDDQ A A NC A A VDDQ B NC CE2 A ADV A CE3 NC C NC A A VDD A A NC D DQb NC VSS NC VSS DQaP NC E NC DQb VSS CE1 VSS NC DQa F VDDQ NC VSS OE VSS DQa VDDQ G NC DQb BWb NC VSS NC DQa H DQb NC VSS WE VSS DQa NC J VDDQ VDD NC VDD NC VDD VDDQ K NC DQb VSS CLK VSS NC DQa L DQb NC VSS NC BWa DQa NC M VDDQ DQb VSS CKE VSS NC VDDQ N DQb NC VSS A1 VSS DQa NC P NC DQbP VSS A0 VSS NC DQa NC R NC A LBO VDD NC A T NC A A NC A A NC U VDDQ TMS TDI TCK TDO DNU VDDQ 3 4 5 128K x 36 1 2 6 7 VDDQ A VDDQ A A NC A A B NC CE2 A ADV A CE3 NC C NC A A VDD A A NC D DQc DQcP VSS NC VSS DQbP DQb E DQc DQc VSS CE1 VSS DQb DQb F VDDQ DQc VSS OE VSS DQb VDDQ G DQc DQc BWc NC BWb DQb DQb H DQc DQc VSS WE VSS DQb DQb J VDDQ VDD NC VDD NC VDD VDDQ K DQd DQd VSS CLK VSS DQa DQa L DQd DQd BWd NC BWa DQa DQa M VDDQ DQd VSS CKE VSS DQa VDDQ N DQd DQd VSS A1 VSS DQa DQa P DQd DQdP VSS A0 VSS DQaP DQa R NC A LBO VDD NC A NC T NC NC A A A NC NC U VDDQ TMS TDI TCK TDO DNU VDDQ 7 x 17 Ball BGA with 1.27 mm Ball Pitch Stock No. 23197-A 11/02 This is an advance datasheet and subject to change without notice. 3 N04N1833F1A N04N1833F1A N04N3633F1A N04N3633F1A Advance Information NanoAmp Solutions Pin Descriptions Signal Type POWER A0, A1 Synch Input Address inputs sampled at the rising edge of CLK. Least significant address bits are used to set the internal burst counter (if used). Ax Synch Input Address inputs 2 through 16/17, sampled at the rising edge of CLK. LBO Synch Input Linear burst order, active low, used for setting the address order of the burst counter. A low selects linear burst order while a high selects interleave burst order and if floating, this input will default to a high (interleave order) This should not be changed while operating the SRAM. ADV Synch Input Advance/load, sampled at the rising edge of clock. When high, the internal burst counter is advanced for the next address and when low, a new address is loaded from the address pins. BWa BWb BWc BWd Synch Input Byte writes, active low, sampled at the rising edge of CLK if WE is low for a write cycle. BWa controls byte a (DQa) inputs, BWb controls byte b (DQb) inputs, BWc controls byte c (DQc) inputs and BWd controls byte d (DQd) inputs. For x18 devices, only BWa and BWb apply. WE Synch Input Write enable, active low, sampled at the rising edge of CLK. A low state initiates a write cycle. CLK Clock Input Clock CE1 Synch Input Chip enable 1, active low, sampled on the rising edge of CLK. Used with CE2 and CE3 and to select the device. CE2 Synch Input Chip enable 2, active high, sampled on the rising edge of CLK. Used with CE1 and CE3 and to select the device. CE3 Synch Input Chip enable 3, active low, sampled on the rising edge of CLK. Used with CE2 and CE1 and to select the device. CKE Synch Input Clock enable, active low and while low, allows CLK to be recognized by the SRAM. While high, CKE inhibits CLK from driving SRAM cycles and extends cycles already in progress. OE Asynch Input Output enable, asynchronous active low, tri-states the output buffers when high and enables the output buffers when low. DQa DQb DQc DQd Synch Input/ Output During a write cycle, the data lines are synchronous inputs that are sampled at the rising edge of CLK to specify data to be written to the memory array. During a read cycle, the data lines are driven out with data from the SRAM array. DQ(a, b, c, d) refer to the bytes a, b, c, d. For x18 devices, only DQa and DQb apply. VDD Power Supply Supplies power to the device core. VDDQ I/O Power Supply Supplies power to the I/O section of the device. VSS Ground supply Ground TMS Input Test Mode Select supplies input command to the TAP controller with TCK. TDI Input Test Data Input supplies serial input to test registers. TDO Output Test Data Output supplies serial data out from test registers. TCK Input Test Clock controls TAP controller and serial data in and data out. NC - No connect DNU - Do Not Use Stock No. 23197-A 11/02 This is an advance datasheet and subject to change without notice. 4 N04N1833F1A N04N1833F1A N04N3633F1A N04N3633F1A Advance Information NanoAmp Solutions Functional Truth Table 1, 7 Address CE1 CE2 CE3 ADV WE BWx2 OE CKE8 CLK3 DQ9 DESELECT NA H X X L X X X L L-H High-Z DESELECT NA X L X L X X X L L-H High-Z DESELECT NA X X H L X X X L L-H High-Z Continue DESELECT NA X X X H X X X L L-H High-Z READ, begin burst Ext L H L L H X L L L-H Data-out READ, continue burst Int X X X H X X L L L-H Data-out 4,10 DUMMY READ, begin burst Ext L H L L H X H L L-H High-Z 5 DUMMY READ, continue burst Int X X X H X X H L L-H High-Z 4,5,10 WRITE, begin burst Ext L H L L L L X L L-H Data-in WRITE, continue burst Int X X X H X L X L L-H Data-in 4,10 WRITE ABORT, begin burst Ext L H L L L H X L L-H High-Z 5 IGNORE CLOCK Current X X X X X X X H L-H - 6,8 Operation Notes 4 Notes: 1. X = don't care; H = logic HIGH; L = logic LOW. 2. BWx = H means all BW signals are high; BWx = L means one or more BW signals are low. 3. L-H refers to the CLK edge transitioning from a low to a high state. 4. All continue burst cycles use the same control inputs. The type of cycle is chosen in the first cycle prior to the continue cycle. 5. Dummy read and write abort commands perform no external operation, they are NOP cycles. 6. If an ignore clock (CKE high) cycle happens during a read, the DQ bus will remain active. If this happens during a write, the DQ bus will remain High-Z, no write occurs. 7. All inputs except OE must meet set-up and hold times. 8. Wait states are inserted by setting CKE high. 9. All outputs will remain in high-Z during power-up. 10. A 2-bit burst counter is included which is incremented for all continue burst cycles. The address wraps around every fourth burst cycle. Write Truth Table 1,2 Function WE BWa BWb BWc BWd READ H X X X X WRITE byte a 3 L L H H H WRITE byte b 3 L H L H H WRITE byte c 3 L H H L H WRITE byte d 3 L H H H L WRITE all byte L L L L L WRITE ABORT L H H H H Notes: 1. This represents the x36 device. For the x18 device, only BWa and BWb are used. 2. X = don't care; H = logic HIGH; L = logic LOW. 3. Multiple bytes may be exercised during a cycle. Stock No. 23197-A 11/02 This is an advance datasheet and subject to change without notice. 5 N04N1833F1A N04N1833F1A N04N3633F1A N04N3633F1A Advance Information NanoAmp Solutions Burst Order Tables Interleave Starting digits Starting digits Starting digits Starting digits LBO = High A1 A1 A1 A1 First address A0 A0 A0 A0 0 0 0 1 1 0 1 1 Second address 0 1 0 0 1 1 1 0 Third address 1 0 1 1 0 0 0 1 Fourth address 1 1 1 0 0 1 0 0 Linear Starting digits First address Starting digits Starting digits A1 LBO = Low Starting digits A1 A1 A1 A0 A0 A0 A0 0 0 0 1 1 0 1 1 Second address 0 1 1 0 1 1 0 0 Third address 1 0 1 1 0 0 0 1 Fourth address 1 1 0 0 0 1 1 0 Note: At the end of a burst of four, the burst counter wraps to the starting address and continues. Stock No. 23197-A 11/02 This is an advance datasheet and subject to change without notice. 6 N04N1833F1A N04N1833F1A N04N3633F1A N04N3633F1A Advance Information NanoAmp Solutions Functional Block Diagram LBO A0 A16(17) 1718) A0-A1 Address Register 15(16) Burst Logic A'0-A'1 17(18) A'0-A'1 Write Address Register CLK CKE 128K x 36 (256K x 18) Memory Array 17(18) K 36(18) CE1 CE2 CE3 ADV WE BWx C o n t r o l Stock No. 23197-A 11/02 36(18) Control Logic Data-in Register 36(18) Steering K OE ZZ DQ0 DQ36(18) R e g i s t e r 36(18) 36(18) Output Buffers This is an advance datasheet and subject to change without notice. 7 N04N1833F1A N04N1833F1A N04N3633F1A N04N3633F1A Advance Information NanoAmp Solutions Read and Write State Diagram D B Deselect W R R D D R Begin Read Begin Write W W B R B B D Burst Read D W R W Burst Write B Key: State diagram shows current state and transitions to possible next states. D = Deselect R = Read W = Write B = Burst (read, write or deselect) Stock No. 23197-A 11/02 This is an advance datasheet and subject to change without notice. 8 N04N1833F1A N04N1833F1A N04N3633F1A N04N3633F1A Advance Information NanoAmp Solutions Functional Operation The N04N1833F1A N04N1833F1A and N04N3633F1A N04N3633F1A are developed for the high performance needs of the networking and communications markets. Devices are available for both pipeline and flow-through modes of operation depending on the particular system needs. All inputs except OEand LBO are synchronized and registered by the rising edges of the clock (CLK). Three chip enables are available for depth expansion with CE1 and CE3 being active low and CE2 active high. For a cycle to start, all three must be active and any one inactive will deselect the device. Read operations are started with CKE, CE1, CE3 and ADV being asserted low at the rising edge of CLK along with WE and CE2 being asserted high. Write operations are started with CKE, CE1, CE3, ADV and WE being asserted low at the rising edge of CLK along with CE2 being asserted high. The byte write enable (BWx) inputs are used to determine which bytes (or all bytes) will be written to. The address inputs are latched and used as the location in memory to start a memory cycle. Clock enable input (CKE) allows operations to be stalled or suspended while CKE is inactive high. In this operation, all internal registers retain data from the previous operation. Output enable (OE), linear burst mode (LBO) and sleep mode (ZZ) are asynchronous signals that control other aspects of the device. OE is used to disable the output buffers at any time. LBO is either tied high for interleave burst order or low for linear burst order. ZZ is used to put the device in a low power sleep mode, while all data is retained in the SRAM memory array. this first cycle, data is driven out of (or flows thru) the SRAM in the same cycle as the activation instead of waiting until the next rising edge of CLK (as in a pipeline device). For a write cycle, all the necessary control signals must be setup at the rising edge of CLK as stated above. The BWx must be setup active low for whichever bytes will be written too at this first rising edge of CLK. The data to be written to the SRAM is not registered until the second rising edge of CLK. This is called a late write cycle as data is not necessary until the second cycle while address and write command information is required at the first cycle. Flow-thru reads and writes can be performed in single access (ADV = L) cycles or burst (ADV = H) cycles. Burst Operation The previous operations discussed were initiated with ADV being asserted low, thereby activating a cycle with a new external address being loaded and used for array operations. If ADV is asserted high at the rising edge of CLK, the internal burst counter is incremented and an internal address is used to access the SRAM array. The burst counter is a four bit counter and can be incremented in two orders, interleave and linear. The burst counter wraps around after four addresses and continues to operate as long as ADV is high and valid CLK cycles are performed. Flow-Thru Operation For a read cycle, all the necessary control signals must be setup at the rising edge of CLK as stated above. The memory array is then accessed. During Stock No. 23197-A 11/02 This is an advance datasheet and subject to change without notice. 9 N04N1833F1A N04N1833F1A N04N3633F1A N04N3633F1A Advance Information NanoAmp Solutions Absolute Maximum Ratings Symbol Description Value VDD Voltage on any VDD pin wrt Ground VIN1 Unit -0.5 to 4.6 V Voltage on any input pin -0.5 to VDDQ +0.5V V VI/O1 Voltage on any DQ pin -0.5 to VDDQ +0.5V V TBIAS Temperature under bias -55 to 125 o TSTOR Storage temperature -65 to150 oC IOUT Current into output circuit 20 mA ESD Static Discharge Voltage > 2001 V ILatch Latch-Up Current > 200 mA C .1) Minimum voltage must not exceed -2V for pulse widths of < 20% tCYC. Pin Capacitance1 Item Symbol Conditions Max Unit Input Capacitance Cin 4 pF Clock Capacitance Cclk 4 pF Input/Output Cpacitance Ci/o Ta = 25oC, VDD = Typ, f = 1MHz 4 pF 1) Not 100% tested. Thermal Resistance1 Item 100-pin TQFP Conditions Still air, soldered on a 4 layer PCB Theta JA Junction to Ambient Theta JC Junction to Case 28 4 Unit o C/W 1) Not 100% tested. Stock No. 23197-A 11/02 This is an advance datasheet and subject to change without notice. 10 N04N1833F1A N04N1833F1A N04N3633F1A N04N3633F1A Advance Information NanoAmp Solutions Operating Conditions and DC Characteristics1 Over the operating range. All voltages referenced to ground (Vss). Min Typ4 Max Unit VDD 3.135 3.3 3.465 V I/O Supply Voltage VDDQ 3.135 3.3 3.465 V Input High Voltage VIH 2.0 VDD + 0.3 V Input Low Voltage VIL ­0.3 0.8 V Output High Voltage5 VOH IOH = -4.0mA Output Low Voltage5 VOL IOL = 8.0mA Operating Current2, 3 IDD Iteml Supply Voltage Conditions 2.4 V V - 04 175 mA - 05 200 - 66 250 - 11 350 - 11 Device selected; All inputs < VIL or > VIH; Frequency = 1/Tcyc (MIN); Outputs open 0.4 375 Deselect Current Standby (CMOS)3 ISB1 Device deselected; All inputs static and < 0.3V or > VDDQ-0.3, Frequency = 0 All 5 mA Deselect Current Clock running (CMOS)3 ISB3 Device deselected; All inputs < 0.3V or > VDD0.3;Frequency = 1/Tcyc - 04 35 mA - 05 40 - 66 50 - 11 70 - 11 80 - 04 35 - 05 40 - 66 60 - 11 80 - 11 90 Deselect Current Clock running (TTL)3 ISB4 Device deselected; All inputs static and < VIL or > VIH, Frequency = 1/Tcyc mA 1) Currents are specified for VDD = VDD max. 2) Does not include output currents. 3) Device selected refers to a device in the active mode. Device deselected refers to a device as defined in the truth table. 4) Typical values measured at VDD TYP and 25oC. 5) Output load B used. Stock No. 23197-A 11/02 This is an advance datasheet and subject to change without notice. 11 N04N1833F1A N04N1833F1A N04N3633F1A N04N3633F1A Advance Information NanoAmp Solutions Leakage Currents Item Symbol Conditions Min Max Units Notes ILI1 0V < VIN < VDD -5.0 5.0 µA 1 -30.0 30.0 ILO Outputs disabled 0V < VIN < VDDQ -5.0 5.0 Input Leakage Current Input Leakage Current of LBO pin Output Leakage Current µA 1. LBO input: ILI = +/- 30µA due to internal resistors for floating conditions. AC Test Conditions Item Value Input Pulse Level 0V to 3.0V Input Rise and Fall Time 1.0V/nS (10% to 90%) Input Timing Reference Level VDD/2 Output Timing Reference Level VDDQ/2 Output Load See diagram below AC Output Load 3.3V 317 50 1.5V DQ Z0 = 50 30 pF * DQ 350 5 pF * Output Load B Output Load A * Includes Jig Capacitance Stock No. 23197-A 11/02 This is an advance datasheet and subject to change without notice. 12 N04N1833F1A N04N1833F1A N04N3633F1A N04N3633F1A Advance Information NanoAmp Solutions AC Timing Characteristics -11 Parameter Symbol Min -10 Max Min -66 Max Min -05 Max Min -04 Max Min Max Unit CLOCK TIMINGS Clock Cycle Time tCYC 8.5 10.0 15.0 20.0 25.0 nS Clock High Pulse Width tCH 1.9 1.9 5.0 6.0 7.0 nS Clock Low Pulse Width tCL 1.9 Clock Frequency FMAX 117 100 66 50 40 MH z Clock high to output valid tCQ 7.5 8.5 11.0 12.0 14.0 nS Output hold from clock high tOH 1.5 1.5 1.5 1.5 1.5 nS Clock to output in low-Z1 tCLZ 3.0 3.0 3.0 3.0 3.0 nS Clock to output in high-Z1 tCHZ 4.2 5.0 5.0 5.0 5.0 nS OE low to output valid ttOE 4.2 5.0 6.0 7.0 8.0 nS OE low to output in low-Z1 tOLZ OE high to output in high-Z1 tOHZ 1.9 5.0 6.0 7.0 nS OUTPUT TIMINGS 0 0 4.2 0 5.0 0 6.0 0 7.0 nS 8.0 nS SETUP AND HOLD TIMES Setup Time tS 2.0 2.0 2.0 2.0 2.5 nS Hold Time tH 0.5 0.5 0.5 1.0 1.0 nS 1) tCLZ, tCHZ, tOLZ, tOHZ are specified with output load B. Stock No. 23197-A 11/02 This is an advance datasheet and subject to change without notice. 13 Stock No. 23197-A 11/02 This is an advance datasheet and subject to change without notice. DQ OE ADDRESS WE ADV CE CKE CLK tH tH tH tH tOLZ tOE tCYC Q(A1) A2 tCL tOHZ tCH Q(A2) tCQ Q(A2+1) tOH Q(A2+2) A3 Q(A2+3) Q(A3) Q(A3+1) Notes: 1. Q(A1) represents the first data accessed from address A1 in the SRAM and Q(A2) represents the first data accessed from address A2. Q(A2+1) represents the second bit accessed within the burst of address A2. 2. CE = L means CE1 = CE3 = L and CE2 = H. CE = H means CE1 = H or CE2 = L or CE3 = H. tH A1 tS tS tS tS tS Q(A3+3) Undefined Don't Care Q(A3+2) tCHZ NanoAmp Solutions N04N1833F1A N04N1833F1A N04N3633F1A N04N3633F1A Advance Information Timing Waveforms for READ Cycles 14 Stock No. 23197-A 11/02 This is an advance datasheet and subject to change without notice. DQ OE ADDRESS WE ADV CE CKE CLK tH tH tH tH Q(AP) tOHZ tCYC tCL tS D (A2) D A2 tCH (A1) (A2+1) D tH (A2+2) D A3 D (A2+3) D (A3) D (A3+1) Notes: 1. Q(AP) represents the data accessed from the previous read cycle. D(A1) represents the data to be written to address A1 in the SRAM and D(A2) represents the data to be written to address A2. D(A2+1) represents the second bit to be written to address A2+1 during the burst. 2. CE = L means CE1 = CE3 = L and CE2 = H. CE = H means CE1 = H or CE2 = L or CE3 = H. tH A1 tS tS tS tS tS D D (A3+3) Undefined Don't Care (A3+2) NanoAmp Solutions N04N1833F1A N04N1833F1A N04N3633F1A N04N3633F1A Advance Information Timing Waveforms for WRITE Cycles 15 Stock No. 23197-A 11/02 This is an advance datasheet and subject to change without notice. DQ OE ADDRESS WE ADV CE CKE CLK tH tH tH tH tCQ tH A2 tS tCYC Q(A1) A3 tCH tH D(A2) tS A4 tCL Q(A3) tCHZ A5 D(A4) A6 tCLZ D(A5) A7 tOH Q(A6) A8 Q(A7) A9 Notes: 1. Q(A1) represents the data accessed from address A1 in the SRAM. D(A2) represents data written to address A2 in the SRAM. 2. CE = L means CE1 = CE3 = L and CE2 = H. CE = H means CE1 = H or CE2 = L or CE3 = H. 3. WE = L means WE and all BWx are L. tH A1 tS tS tS tS tS D(A8) Undefined Don't Care NanoAmp Solutions N04N1833F1A N04N1833F1A N04N3633F1A N04N3633F1A Advance Information Timing Waveforms for Combined READ/WRITE Cycles 16 Stock No. 23197-A 11/02 This is an advance datasheet and subject to change without notice. DQ OE ADDRESS WE ADV CE CKE CLK tH tH tH tH tOLZ A2 tOE tCYC Q(A1) tCH tCHZ Q(A2) A3 tCL tH D(A3) tS A4 tCQ tOH Q(A4) A5 D(A5) Notes: 1. Q(A1) represents data accessed from address A1 in the SRAM. D(A3) represents data written to address A2 in the SRAM. 2. CE = L means CE1 = CE3 = L and CE2 = H. CE = H means CE1 = H or CE2 = L or CE3 = H. tH A1 tS tS tS tS tS Undefined Don't Care NanoAmp Solutions N04N1833F1A N04N1833F1A N04N3633F1A N04N3633F1A Advance Information Timing Waveforms for CE Operation 17 Stock No. 23197-A 11/02 This is an advance datasheet and subject to change without notice. DQ OE ADDRESS WE ADV CE CKE CLK tH tH tH tH tCYC tCQ tCLZ A2 tCH tCL Q(A1) A3 tCHZ tH D(A2) tS A4 Q(A3) tOH Q(A4) A5 Notes: 1. Q(A1) represents data accessed from address A1 in the SRAM. D(A2) represents data written to address A2 in the SRAM. 2. CE = L means CE1 = CE3 = L and CE2 = H. CE = H means CE1 = H or CE2 = L or CE3 = H. tH A1 tS tS tS tS tS Undefined Don't Care NanoAmp Solutions N04N1833F1A N04N1833F1A N04N3633F1A N04N3633F1A Advance Information Timing Waveforms for CKE Operation 18 N04N1833F1A N04N1833F1A N04N3633F1A N04N3633F1A Advance Information NanoAmp Solutions JTAG Serial Boundary Scan The N04N1833F1A N04N1833F1A and N04N3633F1A N04N3633F1A both incorporate JTAG serial boundary scan capability in the BGA packages only. This test function utilizes the test Access Port (TAP) to and operates consistent with IEEE Standard 1149.1-1900, but is not fully compliant since a subset of functions are omitted. The exclusion of these TAP controller functions does not conflict with other 1149.1 compliant devices. This test function allows connectivity scan testing during board level debug. This JTAG port operates using standard I/O levels. Disabling the JTAG Feature There are no issues with using this SRAM and not using the JTAG feature. For normal operation with the TAP controller disabled, TCK must be tied low and TDI and TMS should be left floating or tied to Vdd. TDO should be left unconnected. Performing a TAP Reset Upon power-up, the TAP controller will be in a reset state and it will not interfere with the operation of the SRAM. A reset can be entered by holding TMS at a high level for five consecutive rising edges of TCK. TCK Test Access Port (TAP) Controller TMS Bypass Register Instruction Register TDI TDO Identification Register 32 bits Boundary Scan Register 51/70 bits SRAM I/O Pins JTAG Block Diagram TAP Pin Description Signal Name Type Description TCK Test Clock Input clock Clock for all TAP events. All inputs are captured on the rising edge of TCK. All outputs are driven with the falling edge of TCK. TMS Test Mode Select Input Input for commands to theTAP controller. Sampled on the rising edge of TCK TDI Test Data-In Input Input for serial registers sampled on rising edge of TCK. TDO Test Data-Out Output Output of serial registers that changes on the falling edge of TCK. Stock No. 23197-A 11/02 This is an advance datasheet and subject to change without notice. 19 N04N1833F1A N04N1833F1A N04N3633F1A N04N3633F1A Advance Information NanoAmp Solutions TAP Registers Name Length Description Instruction 3 Holds instruction for the TAP controller. Loaded when placed between TDI and TDO and automatically loaded with IDCODE at power-up and after a reset. Boundary Scan 49 for x18 68 for x36 Loaded with the contents of the RAM Input and Output ring when the TAP controller is in the Capture-DR state and is then placed between the TDI and TDO pins when the controller is moved to the Shift-DR state. Identification Code 32 The ID register is loaded with a vendor-specific code during the Capture-DR state when the IDCODE command is loaded in the instruction register. The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift-DR state. Defined in the ID Register Definition table. Bypass 1 Register allows serial test data to be shifted through the SRAM with minimal delay. TAP Controller Instructions Code Instruction Description 000 EXTEST Captures I/O ring contents and places boundary scan register between TDI and TDO. Places SRAM outputs in High-Z. 001 IDCODE Loads ID register and places it between TDI and TDO. 010 SAMPLE-Z Notes Captures I/O ring contents and places boundary scan register between TDI and TDO. Places SRAM outputs in High-Z. 011 Reserved Reserved for future, do not use. 100 SAMPLE/ PRELOAD Captures I/O ring contents and places boundary scan register between TDI and TDO. Does not implement the preload function. 101 Reserved Reserved for future, do not use. 110 Reserved Reserved for future, do not use. 111 BYPASS Places the bypass register between TDI and TDO. Stock No. 23197-A 11/02 This is an advance datasheet and subject to change without notice. 20 N04N1833F1A N04N1833F1A N04N3633F1A N04N3633F1A Advance Information NanoAmp Solutions TAP Controller State Diagram Test Logic Reset 1 0 Run Test Idle 1 1 Select DR 0 0 0 1 Capture DR 0 Shift DR 1 Shift IR 1 0 1 Exit1 DR 0 Pause DR Pause IR 0 1 0 1 0 Exit2 DR Exit2 IR 1 1 Update DR 1 0 Exit1 IR 0 0 1 Capture IR 0 1 1 Select IR Update IR 0 1 0 Identification Register Description Die Revision Device Depth Device Width Device ID JEDEC ID Code 31. 28 27. 23 22. 18 17. 12 11. 1 128K x 36 xxxxx xxxxx xxxxx xxxxxx xxxxxxxxxxx 256K x 18 xxxxx xxxxx xxxxx xxxxxx xxxxxxxxxxx Bit #s Stock No. 23197-A 11/02 This is an advance datasheet and subject to change without notice. 21 N04N1833F1A N04N1833F1A N04N3633F1A N04N3633F1A Advance Information NanoAmp Solutions TAP DC Operating Conditions Parameter Symbol Min Max Unit Input High Level VIHT 2.0 VDD + 0.3 V Input Low Level VILT -0.3 0.7 V VOHT1 2.0 V IOHT1 = -2.0mA VOHT2 2.0 V IOHT2 = -100uA Output High Level Notes OILT1 Input Leakage Current 0.7 V IOLT1 = 2.0mA OILT2 Output Low Level 0.2 V IOLT2 = 100uA 30 uA -30 ILIT TAP AC Test Conditions Parameter Conditions Input High Level 2.5 V Input Low Level 0.0 V Input Slew Rate 1 nS Input and Output Reference Level 1.25 V 1.25 V 50 DQ Z0 = 50 Stock No. 23197-A 11/02 20 pF This is an advance datasheet and subject to change without notice. 22 N04N1833F1A N04N1833F1A N04N3633F1A N04N3633F1A Advance Information NanoAmp Solutions TAP Timing Diagram ttcyc ttcl TCK ttch tts tth TMS TDI ttcq TDO TAP AC Timing Characteristics Parameter Symbol Min Max Units TCK Cycle Time ttcyc 100 - nS TCK High Pulse Width ttch 40 - nS TCK Low Pulse Width ttcl 40 - nS TMS / TDI Setup Time tts 10 - nS TMS / TDI Hold Time tth 10 - nS TCK Low to Output Valid ttcq - 20 nS Stock No. 23197-A 11/02 This is an advance datasheet and subject to change without notice. 23 N04N1833F1A N04N1833F1A N04N3633F1A N04N3633F1A Advance Information NanoAmp Solutions Boundary Scan Order (119 PBGA) 128Kx36 Bit # Ball 256K x18 Bump ID Bit # Ball Bump ID Bit # Ball Bump ID Bit # Ball Bump ID 1 tbd tbd 36 tbd tbd 1 tbd tbd 27 tbd tbd 2 tbd tbd 37 tbd tbd 2 tbd tbd 28 tbd tbd 3 tbd tbd 38 tbd tbd 3 tbd tbd 29 tbd tbd 4 tbd tbd 39 tbd tbd 4 tbd tbd 30 tbd tbd 5 tbd tbd 40 tbd tbd 5 tbd tbd 31 tbd tbd 6 tbd tbd 41 tbd tbd 6 tbd tbd 32 tbd tbd 7 tbd tbd 42 tbd tbd 7 tbd tbd 33 tbd tbd 8 tbd tbd 43 tbd tbd 8 tbd tbd 34 tbd tbd 9 tbd tbd 44 tbd tbd 9 tbd tbd 35 tbd tbd 10 tbd tbd 45 tbd tbd 10 tbd tbd 36 tbd tbd 11 tbd tbd 46 tbd tbd 11 tbd tbd 37 tbd tbd 12 tbd tbd 47 tbd tbd 12 tbd tbd 38 tbd tbd 13 tbd tbd 48 tbd tbd 13 tbd tbd 39 tbd tbd 14 tbd tbd 49 tbd tbd 14 tbd tbd 40 tbd tbd 15 tbd tbd 50 tbd tbd 15 tbd tbd 41 tbd tbd 16 tbd tbd 51 tbd tbd 16 tbd tbd 42 tbd tbd 17 tbd tbd 52 tbd tbd 17 tbd tbd 43 tbd tbd 18 tbd tbd 53 tbd tbd 18 tbd tbd 44 tbd tbd 19 tbd tbd 54 tbd tbd 19 tbd tbd 45 tbd tbd 20 tbd tbd 55 tbd tbd 20 tbd tbd 46 tbd tbd 21 tbd tbd 56 tbd tbd 21 tbd tbd 47 tbd tbd 22 tbd tbd 57 tbd tbd 22 tbd tbd 48 tbd tbd 23 tbd tbd 58 tbd tbd 23 tbd tbd 49 tbd tbd 24 tbd tbd 59 tbd tbd 24 tbd tbd 50 tbd tbd 25 tbd tbd 60 tbd tbd 25 tbd tbd 51 tbd tbd 26 tbd tbd 61 tbd tbd 26 tbd tbd 27 tbd tbd 62 tbd tbd 28 tbd tbd 63 tbd tbd 29 tbd tbd 64 tbd tbd 30 tbd tbd 65 tbd tbd 31 tbd tbd 66 tbd tbd 32 tbd tbd 67 tbd 5C 33 tbd tbd 68 tbd tbd 34 tbd tbd 69 tbd tbd 35 tbd tbd Stock No. 23197-A 11/02 This is an advance datasheet and subject to change without notice. 24 N04N1833F1A N04N1833F1A N04N3633F1A N04N3633F1A Advance Information NanoAmp Solutions 100-Pin TQFP Package Dimensions E A A1 Pin 1 B1 B C D F H G All dimensions in mm Min Nom Max A Symbol Overall Width Description 15.80 16.00 16.20 A1 Width 13.90 14.00 14.10 B Overall Length 21.80 22.00 22.20 B1 Length 19.90 20.00 20.10 C Pin Pitch D Lead Width 0.22 0.30 0.38 E Package Height 1.35 1.40 1.45 F Standoff 0.05 G Lead Extension H Lead Bend Length Stock No. 23197-A 11/02 Notes 0.65 0.15 1.00 0.45 0.60 0.75 This is an advance datasheet and subject to change without notice. 25 N04N1833F1A N04N1833F1A N04N3633F1A N04N3633F1A Advance Information NanoAmp Solutions 119-Ball BGA Package Dimensions E A D Pin A1 E B TOP VIEW BOTTOM VIEW C F SIDE VIEW All Dimensions in mm Symbol Description Min Nom Max A Package Width 13.80 14.00 14.20 B Package Length 21.80 22.00 22.20 C Package Height D Ball Width 0.75 0.80 E Ball Pitch F Ball Height Stock No. 23197-A 11/02 2.40 0.70 1.27 0.60 0.65 0.70 This is an advance datasheet and subject to change without notice. 26 N04N1833F1A N04N1833F1A N04N3633F1A N04N3633F1A Advance Information NanoAmp Solutions Ordering Information N04NXX N04NXX 33 F1AX-XX C Performance Package Type I/O Width 04 = 40MHz 05 = 50MHz 06 = 66 MHz 10 = 100 MHz 11 = 117 MHz Q = 100-pin TQFP G = 119-ball PBGA 18 = x18 36 = x36 Note: Add -T&R following the part number for Tape and Reel. Orders will be considered in tray if not noted. Revision History Revision # A Date Change Description November 2002 Stock No. 23197-A 11/02 Initial Release This is an advance datasheet and subject to change without notice. 27