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TMS426160 Texas Instruments IC FAST PAGE DRAM, Dynamic RAM visit Texas Instruments
TMS428160 Texas Instruments IC FAST PAGE DRAM, Dynamic RAM visit Texas Instruments
TMS416160 Texas Instruments IC FAST PAGE DRAM, Dynamic RAM visit Texas Instruments
TMS416800 Texas Instruments IC FAST PAGE DRAM, Dynamic RAM visit Texas Instruments
TMS664164 Texas Instruments IC SYNCHRONOUS DRAM, Dynamic RAM visit Texas Instruments
TMS664814 Texas Instruments IC SYNCHRONOUS DRAM, Dynamic RAM visit Texas Instruments

Motorola CMOS Dynamic RAM 1M x 1

Catalog Datasheet MFG & Type PDF Document Tags

MCM91430

Abstract: Motorola CMOS Dynamic RAM 1M MCM32515 128K x 32 20/25 ns Now 64 Pin SIMM (SG) Uses four 1M SRAMs MCM32128A Motorola , Memory 62 = 5 V CMOS 63 = 3.3 V CMOS 67 = 5 V BiCMOS 69 = 3.3 V BiCMOS Density: 0 = 256K 2 = 1M , = First qualified foundry device Width: 5=x9 6=x8 7=x1 8=x4 9 = x 4 with OE Motorola , a CMOS 16K x 16 and NOT a 512K x 90 device. MPC designates devices designed to work with PowerPC , Packaging PowerPC Cache Modules with 16K x 15 CacheTag Motorola MPC105, Motorola MPC106
Motorola
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MCM91430 Motorola CMOS Dynamic RAM 1M Motorola CMOS Dynamic RAM 1M x 1 MCM511000A 1mx1 DRAM DIP TSOP 400 86 MCM517405C MCM518160A MCM518160B MCM518165B MCM518165BV MCM44400C

MCM511000

Abstract: MCM81430S M O TO RO LA SEMICONDUCTOR TECHNICAL DATA MCM81000 1M x 8 Bit Dynamic Random Access Module The MCM81000 is an 8M dynamic random access memory (DRAM) module organized as 1,048,576 x 8 bits. The module is , along with a 0.22 nF (min) decoupling capacitor mounted under each DRAM. The MCM511000A is a 1 .On CMOS high speed, dynamic random access memory organized as 1,048,576 one-bit words and fab ricated with CMOS , fast successive data operations at all 2048 column locations on a selected row of the 1M dynamic RAM
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MCM81000S MCM511000 MCM81430S MCM81000-70 MCM81000-80 MCM81000AS MCM81000L MCM81000LH

MCM8

Abstract: MCM81430S m v s i v i ìv L n SEMICONDUCTOR TECHNICAL DATA 1M x 8 Bit Dynamic Random Access Module The MCM81000 and MCM8L1000 are 8M dynamic random access memory (DRAM) modules organized as 1,048,576 x 8 bits , CMOS high speed, dynamic random access memory organized as 1,048,576 one-bit words and fabricated with , selected row of the 1M dynamic RAM. Read access time in page mode (tCAC)is typically half the regular RAS , 1M x 8 Modules are Available in Two-Chip Versions (MCM81430S) · · · · · · · · MCM81000 MCM8L1000
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MCM8 MCM81OOOS MCM810 8L1000 MCM81000AS70 MCM81000AS80 MCM8L1000AS70

MCM91000-70

Abstract: MCM91000SG MOTOROLA SEMICONDUCTOR TECHNICAL DATA 1M x 9 Bit Dynamic Random Access Memory Module The MCM91000 and MCM9L1000 are 9M dynamic random access memory (DRAM) modules organized as 1,048,576 x 9 bits , .On CMOS high-speed dynamic random access memory organized as 1,048,576 one-bit words and fabri cated with , _ For Applications Requiring W to be Don't Care during CAS-Before-RAS Refresh Cycles 1M x 9 Modules , dynamic nodes within the RAM. During an extended inactive state (greater than 8 milliseconds with the
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MCM91000-70 MCM91000SG motorola mcm91000s MCM91000-80 MCM91000AS 9L1000 MCM91000L70 MCM91000L80

mcm91000as

Abstract: mcm91000s MOTOROLA SEMICONDUCTOR TECHNICAL DATA MCM91000 1M x 9 Bit Dynamic Random Access Memory Module The MCM91000 is a 9M dynamic random access memory (DRAM) module or ganized as 1,048,576 x 9 bits. The , ^ CMOS high-speed dynamic random access memory organized as 1,048,576 one-bit words and fabricated with , at all 2048 column locations on a selected row of the 1M dynamic RAM. Read access time in page mode , CAS-Before-RAS Refresh Cycles · 1M x 9 Modules are also Available in 3-Chip Versions (See Data Sheet for MCM91430
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91000LH70 mcm91000s MCM91000S 91000LH80 91000S70 91000S80 91000AS70

MCM411000J-70

Abstract: MCM411000J70 MOTOROLA SEMICONDUCTOR TECHNICAL DATA MCM411000 MCM41L1000 1M x 1 CMOS Dynamic RAM Page Mode The MCM411000 is a 1.On CMOS high-speed dynamic random access memory. It is organized as 1,048 , of the 1M dynamic RAM. Read access time in page mode (tCAC) ¡s typically half the regular RAS , NC 1? 13 18 A3 [ MOTOROLA DRAM DATA NC AO Vr r W 7 9 PIN ASSIGNMENTS , addressing the 1M RAM: RAS-only refresh cycle and CAS before RAS refresh cycle. Both are discussed in
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MCM411000-80 MCM411000J70 MCM411000J-70 707B-01 822B-01 MCM411000-70 MCM41L1000-70 MCM41L1000-80

Motorola CMOS Dynamic RAM 1M x 1

Abstract: MCM514400 CMOS 1M x 1 DRAMs housed in 20/26 lead SOJ packages, mounted on a substrate along with a 0.22 |iF (min) decoupling capacitor mounted under each DRAM. The MCM514400 is a CMOS high speed, dynamic random access , the regular RAS clock access (tRAC)on the Motorola 1M dynamic RAM. Page mode operation consists of , , Eight 1M x 1 DRAMs, and Twenty Four 0.22 |iF (Min) Decoupling Capacitors â'¢ Unlatched Data Out at , Ã"0V 2 7 1990 MOTOROLA SEMICONDUCTOR wamâ'"mâ'"m^mm TECHNICAL DATA Product Preview 2M x 36
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MCM36200 MCM36L200 Nippon capacitors MCM36200S MCM36L200S MCM36200S-80 MCM36200S-10 MCM36L2

MCM511000AJ70

Abstract: MCM511000A-70 MOTOROLA SEMICONDUCTOR TECHNICAL DATA 1M x 1 CMOS Dynamic RAM Page Mode, Commercial and Industriai Temperature Range The MCM511000A is a 1.0^ CMOS high-speed dynamic random access memory. It is organized as 1,048,576 one-bit words and fabricated with CMOS siiicon-gate process technology. Advanced , fast successive data operations at all 2048 column locations on a selected row of the 1M dynamic RAM , . PF MOTOROLA DRAM M C M 5 1 1 0 0 0 A .M C M 5 1 L1000A 2-5 AC OPERATING CONDITIONS AND
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MCM511000A-70 MCM511000A-80 MCM511000AJ70 MCM511000AJ80 MCM51L1000AJ70 511000A 511000a-80 MCM51L1000A MCM51L1000A-70 MCM51L1OO0A-8O MCM51L1OOOA-80

30 pin 9-bit simm memory

Abstract: mcm514400 packages and four CMOS 1M x 1 DRAMs housed in 20/26 lead SOJ packages, mounted on a substrate along with a , , dynamic random access memory organized as 1,048,576 four-bit words and fabricated with CMOS silicon-gate , '¢ Consists of Sixteen 1M x 4 DRAMs, Eight 1M x 1 DRAMs, and Twenty Four 0.22 n.F (Min) Decoupling Capacitors , 1M dynamic RAM. Page mode operation consists of holding the RAS clock active while cycling the CAS , NOV 1 2 1990 MOTOROLA I SEMICONDUCTOR TECHNICAL DATA Order this data sheet by MCM36200/D
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30 pin 9-bit simm memory NP515 36L200 MCM36200S70 MCM36200SG70 MCM36200S80- MCM36200SG80 MCM36200S10
Abstract: MOTOROLA SEMICONDUCTOR TECHNICAL DATA MCM91430 1M x 9 Bit Dynamic Random Access Memory Module The MCM91430 is a 9M dynamic random access memory (DRAM) module orga nized as 1,048,576 x 9 bits. The , ) decoupling capacitor mounted adjacent to each DRAM. The MCM54400AN is a CMOS high-speed dynamic random access memory organized as 1,048,576 four-bit words and fabricated with CMOS silicon-gate process technology. · , ) MCM91430 5-70 MOTOROLA DRAM CAS BEFORE R Ä § REFRESH COUNTER TEST CYCLE M O TO R O LA D RAM -
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MCM91430-60 MCM91430-70 MCM91430S MCM91430L MCM91430SC 30-PIN
Abstract: MOTOROLA SEMICONDUCTOR TECHNICAL DATA MCM36100R8 Product Preview 1M x 36 Bit Dynamic Random , ,576 x 36 bits. The card is a JEDEC-standard Type 1, 88-pin DRAM card, consisting of eight low power MCM5L4400A DRAMs, mounted on a thin sub strate along with four 1M x 1 TSOP parity DRAMs, decoupling , Eight 1M x 4 DRAMs, Four 1M x 1 DRAMs, 0.22 |iF (Min) Decoupling Capacitors, and Input Buffers · F a s t , industry standard. The MCM5L4400A is a low power 0.7n CMOS high speed, dynamic random access memory -
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MCM36100R8-70 MCM36100R8-60 36100R860 36100R870

MC 5179

Abstract: MCM36100 DRAM SIMM MOTOROLA SEMICONDUCTOR TECHNICAL DATA 1M x 36 Bit Dynamic Random Access Memory Module The MCM36100 is a 36M dynamic random access memory (DRAM) module organized as 1,048,576 x36 bits. The module is , 300 mil SOJ packages and four CMOS 1M x 1 DRAMs housed in 20/26 lead SOJ packages, mounted on a , high-speed dynamic random access memory organized as 1,048,576 four-bit words and fabricated with CMOS , Cycle Refresh: 16 ms (Max) Consists of Eight 1M x 4 DRAMs, Four 1M x 1 DRAMs, and Twelve 0.22 pF (Min
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MC 5179 MCM36100 DRAM SIMM MCM54400A MCM36100-60 MCM36100-70 MCM36100ASH MCM36100AS6O MCM361OOAS70
Abstract: MOTOROLA SEMICONDUCTOR TECHNICAL DATA MCM54400A-V Advance Information 1M x 4 CMOS Dynamic RAM Fast Page Mode, 3.3 V Power Supply The M CM 54400A-V is a 0.7y CMOS high-speed dynamic random access memory. It is organized as 1,048,576 fou r-b it words and fabricated with CMOS sili con- gate , fast successive data operations at all 1024 colum n locations on a selected row of the 1M x 4 dynamic , tice . REV 1 10/95 MOTOROLA DRAM MCM54400A-V 2-145 ABSOLUTE MAXIMUM RATINGS (See Note -
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CM54400A-V80 MCM54400A-V80 MCM54400ANV80 MCM54400ANV80R2 MCM54400ATV80 MCM54400ATV80R2

91430

Abstract: TECHNICAL DATA 1M x 9 Bit Dynamic Random Access Memory Module The MCM91430 and MCM9L1430 are 9M dynamic random access memory (DRAM) modules organized as 1,048,576 x 9 bits. The modules are 30-lead single-in , adjacent to each DRAM. The MCM54400AN is a CMOS high-speed dynamic random access memory organized as 1,048 , - " @ -v a u d d a t a:@ >~K X X X X X X X MOTOROLA DRAM DATA MCM91430*MCM9L1430 5-83 M O TO , , coincident with or fol lowing CAS inactive transition. REFRESH CYCLES The dynamic RAM design is based on
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91430 MCM91430-80 9L1430 MCM91430L60 MCM91430L70 MCM91430L80 MCM9L1430L60
Abstract: MOTOROLA SEMICONDUCTOR TECHNICAL DATA MCM18200R8 Product Preview 2M x 18 Bit Dynamic Random Access Memory Card The MCM18200R8 is a 5 V DRAM Memory Card organized as two banks of 1,046,576 x 18 , DRAMs, mounted on a thin substrate along with four 1M x 1 TSOP parity DRAMs, decoupling capacitors, and , . The MCM5L4400A is a low power 0.7|j CMOS high speed, dynamic random access memory organized as 1,048 , , Four 1M x 1 DRAMs, 0.22 |iF (Min) Decoupling Capacitors, and Input Buffers « Fast Access Time (tRAC -
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MCM18200R8-60 MCM18200R8-70 MCM18200R860 MCM18200R870

motorola 68020 instruction set

Abstract: motorola 68020 manual Technology Ð Reduces system costs / needs less memory µ MOTOROLA Semiconductor Products Sector 1 , Frames 81 MCF5200 93 893 3 1 1Implemented Mnemonics x Addressing modes x Operand sizes , O N T R O L C Operand Exec Pipeline w Technology Ð 0.42µm TLM CMOS µ MOTOROLA , 2Q97 * Dhrystone 1.1 MIPS using Diab 3.6f compiler µ MOTOROLA Semiconductor Products Sector 1 , * Dhrystone 1.1 MIPS using Diab 3.6f compiler µ MOTOROLA Semiconductor Products Sector 1/97 25
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68LC060 MCF5267 motorola 68020 instruction set motorola 68020 manual 68EC030 motorola XCF5102 68EC030 ColdFire v5 MC680 MPC60 MC683 100MH 140MH 68020/CPU32

MCM511000AP70

Abstract: mcm511000aj70 MOTOROLA SC (MEI10RY/ASIC ) SflE D fc>3b7251 Üfl77c 14 1 T 3 IM0T3 r MOTOROLA t rtA riim a m Order this documemby MCM511000A/D " SEMICONDUCTOR TECHNICAL DATA 1M x 1 CMOS Dynamic RAM Page Mode, Commercial and Industrial Temperature Range The MCM511000A is a 1.0|i CMOS high-speed dynamic random access memory. It is organized as 1,048,576 one-bit words and fabricated , locations on a selected row of the 1M dynamic RAM. Read access time in page mode (t C A C ) 's typically
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MCM511000AP70 MCM511000AP80 mcm511000aj MCM511000AZ80 MCM511 MCM51L1000A-80 1ATX23025-3

MCM44400BN70

Abstract: 822B-01 Information MCM44400B MCM4L4400B 1M x 4 CMOS Dynamic RAM Fast Page Mode The MCM44400B is a 0.8µ CMOS high­speed dynamic random access memory. It is organized as 1,048,576 four­bit words and fabricated with , 1M x 4 dynamic RAM. Read access time in page mode (tCAC) is typically half the regular RAS clock , variations in addressing the 1M x 4 RAM: RAS­only refresh cycle, CAS before RAS refresh cycle, and page , . Specifications and information herein are subject to change without notice. REV 1 10/95 © Motorola, Inc
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MCM44400BN70 822B MCM44400BN60 MCM44400BN80 MCM4L4400BN60 MCM44400B/D

MCM44400CN60

Abstract: MCM44400CN70 Information MCM44400C MCM4L4400C 1M x 4 CMOS Dynamic RAM Fast Page Mode The MCM44400C is a 0.8µ CMOS high­speed dynamic random access memory. It is organized as 1,048,576 four­bit words and fabricated with , all 1024 column locations on a selected row of the 1M x 4 dynamic RAM. Read access time in page mode , generating the CAS clock. There are three other variations in addressing the 1M x 4 RAM: RAS­only refresh , MOTOROLA DRAM MCM44400C·MCM4L4400C 1 BLOCK DIAGRAM DQ0 ­ DQ3 W DATA IN BUFFER RAS
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MCM44400CN60 MCM44400CN70 ASC CAPACITOR MCM44400CN80 MCM4L4400CN60 MCM44400C/D

MCM64400BN50

Abstract: MCM64400BN60 Information MCM64400B MCM6L4400B 1M x 4 CMOS Dynamic RAM Fast Page Mode The MCM64400B is a 0.65µ CMOS high­speed dynamic random access memory. It is organized as 1,048,576 four­bit words and fabricated with , column locations on a selected row of the 1M x 4 dynamic RAM. Read access time in page mode (tCAC) is , generating the CAS clock. There are three other variations in addressing the 1M x 4 RAM: RAS­only refresh , without notice. 7/96 © Motorola, Inc. 1996 MOTOROLA DRAM MCM64400B·MCM6L4400B 1 BLOCK
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MCM64400BN50 MCM64400BN60 MCM64400BN70 MCM6L4400BN50 K6010 MCM64400B/D MCM6L400B
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