S19263EJ3V0UM00 S19263EJ3V0UM M8E0904E MC-10118A S19657E PD77630A S19686E - Datasheet Archive

 

Old Company Name in Catalogs and Other Documents On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology

 

To our customers, Old Company Name in Catalogs and Other Documents On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid Renesas Electronics document. We appreciate your understanding. Renesas Electronics website: http://www.renesas.com April 1st, 2010 Renesas Electronics Corporation Issued by: Renesas Electronics Corporation (http://www.renesas.com) Send any inquiries to http://www.renesas.com/inquiry. Notice 1. 2. 3. 4. 5. 6. 7. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website. Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or technical information described in this document. No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or others. You should not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product, whether in whole or in part. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for the incorporation of these circuits, software, and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information. When exporting the products or technology described in this document, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations. You should not use Renesas Electronics products or the technology described in this document for any purpose relating to military applications or use by the military, including but not limited to the development of weapons of mass destruction. Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. Renesas Electronics has used reasonable care in preparing the information included in this document, but Renesas Electronics does not warrant that such information is error free. Renesas Electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein. Renesas Electronics products are classified according to the following three quality grades: "Standard", "High Quality", and "Specific". The recommended applications for each Renesas Electronics product depends on the product's quality grade, as indicated below. You must check the quality grade of each Renesas Electronics product before using it in a particular application. You may not use any Renesas Electronics product for any application categorized as "Specific" without the prior written consent of Renesas Electronics. Further, you may not use any Renesas Electronics product for any application for which it is not intended without the prior written consent of Renesas Electronics. Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for an application categorized as "Specific" or for which the product is not intended where you have failed to obtain the prior written consent of Renesas Electronics. The quality grade of each Renesas Electronics product is "Standard" unless otherwise expressly specified in a Renesas Electronics data sheets or data books, etc. "Standard": 8. 9. 10. 11. 12. Computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic equipment; and industrial robots. "High Quality": Transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anticrime systems; safety equipment; and medical equipment not specifically designed for life support. "Specific": Aircraft; aerospace equipment; submersible repeaters; nuclear reactor control systems; medical equipment or systems for life support (e.g. artificial life support devices or systems), surgical implantations, or healthcare intervention (e.g. excision, etc.), and any other applications or purposes that pose a direct threat to human life. You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas Electronics shall have no liability for malfunctions or damages arising out of the use of Renesas Electronics products beyond such specified ranges. Although Renesas Electronics endeavors to improve the quality and reliability of its products, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Further, Renesas Electronics products are not subject to radiation resistance design. Please be sure to implement safety measures to guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas Electronics product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product. Please use Renesas Electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive. Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of Renesas Electronics. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products, or if you have any other inquiries. (Note 1) "Renesas Electronics" as used in this document means Renesas Electronics Corporation and also includes its majorityowned subsidiaries. (Note 2) "Renesas Electronics product(s)" means any product developed or manufactured by or for Renesas Electronics. User's Manual Multimedia Processor for Mobile Applications Image Composer EMMA MobileTM1 Document No. S19263EJ3V0UM00 S19263EJ3V0UM00 (3rd edition) Date Published September 2009 2008 Printed in Japan [MEMO] 2 User's Manual S19263EJ3V0UM S19263EJ3V0UM NOTES FOR CMOS DEVICES 1 VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (MAX) and VIH (MIN). 2 HANDLING OF UNUSED INPUT PINS Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must be judged separately for each device and according to related specifications governing the device. 3 PRECAUTION AGAINST ESD A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. Environmental control must be adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work benches and floors should be grounded. The operator should be grounded using a wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with mounted semiconductor devices. 4 STATUS BEFORE INITIALIZATION Power-on does not necessarily define the initial status of a MOS device. Immediately after the power source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the reset signal is received. A reset operation must be executed immediately after power-on for devices with reset functions. 5 POWER ON/OFF SEQUENCE In the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. When switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. Use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. The correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. 6 INPUT OF SIGNAL DURING POWER OFF STATE Do not input signals or an I/O pull-up power supply while the device is not powered. The current injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. Input of signals during the power off state must be judged separately for each device and according to related specifications governing the device. User's Manual S19263EJ3V0UM S19263EJ3V0UM 3 The names of other companies and products are the registered trademarks or trademarks of the respective company. · The information in this document is current as of September, 2009. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. · No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may appear in this document. · NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others. · Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. · While NEC Electronics endeavors to enhance the quality and safety of NEC Electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. In addition, NEC Electronics products are not taken measures to prevent radioactive rays in the product design. When customers use NEC Electronics products with their products, customers shall, on their own responsibility, incorporate sufficient safety measures such as redundancy, fire-containment and anti-failure features to their products in order to avoid risks of the damages to property (including public or social property) or injury (including death) to persons, as the result of defects of NEC Electronics products. · NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to NEC Electronics products developed based on a customerdesignated "quality assurance program" for a specific application. The recommended applications of an NEC Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of each NEC Electronics product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to determine NEC Electronics' willingness to support a given application. (Note) (1) "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its majority-owned subsidiaries. (2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as defined above). M8E0904E M8E0904E 4 User's Manual S19263EJ3V0UM S19263EJ3V0UM PREFACE Readers This manual is intended for hardware/software application system designers who wish to understand and use the image composer functions of EMMA Mobile1 (EM1), a multimedia processor for mobile applications. Purpose This manual is intended to explain to users the hardware and software functions of the image composer of EM1, and be used as a reference material for developing hardware and software for systems that use EM1. Organization This manual consists of the following chapters. Chapter 1 Overview Chapter 2 Registers Chapter 3 How to Read This Manual Description of functions Appendix A Terminology It is assumed that the readers of this manual have general knowledge of electricity, logic circuits, and microcontrollers. To understand the functions of the image composer of EM1 in detail Read this manual according to the CONTENTS. To understand the other functions of EM1 Refer to the user's manual of the respective module. To understand the electrical specifications of EM1 Conventions Refer to the Data Sheet. Data significance: Higher digits on the left and lower digits on the right Note: Footnote for item marked with Note in the text Caution: Information requiring particular attention Remark: Supplementary information Numeric representation: Binary . xxxx or xxxxB Decimal . xxxx Hexadecimal . xxxxH Data type: Word . 32 bits Halfword . 16 bits Byte User's Manual S19263EJ3V0UM S19263EJ3V0UM . 8 bits 5 Related Documents The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Document Name Document No. MC-10118A MC-10118A Data sheet S19657E S19657E PD77630A PD77630A Data sheet S19686E S19686E User's manual Audio/Voice and PWM Interfaces S19253E S19253E DDR SDRAM Interface S19254E S19254E DMA Controller S19255E S19255E 2 I C Interface S19256E S19256E ITU-R BT.656 Interface S19257E S19257E LCD Controller S19258E S19258E MICROWIRE S19259E S19259E NAND Flash Interface S19260E S19260E SPI S19261E S19261E UART Interface S19262E S19262E Image Composer S19264E S19264E System Control/General-Purpose I/O Interface S19265E S19265E Timer S19266E S19266E Terrestrial Digital TV Interface S19267E S19267E Camera Interface S19285E S19285E USB Interface S19359E S19359E SD Memory Card Interface S19361E S19361E PDMA S19373E S19373E One Chip (MC-10118A MC-10118A) S19598E S19598E One Chip (PD77630A PD77630A) Caution This manual Image Processor Unit S19687E S19687E The related documents listed above are subject to change without notice. Be sure to use the latest version of each document when designing. 6 User's Manual S19263EJ3V0UM S19263EJ3V0UM CONTENTS CHAPTER 1 OVERVIEW.10 1.1 General.10 1.2 Features .10 1.3 Function Block Diagram .11 CHAPTER 2 REGISTERS .12 2.1 Registers.12 2.2 Register Functions .16 2.2.1 Control register .16 2.2.2 Update reserve register.18 2.2.3 Startup register .19 2.2.4 Status register.21 2.2.5 CPU double buffer control register .22 2.2.6 Gamma correction control register .23 2.2.7 Gamma correction table address register . 24 2.2.8 Gamma correction table data register . 25 2.2.9 Display area address register .26 2.2.10 Address addition value register.27 2.2.11 Format register.28 2.2.12 WB image size register .29 2.2.13 Horizontal/vertical flip setting register.30 2.2.14 Y gain offset register .31 2.2.15 U (V) gain offset registers .32 2.2.16 YUV2RGB conversion mode register. 33 2.2.17 Custom coefficient registers.34 2.2.18 Layer control registers.36 2.2.19 Layer format registers .37 2.2.20 Transparent color control registers .38 2.2.21 Layer transparent color registers . 39 2.2.22 Alpha registers .40 2.2.23 Resize registers .41 2.2.24 Address addition value registers .42 2.2.25 Buffer start address registers .43 2.2.26 Layer display position registers.44 2.2.27 Layer display size registers.45 2.2.28 Layer 2 double buffer control registers. 46 2.2.29 Layer 2 byte lane registers.47 2.2.30 Layer 2 horizontal/vertical flip control registers . 50 2.2.31 ARGB4444 ARGB4444 mode register .51 2.2.32 Interrupt setting registers .52 CHAPTER 3 DESCRIPTION OF FUNCTIONS .59 3.1 Image Formats .59 3.1.1 Supported image formats.59 User's Manual S19263EJ3V0UM S19263EJ3V0UM 7 3.1.2 Conversion rule .61 3.1.3 Gain and offset adjustment .61 3.1.4 YUV-to-RGB conversion .61 3.1.5 Dithering.62 3.2 Image Synthesis Function .64 3.2.1 Layer definition .64 3.2.2 Transparent colors (key color).66 3.2.3 Alpha blending .67 3.2.4 Image flip.68 3.2.5 Simple resizing .68 3.2.6 Double buffer.69 3.2.7 ARGB4444 ARGB4444 format .70 3.3 Gamma Correction Function .71 3.3.1 Gamma correction.71 3.3.2 Usage of gamma correction function.72 3.4 Operation Timing .73 3.4.1 LCD interface .73 3.4.2 Register update .75 APPENDIX A TERMINOLOGY. 76 8 User's Manual S19263EJ3V0UM S19263EJ3V0UM LIST OF FIGURES Figure No. Title Page Figure 1-1. Function Block Diagram.11 Figure 2-1. Status Transition.20 Figure 2-2. Flipping of Images .30 Figure 3-1. Frame Buffer Definition.59 Figure 3-2. Color Masking by Dithering.63 Figure 3-3. Layer Definition.64 Figure 3-4. Duplicated Setting of Layers at the Same Depth .64 Figure 3-5. Transparent Color Function .66 Figure 3-6. Alpha Blending .67 Figure 3-7. Operation When Image Flipping Is Enabled .68 Figure 3-8. Operation When Simple Resizing Is Enabled .68 Figure 3-9. Operation When Double Buffer Function Is Enabled .69 Figure 3-10. Gamma Correction Tables.71 Figure 3-11. Gamma Correction .72 Figure 3-12. Startup Timing Between IMC and LCD Controller .73 Figure 3-13. Timing of Display Data Interface Between IMC and LCD Controller.74 Figure 3-14. Relationship Between Update Register and V-Sync/Update Target Registers.75 LIST OF TABLES Table No. Title Page Table 2-1. Interrupts.52 Table 3-1. Formats Supported by IMC.59 Table 3-2. Format Selectable for Each Layer .60 Table 3-3. Formats and Start Address Setting Registers.60 Table 3-4. Format Conversion Rules .61 Table 3-5. Gain/Offset Adjustment Register .61 Table 3-6. Dithering Table Values.62 Table 3-7. Probability of Dithering Error Dispersion .62 Table 3-8. Setting Parameters .65 Table 3-9. Transparent Color Setting Registers.66 Table 3-10. Alpha Blending Setting Registers.67 User's Manual S19263EJ3V0UM S19263EJ3V0UM 9 CHAPTER 1 OVERVIEW 1.1 General The image composer (IMC) generates images to be displayed in the LCD by the LCD controller. 1.2 Features The main features of the IMC are as follows. Supported image size Horizontal direction: Up to 2,046 pixels Vertical direction: Up to 2,046 lines Data format Input: RGB565 RGB565, RGB666 RGB666, ARGB4444 ARGB4444, YUV422Note 1, YUV420Note 2 Output: RGB565 RGB565, RGB666 RGB666 YUV-to-RGB conversion, dithering, gain offset Gain and offset can be adjusted for YUV components, from 0 to x2 When the input data format is YUV, RGB conversion can be performed with two types of coefficients Dithering by using 2 × 2 matrix upon subtracting colors for converting images into RGB666 RGB666 Overlay function Up to four layers can be synthesized. (Features of each layer are described later.) Position and size of synthesized planes can be set flexibly. Each layer can be defined independently in two dimensions, and formatting, mirror flipping, resizing, double buffering, and gain/offset adjustment can be set separately. (Whether this function is supported varies in each layer.) Transparent color and alpha blending can be used for the two front layers. Gamma adjustment by table referencing Notes 1. The YUV422 YUV422 format has three storage methods: Pixel Interleave, in which 2-pixel data (Y component × 2, U component × 1, V component × 1) is stored as a set of one word, Semi-Planar, in which Y components are stored as a plane and UV components are stored as a plane, and Planar, in which YUV components are stored as three respective planes. 2. The YUV420 YUV420 format has two storage methods: Semi-Planar, in which Y components are stored as a plane and UV components are stored as a plane and Planar, in which YUV components are stored as three respective planes. 10 User's Manual S19263EJ3V0UM S19263EJ3V0UM CHAPTER 1 OVERVIEW 1.3 Function Block Diagram Figure 1-1. Function Block Diagram IMC Clock Reset APB I/F system bus 2nd reg. All internal units APB Clock CLKCONT Data buffer Front controller Layer MIX Middle controller AXI AXI I/F Gain/Offset YUV2RGB Back controller Output FIFO AHB AHBW I/F LCD macro interface Local bus Gamma transfer Data to LCD User's Manual S19263EJ3V0UM S19263EJ3V0UM 11 CHAPTER 2 REGISTERS The IMC registers can be accessed via the APB bus only in 32-bit (word) units. 2.1 Registers Base address: 4026_0000H 0000H Caution Among addresses 4026_0000H 0000H to 4026_FFFCH, the addresses not listed in the following tables are reserved. Write accessing reserved areas is prohibited. An undefined value is returned for read access. (1/4) Address Register Name Symbol R/W Frame Sync After Reset Function setting registers 0000H 0000H Control register IMC_CONTROL R/W × 0000_0000H 0000H 0004H 0004H Update reserve register IMC_REFRESH R/W 0000_0000H 0000H R/W 0000_0000H 0000H R 0000_0000H 0000H Image synthesis startup registers 0010H 0010H Startup register IMC_START 0014H 0014H Status register IMC_STATUS 0018H 0018H CPU double buffer control register IMC_CPUBUFSEL R/W 0000_0000H 0000H Gamma correction registers 0020H 0020H Gamma correction control register IMC_GAMMA_EN R/W × 0000_0000H 0000H 0024H 0024H Gamma correction table address register IMC_GAMMA_ADR R/W × 0000_0000H 0000H 0028H 0028H Gamma correction table data register IMC_GAMMA_DATA R/W × 0000_0000H 0000H Registers for settings for immediate startup 0040H 0040H Display area address register IMC_WB_AREAADR R/W × 0000_0000H 0000H 0044H 0044H Address addition value register IMC_WB_HOFFSET R/W × 0000_0000H 0000H 0048H 0048H Format register IMC_WB_FORMAT R/W × 0000_0000H 0000H 004CH 004CH WB image size register IMC_WB_SIZE R/W × 0000_0000H 0000H Registers for setting common items to all layers 0100H 0100H Horizontal/vertical flip setting register IMC_MIRROR R/W 0000_0000H 0000H 0104H 0104H Y gain offset register IMC_YGAINOFFSET R/W × 0000_0080H 0080H 0108H 0108H U gain offset register IMC_UGAINOFFSET R/W × 0000_0080H 0080H 010CH 010CH V gain offset register IMC_VGAINOFFSET R/W × 0000_0080H 0080H 0110H 0110H YUV2RGB conversion mode register IMC_YUV2RGB R/W × 0000_0000H 0000H 0114H 0114H Custom coefficient register (Coef R0) IMC_COEF_R0 R/W × 0000_0000H 0000H 0118H 0118H Custom coefficient register (Coef R1) IMC_COEF_R1 R/W × 0000_0000H 0000H 011CH 011CH Custom coefficient register (Coef R2) IMC_COEF_R2 R/W × 0000_0000H 0000H 0120H 0120H Custom coefficient register (Coef R3) IMC_COEF_R3 R/W × 0000_0000H 0000H 0124H 0124H Custom coefficient register (Coef G0) IMC_COEF_G0 R/W × 0000_0000H 0000H 0128H 0128H Custom coefficient register (Coef G1) IMC_COEF_G1 R/W × 0000_0000H 0000H 12 User's Manual S19263EJ3V0UM S19263EJ3V0UM CHAPTER 2 REGISTERS (2/4) Address Register Name Symbol R/W Frame Sync After Reset Registers for setting common items to all layers 012CH 012CH Custom coefficient register (Coef G2) IMC_COEF_G2 R/W 0000_0000H 0000H 0130H 0130H Custom coefficient register (Coef G3) IMC_COEF_G3 R/W 0000_0000H 0000H 0134H 0134H Custom coefficient register (Coef B0) IMC_COEF_B0 R/W 0000_0000H 0000H 0138H 0138H Custom coefficient register (Coef B1) IMC_COEF_B1 R/W 0000_0000H 0000H 013CH 013CH Custom coefficient register (Coef B2) IMC_COEF_B2 R/W 0000_0000H 0000H 0140H 0140H Custom coefficient register (Coef B3) IMC_COEF_B3 R/W 0000_0000H 0000H Layer 0 setting registers 0200H 0200H Layer 0 control register IMC_L0_CONTROL R/W 0000_0000H 0000H 0204H 0204H Layer 0 format register IMC_L0_FORMAT R/W 0000_0000H 0000H 0210H 0210H Layer 0 transparent color control register IMC_L0_KEYENABLE R/W 0000_0000H 0000H 0214H 0214H Layer 0 transparent color register IMC_L0_KEYCOLOR R/W × 0000_0000H 0000H 0218H 0218H Layer 0 alpha register IMC_L0_ALPHA R/W 0000_0000H 0000H 0220H 0220H Layer 0 resize register IMC_L0_RESIZE R/W 0000_0000H 0000H 0230H 0230H Layer 0 address addition value register IMC_L0_OFFSET R/W 0000_0000H 0000H 0234H 0234H Layer 0 start address register IMC_L0_FRAMEADR R/W 0000_0000H 0000H 0250H 0250H Layer 0 display position register IMC_L0_POSITION R/W 0000_0000H 0000H 0254H 0254H Layer 0 display size register IMC_L0_SIZE R/W 0000_0000H 0000H R/W 0000_0000H 0000H Layer 1A setting registers 0300H 0300H Layer 1A control register IMC_L1A_CONTROL 0304H 0304H Layer 1x format register IMC_L1X_FORMAT R/W 0000_0000H 0000H 0310H 0310H Layer 1A transparent color control register IMC_L1A_KEYENABLE R/W 0000_0000H 0000H 0314H 0314H Layer 1x transparent color register IMC_L1X_KEYCOLOR R/W 0000_0000H 0000H 0318H 0318H Layer 1A alpha register IMC_L1A_ALPHA R/W 0000_0000H 0000H 0320H 0320H Layer 1x resize register IMC_L1X_RESIZE R/W 0000_0000H 0000H 0330H 0330H Layer 1x address addition value register IMC_L1X_OFFSET R/W 0000_0000H 0000H 0334H 0334H Layer 1A start address register IMC_L1A_FRAMEADR R/W 0000_0000H 0000H 0350H 0350H Layer 1A display position register IMC_L1A_POSITION R/W 0000_0000H 0000H 0354H 0354H Layer 1A display size register IMC_L1A_SIZE R/W 0000_0000H 0000H Layer 1B setting registers 0400H 0400H Layer 1B control register IMC_L1B_CONTROL R/W 0000_0000H 0000H 0410H 0410H Layer 1B transparent color control register IMC_L1B_KEYENABLE R/W 0000_0000H 0000H 0418H 0418H Layer 1B alpha register IMC_L1B_ALPHA R/W 0000_0000H 0000H 0434H 0434H Layer 1B start address register IMC_L1B_FRAMEADR R/W 0000_0000H 0000H 0450H 0450H Layer 1B display position register IMC_L1B_POSITION R/W 0000_0000H 0000H 0454H 0454H Layer 1B display size register IMC_L1B_SIZE R/W 0000_0000H 0000H User's Manual S19263EJ3V0UM S19263EJ3V0UM 13 CHAPTER 2 REGISTERS (3/4) Address Register Name Symbol R/W Frame Sync After Reset Layer 1C setting registers 0500H 0500H Layer 1C control register IMC_L1C_CONTROL R/W 0000_0000H 0000H 0510H 0510H Layer 1C transparent color control register IMC_L1C_KEYENABLE R/W 0000_0000H 0000H 0518H 0518H Layer 1C alpha register IMC_L1C_ALPHA R/W 0000_0000H 0000H 0534H 0534H Layer 1C start address register IMC_L1C_FRAMEADR R/W 0000_0000H 0000H 0550H 0550H Layer 1C display position register IMC_L1C_POSITION R/W 0000_0000H 0000H 0554H 0554H Layer 1C display size register IMC_L1C_SIZE R/W 0000_0000H 0000H Layer 2A setting registers 0600H 0600H Layer 2A control register IMC_L2A_CONTROL R/W 0000_0000H 0000H 0604H 0604H Layer 2A format register IMC_L2A_FORMAT R/W 0000_0000H 0000H 0608H 0608H Layer 2A double buffer control register IMC_L2A_BUFSEL R/W 0000_0000H 0000H 060CH 060CH Layer 2A byte lane register IMC_L2A_BYTELANE R/W 0000_E4E4H 0620H 0620H Layer 2A resize register IMC_L2A_RESIZE R/W 0000_0000H 0000H 0624H 0624H Layer 2A horizontal/vertical flip control IMC_L2A_MIRROR R/W 0000_0000H 0000H register 0630H 0630H Layer 2A address addition value register IMC_L2A_OFFSET R/W 0000_0000H 0000H 0634H 0634H Layer 2A start address register (YP) IMC_L2A_FRAMEADR_YP R/W 0000_0000H 0000H 0638H 0638H Layer 2A start address register (UP) IMC_L2A_FRAMEADR_UP R/W 0000_0000H 0000H 063CH 063CH Layer 2A start address register (VP) IMC_L2A_FRAMEADR_VP R/W 0000_0000H 0000H 0640H 0640H Layer 2A start address register (YQ) IMC_L2A_FRAMEADR_YQ R/W 0000_0000H 0000H 0644H 0644H Layer 2A start address register (UQ) IMC_L2A_FRAMEADR_UQ R/W 0000_0000H 0000H 0648H 0648H Layer 2A start address register (VQ) IMC_L2A_FRAMEADR_VQ R/W 0000_0000H 0000H 0650H 0650H Layer 2A display position register IMC_L2A_POSITION R/W 0000_0000H 0000H 0654H 0654H Layer 2A display size register IMC_L2A_SIZE R/W 0000_0000H 0000H Layer 2B setting registers 0700H 0700H Layer 2B control register IMC_L2B_CONTROL R/W 0000_0000H 0000H 0704H 0704H Layer 2B format register IMC_L2B_FORMAT R/W 0000_0000H 0000H 0708H 0708H Layer 2B double buffer control register IMC_L2B_BUFSEL R/W 0000_0000H 0000H 070CH 070CH Layer 2B byte lane register IMC_L2B_BYTELANE R/W 0000_E4E4H 0720H 0720H Layer 2B resize register IMC_L2B_RESIZE R/W 0000_0000H 0000H Layer 2B horizontal/vertical flip control IMC_L2B_MIRROR R/W 0000_0000H 0000H 0724H 0724H register 0730H 0730H Layer 2B address addition value register IMC_L2B_OFFSET R/W 0000_0000H 0000H 0734H 0734H Layer 2B start address register (YP) IMC_L2B_FRAMEADR_YP R/W 0000_0000H 0000H 0738H 0738H Layer 2B start address register (UP) IMC_L2B_FRAMEADR_UP R/W 0000_0000H 0000H 073CH 073CH Layer 2B start address register (VP) IMC_L2B_FRAMEADR_VP R/W 0000_0000H 0000H 0740H 0740H Layer 2B start address register (YQ) IMC_L2B_FRAMEADR_YQ R/W 0000_0000H 0000H 0744H 0744H Layer 2B start address register (UQ) IMC_L2B_FRAMEADR_UQ R/W 0000_0000H 0000H 0748H 0748H Layer 2B start address register (VQ) IMC_L2B_FRAMEADR_VQ R/W 0000_0000H 0000H 0750H 0750H Layer 2B display position register IMC_L2B_POSITION R/W 0000_0000H 0000H 0754H 0754H Layer 2B display size register IMC_L2B_SIZE R/W 0000_0000H 0000H 14 User's Manual S19263EJ3V0UM S19263EJ3V0UM CHAPTER 2 REGISTERS (4/4) Address Register Name Symbol R/W Frame Sync After Reset Layer BG setting registers 0804H 0804H Layer BG format register IMC_BG_FORMAT R/W 0000_0000H 0000H 0820H 0820H Layer BG resize register IMC_BG_RESIZE R/W 0000_0000H 0000H 0830H 0830H Layer BG address addition value register IMC_BG_OFFSET R/W 0000_0000H 0000H 0834H 0834H Layer BG start address register IMC_BG_FRAMEADR R/W 0000_0000H 0000H IMC_ARGBMODE R/W 0000_0000H 0000H Special register 1000H 1000H ARGB4444 ARGB4444 mode register Interrupt control registers 0900H 0900H Interrupt status register IMC_INTSTATUS R 0000_0000H 0000H 0904H 0904H Interrupt raw status register IMC_INTRAWSTATUS R 0000_0000H 0000H 0908H 0908H Interrupt enable set register IMC_INTENSET R/W 0000_0000H 0000H 090CH 090CH Interrupt enable clear register IMC_INTENCLR W 0000_0000H 0000H 0910H 0910H Interrupt source clear register IMC_INTFFCLR W 0000_0000H 0000H 0914H 0914H AHBR error address register IMC_AHBRERRADR R/W 0000_0000H 0000H 0918H 0918H AHBW error address register IMC_AHBWERRADR R/W 0000_0000H 0000H Registers marked with in the Frame Sync column are registers with which setting changes made in the register take effect when the frame start signal is received from the LCD controller (V-sync register). Registers marked with are registers with which setting changes made in the register take effect when the frame start signal is received from the LCD controller while the update reserve register is set (update target register). Registers marked with × are registers with which setting changes made in the register take effect immediately (immediately-reflected register). Changing the settings during macro operation is prohibited. When the IMC operates in immediate startup mode, startup by setting the startup register is regarded as the request for frame transmission start from the LCD controller, and register values are updated. When a two-stage register is read, the values of the first-stage register (values to be updated at the next frame) are read out. For details on the update register, see 0 3.4.2 Register update. User's Manual S19263EJ3V0UM S19263EJ3V0UM 15 CHAPTER 2 REGISTERS 2.2 Register Functions 2.2.1 Control register This register (IMC_CONTROL: 4026_0000H 0000H) sets the basic IMC operation. This is an immediately-reflected register, so changing the settings during operation (STATUS bit of IMC_STATUS register 0) is prohibited. 31 30 29 28 27 23 25 24 19 18 17 16 11 10 9 8 1 0 FORMAT DBGMODE 26 STARTMODE Reserved 22 21 20 Reserved 15 14 13 12 Reserved 7 CLKCNT 6 5 4 3 2 Reserved Name R/W Bit After Reset DBGMODE R/W 31 0 Function Sets the priority for supplying synthesized data to the LCD controller (with WB) 0: Availability of FIFO in LCD controller (IMC overrun is more likely to occur) 1: Availability of FIFO in LCD controller and transmit FIFO in IMC (IMC underrun is more likely to occur) Reserved R 30:13 0 Reserved. When these bits are read, 0 is returned for each bit. CLKCNT R/W 12:8 0 Enables the automatic clock control function in the IMC. 0: Disable (Clock is constantly supplied while the IMC is operating.) 1: Enable (Automatic clock control implemented in frame units.) Bit Block Clock stop condition bit 8 Front control When Layer 0 not used bit 9 Middle control When Layer 1x not used bit 10 Y2R When YUV format not used bit 11 Gamma correction When Gamma correction function not used bit 12 Write Back When writeback function not used Reserved R 7:2 0 Reserved. When these bits are read, 0 is returned for each bit. FORMAT R 1 0 Indicates the data format set by the LCD controller. 0: RGB666 RGB666 1: RGB565 RGB565 (IMC output format in LCD-synchronous mode) STARTMODE R/W 0 0 Sets the IMC startup mode. 0: LCD-synchronous mode (started by request from LCD controller) 1: Immediate startup mode (started by IMC_START register) 16 User's Manual S19263EJ3V0UM S19263EJ3V0UM CHAPTER 2 REGISTERS When using the IMC with the settings made in the LCD controller, the startup signal is sent at the beginning of a frame transferred between the LCD controller and IMC. If STARTMODE = 0 in the IMC, the IMC starts operation at this timing. User's Manual S19263EJ3V0UM S19263EJ3V0UM 17 CHAPTER 2 REGISTERS 2.2.2 Update reserve register This register (IMC_REFRESH: 4026_0004H 0004H) is used to reflect the values set to the update target registers (registers marked with in the Frame Sync column in the register list) in the IMC, to the internal operation. 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 Reserved 23 22 21 20 Reserved 15 14 13 12 Reserved 7 6 5 4 Reserved Name UPDATE R/W Bit After Reset Function Reserved R 31:1 0 Reserved. When these bits are read, 0 is returned for each bit. UPDATE R/W 0 0 Used to reserve register updates. 0: Does not update. 1: Update reserved. An update end interrupt is issued when the register is updated. (The interrupt is issued immediately if the IMC has been started immediately while update reservation is set, or when the next frame begins if the IMC has been started in synchronization with the LCD controller.) The UPDATE bit is automatically cleared to 0 at the same time as update. Refer to 0 3.4.2 Register update for details on the circuit structure. 18 User's Manual S19263EJ3V0UM S19263EJ3V0UM CHAPTER 2 REGISTERS 2.2.3 Startup register This register (IMC_START: 4026_0010H 0010H) is used to start the IMC in immediate startup mode (single startup). This is a V-sync register. 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 Reserved 23 22 21 20 Reserved 15 14 13 12 Reserved 7 6 5 4 Reserved Name IMCSTART R/W Bit After Reset Function Reserved R 31:1 0 Reserved. When these bits are read, 0 is returned for each bit. IMCSTART W 0 0 Starts the IMC in immediate startup mode (STARTMODE = 1). 1: Startup When the STARTMODE bit of the control register (IMC_CONTROL) is set to 0 (LCD-synchronous operation), the setting of this register is ignored and the IMC is started in synchronization with the LCD operation. If this register is set to 1 while the STARTMODE bit is 1 (immediate startup), the IMC performs synthesis processing for one plane and stops automatically. Writing to this register is ignored when the IMC cannot start, such as when the IMC is in the LCD-synchronous mode or being operating. User's Manual S19263EJ3V0UM S19263EJ3V0UM 19 CHAPTER 2 REGISTERS Figure 2-1. Status Transition Transit timing Transits in sync with frame Transits immediately STATUS = 0 Transits automatically after processing of one frame is completed Stop STARTMODE = 0 Started via LCD STARTMODE = 0 Stopped via LCD Sync with LCD STATUS = 1 or 2 (Depends on whether data is written back) STARTMODE = 1 IMCSTART = 1 Sync with LCD STARTMODE 0: In sync with LCD STATUS = 3 Single startup Single Startup 1: Immediately Start trigger Setting IMC_START register Constantly supplied Not supplied Write back operation 20 V-sync signal from LCD Supply to LCD Request from LCD Constantly supplied User's Manual S19263EJ3V0UM S19263EJ3V0UM CHAPTER 2 REGISTERS 2.2.4 Status register This register (IMC_STATUS: 4026_0014H 0014H) indicates the IMC operating status. The IMC operating status can be checked by reading this register. This is a V-sync register. 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 Reserved 23 22 21 20 Reserved 15 14 13 12 Reserved 7 6 5 4 Reserved Name R/W Bit After Reset Reserved R 31:2 0 STATUS R 1:0 0 STATUS Function Reserved. When these bits are read, 0 is returned for each bit. Indicates the IMC operating status. 00: Stopped 01: Supplying display data to the LCD controller (without WB). 10: Supplying display data to the LCD controller (with WB) 11: Operating in single startup mode (WB only). User's Manual S19263EJ3V0UM S19263EJ3V0UM 21 CHAPTER 2 REGISTERS 2.2.5 CPU double buffer control register This register (IMC_CPUBUFSEL: 4026_0018H 0018H) switches buffers P and Q when double buffer of layers 2A and 2B is controlled by the CPU. The setting of this register is applied to both layers 2A and 2B. This is a V-sync register whose setting is reflected internally in synchronization with frame reception. It is not an update target register. 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 Reserved 23 22 21 20 Reserved 15 14 13 12 Reserved 7 6 5 4 Reserved Name BUFSEL R/W Bit After Reset Function Reserved R 31:1 0 Reserved. When these bits are read, 0 is returned for each bit. BUFSEL R/W 0 0 Selects buffer P or Q when double buffer of layers 2A and 2B is controlled by the CPU. 0: Buffer P 1: Buffer Q This setting is ignored when double buffer of layers 2A and 2B is controlled in A/B-fixed mode. 22 User's Manual S19263EJ3V0UM S19263EJ3V0UM CHAPTER 2 REGISTERS 2.2.6 Gamma correction control register This register (IMC_GAMMA_EN: 4026_0020H 0020H) controls the gamma correction function. This is an immediatelyreflected register, and changing the settings is prohibited while the IMC is operating. For details on the gamma correction function, see 3.3 Gamma Correction Function. 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 Reserved 23 22 21 20 Reserved 15 14 13 12 Reserved 7 6 5 4 Reserved Name Reserved GAMMAEN GAMMAEN R/W Bit After Reset Function R 31:1 0 Reserved. When these bits are read, 0 is returned for each bit. R/W 0 0 Sets whether to enable gamma correction. 0: Disables gamma correction 1: Enables gamma correction The gamma correction table values can be changed only when this register is set to 0. Before setting the gamma correction table values, set bit 11 (gamma correction CLK control) of the control register (IMC_CONTROL) to 0 (automatic control disabled, CLK constantly supplied). User's Manual S19263EJ3V0UM S19263EJ3V0UM 23 CHAPTER 2 REGISTERS 2.2.7 Gamma correction table address register This register (IMC_GAMMA_ADR: 4026_0024H 0024H) sets the gamma correction table address to be accessed for reading or writing. This is an immediately-reflected register, and changing the settings is prohibited while the IMC is operating. For details on the gamma correction function, see 3.3 Gamma Correction Function. 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 Reserved 23 22 21 20 Reserved 15 14 13 12 Reserved 7 6 5 4 Reserved Name Reserved GAMMAADR GAMMAADR R/W Bit After Reset Function R 31:6 0 Reserved. When these bits are read, 0 is returned for each bit. R/W 5:0 0 Sets the gamma correction table address to be accessed. To accelerate writing to the gamma table, perform write to the IMC_GAMMA_DATA register; the values of this register are then incremented automatically. Before setting the gamma correction table values, set bit 11 (gamma correction CLK control) of the control register (IMC_CONTROL) to 0 (automatic control disabled, CLK constantly supplied). 24 User's Manual S19263EJ3V0UM S19263EJ3V0UM CHAPTER 2 REGISTERS 2.2.8 Gamma correction table data register This register (IMC_GAMMA_DATA: 4026_0028H 0028H) is used to access the gamma correction table based on the address set with the GAMMAADR bit of the gamma correction table address register. The gamma correction table cannot be accessed when gamma correction is enabled. Setting this register is prohibited while gamma correction is enabled because the write operation is ignored and the read operation may read out invalid data. This is an immediately-reflected register, and changing the settings is prohibited while the IMC is operating. When this register is read, data is latched from the memory at the first read, and is read out via the APB bus at the second read. Therefore, be sure to read this register twice in succession and use the data acquired at the second read. For details on the gamma correction function, see 3.3 Gamma Correction Function. 31 30 29 28 27 26 25 24 19 18 17 16 10 9 8 1 0 Reserved 23 22 21 20 Reserved 15 GAMMARED 14 13 12 Reserved 7 GAMMAGREEN 6 5 4 Reserved Name Reserved GAMMARED 11 3 2 GAMMABLUE R/W Bit After Reset Function R 31:22 0 Reserved. When these bits are read, 0 is returned for each bit. R/W 21:16 0 Sets the correction value for the Red data at the address specified with GAMMAADR. Reserved GAMMAGREEN R 15:14 0 Reserved. When these bits are read, 0 is returned for each bit. R/W 13:8 0 Sets the correction value for the Green data at the address specified with GAMMAADR. Reserved GAMMABLUE R 7:6 0 Reserved. When these bits are read, 0 is returned for each bit. R/W 5:0 0 Sets the correction value for the Blue data at the address specified with GAMMAADR. To accelerate writing to the gamma table, perform write to this register; the values of the IMC_GAMMA_ADR register are then incremented automatically. This setting does not affect the read operation. Before setting the gamma correction table values, set bit 11 (gamma correction CLK control) of the control register (IMC_CONTROL) to 0 (automatic control disabled, CLK constantly supplied). User's Manual S19263EJ3V0UM S19263EJ3V0UM 25 CHAPTER 2 REGISTERS 2.2.9 Display area address register This register (IMC_WB_AREAADR: 4026_0040H 0040H) sets the start address of the frame buffer area for WB, when the IMC is operating in the immediate startup mode. This is an immediately-reflected register, so changing of settings during operation is prohibited. When the IMC is operating in the LCD-synchronous mode, the values set in this register are ignored and the WB buffer area set by the LCD controller is used. 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 0 0 AREAADR 23 22 21 20 AREAADR 15 14 13 12 AREAADR 7 6 5 4 AREAADR Name AREAADR R/W Bit After Reset R/W 31:0 0 Function Sets the first address of the frame buffer. (The lower 2 bits are fixed to 0.) For details, see Figure 3-1. Frame Buffer Definition. 26 User's Manual S19263EJ3V0UM S19263EJ3V0UM CHAPTER 2 REGISTERS 2.2.10 Address addition value register This register (IMC_WB_HOFFSET: 4026_0044H 0044H) sets the total byte count in the horizontal direction of the frame buffer area for WB, when the IMC is operating in the immediate startup mode. This is an immediately-reflected register, so changing of settings during operation is prohibited. When the IMC is operating in the LCD-synchronous mode, the values set in this register are ignored and the WB buffer area horizontal size set by the LCD controller is used. 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 1 0 0 0 Reserved 23 22 21 20 Reserved 15 14 13 12 Reserved 7 HOFFSET 6 5 4 3 2 HOFFSET Name R/W Bit After Reset Reserved R 31:13 0 HOFFSET R/W 12:0 0 Function Reserved. When these bits are read, 0 is returned for each bit. Sets the total byte count in horizontal direction of the frame buffer area. (The lower 2 bits are fixed to 0.) The address addition value which is required for storing valid pixel data varies depending on the horizontal pixel count set in the WB image size register and the value set in the format register. Observe the constraints on each image format and be sure not to set a value lower than the minimum value. User's Manual S19263EJ3V0UM S19263EJ3V0UM 27 CHAPTER 2 REGISTERS 2.2.11 Format register This register (IMC_WB_FORMAT: 4026_0048H 0048H) sets the format of data input to the frame buffer area for WB, when the IMC is operating in the immediate startup mode. This is an immediately-reflected register, so changing of settings during operation is prohibited. When the IMC is operating in the LCD-synchronous mode, the values set in this register are ignored and the format of input data for WB set by the LCD controller is used. 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 Reserved 23 22 21 20 Reserved 15 14 13 12 Reserved 7 6 5 4 Reserved Name R/W Bit After Reset Reserved R 31:1 0 FORMAT R/W 0 0 Function Reserved. When these bits are read, 0 is returned for each bit. Sets the input data format. For details, see 3.1.1 Supported image formats. 0: RGB666 RGB666 1: RGB565 RGB565 28 FORMAT User's Manual S19263EJ3V0UM S19263EJ3V0UM CHAPTER 2 REGISTERS 2.2.12 WB image size register This register (IMC_WB_SIZE: 4026_004CH 004CH) sets the size of WB images when the IMC is operating in the immediate startup mode. This is an immediately-reflected register, so changing of settings during operation is prohibited. When the IMC is operating in the LCD-synchronous mode, the values set in this register are ignored and the display image size set by the LCD controller is used. 31 30 29 28 27 26 Reserved 23 22 25 24 VSIZE 21 20 19 18 17 16 11 10 9 8 VSIZE 15 14 13 12 Reserved 7 6 HSIZE 5 4 3 2 1 HSIZE Name Reserved VSIZE R/W Bit After Reset R 31:27 0 R/W 26:16 0 0 0 Function Reserved. When these bits are read, 0 is returned for each bit. Sets the vertical size of WB images (up to 2,046 lines, in line units) Reserved HSIZE R 15:11 0 Reserved. When these bits are read, 0 is returned for each bit. R/W 10:0 0 Sets the horizontal size of WB images (up to 2,046 pixels, in 2-pixel units, the lowest bit is fixed to 0) User's Manual S19263EJ3V0UM S19263EJ3V0UM 29 CHAPTER 2 REGISTERS 2.2.13 Horizontal/vertical flip setting register This register (IMC_MIRROR: 4026_0100H 0100H) is used to flip images output from the IMC (data after synthesis) horizontally or vertically. Horizontal or vertical flip is performed after layers are overlaid, so care must be exercised when displaying layers including texts. This is a V-sync register, so the setting takes effect at the beginning of the first frame after setting change. 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 Reserved 23 22 21 20 Reserved 15 14 13 12 Reserved 7 6 5 4 Reserved Name R/W Bit After Reset Reserved R 31:2 0 MIRROR R/W 1:0 0 MIRROR Function Reserved. When these bits are read, 0 is returned for each bit. Sets flipping of images. 00: No flip 01: Horizontal flip 10: Vertical flip 11: Horizontal and vertical flip Figure 2-2. Flipping of Images Normal MIRROR = 00B Flipped vertically MIRROR = 10B 30 Flipped horizontally Flipped horizontally and vertically MIRROR = 11B MIRROR = 01B User's Manual S19263EJ3V0UM S19263EJ3V0UM CHAPTER 2 REGISTERS 2.2.14 Y gain offset register This register (IMC_YGAINOFFSET: 4026_0104H 0104H) is used to adjust the gain for Y (luminance) by multiplying by 0 to 255/128 and adjusts the offset in the range of 128 to 127, for YUV format images to be input. The YUV format can be specified for layers 2A and 2B, and the same setting is applied to both layers. This is an immediately-reflected register, so changing of settings during operation is prohibited. 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 Reserved 23 22 21 20 Reserved 15 14 13 12 YOFFSET 7 6 5 4 YGAIN Name R/W Bit After Reset Reserved R 31:16 0 YOFFSET R/W 15:8 00H Function Reserved. When these bits are read, 0 is returned for each bit. Sets the offset for the Y value by using signed 8-bit data. (2's complement) (128 to 127) YGAIN R/W 7:0 80H Sets the offset for the Y value. Values from 0 to 255 can be set, and the gain is set value/128. YGAIN * Yin YOFFSET Yout 128 Calculation of desired value: Multiply Yin by YGAIN divided by 128, rounding to one decimal place, and then add YOFFSET to calculate the approximate value (Yout) in the range of 0 to 255. Caution When YGAIN = 0, the value set to the YOFFSET bit is used as unsigned 8-bit data (0 to 255), and Yout is assumed to be equal to YOFFSET. User's Manual S19263EJ3V0UM S19263EJ3V0UM 31 CHAPTER 2 REGISTERS 2.2.15 U (V) gain offset registers These registers (IMC_UGAINOFFSET: 4026_0108H 0108H and IMC_VGAINOFFSET: 4026_010CH 010CH) are used to adjust the gain for U (color difference in blue) and V (color difference in red) by multiplying by 0 to 255/128 and the offset in the range of 128 to 127, for YUV format images to be input. The YUV format can be specified for layers 2A and 2B, and the same setting is applied to both layers. Since the U and V components are represented in offset binary coding with 80H positioned as the center, 80H is subtracted, converted into values ranging from 128 to 127, the gain is multiplied, and then the offset value and 80H are added. These are immediately-reflected registers, so changing of settings during operation is prohibited. 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 2 1 0 Reserved 23 22 21 20 Reserved 15 14 13 12 U (V) OFFSET 7 6 5 4 3 U (V) GAIN Name R/W Bit After Reset Reserved R 31:16 0 UOFFSET R/W 15:8 00H (VOFFSET) UGAIN Function Reserved. When these bits are read, 0 is returned for each bit. Sets the offset for the U (V) value by using signed 8-bit data. (128 to 127) R/W 7:0 (VGAIN) 80H Sets the offset for the U (V) value. Values from 0 to 255 can be set, and the gain is set value/128. UGAIN Uout * Uin 80 H UOFFSET 80 H 128 VGAIN Vout * Vin 80 H VOFFSET 80 H 128 Calculation of desired value: Multiply (Uin 80H) oy (Yin 80H) by UGAIN or VGAIN divided by 128, rounding to one decimal place, and then add 80H and UOFFSET or VOFFSET to calculate the approximate value in the range of 0 to 255. Cautions 1. When UGAIN/VGAIN = 0, the value set to the UOFFSET/VOFFSET bit is used as unsigned 8bit data (0 to 255) and Uout is assumed to be equal to UOFFSET (Vout = VOFFSET). 2. During multiplication, the fraction is dropped by adding 0.5. In the case of negative values, 0.5 is rounded up to 0. 32 User's Manual S19263EJ3V0UM S19263EJ3V0UM CHAPTER 2 REGISTERS 2.2.16 YUV2RGB conversion mode register This register (IMC_YUV2RGB: 4026_0110H 0110H) selects a calculation coefficient from ITU-R BT.601-compliant, ITU-R BT.709-compliant, custom coefficient (with or without Y value subtracted by 16) for converting YUV format input data into RGB format data. The data format after conversion is RGB888 RGB888, each data consists of 8 bits, and data is further converted into RGB666 RGB666, which is to be used for overlay processing in the IMC. This register also sets whether to perform dithering during conversion. This is an immediately-reflected register, so changing of settings during operation is prohibited. 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 Reserved 23 22 21 20 Reserved 15 14 13 12 Reserved 7 6 5 4 DITHER 3 2 1 Reserved Name R/W Bit R 31:9 0 DITHER R/W 8 0 TRANSMODE After Reset Reserved 0 Function Reserved. When these bits are read, 0 is returned for each bit. Enables dithering. For details, see 3.1.5 Dithering. 0: Does not perform dithering (rounding on or off). 1: Performs dithering. Reserved TRANS MODE R 7:2 0 Reserved. When these bits are read, 0 is returned for each bit. R/W 1:0 0 Selects the coefficient for YUV-to-RGB conversion. 00: ITU-R BT.601-compliant 01: ITU-R BT.709-compliant 10: Custom coefficient (Y value is subtracted by 16) 11: Custom coefficient (Y value is used as is) For details on conversion methods according to the TRANSMODE bit settings, see 2.2.17 Custom coefficient registers. User's Manual S19263EJ3V0UM S19263EJ3V0UM 33 CHAPTER 2 REGISTERS 2.2.17 Custom coefficient registers (IMC_COEF_R0: 4026_0114H 0114H) (IMC_COEF_G0: 4026_0124H 0124H) (IMC_COEF_B0: 4026_0134H 0134H) (IMC_COEF_R1: 4026_0118H 0118H) (IMC_COEF_G1: 4026_0128H 0128H) (IMC_COEF_B1: 4026_0138H 0138H) (IMC_COEF_R2: 4026_011CH 011CH) (IMC_COEF_G2: 4026_012CH 012CH) (IMC_COEF_B2: 4026_013CH 013CH) (IMC_COEF_R3: 4026_0120H 0120H) (IMC_COEF_G3: 4026_0130H 0130H) (IMC_COEF_B3: 4026_0140H 0140H) These registers set the coefficient for YUV-to-RGB conversion. The set values are used for matrix calculation when the TRANSMODE bit is set to 2 or 3. The values set in these registers are ignored when the TRANSMODE bit is set to 0 or 1. These are immediately-reflected register, so changing of settings during operation is prohibited. 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 Reserved 23 22 21 20 Reserved 15 14 13 12 Reserved 7 6 COEF 5 4 3 2 1 0 COEF Name Reserved COEF R/W Bit After Reset Function R 31:11 0 Reserved. When these bits are read, 0 is returned for each bit. R/W 10:0 0 Signed 11-bit data (2's complement) (1024 to 1023) YUV-to RGB conversion is calculated with the 4 × 4 matrix calculation. Y 16 R R 0 R1 R 2 R3 U 128 1 G G 0 G1 G 2 G 3 * * B B 0 B1 B 2 B3 V 128 256 1 When the TRANSMODE bit of the IMC_YUV2RGB register is set to 3, 16 is not subtracted from the Y value. Y R R 0 R1 R 2 R3 U 128 1 * G G 0 G1 G 2 G 3 * V 128 256 B B 0 B1 B 2 B3 1 As a result, the RGB values are calculated as follows. 34 User's Manual S19263EJ3V0UM S19263EJ3V0UM CHAPTER 2 REGISTERS R ( R0 * (Y 16) R1 * (U 128) R 2 * (V 128) R3) / 256 G (G 0 * (Y 16) G1 * (U 128) G 2 * (V 128) G 3) / 256 B ( B0 * (Y 16) B1 * (U 128) B 2 * (V 128) B3) / 256 R ( R0 * Y R1 * (U 128) R 2 * (V 128) R3) / 256 G (G 0 * Y G1 * (U 128) G 2 * (V 128) G3) / 256 B ( B0 * Y B1 * (U 128) B 2 * (V 128) B3) / 256 .16 is subtracted from Y value .Y value is used as is All twelve coefficients can be set by using signed 11-bit values (1024 to 1023). When the TRANSMODE of the IMC_YUV2RGB register is set to 0 (ITU-R BT.601-compliant) or 1 (ITU-R BT.709compliant), each coefficient is automatically replaced by the following coefficients. ITU-BT601-compliant (TRANS MODE = 0) 0 409 0 R 0 R1 R 2 R3 298 G 0 G1 G 2 G 3 298 100 208 0 B 0 B1 B 2 B3 298 517 0 0 Conversion is performed based on the above coefficient in the mode in which the Y value is subtracted by 16. As a result, the RGB values are calculated as follows. R (298 * (Y 16) 0 * U 409 * V 0) / 256 G (298 * (Y 16) 100 * U 208 * V 0) / 256 B (298 * (Y 16) 517 * U 0 * V 0) / 256 ITU-BT709-compliant (TRANS MODE = 1) 0 459 0 R 0 R1 R 2 R3 298 G 0 G1 G 2 G 3 298 55 137 0 B 0 B1 B 2 B3 298 541 0 0 Conversion is performed based on the above coefficient in the mode in which the Y value is subtracted by 16. As a result, the RGB values are calculated as follows. R (298 * (Y 16) 0 * U 459 * V 0) / 256 G (298 * (Y 16) 55 * U 137 * V 0) / 256 B (298 * (Y 16) 541 * U 0 * V 0) / 256 Since the U and V components are represented in offset binary coding in the circuit, with 80H positioned as the center, 128 is subtracted before RGB calculation and substituted into the above formulas. The RGB value after conversion is obtained by rounding the resultant to one decimal place and being clipped in the range of 0 to 255. User's Manual S19263EJ3V0UM S19263EJ3V0UM 35 CHAPTER 2 REGISTERS 2.2.18 Layer control registers Layer 0 control register (IMC_L0_CONTROL: 4026_0200H 0200H) Layer 1A control register (IMC_L1A_CONTROL: 4026_0300H 0300H) Layer 1B control register (IMC_L1B_CONTROL: 4026_0400H 0400H) Layer 1C control register (IMC_L1C_CONTROL: 4026_0500H 0500H) Layer 2A control register (IMC_L2A_CONTROL: 4026_0600H 0600H) Layer 2B control register (IMC_L2B_CONTROL: 4026_0700H 0700H) These registers set turning on/off of the overlay function for individual layer (six layers, except for the background). These are update target registers. 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 Reserved 23 22 21 20 Reserved 15 14 13 12 Reserved 7 6 5 4 Reserved Name R/W Bit After Reset Reserved R 31:1 0 LAYERON R/W 0 0 Function Reserved. When these bits are read, 0 is returned for each bit. Sets whether to enable synthesis of the target layers. 0: Disables layer 1: Enables layer 36 LAYERON User's Manual S19263EJ3V0UM S19263EJ3V0UM CHAPTER 2 REGISTERS 2.2.19 Layer format registers Layer 0 format register (IMC_L0_FORMAT: 4026_0204H 0204H) Layer 1x format register (IMC_L1X_FORMAT: 4026_0304H 0304H) Layer 2A format register (IMC_L2A_FORMAT: 4026_0604H 0604H) Layer 2B format register (IMC_L2B_FORMAT: 4026_0704H 0704H) Layer BG format register (IMC_BG_FORMAT: 4026_0804H 0804H) These registers set the format of data to be stored in each layer. These are update target registers. The supported format varies in each layer. The available formats are listed in the following tables. Layer 0 and layer 1x format registers Name Reserved FORM R/W Bit After Reset Function R 31:1 0 Reserved. When these bits are read, 0 is returned for each bit. R/W 0 0 Specifies the format of data to be stored in the target layer. 0: RGB666 RGB666 1: RGB565 RGB565 Layer 2A and layer 2B format registers Name Reserved FORM R/W Bit After Reset Function R 31:3 0 Reserved. When these bits are read, 0 is returned for each bit. R/W 2:0 0 Specifies the format of data to be stored in the target layer. 000: RGB666 RGB666 001: RGB565 RGB565 010: YUV422 YUV422 Interleave 011: YUV422 YUV422 Semi-Planar 100: YUV422 YUV422 Planar 101: YUV420 YUV420 Semi-Planar 110 or 111: YUV420 YUV420 Planar Layer BG format register Name Reserved FORM R/W Bit After Reset Function R 31:2 0 Reserved. When these bits are read, 0 is returned for each bit. R/W 1:0 0 Specifies the format of data to be stored in the target layer. 00: RGB666 RGB666 01: RGB565 RGB565 10: Fixed to black (ALL0) 11: Fixed background color (set by LCD_BACKCOLOR register) User's Manual S19263EJ3V0UM S19263EJ3V0UM 37 CHAPTER 2 REGISTERS 2.2.20 Transparent color control registers These registers (IMC_L0_KEYENABLE: 4026_0210H 0210H, IMC_L1A_KEYENABLE: 4026_0310H 0310H, IMC_L1B_ KEYENABLE: 4026_0410H 0410H and IMC_L1C_ KEYENABLE: 4026_0510H 0510H) set turning on/off of the transparent color for individual layer (layer 0 and layers 1A to 1C). These are update target registers. 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 Reserved 23 22 21 20 Reserved 15 14 13 12 Reserved 7 6 5 4 Reserved Name Reserved KEYEN KEYEN R/W Bit After Reset Function R 31:1 0 Reserved. When these bits are read, 0 is returned for each bit. R/W 0 0 Sets turning on/off the transparent color for the target layer. 0: Transparent color function OFF 1: Transparent color function ON 38 User's Manual S19263EJ3V0UM S19263EJ3V0UM CHAPTER 2 REGISTERS 2.2.21 Layer transparent color registers These registers (IMC_L0_KEYCOLOR: 4026_0214H 0214H and IMC_L1X_KEYCOLOR: 4026_0314H 0314H) specify the key colors used for implementing the transparent color function for the target layer. These are immediately-reflected registers. The set values are commonly applied to layers 1A, 1B and 1C. 31 30 29 28 27 26 25 24 19 18 17 16 10 9 8 2 1 0 Reserved 23 22 21 20 Reserved KEYR 15 14 13 12 11 Reserved KEYG 7 6 5 4 Reserved Name Reserved KEYR Reserved KEYG Reserved KEYB Caution 3 KEYB R/W Bit After Reset Function R 31:22 0 Reserved. When these bits are read, 0 is returned for each bit. R/W 21:16 0 Specifies red data component for the transparent color. R 15:14 0 Reserved. When these bits are read, 0 is returned for each bit. R/W 13:8 0 Specifies green data component for the transparent color. R 7:6 0 Reserved. When these bits are read, 0 is returned for each bit. R/W 5:0 0 Specifies blue data component for the transparent color. When data in the target layer is of the RGB666 RGB666 format, the condition for transparency processing is a match of all 18 bits. In the RGB565 RGB565 format, the most significant bits of components of R and B are extended to the least significant bits, and if the values match the value of 6 bits in either of these registers, transparency processing is performed. User's Manual S19263EJ3V0UM S19263EJ3V0UM 39 CHAPTER 2 REGISTERS 2.2.22 Alpha registers These registers (IMC_L0_ALPHA: 4026_0218H 0218H, IMC_L1A_ALPHA: 4026_0318H 0318H, IMC_L1B_ALPHA: 4026_0418H 0418H and IMC_L1C_ALPHA: 4026_0518H 0518H) set items related to alpha blending for synthesis of the target layers. These are update target registers. 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 Reserved 23 22 21 20 Reserved 15 14 13 12 Reserved 7 6 5 REVERSE 4 3 Reserved Name 2 1 0 ALPHA R/W Bit After Reset Function Reserved R 31:9 0 Reserved. When these bits are read, 0 is returned for each bit. REVERSE R/W 8 0 Reverse the ALPHA setting. Reads 63-ALPHA 63-ALPHA as newly set ALPHA. Reserved ALPHA R 7:6 0 Reserved. When these bits are read, 0 is returned for each bit. R/W 5:0 0 Sets the transparency. Setting range: 0 to 63 (0 = transparent, 63 = opaque) Remark 0 = opaque and 63 = transparent when REVERSE = 1. Transparency of 0 to 100% is achieved by set values ranging from 0 to 63. When calculating the desired value, PixOut after synthesis is as follows, where pixel data of the layer subject to transparency processing = PixA, and background = PixB. When ALPHA = 0 to 62 PixOut = {ALPHA × PixA + (64 ALPHA) × PixB} /64 (pixels = 6 bits, with rounding up or down) When ALPHA = 63 PixOut = PixA. The element of PixB is not reflected in the overlaid result. + Layer 0 (transparent background) 40 = Another layer ALPHA value (when REVERSE = 0) 63 (opaque) >> 32 >> 0 (transparent) User's Manual S19263EJ3V0UM S19263EJ3V0UM CHAPTER 2 REGISTERS 2.2.23 Resize registers Layer 0 resize register (IMC_L0_RESIZE: 4026_0220H 0220H) Layer 1x resize register (IMC_L1X_RESIZE: 4026_0320H 0320H) Layer 2A resize register (IMC_L2A_RESIZE: 4026_0620H 0620H) Layer 2B resize register (IMC_L2B_RESIZE: 4026_0720H 0720H) Layer BG resize register (IMC_BG_RESIZE: 4026_0820H 0820H) These registers enable resizing of overlaid layers. Only resizing to double the simple copy is supported. Image data read from a frame buffer is copied to 2 pixels in horizontal and vertical directions and used as the output image. The display area is not doubled during synthesis, but data stored in the frame buffer is just enlarged to fit into the specified displayed area. These are update target registers. 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 Reserved 23 22 21 20 Reserved 15 14 13 12 Reserved 7 6 5 4 Reserved Name Reserved RESIZEEN RESIZEEN R/W Bit After Reset Function R 31:1 0 Reserved. When these bits are read, 0 is returned for each bit. R/W 0 0 Sets whether to enable the resize function. 0: Does not resize images. 1: Resize images. Layer 0 (transparent background) + Not resized Resized Another layer User's Manual S19263EJ3V0UM S19263EJ3V0UM 41 CHAPTER 2 REGISTERS 2.2.24 Address addition value registers Layer 0 address addition value register (IMC_L0_OFFSET: 4026_0230H 0230H) Layer 1x address addition value register (IMC_L1X_OFFSET: 4026_0330H 0330H) Layer 2A address addition value register (IMC_L2A_OFFSET: 4026_0630H 0630H) Layer 2B address addition value register (IMC_L2B_OFFSET: 4026_0730H 0730H) Layer BG address addition value register (IMC_BG_OFFSET: 4026_0830H 0830H) These registers set the horizontal size of the frame buffer of the target layers. Because the number of settable pixels varies in each layer, the bit width of address addition values also varies according to the layer. These are update target registers. Layer 0 address addition value register Name R/W Bit After Reset Function Reserved R 31:10 0 Reserved. When these bits are read, 0 is returned for each bit. HOFFSET R/W 9:0 0 Sets the address addition value for the target layer. (The lower 2 bits are fixed to 0.) Layer 1x address addition value register Name R/W Bit After Reset Function Reserved R 31:13 0 Reserved. When these bits are read, 0 is returned for each bit. HOFFSET R/W 12:0 0 Sets the address addition value for the target layer. (The lower 2 bits are fixed to 0.) Layer 2A/2B/BG address addition value registers Name R/W Bit After Reset Function Reserved R 31:13 0 Reserved. When these bits are read, 0 is returned for each bit. HOFFSET R/W 12:0 0 Sets the address addition value for the target layer. (The lower 2 bits are fixed to 0.) For the definition of frame buffers, see Figure 3-1. Frame Buffer Definition. 42 User's Manual S19263EJ3V0UM S19263EJ3V0UM CHAPTER 2 REGISTERS 2.2.25 Buffer start address registers Layer 0 start address register (IMC_L0_FRAMEADR: 4026_0234H 0234H) Layer 1A start address register (IMC_L1A_FRAMEADR: 4026_0334H 0334H) Layer 1B start address register (IMC_L1B_FRAMEADR: 4026_0434H 0434H) Layer 1C start address register (IMC_L1C_FRAMEADR: 4026_0534H 0534H) Layer 2A start address register (YP) (IMC_L2A_FRAMEADR_YP: 4026_0634H 0634H) Layer 2A start address register (UP) (IMC_L2A_FRAMEADR_UP: 4026_0638H 0638H) Layer 2A start address register (VP) (IMC_L2A_FRAMEADR_VP: 4026_063CH 063CH) Layer 2A start address register (YQ) (IMC_L2A_FRAMEADR_YQ: 4026_0640H 0640H) Layer 2A start address register (UQ) (IMC_L2A_FRAMEADR_UQ: 4026_0644H 0644H) Layer 2A start address register (VQ) (IMC_L2A_FRAMEADR_VQ: 4026_0648H 0648H) Layer 2B start address register (YP) (IMC_L2B_FRAMEADR_YP: 4026_0734H 0734H) Layer 2B start address register (UP) (IMC_L2B_FRAMEADR_UP: 4026_0738H 0738H) Layer 2B start address register (VP) (IMC_L2B_FRAMEADR_VP: 4026_073CH 073CH) Layer 2B start address register (YQ) (IMC_L2B_FRAMEADR_YQ: 4026_0740H 0740H) Layer 2B start address register (UQ) (IMC_L2B_FRAMEADR_UQ: 4026_0744H 0744H) Layer 2B start address register (VQ) (IMC_L2B_FRAMEADR_VQ: 4026_0748H 0748H) Layer BG start address register (IMC_BG_FRAMEADR: 4026_0834H 0834H) These registers set the start address of the frame buffer of the target layers. These are update target registers. 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 0 0 FRAMEADR 23 22 21 20 FRAMEADR 15 14 13 12 FRAMEADR 7 6 5 4 FRAMEADR Name FRAMEADR R/W Bit After Reset R/W 31:0 0 Function Sets the start address of the frame buffer of the target layer. (The lower 2 bits are fixed to 0.) For the definition of frame buffers, see Figure 3-1. Frame Buffer Definition. The start address register used for layer 2 varies depending on the image format. For details, see Table 3-3. Formats and Start Address Setting Registers. User's Manual S19263EJ3V0UM S19263EJ3V0UM 43 CHAPTER 2 REGISTERS 2.2.26 Layer display position registers Layer 0 display position register (IMC_L0_POSITION: 4026_0250H 0250H) Layer 1A display position register (IMC_L1A_POSITION: 4026_0350H 0350H) Layer 1B display position register (IMC_L1B_POSITION: 4026_0450H 0450H) Layer 1C display position register (IMC_L1C_POSITION: 4026_0550H 0550H) Layer 2A display position register (IMC_L2A_POSITION: 4026_0650H 0650H) Layer 2B display position register (IMC_L2B_POSITION: 4026_0750H 0750H) These registers set the overlay position when overlaying the target layers in pixel units. These are update target registers 31 30 29 28 27 26 Reserved 23 22 25 24 POSY 21 20 19 18 17 16 11 10 9 8 POSY 15 14 13 12 Reserved 7 6 POSX 5 4 3 2 1 0 POSX Name Reserved POSY R/W Bit After Reset R 31:27 0 R/W 26:16 0 Function Reserved. When these bits are read, 0 is returned for each bit. Sets the Y coordinate at which layer display begins. (0 to 2,046 in pixel units) Reserved POSX R 15:11 0 Reserved. When these bits are read, 0 is returned for each bit. R/W 10:0 0 Sets the X coordinate at which layer display begins (0 to 2,046 in pixel units) POSY Display image Any layer POSX Background layer 44 User's Manual S19263EJ3V0UM S19263EJ3V0UM CHAPTER 2 REGISTERS 2.2.27 Layer display size registers Layer 0 display size register (IMC_L0_SIZE: 4026_0254H 0254H) Layer 1A display size register (IMC_L1A_SIZE: 4026_0354H 0354H) Layer 1B display size register (IMC_L1B_SIZE: 4026_0454H 0454H) Layer 1C display size register (IMC_L1C_SIZE: 4026_0554H 0554H) Layer 2A display size register (IMC_L2A_SIZE: 4026_0654H 0654H) Layer 2B display size register (IMC_L2B_SIZE: 4026_0754H 0754H) These registers set the size of the overlaid layers, in pixel units. Note that the size that can be displayed in each layer varies. These are update target registers. Bits 31 to 24 and 15 to 8 are reserved. Writing any value other than 0 is prohibited. When these values are read, 0 is returned for each bit. Layer 0 display size register Name SIZEY R/W Bit After Reset R/W 23:16 Function 0 Sets the vertical display size of the target layer. (0 to 255 in pixel units) SIZEX R/W 7:0 0 Sets the horizontal display size of the target layer. (0 to 255 in pixel units) Layer 1x display size register Name SIZEY R/W Bit After Reset R/W 26:16 Function 0 Sets the vertical display size of the target layer. (0 to 2,046 in pixel units) SIZEX R/W 10:0 0 Sets the horizontal display size of the target layer. (0 to 2,046 in pixel units) Layer 2x display size register Name SIZEY R/W Bit After Reset R/W 26:16 Function 0 Sets the vertical display size of the target layer. (0 to 2,046 in pixel units) SIZEX R/W 10:0 0 Sets the horizontal display size of the target layer. (0 to 2,046 in pixel units) POSY Displayed image Any layer SIZEY POSX SIZEX Background layer User's Manual S19263EJ3V0UM S19263EJ3V0UM 45 CHAPTER 2 REGISTERS 2.2.28 Layer 2 double buffer control registers These registers (IMC_L2A_BUFSEL: 4026_0608H 0608H and IMC_L2B_BUFSEL: 4026_0708H 0708H) switch the P and Q planes in layers 2A and 2B. These are update target registers. 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 Reserved 23 22 21 20 Reserved 15 14 13 12 Reserved 7 6 5 4 Reserved Name Reserved DBCNT R/W Bit After Reset R 31:2 0 R/W 1:0 0 DBCNT Function Reserved. When these bits are read, 0 is returned for each bit. Selects how to control double buffers. 00: Fixed to plane P. 01: Fixed to plane Q. 10: Control via CPU (follows the IMC_CPUBUFSEL register settings) 11: Setting prohibited. 46 User's Manual S19263EJ3V0UM S19263EJ3V0UM CHAPTER 2 REGISTERS 2.2.29 Layer 2 byte lane registers These registers (IMC_L2A_BYTELANE: 4026_060CH 060CH and IMC_L2B_BYTELANE: 4026_070CH 070CH) switch byte sequence in data of 32 bits (word) when reading data of layers 2A and 2B from the frame buffer. These are immediately-reflected registers. 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 2 1 0 Reserved 23 22 21 20 Reserved 15 14 13 12 Y_BYTELANE 7 6 5 4 3 UV_BYTELANE (1/2) Name R/W Bit After Reset Reserved R 31:16 0 Y_BYTE R/W 15:8 E4H Function Reserved. When these bits are read, 0 is returned for each bit. In YUV Interleave mode LANE Y_BYTELANE Bits Set Value 15:14 Bytes to which V0 is stored (0 to 3) 13:12 Bytes to which U0 is stored (0 to 3) 11:10 Bytes to which Y1 is stored (0 to 3) 9:8 Bytes to which Y0 is stored (0 to 3) In YUV Semi-Planar/ Planar modes Y_BYTELANE Bits Set Value 15:14 Bytes to which Y3 is stored (0 to 3) 13:12 Bytes to which Y2 is stored (0 to 3) 11:10 Bytes to which Y1 is stored (0 to 3) 9:8 Bytes to which Y0 is stored (0 to 3) In other modes The set values are ignored. User's Manual S19263EJ3V0UM S19263EJ3V0UM 47 CHAPTER 2 REGISTERS (2/2) Name R/W UV_BYTE Bit After Reset R/W 7:0 Function E4H In YUV Semi-Planar mode LANE UV_BYTELANE Bits Set Value 7:6 Bytes to which V1 is stored (0 to 3) 5:4 Bytes to which U1 is stored (0 to 3) 3:2 Bytes to which V0 is stored (0 to 3) 1:0 Bytes to which U0 is stored (0 to 3) In YUV Planar mode UV_BYTELANE Bits Set Value 7:6 Bytes to which V3/V3 is stored (0 to 3) 5:4 Bytes to which U2/V2 is stored (0 to 3) 3:2 Bytes to which U1/V1 is stored (0 to 3) 1:0 Bytes to which U0/V0 is stored (0 to 3) In other modes The set values are ignored. When the YUV format is set for layers 2A and 2B, the IMC changes the byte sequence when data is read from the memory, according to the BYTELANE set value. Set the BYTELANE so that the YUV data is reordered as expected by the IMC. With YUV Interleave, the IMC expects the following byte sequence. V0 U0 Y1 Y0 Bits 31-24 Bits 23-16 Bits 15-8 Bits 7-0 With YUV Semi-Planar, the IMC expects the following byte sequence. Y3 Y2 Y1 Y0 Bit 31-24 Bits 23-16 Bits 15-8 Bits 7-0 V1 U1 V0 U0 Bits 31-24 Bits 23-16 Bits 15-8 Bits 7-0 With YUV Planar, the IMC expects the following byte sequence. Y3 Y1 Y0 Bits 23-16 Bits 15-8 Bits 7-0 U3/V3 Bits 31-24 48 Y2 Bits 31-24 U2/V2 Bits 23-16 U1/V1 Bits 15-8 U0/V0 Bits 7-0 User's Manual S19263EJ3V0UM S19263EJ3V0UM CHAPTER 2 REGISTERS The following shows the operation with BYTELANE set values. AHB bus RDATA[31:0] 31 0 3 [7:6] 2 [5:4] 31-24 1 [3:2] 23-16 0 Register settings [1:0] 15-8 7-0 User's Manual S19263EJ3V0UM S19263EJ3V0UM 49 CHAPTER 2 REGISTERS 2.2.30 Layer 2 horizontal/vertical flip control registers These registers (IMC_L2A_MIRROR: 4026_0624H 0624H and IMC_L2B_MIRROR: 4026_0724H 0724H) control horizontal/vertical flip of layers 2A and 2B. These are update target registers. 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 Reserved 23 22 21 20 Reserved 15 14 13 12 Reserved 7 6 5 4 Reserved Name R/W Bit After Reset Reserved R 31:2 0 MIRROR R/W 1:0 0 MIRROR Function Reserved. When these bits are read, 0 is returned for each bit. Sets the image flip direction. 00: No flip 01: Horizontal flip 10: Vertical flip 11: Horizontal and vertical flip Horizontal and vertical flip can be controlled for individual planes in layer 2. Flipping of layer 2 (setting with this register) and flipping of entire image (setting with IMC_MIRROR register) can be set at the same time, but setting both registers cancels the effect. Layer 2A + Background layer Normal MIRROR = 00B Flipped vertically MIRROR = 10B Flipped horizontally MIRROR = 01B Flipped horizontally and vertically MIRROR = 11B Layer 2A is flipped horizontally and the entire image is flipped vertically. 50 Layer 2A seems to be flipped horizontally and vertically, but the overlay position is reversed vertically. User's Manual S19263EJ3V0UM S19263EJ3V0UM CHAPTER 2 REGISTERS 2.2.31 ARGB4444 ARGB4444 mode register This register (IMC_ARGBMODE: 4026_1000H 1000H) selects the layer that uses the ARGB4444 ARGB4444 format. For details on the operation, see 3.2.7 ARGB4444 ARGB4444 format. 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 L1C_ARGB L1B_ARGB L1A_ARGB L0_ARGB 3 2 1 0 Reserved 23 22 21 20 Reserved 15 14 13 12 Reserved 7 6 5 4 Reserved Name R/W Bit After Reset R 31:12 0 Reserved. When these bits are read, 0 is returned for each bit. L1C_ARGB R/W 11 0 Enables the use of the ARGB4444 ARGB4444 format for the relevant layer. L1B_ARGB R/W 10 0 The ARGB444 ARGB444 format is enabled when all these bits are set to 1, the L1A_ARGB R/W 9 0 transparent color is set for the layer (KEYENABLE register = 1), and L0_ARGB R/W 8 0 RGB565 RGB565 is selected for the layer. Reserved R/W 7:0 0 Reserved Function Reserved. When these bits are read, 0 is returned for each bit. (Setting prohibited.) User's Manual S19263EJ3V0UM S19263EJ3V0UM 51 CHAPTER 2 REGISTERS 2.2.32 Interrupt setting registers These registers set various interrupt parameters. The IMC can issue five types of interrupts. Control of each interrupt is assigned to each bit of the interrupt setting registers. For details, see Table 2-1 Interrupts. Table 2-1. Interrupts Interrupt Name Source Bit Assignment AHBR error response interrupt Issued when a response other than OKAY is received from 4 the AHB read side. AHBW error response interrupt Issued when a response other than OKAY is received from 3 the AHB write side. WB end interrupt Issued when writeback to a cache frame is completed. 2 Overrun interrupt Issued when writeback to a cache frame overruns. 1 Register update end interrupt Issued when the update target register is updated. 0 A WB end interrupt occurs when the IMC finishes writing data to a cache frame. There is a latency until the written data is actually stored in the memory, because write is performed via a bus bridge or bus switch. When AHB (R/W) abnormal response occurrence interrupt receives all except for the OKAY response of the AHB bus (Error/Retry/Split), interrupt is issued. There is a possibility that unjust data access occurred, but without stopping processing, IMC keeps moving just as it is. The AHB address value when interrupting and occurring, is stocked in an error address register. An AHBR error response interrupt is generated when a response other than OKAY (EXOKAY, SLVERR, or DECERR) is returned from the AXI bus. At this time, the valid address is not stored but 0000_0000H 0000H is held in the error address register, and only the LOCK bit is set. Details on the interrupt setting registers are described below. 52 User's Manual S19263EJ3V0UM S19263EJ3V0UM CHAPTER 2 REGISTERS (1) Interrupt status register This is a read-only register (IMC_INTSTATUS: 4026_0900H 0900H) that indicates the status of interrupt sources. The statuses of the interrupt sources enabled with the interrupt enable set register can be read. This is an immediately-reflected register, so changing of settings during operation is prohibited. 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 4 3 2 1 0 AHBRERR AHBWERR WBEND OVERRUN REFRESH Reserved 23 22 21 20 Reserved 15 14 13 12 Reserved 7 6 5 Reserved Name R/W Bit After Reset Function Reserved R 31:5 0 Reserved. When these bits are read, 0 is returned for each bit. AHBRERR R 4 0 Indicates the status of an AHBR error response interrupt. 0: No interrupt source 1: Interrupt source occurred AHBWERR R 3 0 Indicates the status of an AHBW error response interrupt. 0: No interrupt source 1: Interrupt source occurred WBEND R 2 0 Indicates the status of a WB end interrupt. 0: No interrupt source 1: Interrupt source occurred OVERRUN R 1 0 Indicates the status of an overrun interrupt. 0: No interrupt source 1: Interrupt source occurred REFRESH R 0 0 Indicates the status of a register update end interrupt. 0: No interrupt source 1: Interrupt source occurred User's Manual S19263EJ3V0UM S19263EJ3V0UM 53 CHAPTER 2 REGISTERS (2) Interrupt raw status register This is a read-only register (IMC_INTRAWSTATUS: 4026_0904H 0904H) that indicates the statuses of interrupt sources. The bits corresponding to the interrupt sources are set regardless of the settings of the interrupt enable set register and the interrupt enable clear register. This is an immediately-reflected register, so changing of settings during operation is prohibited. 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 4 3 2 1 0 AHBRERR AHBWERR WBEND OVERRUN REFRESH RAW RAW RAW RAW RAW Reserved 23 22 21 20 Reserved 15 14 13 12 Reserved 7 6 5 Reserved Name R/W Bit After Reset Function Reserved R 31:5 0 Reserved. When these bits are read, 0 is returned for each bit. AHBRERRRAW R 4 0 Indicates the raw status of an AHBR error response interrupt. 0: No interrupt source 1: Interrupt source occurred AHBWERRRAW R 3 0 Indicates the raw status of an AHBW error response interrupt. 0: No interrupt source 1: Interrupt source occurred WBENDRAW R 2 0 Indicates the raw status of a WB end interrupt.