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Part Manufacturer Description Datasheet BUY
LTC3730CG#TRPBF Linear Technology LTC3730 - 3-Phase, 5-Bit Intel Mobile VID, 600kHz, Synchronous Buck Controller; Package: SSOP; Pins: 24; Temperature Range: 0°C to 70°C visit Linear Technology - Now Part of Analog Devices Buy
LTC3730CG Linear Technology LTC3730 - 3-Phase, 5-Bit Intel Mobile VID, 600kHz, Synchronous Buck Controller; Package: SSOP; Pins: 24; Temperature Range: 0°C to 70°C visit Linear Technology - Now Part of Analog Devices Buy
LTC3730CG#TR Linear Technology LTC3730 - 3-Phase, 5-Bit Intel Mobile VID, 600kHz, Synchronous Buck Controller; Package: SSOP; Pins: 24; Temperature Range: 0°C to 70°C visit Linear Technology - Now Part of Analog Devices Buy
LTC3730CG#PBF Linear Technology LTC3730 - 3-Phase, 5-Bit Intel Mobile VID, 600kHz, Synchronous Buck Controller; Package: SSOP; Pins: 24; Temperature Range: 0°C to 70°C visit Linear Technology - Now Part of Analog Devices Buy
LTC3735EUHF#TR Linear Technology LTC3735 - 2-Phase, High Efficiency DC/DC Controller for Intel Mobile CPUs; Package: QFN; Pins: 38; Temperature Range: -40°C to 85°C visit Linear Technology - Now Part of Analog Devices Buy
LTC3735EUHF#PBF Linear Technology LTC3735 - 2-Phase, High Efficiency DC/DC Controller for Intel Mobile CPUs; Package: QFN; Pins: 38; Temperature Range: -40°C to 85°C visit Linear Technology - Now Part of Analog Devices Buy

Mobile DDR SDRAM

Catalog Datasheet MFG & Type PDF Document Tags

TRCD3C

Abstract: mobile ddr Mobile DDR SDRAM MOBILE DDR SDRAM Device Operations & Timing Diagram 1 DEVICE OPERATIONS Mobile DDR SDRAM Precharge The precharge command is used to precharge or close a bank that , deactivating the CS signal. In this mode, Mobile DDR SDRAM should ignore all the control inputs. The Mobile , OPERATIONS Mobile DDR SDRAM Row Active The Bank Activation command is issued by holding CAS and WE high with CS and RAS low at the rising edge of the clock(CK). The Mobile DDR SDRAM has four
Samsung Electronics
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H5MS5162

Abstract: h5ms5162dfr-j3m 512Mbit MOBILE DDR SDRAM based on 8M x 4Bank x16 I/O Specification of 512Mb (32Mx16bit) Mobile , Apr. 2009 Rev 1.3 / Apr. 2009 2 11 Mobile DDR SDRAM 512Mbit (32M x 16bit) H5MS5162DFR Series FEATURES SUMMARY clock cycle Mobile DDR SDRAM - Double data rate , READ - Keep to the JEDEC Standard regulation (Low Power DDR SDRAM) Mobile DDR SDRAM INTERFACE , ) INITIALIZING THE MOBILE DDR SDRAM - Occurring at device power up or interruption of device power - DPD
Hynix Semiconductor
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DDR333 DDR400 DDR370 H5MS5162 h5ms5162dfr-j3m hynix mcp 200MH

H5MS5122DFR

Abstract: H5MS5122DFR-J3M 512Mbit MOBILE DDR SDRAM based on 4M x 4Bank x32 I/O Specification of 512Mb (16Mx32bit) Mobile , 4M x 32bits) MOBILE DDR SDRAM Revision History Revision No. History Draft Date Remark , Mobile DDR SDRAM 512Mbit (16M x 32bit) H5MS5122DFR Series / H5MS5132DFR Series FEATURES SUMMARY Mobile DDR SDRAM - Double data rate architecture: two data transfer per clock cycle MODE RERISTER , (Low Power DDR SDRAM) Mobile DDR SDRAM INTERFACE - x32 bus width - Multiplexed Address (Row
Hynix Semiconductor
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H5MS5122DFR-J3M h5ms 512MB

hynix ddr ram

Abstract: H5MS1222EFP 128Mbit MOBILE DDR SDRAM based on 1M x 4Bank x32 I/O Specification of 128M (4Mx32bit) Mobile , . 2008 Rev 1.0 / Jun. 2008 2 Mobile DDR SDRAM 128Mbit (4M x 32bit) H5MS1222EFP Series FEATURES SUMMARY Mobile DDR SDRAM - Double data rate architecture: two data transfer per clock cycle , regulation (Low Power DDR SDRAM) Mobile DDR SDRAM INTERFACE - x32 bus width: HY5MS5B2ALFP - , DDR SDRAM. - Keep to the JEDEC Standard regulation INITIALIZING THE MOBILE DDR SDRAM - Occurring
Hynix Semiconductor
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hynix ddr ram 128MB

H5MS1G62

Abstract: H5MS1G62MFP-J3M 1Gbit MOBILE DDR SDRAM based on 16M x 4Bank x16 I/O Specification of 1Gb (64Mx16bit) Mobile DDR , SDRAM 1Gbit (64M x 16bit) H5MS1G62MFP Series Document Title 1Gbit (4Bank x 16M x 16bit) MOBILE DDR , / Jul. 2008 2 Mobile DDR SDRAM 1Gbit (64M x 16bit) H5MS1G62MFP Series FEATURES SUMMARY Mobile DDR SDRAM - Double data rate architecture: two data transfer per clock cycle MODE RERISTER , (Low Power DDR SDRAM) Mobile DDR SDRAM INTERFACE - x16 bus width - Multiplexed Address (Row
Hynix Semiconductor
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H5MS1G62 H5MS1G62MFP-J3M h5ms1g ap die hen mcp H5MS1G62MFP-K3M
Abstract: 512Mbit MOBILE DDR SDRAM based on 4M x 4Bank x32 I/ Document Title 512MBit (4Bank x 4M x 32bits) MOBILE DDR SDRAM Revision History Revision No. 0.1 0.2 - Initial Draft - Added SRR function and timing , Mobile DDR SDRAM 512Mbit (16M x 32bit) HY5MS7B2BLF(P) Series FEATURES SUMMARY Mobile DDR SDRAM - Double data rate architecture: two data transfer per clock cycle Mobile DDR SDRAM INTERFACE - x32 bus , mode is a feature supported by Mobile DDR SDRAM. - Keep to the JEDEC Standard regulation INITIALIZING Hynix Semiconductor
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LPDDR333 LPDDR266 LPDDR200

LPDDR200

Abstract: HY5MS7B6BLFP 512Mbit MOBILE DDR SDRAM based on 8M x 4Bank x16 I/O Document Title 512Mbit (4Bank x 8M x 16bits) MOBILE DDR SDRAM Revision History Revision No. 0.1 0.2 - Initial Draft - Added SRR function and timing , patent licenses are implied. Rev 1.3 / Jun. 2007 1 Mobile DDR SDRAM 512Mbit (32M x 16bit) HY5MS7B6BLF(P) Series 11 FEATURES SUMMARY Mobile DDR SDRAM - Double data rate architecture: two data transfer per clock cycle Mobile DDR SDRAM INTERFACE - x16 bus width: HY5MS7B6BLFP - Multiplexed Address
Hynix Semiconductor
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HY5MS7B6BLFP

hynix mcp

Abstract: HY5MS5B6BL 128Mbit MOBILE DDR SDRAM based on 2M x 4Bank x16 I/O Specification of 128M (8Mx16bit) Mobile , DDR SDRAM based on 2M x 4Bank x16 I/O Document Title 128Mbit (4Bank x 2M x 16bits) MOBILE DDR , licenses are implied. Rev 1.1 / July. 2009 2 Mobile DDR SDRAM 128Mbit (8M x 16bit) H5MS1262EFP Series FEATURES SUMMARY clock cycle Mobile DDR SDRAM - Double data rate , READ - Keep to the JEDEC Standard regulation (Low Power DDR SDRAM) Mobile DDR SDRAM INTERFACE CAS
Hynix Semiconductor
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HY5MS5B6BL 2Mx16

HY5MS5B6BLFP

Abstract: HY5MS5B6BL 128Mbit MOBILE DDR SDRAM based on 2M x 4Bank x16 I/O Specification of 128M (8Mx16bit) Mobile DDR , circuits described. No patent licenses are implied. Rev 1.0 / Jun. 2008 1 Mobile DDR SDRAM 128Mbit (8M x 16bit) H5MS1262EFP Series Document Title 128Mbit (4Bank x 2M x 16bits) MOBILE DDR SDRAM , Remark Preliminary Preliminary Rev 1.0 / Jun. 2008 2 Mobile DDR SDRAM 128Mbit (8M x 16bit) H5MS1262EFP Series FEATURES SUMMARY Mobile DDR SDRAM - Double data rate architecture: two data transfer
Hynix Semiconductor
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HY5MS5B6BLFP

h5ms1g22

Abstract: 1Gbit MOBILE DDR SDRAM based on 8M x 4Bank x32 I/O Specification of 1Gb (32Mx32bit) Mobile DDR , circuits described. No patent licenses are implied. Rev 1.1 / May 2008 1 Mobile DDR SDRAM 1Gbit (32M x , / May 2008 2 Mobile DDR SDRAM 1Gbit (32M x 32bit) H5MS1G22MFP Series / H5MS1G32MFP Series FEATURES SUMMARY ● Mobile DDR SDRAM - Double data rate architecture: two data transfer per clock cycle , Standard regulation (Low Power DDR SDRAM) ● Mobile DDR SDRAM INTERFACE - x32 bus width -
Hynix Semiconductor
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h5ms1g22

H5MS5162

Abstract: h5ms 512Mbit MOBILE DDR SDRAM based on 8M x 4Bank x16 I/O Specification of 512Mb (32Mx16bit) Mobile , use of circuits described. No patent licenses are implied. Rev 1.1 / May 2008 1 Mobile DDR SDRAM , Preliminary Preliminary 1.1 May 2008 Rev 1.1 / May 2008 2 Mobile DDR SDRAM 512Mbit (32M x 16bit) H5MS5162DFR Series 11 FEATURES SUMMARY Mobile DDR SDRAM - Double data rate architecture: two data transfer per clock cycle Mobile DDR SDRAM INTERFACE - x16 bus width - Multiplexed Address
Hynix Semiconductor
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K4M56163PI

Abstract: SDRAM16MX16 K4X56163PI - L(F)E/G Mobile DDR SDRAM 16Mx16 Mobile DDR SDRAM 1. FEATURES · VDD/VDDQ = 1.8V , 2007 K4X56163PI - L(F)E/G Mobile DDR SDRAM 5. FUNCTIONAL BLOCK DIAGRAM CK, CK LWE I , Register WE -5- DM October 2007 K4X56163PI - L(F)E/G Mobile DDR SDRAM 6. Package , 2007 K4X56163PI - L(F)E/G Mobile DDR SDRAM 7. Input/Output Function Description Symbol , connection is present. -7- October 2007 K4X56163PI - L(F)E/G Mobile DDR SDRAM 8. Functional
Samsung Electronics
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DDR266 K4M56163PI SDRAM16MX16 60FBGA K4X56163PI-L 166MH 133MH
Abstract: 256Mbit MOBILE DDR SDRAM based on 2M x 4Bank x32 I/O Document Title 256MBit (4Bank x 2M x 32bits) MOBILE DDR SDRAM Revision History Revision No. History Draft Date Remark 0.1 - , licenses are implied. Rev 1.1 / May. 2008 1 Mobile DDR SDRAM 256Mbit (8M x 32bit) HY5MS5B2ALFP Series FEATURES SUMMARY ● Mobile DDR SDRAM - Double data rate architecture: two data transfer per clock cycle , Standard regulation (Low Power DDR SDRAM) ● Mobile DDR SDRAM INTERFACE - x32 bus width: HY5MS5B2ALFP Hynix Semiconductor
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256MB LPDDR266/200

H5MS1G22

Abstract: h5ms1g 1Gbit MOBILE DDR SDRAM based on 8M x 4Bank x32 I/O Specification of 1Gb (32Mx32bit) Mobile DDR , circuits described. No patent licenses are implied. Rev 1.2 / Jun. 2008 1 Mobile DDR SDRAM 1Gbit (32M x , Preliminary Rev 1.2 / Jun. 2008 2 Mobile DDR SDRAM 1Gbit (32M x 32bit) H5MS1G22MFP Series / H5MS1G32MFP Series FEATURES SUMMARY Mobile DDR SDRAM - Double data rate architecture: two data transfer per clock cycle Mobile DDR SDRAM INTERFACE - x32 bus width - Multiplexed Address (Row address and
Hynix Semiconductor
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Abstract: 512Mbit MOBILE DDR SDRAM based on 4M x 4Bank x32 I/O Document Title 512MBit (4Bank x 4M x 32bits) MOBILE DDR SDRAM Revision History Revision No. 0.1 0.2 - Initial Draft - Added SRR function and timing , 1.1 / Apr. 2007 1 11 Mobile DDR SDRAM 512Mbit (16M x 32bit) HY5MS7B2BLF(P) Series FEATURES SUMMARY Mobile DDR SDRAM - Double data rate architecture: two data transfer per clock cycle Mobile DDR , FBGA CLOCK STOP MODE - Clock stop mode is a feature supported by Mobile DDR SDRAM. - Keep to the JEDEC Hynix Semiconductor
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DDR222

Abstract: DDR266 EMD28164PA 128M: 8M x 16 Mobile DDR SDRAM Document Title 128M: 8M x 16 Mobile DDR SDRAM , office. 1 Rev 1.0 EMD28164PA 128M: 8M x 16 Mobile DDR SDRAM 128M : 8M x 16bit Mobile DDR , Rev 1.0 EMD28164PA 128M: 8M x 16 Mobile DDR SDRAM Table 2: Pad Description Symbol Type , 16 Mobile DDR SDRAM Device Operation Simplified State Diagram Power On Power applied , : 8M x 16 Mobile DDR SDRAM Electrical Specifications Table 3: ABSOLUTE MAXIMUM RATINGS Parameter
Emerging Memory & Logic Solutions
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DDR222 EMD28164PA-60 EMD28164PA-75 EMD28164PA-90 143MH 125MH 111MH 100MH

DDR266

Abstract: DDR332 Preliminary EMD56164P 256M: 16M x16 Mobile DDR SDRAM Document Title 256M: 16M x 16 Mobile , office. 1 Rev 0.0 Preliminary EMD56164P 256M: 16M x 16 Mobile DDR SDRAM 256M : 16M x 16bit Mobile DDR SDRAM FEATURES · 1.8V power supply, 1.8V I/O power · LVCMOS compatible with , Rev 0.0 Preliminary EMD56164P 256M: 16M x 16 Mobile DDR SDRAM Table 2: PAD DISCRIPTION , x16 Mobile DDR SDRAM Device Operation Simplified State Diagram Power On Power applied
Emerging Memory & Logic Solutions
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DDR332 EMD56164P-60 EMD56164P-75

DDR332

Abstract: EMD12324P Preliminary EMD12324P 512M: 16M x 32 Mobile DDR SDRAM Document Title 512M: 16M x 32 Mobile , office. 1 Rev 0.0 Preliminary EMD12324P 512M: 16M x 32 Mobile DDR SDRAM 512M : 16M x 32bit Mobile DDR SDRAM FEATURES 1.8V power supply, 1.8V I/O power LVCMOS compatible with multiplexed , EMD12324P 512M: 16M x 32 Mobile DDR SDRAM Table 2: Pad Description Symbol Type Descriptions , Preliminary EMD12324P 512M: 16M x 32 Mobile DDR SDRAM Device Operation Simplified State Diagram
Emerging Memory & Logic Solutions
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EMD12324P-60 EMD12324P-75 512M

DDR266

Abstract: DDR332 Preliminary EMD56324P 256M: 8M x 32 Mobile DDR SDRAM Document Title 256M: 8M x 32 Mobile , office. 1 Rev 0.0 Preliminary EMD56324P 256M: 8M x 32 Mobile DDR SDRAM 256M : 8M x 32bit Mobile DDR SDRAM FEATURES · 1.8V power supply, 1.8V I/O power · LVCMOS compatible with multiplexed , EMD56324P 256M: 8M x 32 Mobile DDR SDRAM Table 2: Pad Description Symbol Type Descriptions , Preliminary EMD56324P 256M: 8M x 32 Mobile DDR SDRAM Device Operation Simplified State Diagram
Emerging Memory & Logic Solutions
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EMD56324P-60 EMD56324P-75

taylor

Abstract: AS4C32M16MD1 512M Mobile DDR SDRAM 8Mb x 16 bits x 4 Banks GENERAL DESCRIPTION The , -4Jan2014 AS4C32M16MD1 512M Mobile DDR SDRAM 8Mb x 16 bits x 4 Banks PIN CONFIGURATION Alliance Memory, Inc., 551 , Rev1-4Jan2014 AS4C32M16MD1 512M Mobile DDR SDRAM 8Mb x 16 bits x 4 Banks INPUT / OUTPUT FUNCTION , Mobile DDR SDRAM 8Mb x 16 bits x 4 Banks FUNCTIONAL BLOCK DIAGRAM Alliance Memory, Inc., 551 Taylor , -4Jan2014 AS4C32M16MD1 512M Mobile DDR SDRAM 8Mb x 16 bits x 4 Banks SIMPLIFIED STATE DIAGRAM CKEH : Clock Enable
Alliance Memory
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taylor
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