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STELLARIS-3P-CMXSI-MICRONET-STACK Texas Instruments CMX-MicroNet visit Texas Instruments
BEMICRONIO-2-PROCSDK-REF Texas Instruments Altera/Arrow BeMicro Nios II Processor SDK with DP83848 in USB Stick Format visit Texas Instruments
LP2994EVAL Texas Instruments DDR Termination Regulator visit Texas Instruments
ISL6532CCRZ-T Intersil Corporation ACPI Regulator/Controller for Dual Channel DDR Memory Systems; QFN28; Temp Range: 0° to 70° visit Intersil Buy
ISL6444CAZ Intersil Corporation PWM Controller with DDR Memory Option for Gateway Applications; QSOP28; Temp Range: 0° to 70° visit Intersil Buy
ISL6353IRTZ-T Intersil Corporation Multiphase PWM Regulator for VR12 DDR Memory Systems; TQFN40; Temp Range: See Datasheet visit Intersil Buy

Micron DDR marking H12

Catalog Datasheet MFG & Type PDF Document Tags

ADQ12

Abstract: ADQ14 , Burst Mode Flash Memory and 128/256-Mb (8/16-M x 16-bit) DDR DRAM ADVANCE INFORMATION Data Sheet , Mode Flash Memory and 128/256-Mb (8/16-M x 16-bit) DDR DRAM ADVANCE INFORMATION Data Sheet , component. Refer to the DDR SDRAM Type 1 data sheet (revision A2) for full electrical specifications of the DDR SDRAM component. Refer to the DDR SDRAM Type 5 data sheet (revision A0) for full electrical specifications of the DDR SDRAM component The S72NS Series is a product line of stacked Multi-Chip Product (MCP
Spansion
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S72NS-N S72NS128 ADQ12 ADQ14 Multi-Chip Package MEMORY S72NS512ND0 S29NS-N 128/256-M 256ND0

MICRON diode 2u

Abstract: 24256 to the Micron Web site: www.micron.com/dramds FEATURES 144-Ball T-FBGA · 2.5V VEXT, 1.8V VDD , Non-interruptible sequential burst of two (2-bit prefetch) and four (4-bit prefetch) DDR · Target 600 Mb/s/p data , issued in total each 32ms) OPTIONS MARKING · Clock Cycle Timing 3.3ns (300 MHz) 4ns (250 MHz , DESCRIPTION 8 Meg x 32 16 Meg x 16 GENERAL DESCRIPTION The Micron ® 256Mb Reduced Latency DRAM (RLDRAM) contains 8 banks x32Mb of memory accessible with 32-bit or 16-bit I/Os in a double data rate (DDR) format
Micron Technology
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MT49H8M32 MT49H16M16 MT49H8M32FM MICRON diode 2u 24256 MARKING WB1 Micron DDR marking H12 micron power resistor WR1 marking code 144-B MT49H16M

smd diode schottky code marking 2U

Abstract: smd wb3 to the Micron Web site: www.micron.com/dramds FEATURES 144-Ball T-FBGA · 2.5V VEXT, 1.8V VDD , Non-interruptible sequential burst of two (2-bit prefetch) and four (4-bit prefetch) DDR · Target 600 Mb/s/p data , issued in total each 32ms) OPTIONS MARKING · Clock Cycle Timing 3.3ns (300 MHz) 4ns (250 MHz , DESCRIPTION 8 Meg x 32 16 Meg x 16 GENERAL DESCRIPTION The Micron ® 256Mb Reduced Latency DRAM (RLDRAM) contains 8 banks x32Mb of memory accessible with 32-bit or 16-bit I/Os in a double data rate (DDR) format
Micron Technology
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smd diode schottky code marking 2U smd wb3 smd diode marking codes 2U smd marking WB3 smd wb1 smd diode schottky code marking 2F

smd marking codes BA5

Abstract: LATENCY (RLDRAM II) FEATURES · 288Mb · 400 MHz DDR operation (800 Mb/s/pin data rate) · Organization - , GENERAL DESCRIPTION The Micron® 288Mb Reduced Latency DRAM (RLDRAM) is a high-speed memory device , achieves a peak bandwidth of 28.8 Gb/s using two separate 18-bit double data rate (DDR) ports and a maximum system clock of 400 MHz. The double data rate (DDR) separate I/O interface transfers two 18- or 9 , ) 5ns (200 MHz) · Configuration 16 Meg x 18 32 Meg x 9 · Package 144-ball, 11mm x 18.5mm FBGA MARKING
Micron Technology
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smd marking codes BA5 MT49H16M18C MT49H32M9C
Abstract: LATENCY (RLDRAM II) FEATURES · 288Mb · 400 MHz DDR operation (800 Mb/s/pin data rate) · Organization - , GENERAL DESCRIPTION The Micron® 288Mb Reduced Latency DRAM (RLDRAM) is a high-speed memory device , achieves a peak bandwidth of 28.8 Gb/s using two separate 18-bit double data rate (DDR) ports and a maximum system clock of 400 MHz. The double data rate (DDR) separate I/O interface transfers two 18- or 9 , ) 5ns (200 MHz) · Configuration 16 Meg x 18 32 Meg x 9 · Package 144-ball, 11mm x 18.5mm uBGA MARKING Micron Technology
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smd dk qk

Abstract: SMD MARKING CODE ACY LATENCY (RLDRAM II) FEATURES · 288Mb · 400 MHz DDR operation (800 Mb/s/pin data rate) · Organization - , GENERAL DESCRIPTION The Micron® 288Mb Reduced Latency DRAM (RLDRAM) is a high-speed memory device , achieves a peak bandwidth of 28.8 Gb/s using two separate 18-bit double data rate (DDR) ports and a maximum system clock of 400 MHz. The double data rate (DDR) separate I/O interface transfers two 18- or 9 , ) 5ns (200 MHz) · Configuration 16 Meg x 18 32 Meg x 9 · Package 144-ball, 11mm x 18.5mm FBGA MARKING
Micron Technology
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smd dk qk SMD MARKING CODE ACY RLDRAM smd marking codes BA2

SMD d1c

Abstract: qkx capacitor LATENCY (RLDRAM II) FEATURES · 288Mb · 400 MHz DDR operation (800 Mb/s/pin data rate) · Organization - , GENERAL DESCRIPTION The Micron® 288Mb Reduced Latency DRAM (RLDRAM) is a high-speed memory device , achieves a peak bandwidth of 28.8 Gb/s using two separate 18-bit double data rate (DDR) ports and a maximum system clock of 400 MHz. The double data rate (DDR) separate I/O interface transfers two 18- or 9 , ) 5ns (200 MHz) · Configuration 16 Meg x 18 32 Meg x 9 · Package 144-ball, 11mm x 18.5mm FBGA MARKING
Micron Technology
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SMD d1c qkx capacitor smd codes marking A21

BA5 marking

Abstract: BA7 marking (RLDRAM II) MT49H16M18C MT49H32M9C Features Figure 1: 144-Ball FBGA · 288Mb · 400 MHz DDR , 32 Meg x 9 RLDRAM II Marking · Clock Cycle Timing 2.5ns (400 MHz) 3.3ns (300 MHz) 5ns (200 , : Table 1: -25 -33 -5 MT49H16M18CFM MT49H32M9CFM FM BM (lead-free)1 1. Contact Micron for , 11/04 EN 1 ©2004 Micron Technology, Inc. All rights reserved. PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. 16 MEG x 18, 32 MEG x 9 2.5V VEXT
Micron Technology
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BA5 marking BA7 marking plastic BA5 marking code A53 SMD Marking Code ba7 transistor smd cod MT49H16M18CFM- MT49H32M9CFM- MT49H8M18C
Abstract: (RLDRAM II) Features · 288Mb · 400 MHz DDR operation (800 Mb/s/pin data rate) · Organization · 16 Meg x , Meg x 9 · Package 144-ball FBGA (11mm x 18.5mm) NOTE: Marking -25 -33 -5 MT49H16M18CFM MT49H32M9CFM FM BM (lead-free)1 1. Contact Micron for availability of lead-free products. pdf: 09005aef80a41b59/zip: 09005aef811ba111 MT49H8M18C_1.fm - Rev. F 11/04 EN 1 ©2004 Micron Technology, Inc. All rights reserved. PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT Micron Technology
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Abstract: 93 mW (Typical) External Memory Support: ­ 166-MHz Mobile DDR SDRAM ­ 33.3-MHz Serial FLASH 176 , Color Space Conversion ­ Gamma Correction DMD DDR Data DMD DDR Control Flash I/F DMD Reset , frame for intervals in which no new frame has been received. Mobile DDR RAM Optical Sensor CTL(9 , JANUARY 2012 ­ REVISED JULY 2013 www.ti.com Device Marking The device marking consists of the fields , Material LLLLLLLL.ZZ KOREAYYWW G8 Pin #1 ID Figure 9. Device Marking SIGNAL FUNCTIONAL Texas Instruments
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DLPC300 DLPS023B DLP3000 RGB888 RGB666 RGB565
Abstract: REDUCED LATENCY (RLDRAM II) FEATURES · 288Mb · 400 MHz DDR operation (800 Mb/s/pin data rate) · , DESCRIPTION The Micron® 288Mb Reduced Latency DRAM (RLDRAM) is a high speed memory device designed for high , (DDR) interface transfers two 36-, 18-, or 9-bit wide data word per clock cycle at the I/O pins. Output , Configuration 8 Meg x 36 16 Meg x 18 32 Meg x 9 · Package 144-pin, 11mm x 18.5mm uBGA MARKING -2.5 -3.3 -5 , , Pub. 03/03 1 Micron Technology, Inc., reserves the right to change products or specifications Micron Technology
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MT49H8M36 MT49H16M18 MT49H32M9

MARKING H1 AMP

Abstract: REDUCED LATENCY (RLDRAM II) FEATURES · 288Mb · 400 MHz DDR operation (800 Mb/s/pin data rate) · , DESCRIPTION The Micron® 288Mb Reduced Latency DRAM (RLDRAM) is a high speed memory device designed for high , (DDR) interface transfers two 36-, 18-, or 9-bit wide data word per clock cycle at the I/O pins. Output , Configuration 8 Meg x 36 16 Meg x 18 32 Meg x 9 · Package 144-pin, 11mm x 18.5mm FBGA MARKING -2.5 -3.3 -5 , , Pub. 03/03 1 Micron Technology, Inc., reserves the right to change products or specifications
Micron Technology
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MARKING H1 AMP
Abstract: REDUCED LATENCY (RLDRAM II) FEATURES · 288Mb · 400 MHz DDR operation (800 Mb/s/pin data rate) · , DESCRIPTION The Micron® 288Mb Reduced Latency DRAM (RLDRAM) is a high speed memory device designed for high , (DDR) interface transfers two 36-, 18-, or 9-bit wide data word per clock cycle at the I/O pins. Output , Configuration 8 Meg x 36 16 Meg x 18 32 Meg x 9 · Package 144-pin, 11mm x 18.5mm FBGA MARKING -2.5 -3.3 -5 , , Pub. 03/03 1 Micron Technology, Inc., reserves the right to change products or specifications Micron Technology
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plastic BA7 marking code

Abstract: REDUCED LATENCY (RLDRAM II) FEATURES · 288Mb · 400 MHz DDR operation (800 Mb/s/pin data rate) · , DESCRIPTION The Micron® 288Mb Reduced Latency DRAM (RLDRAM) is a high speed memory device designed for high , (DDR) interface transfers two 36-, 18-, or 9-bit wide data word per clock cycle at the I/O pins. Output , Configuration 8 Meg x 36 16 Meg x 18 32 Meg x 9 · Package 144-pin, 11mm x 18.5mm uBGA MARKING -2.5 -3.3 -5 , , Pub. 03/03 1 Micron Technology, Inc., reserves the right to change products or specifications
Micron Technology
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plastic BA7 marking code
Abstract: Automatic Gain Control 60 MHz Double Data Rate (DDR) DMD Interface External Memory Support: 100 MHz SDR , I/F processing · Horizontal and vertical flip processing DMD DDR Data 10 DMD DDR Control Flash , clock JTAG, test mode select JTAG, serial data out NO. H2 H1 C1 G12 H12 H13 J3 H5 F4 H14 I/O TYPE I1 O1 , signal DMD data pins. DMD Data pins are double data rate (DDR) signals that are clocked on both edges of , DLPC100 ASIC DMD interface consists of a 60.0 MHz (nominal) DDR output-only interface with LVCMOS Texas Instruments
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DLPS019B DLP1700 DLPR100 BT656-YUV 256-P ISO/TS16949

marking code a02 SMD Transistor

Abstract: transistor SMD DK · 288Mb · 400 MHz DDR operation (800 Mb/s/pin data rate) · Organization - 8 Meg x 36, 16 Meg x 18 , VDDQ I/O · On-die termination (ODT) RTT OPTIONS GENERAL DESCRIPTION The Micron® 288Mb Reduced , -bit interface and a maximum system clock of 400 MHz. The double data rate (DDR) interface transfers two 36 , high-speed data transfer rates and a simple upgrade path from former products. MARKING · Clock Cycle , /03 PRODUCTS NOTE: 1. Burst of 8 on x18 and x9 devices only. 1 Micron Technology, Inc
Micron Technology
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marking code a02 SMD Transistor transistor SMD DK Diode A3X marking BAX smd transistor marking d1c transistor smd marking BA RE

MT49H8M18C

Abstract: marking ba5 (RLDRAM®) II MT49H16M18C For the latest data sheet, refer to Micron's Web site: www.micron.com/rldram Features · 400 MHz DDR operation (800 Mb/s/pin data rate) · Organization ­ 16 Meg x 18 separate I/O ­ 8 , 144-ball uBGA ­ 144-ball uBGA (Pb-free) ­ 144-ball FBGA ­ 144-ball FBGA (Pb-Free) Marking -25 -33 -5 MT49H16M18C None IT Part Number MT49H16M18CHU-xx FM2 BM1,2 HU HT Notes: 1. Contact Micron , : 09005aef80a41b59/Source: 09005aef811ba111 MT49H8M18C_1.fm - Rev. H 9/06 EN 1 Micron Technology, Inc
Micron Technology
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marking ba5 15READ
Abstract: ) Marking -25 -33 -5 MT49H16M18C None IT FM BM1 Notes: 1. Contact Micron for availability of , ®) II MT49H16M18C For the latest data sheet, refer to Micron's Web site: www.micron.com/rldram Features · 400 MHz DDR operation (800 Mb/s/pin data rate) · Organization 16 Meg x 18 separate I/O 8 banks , MT49H16M18CFM-xx PDF: 09005aef80a41b59/Source: 09005aef811ba111 MT49H8M18C_1.fm - Rev. G 7/05 EN 1 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002 Micron Micron Technology
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Abstract: REDUCED LATENCY (RLDRAM II) Features · 288Mb · 400 MHz DDR operation (800 Mb/s/pin data rate) · , Meg x 9 · Package 144-pin, 11mm x 18.5mm FBGA NOTE: Marking -2.5 -3.3 -5 MT49H16M18CFM MT49H32M9CFM FM BM (Lead-free)1 1. Contact Micron for availability of lead-free products. (Source MDM Number) MT49H8M18C_1.fm - Rev. 4 5/04 EN 1 ©2004 Micron Technology, Inc. All rights reserved , TO CHANGE BY MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON'S PRODUCTION Micron Technology
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chip dmd ti dlp

Abstract: K4M28163PH-BG75 Automatic Gain Control 60 MHz Double Data Rate (DDR) DMD Interface External Memory Support: 100 MHz SDR , flip processing DMD DDR Data 10 DMD DDR Control Flash I/F I2C Bus Oscillator CONTROL , . (Must be tied low for proper operation) MSEL_1 H12 I1 Asynch Mode selection signals , rate (DDR) signals that are clocked on both edges of DMD_DCLK. DMD data clock 24-bit data is , DMD Interface The DLPC100 ASIC DMD interface consists of a 60.0 MHz (nominal) DDR output-only
Texas Instruments
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DLPS019A chip dmd ti dlp K4M28163PH-BG75 DPP1500 DLP pico projector RGB565 to rgb888 samsung dmd chip
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