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STELLARIS-3P-CMXSI-MICRONET-STACK Texas Instruments CMX-MicroNet ri Buy
BEMICRONIO-2-PROCSDK-REF Texas Instruments Altera/Arrow BeMicro Nios II Processor SDK with DP83848 in USB Stick Format ri Buy
1206USB-672MBB Coilcraft Inc Data Line Filter, 2 FUNCTIONS, DATA LINE FILTER, SURFACE MOUNT ri Buy

Micron DDR marking H12

Catalog Datasheet Results Type PDF Document Tags
Abstract: , Burst Mode Flash Memory and 128/256-Mb (8/16-M 8/16-M x 16-bit) DDR DRAM ADVANCE INFORMATION Data Sheet , /Write, Burst Mode Flash Memory and 128/256-Mb (8/16-M 8/16-M x 16-bit) DDR DRAM ADVANCE INFORMATION Data , the Flash memory component. Refer to the DDR SDRAM Type 1 data sheet (revision A2) for full electrical specifications of the DDR SDRAM component. Refer to the DDR SDRAM Type 5 data sheet (revision A0) for full electrical specifications of the DDR SDRAM component The S72NS S72NS Series is a product line of ... Original
datasheet

17 pages,
302.4 Kb

S72NS512ND0 F12 MARK MICRON mcp NS512 S29NS-N S72NS-N ADQ14 Multi-Chip Package MEMORY ADQ12 8/16-M S72NS-N abstract
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Abstract: LATENCY (RLDRAM II) FEATURES · 288Mb · 400 MHz DDR operation (800 Mb/s/pin data rate) · Organization - , GENERAL DESCRIPTION The Micron® 288Mb Reduced Latency DRAM (RLDRAM) is a high-speed memory device , achieves a peak bandwidth of 28.8 Gb/s using two separate 18-bit double data rate (DDR) ports and a maximum system clock of 400 MHz. The double data rate (DDR) separate I/O interface transfers two 18- or 9-bit , ) 5ns (200 MHz) · Configuration 16 Meg x 18 32 Meg x 9 · Package 144-ball, 11mm x 18.5mm FBGA MARKING ... Original
datasheet

46 pages,
580.39 Kb

smd marking codes BA5 smd dk qk SMD MARKING CODE ACY datasheet abstract
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Abstract: LATENCY (RLDRAM II) FEATURES · 288Mb · 400 MHz DDR operation (800 Mb/s/pin data rate) · Organization - , GENERAL DESCRIPTION The Micron® 288Mb Reduced Latency DRAM (RLDRAM) is a high-speed memory device , achieves a peak bandwidth of 28.8 Gb/s using two separate 18-bit double data rate (DDR) ports and a maximum system clock of 400 MHz. The double data rate (DDR) separate I/O interface transfers two 18- or 9-bit , ) 5ns (200 MHz) · Configuration 16 Meg x 18 32 Meg x 9 · Package 144-ball, 11mm x 18.5mm FBGA MARKING ... Original
datasheet

46 pages,
608.78 Kb

SMD MARKING CODE ACY SMD d1c datasheet abstract
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Abstract: LATENCY (RLDRAM II) FEATURES · 288Mb · 400 MHz DDR operation (800 Mb/s/pin data rate) · Organization - , GENERAL DESCRIPTION The Micron® 288Mb Reduced Latency DRAM (RLDRAM) is a high-speed memory device , achieves a peak bandwidth of 28.8 Gb/s using two separate 18-bit double data rate (DDR) ports and a maximum system clock of 400 MHz. The double data rate (DDR) separate I/O interface transfers two 18- or 9-bit , ) 5ns (200 MHz) · Configuration 16 Meg x 18 32 Meg x 9 · Package 144-ball, 11mm x 18.5mm µBGA MARKING ... Original
datasheet

46 pages,
577.2 Kb

datasheet abstract
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Abstract: to the Micron Web site: www.micron.com/dramds FEATURES 144-Ball T-FBGA · 2.5V VEXT, 1.8V VDD , Non-interruptible sequential burst of two (2-bit prefetch) and four (4-bit prefetch) DDR · Target 600 Mb/s/p data , issued in total each 32ms) OPTIONS MARKING · Clock Cycle Timing 3.3ns (300 MHz) 4ns (250 MHz , DESCRIPTION 8 Meg x 32 16 Meg x 16 GENERAL DESCRIPTION The Micron ® 256Mb Reduced Latency DRAM (RLDRAM) contains 8 banks x32Mb of memory accessible with 32-bit or 16-bit I/Os in a double data rate (DDR) format ... Original
datasheet

43 pages,
649.39 Kb

Micron 4g diode wb7 diode marking code 4n MICRON 63 code Marking wb6 5256 DRAM 43256 MT49H16M16 MT49H16M16FM MT49H8M32 MT49H8M32FM Marking D1c MARKING WB1 marking WB4 datasheet abstract
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Abstract: to the Micron Web site: www.micron.com/dramds FEATURES 144-Ball T-FBGA · 2.5V VEXT, 1.8V VDD , Non-interruptible sequential burst of two (2-bit prefetch) and four (4-bit prefetch) DDR · Target 600 Mb/s/p data , issued in total each 32ms) OPTIONS MARKING · Clock Cycle Timing 3.3ns (300 MHz) 4ns (250 MHz , DESCRIPTION 8 Meg x 32 16 Meg x 16 GENERAL DESCRIPTION The Micron ® 256Mb Reduced Latency DRAM (RLDRAM) contains 8 banks x32Mb of memory accessible with 32-bit or 16-bit I/Os in a double data rate (DDR) format ... Original
datasheet

43 pages,
440.54 Kb

MARKING d2b smd transistor marking 12G smd diode marking G12 WR1 marking code MARKING WB1 MICRON diode 2u smd wb2 smd diode schottky code marking 1A smd code book 9u wb3 smd code SMD marking CODE 2U smd transistor 12p datasheet abstract
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Abstract: (RLDRAM II) Features · 288Mb · 400 MHz DDR operation (800 Mb/s/pin data rate) · Organization · 16 Meg x , Meg x 9 · Package 144-ball FBGA (11mm x 18.5mm) NOTE: Marking -25 -33 -5 MT49H16M18CFM MT49H16M18CFM MT49H32M9CFM MT49H32M9CFM FM BM (lead-free)1 1. Contact Micron for availability of lead-free products. pdf: 09005aef80a41b59/zip: 09005aef811ba111 MT49H8M18C MT49H8M18C_1.fm - Rev. F 11/04 EN 1 ©2004 Micron Technology, Inc. All rights reserved. PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT ... Original
datasheet

44 pages,
1021.91 Kb

datasheet abstract
datasheet frame
Abstract: (RLDRAM II) MT49H16M18C MT49H16M18C MT49H32M9C MT49H32M9C Features Figure 1: 144-Ball FBGA · 288Mb · 400 MHz DDR , 32 Meg x 9 RLDRAM II Marking · Clock Cycle Timing 2.5ns (400 MHz) 3.3ns (300 MHz) 5ns (200 , : Table 1: -25 -33 -5 MT49H16M18CFM MT49H16M18CFM MT49H32M9CFM MT49H32M9CFM FM BM (lead-free)1 1. Contact Micron for , 11/04 EN 1 ©2004 Micron Technology, Inc. All rights reserved. PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. 16 MEG x 18, 32 MEG x 9 2.5V VEXT ... Original
datasheet

44 pages,
1024.64 Kb

MARKING A53 diode smd marking BAX Marking D1c MARKING SMD x9 A22 SMD MARKING CODE SMD d2c SMD MARKING CODE A12 transistor SMD DK rc MT49H32M9C MT49H16M18C transistor smd zq Transistor smd marking A53 smd cod datasheet abstract
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Abstract: ) Marking -25 -33 -5 MT49H16M18C MT49H16M18C None IT FM BM1 Notes: 1. Contact Micron for availability of , ®) II MT49H16M18C MT49H16M18C For the latest data sheet, refer to Micron's Web site: www.micron.com/rldram Features · 400 MHz DDR operation (800 Mb/s/pin data rate) · Organization 16 Meg x 18 separate I/O 8 banks , MT49H16M18CFM-xx PDF: 09005aef80a41b59/Source: 09005aef811ba111 MT49H8M18C MT49H8M18C_1.fm - Rev. G 7/05 EN 1 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002 Micron ... Original
datasheet

48 pages,
1400.52 Kb

MT49H16M18C MT49H16M18C abstract
datasheet frame
Abstract: LATENCY (RLDRAM II) FEATURES · 288Mb · 400 MHz DDR operation (800 Mb/s/pin data rate) · Organization - , GENERAL DESCRIPTION The Micron® 288Mb Reduced Latency DRAM (RLDRAM) is a high-speed memory device , achieves a peak bandwidth of 28.8 Gb/s using two separate 18-bit double data rate (DDR) ports and a maximum system clock of 400 MHz. The double data rate (DDR) separate I/O interface transfers two 18- or 9-bit , ) 5ns (200 MHz) · Configuration 16 Meg x 18 32 Meg x 9 · Package 144-ball, 11mm x 18.5mm FBGA MARKING ... Original
datasheet

47 pages,
680.28 Kb

datasheet abstract
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www.datasheetarchive.com/download/36331940-595893ZC/ird.cd.contents.zip (user.manual.lpc24xx.pdf)
NXP 23/10/2012 35869.34 Kb ZIP ird.cd.contents.zip