NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
MEPUM05006-J21 001227DAA1 MEPUM05006-J20 MEPUM05006-J10 11RAM 11ARAM 13RAM - Datasheet Archive
MeP (MeP-c4) MeP MeP-c4 MeP (MeP-c4) ( MEPUM05006-J21 -i- MeP MeP-c4 "" 001227DAA1 © TOSHIBA CORPORATION
MeP (MeP-c4) MeP MeP-c4 MeP (MeP-c4) ( MEPUM05006-J21 MEPUM05006-J21 -i- MeP MeP-c4 "" 001227DAA1 001227DAA1 © TOSHIBA CORPORATION 2005 All Rights Reserved MEPUM05006-J21 MEPUM05006-J21 - ii - MeP MeP-c4 1. . 1 1.1. . 2 1.2. . 2 1.2.1. . 2 1.2.2. . 2 1.2.3. . 2 1.2.4. . 2 2. . 3 2.1. MeP . 4 2.2. MeP . 5 2.2.1. BIU . 5 2.2.2. . 6 2.2.3. RAM . 7 2.2.4. . 8 2.2.5. . 9 2.2.6. /. 9 2.2.7. . 10 2.2.8. PRN . 10 2.2.9. . 10 2.3. MeP. 11 2.4. MeP. 12 2.4.1. RAM . 12 2.4.2. RAM. 14 2.4.3. . 16 2.4.4. . 24 3. . 30 3.1. MeP . 31 3.1.1. BIU . 31 3.1.2. . 37 3.1.3. . 42 3.1.4. xInt . 44 3.1.5. NMI. 44 3.1.6. . 45 3.1.7. Sleep/Halt . 46 3.2. MeP . 47 3.2.1. RAM . 47 3.2.2. RAM . 49 3.2.3. . 51 3.2.4. . 55 MEPUM05006-J21 MEPUM05006-J21 - iii - MeP MeP-c4 MEPUM05006-J21 MEPUM05006-J21 (2005 11 25 ) · P.10 2.2.8 (PRN) MEPUM05006-J20 MEPUM05006-J20 (2005 11 05 ) · MEPUM05006-J10a (2005 09 26 ) · MEPUM05006-J10 MEPUM05006-J10 (2005 08 25 ) · MEPUM05006-J21 MEPUM05006-J21 - iv - MeP MeP-c4 1. MEPUM05006-J21 MEPUM05006-J21 -1- MeP MeP-c4 1.1. Media embedded ProcessorMePMeP MeP (MeP-c4) MeP MeP MeP DSP 1.2. 1.2.1. 16 0x 0x2A 10 42 10 2 K 1024 1.2.2. byte halfword word doubleword 1.2.3. 8 bit B 2 16 4 32 8 64 assert deassert 1.2.4. MM . MeP ME . MeP BIU . DMAC . DMA LM . HE . I/F . LB . CB . GBIF . I/F DS . MEPUM05006-J21 MEPUM05006-J21 -2- MeP MeP-c4 2. MeP (MeP-c4) bibrAddr bibrRe bibrWe C bibrBe [31:0] BIUGBIF BIUGBIF BIUGBIF [7:0] or BIUGBIF [3:0] bibrBe[7] : bibrBe[6] : bibrBe[5] : bibrBe[4] : bibrBe[3] : bibrBe[2] : bibrBe[1] : bibrBe[0] : d 0 0 d 63:56 55:48 47:40 39:32 31:24 23:16 15:8 7:0 / O C B resetB MeP MeP input, output MeP d MeP MEPUM05006-J21 MEPUM05006-J21 -3- MeP MeP-c4 2.1. MeP MeP 1MePMePI/F MeP I/F MeP(MeP-c4) I/F 32 UCI I/F RAM BIU I/F RAM UCI DSP I/F DSP I/F BIU I/F I/F DMA 1 MeP BIU I/F BIU I/O I/F RAM RAM I/F MeP DSP DMA I/F MeP DIMEJTAG // NMI MeP (Halt,Sleep)MeP MEPUM05006-J21 MEPUM05006-J21 -4- MeP MeP-c4 2.2. MeP 2.2.1. BIU BIU 32 64 bibrLock 1 bibrAddr bibrRe bibrWe C bibrBe bibrBstart bibrBurst bibrBstsz BIU [31:0] [7:0] [3:0] or BIUGBIF BIUGBIF BIUGBIF BIUGBIF BIUGBIF BIUGBIF BIUGBIF [4:0] bibrData brbiData bibrBe[7:0] bibrBe[7] : [63:56] bibrBe[6] : [55:48] bibrBe[5] : [47:40] bibrBe[4] : [39:32] bibrBe[3] : [31:24] bibrBe[2] : [23:16] bibrBe[1] : [15:8] bibrBe[0] : [7:0] bibrBe[3:0] bibrBe[3] : [31:24] bibrBe[2] : [23:16] bibrBe[1] : [15:8] bibrBe[0] : [7:0] 00100 4 01000 8 10000 16 d 0 0 d 0 d d C bibrData [63:0] [31:0] or BIUGBIF C brbiData [63:0] [31:0] or GBIFBIU GBIFBIU BIUGBIF GBIFBIU 0 brbiAck O bibrLock brbiBerr d MEPUM05006-J21 MEPUM05006-J21 -5- MeP MeP-c4 1 2 2.2.2. bibrAddr 3 bibrAddr BIU 32'h0000_0003 32'h0000_0000 bibrBe bibrBe[7:0] 8'b0000_0001, 8'b0000_0010, 8'b0000_0100, 8'b0000_1000 8'b0001_0000, 8'b0010_0000, 8'b0100_0000, 8'b1000_0000 8'b0000_0011, 8'b0000_1100, 8'b0011_0000, 8'b1100_0000 8'b0000_1111, 8'b1111_0000, 8'b1111_1111 bibrBe[3:0] 4'b0001, 4'b0010, 4'b0100, 4'b1000, 4'b0011, 4'b1100, 4'b1111 32 64 RAMRAM 2 2 O lblmReq O lblmRe C lblmWe O LBLM LBLM [7:0] or LBLM [3:0] O lblmIDBank [19:9] O lblmAddr [19:0] C lblmData [63:0] or O [31:0] C lmlbData [63:0] or O [31:0] lblmWe lblmData lblmWe[7:0] lblmWe[7] : [63:56] lblmWe[6] : [55:48] lblmWe[5] : [47:40] lblmWe[4] : [39:32] lblmWe[3] : [31:24] lblmWe[2] : [23:16] lblmWe[1] : [15:8] lblmWe[0] : [7:0] lblmWe[3:0] lblmWe[3] : [31:24] lblmWe[2] : [23:16] lblmWe[1] : [15:8] lblmWe[0] : [7:0] LBLM RAM/ RAM LBLM LBLM LMLB d MEPUM05006-J21 MEPUM05006-J21 -6- MeP MeP-c4 RAM 2.2.3. RAM 3DSPRAM 3 RAM O xDspLowDmem input RAM 1 0: DMAC2> DSP > MeP () 1: DMAC2 > (DSP, MeP ) DSP, MeP - 1 Sleep 2 DMAC MeP I/F DMAC MeP RAM xDspLowDmem 1 DSP MeP RAM DSP MeP DSP RAM MeP MeP DSP RAM MeP RAM (lmdp?Busy) DSP MeP DSP MeP MeP MEPUM05006-J21 MEPUM05006-J21 -7- MeP MeP-c4 2.2.4. 4 DSP DMA 4 O O O O O lscbAddr lscbRe lscbWe lscbData cblsData [15:0] MECB MECB MECB [31:0] MECB [31:0] CBME d 0 0 d MEPUM05006-J21 MEPUM05006-J21 -8- MeP MeP-c4 2.2.5. 5 5 O xDint 0 EJTAG DRET MeP input O xDm output O xProbeEn input O xDretStall input O xDBSDAO output 0 O xDBSEL input O xDBSDI input O xJTRST output EJTAG DIME DBG JTRST JTRST O xDtrigger output 0 2.2.6. / xInt/ 6cpuclkcore, cpuclkmem MePxIntMeP 6 cpuclk / input ( OFF halt, sleep ) O cpuclkcore input halt, sleep O cpuclkmem input sleep C xInt [CD] input O C= D= xNmi input 1 xInt[0:0]xInt MEPUM05006-J21 MEPUM05006-J21 -9- MeP MeP-c4 2.2.7. (1) 7 7 reset (2) input H 8 8 resetB 2.2.8. input L PRN 9IDPRN PRN 9 (PRN) xPRN [7:0] input MeP xRPN 2.2.9. 10 xAwake 10 xSleep xHalt O xAwake Sleep/Halt output ME sleep 0 output ME halt 0 output ME sleep,halt 0 MEPUM05006-J21 MEPUM05006-J21 - 10 - MeP MeP-c4 2.3. MeP MeP 2 1 SRAM RAM RAM RAM RAM RAM RAM RAM 2 RAM 3 MeP (Way0) (Way1) 2 MeP MeP MEPUM05006-J21 MEPUM05006-J21 - 11 - MeP MeP-c4 2.4. MeP 2.4.1. RAM RAM ? 0,1 RAM 11RAM 11RAM 11 C imb?Addr O O imb?Data O imb?ME O imb?WE O imb?BE O imb?SLEEP O moi?Data RAM [A:0] ? d [63:0] ? d ? 0 ? 0 imb?ME Read: 0 Write: 1 d [7:0] ? imb?Data, moi?Data imb?BE[7] : [63:56] imb?BE[6] : [55:48] imb?BE[5] : [47:40] imb?BE[4] : [39:32] imb?BE[3] : [31:24] imb?BE[2] : [23:16] imb?BE[1] : [15:8] imb?BE[0] : [7:0] 0 ? imb?ME [63:0] ? imb?ME 11ARAM 11ARAM 12 MEPUM05006-J21 MEPUM05006-J21 - 12 - MeP MeP-c4 12 RAM A 0 1 1KB 5 5 2KB 6 6 4KB 7 7 6KB 8 7 8KB 8 8 12KB 9 8 16KB 9 9 24KB 10 9 32KB 10 10 MEPUM05006-J21 MEPUM05006-J21 - 13 - MeP MeP-c4 2.4.2. RAM RAM ? 0,1,2,3 RAM 13RAM 13RAM 13 RAM C dmb?Addr [A:0] ? d O C dmb?Data [B:0] ? d O O dmb?ME ? 1 O dmb?WE ? 2 dmb?ME Read: 0 Write: 1 d C dmb?BE [C:0] ? O dmb?Data, mod?Data dmb?BE[7] : [63:56] dmb?BE[6] : [55:48] dmb?BE[5] : [47:40] dmb?BE[4] : [39:32] dmb?BE[3] : [31:24] dmb?BE[2] : [23:16] dmb?BE[1] : [15:8] dmb?BE[0] : [7:0] 0 O dmb?SLEEP ? dmb?ME C mod?Data [B:0] ? O dmb?ME 1 dmb?ME DSP- dplm0Re, dplm1Re, dplm0We, dplm1We 0 dmb?ME MEPUM05006-J21 MEPUM05006-J21 - 14 - MeP MeP-c4 2 dmb?WE DSP- dplm0We, dplm1We lblmWe 0 dmb?We 13ARAM 13ARAM 14 13B,CBIUDSP 15 14 RAM A 0 1 2 3 2 1KB 5 5 2KB 6 6 4KB 7 7 6KB 7 7 8KB 8 8 12KB 8 8 16KB 9 9 24KB 10 9 9 9 48KB 10 10 10 96KB 4 9 10 24KB 3 9 32KB 11 11 11 32KB 9 9 9 10 10 10 10 128KB 128KB 15 9 64KB 11 11 11 11 RAM B,C BIU DSP B C 32 32 32 31 3 32 32 / 64 63 7 32 64 / 32/ 64 63 7 32 / 32/ 64 63 7 64 64 / 32/ 64 63 7 64 / 32/ 64 63 7 MEPUM05006-J21 MEPUM05006-J21 - 15 - MeP MeP-c4 2.4.3. (1) () 16 2Way 16 C ikdaAddr O O ikdaData O ikdaME O ikdaWE O ikdaBE O ikdaSLEEP O moidData [A:0] d [63:0] d 0 0 ikdaME Read: 0 Write: 1 d [7:0] ikdaData, moidData ikdaBE[7] : [63:56] ikdaBE[6] : [55:48] ikdaBE[5] : [47:40] ikdaBE[4] : [39:32] ikdaBE[3] : [31:24] ikdaBE[2] : [23:16] ikdaBE[1] : [15:8] ikdaBE[0] : [7:0] 0 ikdaME [63:0] ikdaME MEPUM05006-J21 MEPUM05006-J21 - 16 - MeP MeP-c4 16A 17 17 A A 1KB 6 2KB 7 4KB 8 8KB 9 16KB 10 MEPUM05006-J21 MEPUM05006-J21 - 17 - MeP MeP-c4 (2) Way0 (2Way ) Way0 18 18 C ikda0Addr O O ikda0Data O ikda0ME O ikda0WE O ikda0BE O ikda0SLEEP O moieData Way0 [A:0] d [63:0] d 0 0 ikda0ME Read: 0 Write: 1 d [7:0] ikda0Data, moieData ikda0BE[7] : [63:56] ikda0BE[6] : [55:48] ikda0BE[5] : [47:40] ikda0BE[4] : [39:32] ikda0BE[3] : [31:24] ikda0BE[2] : [23:16] ikda0BE[1] : [15:8] ikda0BE[0] : [7:0] 0 ikda0ME [63:0] ikda0ME 18A 19 MEPUM05006-J21 MEPUM05006-J21 - 18 - MeP MeP-c4 19 Way0 A A 1KB 5 2KB 6 4KB 7 8KB 8 16KB 9 MEPUM05006-J21 MEPUM05006-J21 - 19 - MeP MeP-c4 (3) Way1 (2Way ) Way1 20 20 C ikda1Addr O O ikda1Data O ikda1ME O ikda1WE O ikda1BE O ikda1SLEEP O moifData Way1 [A:0] d [63:0] d 0 0 ikda1ME Read: 0 Write: 1 d [7:0] ikda1Data, moifData ikda1BE[7] : [63:56] ikda1BE[6] : [55:48] ikda1BE[5] : [47:40] ikda1BE[4] : [39:32] ikda1BE[3] : [31:24] ikda1BE[2] : [23:16] ikda1BE[1] : [15:8] ikda1BE[0] : [7:0] 0 ikda1ME [63:0] ikda1ME 20A 21 MEPUM05006-J21 MEPUM05006-J21 - 20 - MeP MeP-c4 21 Way1 A A 1KB 5 2KB 6 4KB 7 8KB 8 16KB 9 MEPUM05006-J21 MEPUM05006-J21 - 21 - MeP MeP-c4 (4) 22 22 C iktgAddr O C iktgData O O iktgME O iktgWE C iktgBE O O iktgSLEEP C moitData O [B:0] d [A:0] d 0 0 iktgME Read: 0 Write: 1 d [A:0] bit 1 0 0 iktgME [A:0] iktgME MEPUM05006-J21 MEPUM05006-J21 - 22 - MeP MeP-c4 22A,B 232way 24 23 A,B 64 32 1KB 2KB 4KB 8KB 16KB 24 A 22 21 20 19 18 B 4 5 6 7 8 B 3 4 5 6 7 128 A 22 21 20 19 18 B 2 3 4 5 6 2way A,B 64 32 1KB 2KB 4KB 8KB 16KB A 22 21 20 19 18 A 48 46 44 42 40 B 3 4 5 6 7 A 48 46 44 42 40 B 2 3 4 5 6 128 A 48 46 44 42 40 B 1 2 3 4 5 MEPUM05006-J21 MEPUM05006-J21 - 23 - MeP MeP-c4 2.4.4. (1) 25 25 C dkdaAddr O O dkdaData O dkdaME O dkdaWE O dkdaBE [A:0] () d [B:0] () d () 0 () 0 dkdaME Read: 0 Write: 1 d [C:0] () dkdaData, moddData dkdaBE[15] : [127:120] dkdaBE[14] : [119:112] dkdaBE[13] : [111:104] dkdaBE[12] : [103:96] dkdaBE[11] : [95:88] dkdaBE[10] : [87:80] dkdaBE[9] : [79:72] dkdaBE[8] : [71:64] dkdaBE[7] : [63:56] dkdaBE[6] : [55:48] dkdaBE[5] : [47:40] dkdaBE[4] : [39:32] dkdaBE[3] : [31:24] dkdaBE[2] : [23:16] dkdaBE[1] : [15:8] dkdaBE[0] : [7:0] MEPUM05006-J21 MEPUM05006-J21 - 24 - MeP MeP-c4 0 O dkdaSLEEP () dkdaME O moddData [B:0] () dkdaME 25A,B,C 262way 27 26 A,B,C 1KB 2KB 4KB 8KB 16KB 27 A 6 7 8 9 10 B 63 63 63 63 63 C 7 7 7 7 7 2way A,B,C 1KB 2KB 4KB 8KB 16KB A 5 6 7 8 9 B 127 127 127 127 127 C 15 15 15 15 15 MEPUM05006-J21 MEPUM05006-J21 - 25 - MeP MeP-c4 (2) 28 28 C dktgAddr O C dktgData O O dktgME O dktgWE C dktgBE O O dktgSLEEP C modtData O [B:0] () d [A:0] () d () 0 () 0 dktgME Read: 0 Write: 1 d [A:0] () bit 1 0 0 () dktgME [A:0] () dktgME MEPUM05006-J21 MEPUM05006-J21 - 26 - MeP MeP-c4 28A,B 292way 30 29 A,B 64 32 1KB 2KB 4KB 8KB 16KB 30 A 22 21 20 19 18 B 4 5 6 7 8 B 3 4 5 6 7 128 A 22 21 20 19 18 B 2 3 4 5 6 2way A,B 64 32 1KB 2KB 4KB 8KB 16KB A 22 21 20 19 18 A 48 46 44 42 40 B 3 4 5 6 7 A 48 46 45 42 40 B 2 3 4 5 6 128 A 48 46 44 42 40 B 1 2 3 4 5 MEPUM05006-J21 MEPUM05006-J21 - 27 - MeP MeP-c4 (3) 31 31 C dkdiAddr O O dkdiData O dkdiME O dkdiWE O dkdiBE O dkdiSLEEP O modiData [B:0] () d [A:0] () d () 0 0 () dkdiME Read: 0 Write: 1 d [A:0] () 0 () dkdiME [A:0] () dkdiME MEPUM05006-J21 MEPUM05006-J21 - 28 - MeP MeP-c4 31A,B 322way 33 32 A,B 64 32 1KB 2KB 4KB 8KB 16KB 33 A 4 5 6 7 8 B 0 0 0 0 0 A 3 4 5 6 7 B 0 0 0 0 0 128 A 2 3 4 5 6 B 0 0 0 0 0 2way A,B 64 32 1KB 2KB 4KB 8KB 16KB A 3 4 5 6 7 B 1 1 1 1 1 A 2 3 4 5 6 B 1 1 1 1 1 128 A 1 2 3 4 5 B 1 1 1 1 1 MEPUM05006-J21 MEPUM05006-J21 - 29 - MeP MeP-c4 3. MEPUM05006-J21 MEPUM05006-J21 - 30 - MeP MeP-c4 3.1. MeP BIU 3.1.1. (1) 1 2 3 4 cpuclk bibrAddr[31:0] bibrBe[7:0] bibrBstart bibrRe bibrWe bibrBurst bibrBstsz[4:0] brbiAck brbiData[63:0] Cycle 1: Cycle 2: Cycle 3: Cycle 4: bibrAddr[31:0], bibrBe[7:0] bibrBstart 1 bibrRe bibrBurst bibrBstart brbiAck I/F brbiAck I/F brbiAck I/F brbiData[63:0] bibrRe bibrAddr[31:0], bibrBe[7:0] MEPUM05006-J21 MEPUM05006-J21 - 31 - MeP MeP-c4 (2) 1 2 3 4 5 6 7 8 9 cpuclk bibrAddr[31:0] 32n +8 +16 +24 bibrBe[7:0] bibrBstart bibrRe bibrWe bibrBurst bibrBstsz[4:0] brbiAck brbiData[63:0] Cycle 1: Cycle 2: Cycle 3: Cycle 4: Cycle 5 ~8: Cycle 9: bibrAddr[31:0], bibrBe[7:0] bibrBe[7:0] bibrBstart 1 bibrRe bibrBurst bibrBstsz[4:0] bibrBstart brbiAck I/F brbiAck I/F brbiAck I/F brbiData[63:0] bibrAddr[31:0] I/F brbiAck bibrAddr[31:0] I/F brbiAck , bibrRe,bibrBurst bibrAddr[31:0],bibrBe[7:0],bibrBstsz[4:0] MEPUM05006-J21 MEPUM05006-J21 - 32 - MeP MeP-c4 (3) 1 2 3 4 cpuclk bibrAddr[31:0] bibrBe[7:0] bibrBstart bibrRe bibrWe bibrBurst bibrBstsz[4:0] brbiAck bibrData[63:0] Cycle 1: bibrAddr[31:0], bibrBe[7:0] bibrData[63:0] bibrBstart 1 bibrWe bibrBurst Cycle 2: bibrBstart brbiAck Cycle 3: I/F brbiAck Cycle 4: I/F brbiAck bibrWe bibrAddr[31:0], bibrBe[7:0],bibrData[63:0] MEPUM05006-J21 MEPUM05006-J21 - 33 - MeP MeP-c4 (4) 1 2 3 4 5 6 7 8 9 cpuclk bibrAddr[31:0] 32n +8 +16 +24 bibrBe[7:0] bibrBstart bibrRe bibrWe bibrBurst bibrBstsz[4:0] brbiAck bibrData[63:0] Cycle 1: bibrAddr[31:0], bibrBe[7:0] bibrBe[7:0] bibrData[63:0] bibrBstart 1 bibrWe bibrBurst bibrBstsz[4:0] Cycle 2: bibrBstart brbiAck Cycle 3: I/F brbiAck Cycle 4: I/F brbiAck bibrData[63:0] bibrAddr[31:0] Cycle 5 ~8: I/F brbiAck bibrAddr[31:0] Cycle 9: I/F brbiAck bibrWe,bibrBurst bibrAddr[31:0]bibrBe[7:0]bibrBstsz[4:0] bibrData[63:0] MEPUM05006-J21 MEPUM05006-J21 - 34 - MeP MeP-c4 (5) BTSTM 1 2 3 4 5 6 7 8 9 cpuclk bibrLock bibrAddr[31:0] bibrBe[7:0] bibrBstart bibrRe bibrWe bibrBurst bibrBstsz[4:0] brbiAck brbiData[63:0] bibrData[63:0] BTSTM bibrLock MEPUM05006-J21 MEPUM05006-J21 - 35 - MeP MeP-c4 (6) 1 2 cpuclk brbiBerr () EXC EXC.BER 1 DBG DBG.BSF 1 () DBG.BSF EXC.BER () brbiBerr MEPUM05006-J21 MEPUM05006-J21 - 36 - MeP MeP-c4 3.1.2. (1) 1 2 3 4 5 6 7 8 cpuclk lblmReq lblmRe lblmWe lblmIDBank lblmAddr lmlbData a a a lblmData Cycle1 Cycle2 Cycle3 lblmReq lblmIDBank RAM RAM lblmRe RAM lblmAddr MeP lmlbData RAM RAM MEPUM05006-J21 MEPUM05006-J21 - 37 - MeP MeP-c4 (2) 1 2 3 4 5 6 7 8 cpuclk lblmReq lblmRe lblmWe lblmIDBank lblmAddr lmlbData a b c d e a b c d a e b c d e lblmData RAM RAM MEPUM05006-J21 MEPUM05006-J21 - 38 - MeP MeP-c4 (3) 1 2 3 4 5 6 7 8 cpuclk lblmReq lblmRe lblmWe lblmIDBank lblmAddr a a lmlbData lblmData Cycle1 Cycle2 a lblmReq lblmIDBank RAM RAM lblmWe RAM lblmAddr lblmData MeP RAM RAM MEPUM05006-J21 MEPUM05006-J21 - 39 - MeP MeP-c4 (4) 1 2 3 4 5 6 7 8 cpuclk lblmReq lblmRe lblmWe lblmIDBank lblmAddr a b c d e a b c d e a b c d e lmlbData lblmData RAM RAM MEPUM05006-J21 MEPUM05006-J21 - 40 - MeP MeP-c4 (5) 1 2 3 4 5 6 7 8 cpuclk lblmReq lblmRe lblmWe lblmIDBank lblmAddr a b c d e a b c d a lmlbData lblmData e b c d e MEPUM05006-J21 MEPUM05006-J21 - 41 - MeP MeP-c4 3.1.3. MeP LDCB STCB () (1) ldcb 1 2 3 cpuclk lscbAddr[15:0] lscbRe cblsData[31:0] Cycle 1: Cycle 2: Cycle 3: (lscbAddr)(lscbRe) lscbAddr lscbRe MeP (cblsData) () ldcb MeP ldcb 1 ldcb ldcb ldcb MEPUM05006-J21 MEPUM05006-J21 - 42 - MeP MeP-c4 (2) stcb 1 cpuclk lscbAddr[15:0] lscbWe lscbData[31:0] Cycle 1: (3) (lscbAddr)(lscbData) (lscbWe) ldcb ldcb MEPUM05006-J21 MEPUM05006-J21 - 43 - MeP MeP-c4 xInt 3.1.4. (1) cpuclk xInt[C]-[0] xInt[C][0] cpuclk C 1 1-32 C 310 C=1 xInt xInt[C]xInt[0] xInt[C]xInt[0] (2) cpuclk xInt[C]-[0] xInt[C]xInt[0] cpuclk xInt[C][0] 1 INTC ISR ISR 0 3.1.5. NMI cpuclk xNmi NMI xNmi cpuclk xNmi NMI NMI NMI MeP MEPUM05006-J21 MEPUM05006-J21 - 44 - MeP MeP-c4 3.1.6. (1) 10 cpuclk reset reset cpuclk reset 10 H MeP MeP MeP reset L MeP (2) reset reset_B(reset_B L MeP L F/F LMeP MeP MeP reset_B HMeP cpuclk reset_B H F/F F/F F/F F/F cpuclk resetB MEPUM05006-J21 MEPUM05006-J21 - 45 - MeP MeP-c4 F/F cpuclk resetB Sleep/Halt 3.1.7. (1) Sleep cpuclk xSleep MeP SLEEP MeP xSleep xSleep HE (2) Halt cpuclk xHalt MeP HALT MeP xHalt xHalt HE MEPUM05006-J21 MEPUM05006-J21 - 46 - MeP MeP-c4 3.2. MeP 3.2.1. RAM 1 2 3 4 5 6 cpuclk imb?ME imb?WE imb?SLEEP imb?Addr imb?BE imb?Data moi?Data Cycle1 Cycle imb?ME RAM imb?SLEEP imb?WE L RAM moi?Data MEPUM05006-J21 MEPUM05006-J21 - 47 - MeP MeP-c4 1 2 3 4 5 6 cpuclk imb?ME imb?WE imb?SLEEP imb?Addr imb?BE imb?Data moi?Data Cycle1 imb?ME RAM imb?SLEEP imb?WE H imb?Data MEPUM05006-J21 MEPUM05006-J21 - 48 - MeP MeP-c4 3.2.2. RAM 1 2 3 4 5 6 cpuclk dmb?ME dmb?WE dmb?SLEEP dmb?Addr dmb?BE dmb?Data mod?Data Cycle1 Cycle dmb?ME RAM dmb?SLEEP dmb?WE L RAM mod?Data MEPUM05006-J21 MEPUM05006-J21 - 49 - MeP MeP-c4 1 2 3 4 5 6 cpuclk dmb?ME dmb?WE dmb?SLEEP dmb?Addr dmb?BE dmb?Data mod?Data Cycle1 dmb?ME RAM dmb?SLEEP dmb?WE H dmb?Data MEPUM05006-J21 MEPUM05006-J21 - 50 - MeP MeP-c4 3.2.3. (1) Way Way (0,1) 1 2 3 4 5 6 cpuclk ikdaME ikdaWE ikdaSLEEP ikdaAddr ikdaBE ikdaData moidData Cycle1 Cycle ikdaME ikdaSLEEP ikdaWE L moidData MEPUM05006-J21 MEPUM05006-J21 - 51 - MeP MeP-c4 1 2 3 4 5 6 cpuclk ikdaME ikdaWE ikdaSLEEP ikdaAddr ikdaBE ikdaData moidData Cycle1 ikdaME ikdaSLEEP ikdaWE H ikdaData MEPUM05006-J21 MEPUM05006-J21 - 52 - MeP MeP-c4 (2) 1 2 3 4 5 6 cpuclk iktgME iktgWE iktgSLEEP iktgAddr iktgBE iktgData moitData Cycle1 Cycle iktgME iktgSLEEP iktgWE L moitData MEPUM05006-J21 MEPUM05006-J21 - 53 - MeP MeP-c4 1 2 3 4 5 6 cpuclk iktgME iktgWE iktgSLEEP iktgAddr iktgBE iktgData moitData Cycle1 iktgME iktgSLEEP iktgWE H iktgData MEPUM05006-J21 MEPUM05006-J21 - 54 - MeP MeP-c4 3.2.4. (3) 1 2 3 4 5 6 cpuclk dkdaME dkdaWE dkdaSLEEP dkdaAddr dkdaBE dkdaData moddData Cycle1 Cycle dkdaME dkdaSLEEP dkdaWE L moddData MEPUM05006-J21 MEPUM05006-J21 - 55 - MeP MeP-c4 1 2 3 4 5 6 cpuclk dkdaME dkdaWE dkdaSLEEP dkdaAddr dkdaBE dkdaData moddData Cycle1 dkdaME dkdaSLEEP dkdaWE H dkdaData MEPUM05006-J21 MEPUM05006-J21 - 56 - MeP MeP-c4 (4) 1 2 3 4 5 6 cpuclk dktgME dktgWE dktgSLEEP dktgAddr dktgBE dktgData modtData Cycle1 Cycle dktgME dktgSLEEP dktgWE L modtData MEPUM05006-J21 MEPUM05006-J21 - 57 - MeP MeP-c4 1 2 3 4 5 6 cpuclk dktgME dktgWE dktgSLEEP dktgAddr dktgBE dktgData modtData Cycle1 dktgME dktgSLEEP dktgWE H dktgData MEPUM05006-J21 MEPUM05006-J21 - 58 - MeP MeP-c4 (5) 1 2 3 4 5 6 cpuclk dkdiME dkdiWE dkdiSLEEP dkdiAddr dkdiBE dkdiData modiData Cycle1 Cycle dkdiME dkdiSLEEP dkdiWE L modiData MEPUM05006-J21 MEPUM05006-J21 - 59 - MeP MeP-c4 1 2 3 4 5 6 cpuclk dkdiME dkdiWE dkdiSLEEP dkdiAddr dkdiBE dkdiData modiData Cycle1 dkdiME dkdiSLEEP dkdiWE H dkdiData MEPUM05006-J21 MEPUM05006-J21 - 60 -