Top Results
| Part | Manufacturer | Description | Datasheet | BUY |
|---|---|---|---|---|
| TLK100PHPR | Texas Instruments | Industrial Ethernet PHY 48-HTQFP -40 to 85 |  |
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| TNETE2101PZ | Texas Instruments | 3.3V Single 10/100 Mb Physical Layer Device 100-LQFP 0 to 0 | |
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| TSB11LV01PT | Texas Instruments | IEEE 1394-1995, 3.3V, 1-Port, 100Mbps Physical Layer Controller 48-LQFP | |
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| 5962-9677201QXA | Texas Instruments | Single-Port Backplane Physical Layer Transceiver 68-CFP -55 to 125 | |
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| XIO1100GGB | Texas Instruments | x1 PCI Express PHY 100-BGA MICROSTAR 0 to 70 | |
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| TSB41BA3DIPFP | Texas Instruments | S400 Capable 1394b Physical Layer (Phy) 80-HTQFP -40 to 85 | |
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Marvell PHY 88E1111 layout
| Catalog Datasheet | MFG & Type | Document Tags | |
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88E1111Abstract: Marvell PHY 88E1111 Datasheet Oscillator 2 88E1111 PHY 88E1112 PHY SGMII MAC Device SMA Marvell 88E1112/1118 Evaluation , interoperability tests between a LatticeSCTM device and the Marvell 88E1111/88E1112 devices. Specifically, this , 88E1111/ 88E1112 devices. · SGMII Physical Layer Interoperability testing of the LatticeSC and Marvell , Layer Interoperability Lattice Semiconductor Marvell Alaska Ultra 88E1111/88E1112 Overview , the PHY Register Control Panel. 5 LatticeSC/Marvell Serial-GMII (SGMII) Physical Layer |
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Marvell PHY 88E1111 Datasheet marvell 88E1111 register RGMII sgmii marvell 88E1118 Marvell PHY 88E1118 Marvell PHY 88E1111 layout TN1127 1000M 1000BASE-SX SMB-2000 GX-1420B 88E1111/88E1112 |
Marvell PHY 88E1111 layoutAbstract: 88E1111 PHY registers single-port 88E1111 product performs all of the physical layer (PHY) functions for half- and full-duplex , testing and diagnostics APPLICATIONS The Marvell Alaska single-port 88E1111 transceiver is the Þrst , PHY (88E1111) MAC Interface Options: ¥ GMII/MII ¥ RGMII ¥ SGMII ¥ TBI ¥ RTBI ¥ Serial , Single-Port PHY (88E1111) Serial Interface Fiber Optics Media Types: ¥ 1000BASE-LX ¥ 1000BASE , (88E1111) Fiber Applications Diagram The Marvell Alaska single-port GbE transceivers come with a |
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88E1111 PHY registers 88E1111 layout 88e1111 board layout 88e1111 phy mii EVALUATION BOARD 88E1111 88E1111 and SFP applications 10BASE-T 100BASE-TX 1000BASE-T 1000BASE-X LINK10 LINK100 |
88E1111Abstract: Marvell PHY 88E1111 Datasheet a LatticeSCTM device and the MARVELL 88E1111/88E1112 devices. Specifically, this technical note discusses the following topics: · Overview of LatticeSC devices and MARVELL AlaskaTM Ultra 88E1111/ 88E1112 devices. · Gigabit Ethernet Physical Layer Interoperability testing of the LatticeSC and MARVELL 88E1111 , Cyclic Redundancy Code (CRC) checking. Marvell Alaska Ultra 88E1111/88E1112 Overview 88E1111/88E1112 , LatticeSC device and the MARVELL 88E1111/ 88E1112 devices. The purpose of these tests is to confirm the |
Lattice Semiconductor Original |
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Marvell 88E1112 Marvell 88E1111 Marvell PHY 88E1118 Datasheet 88e111 Marvell 88E1111 specification 88E1112 reference design TN1120 1-800-LATTICE |
88E1111Abstract: 88E1118 RJ45 88E1111 PHY On-board Oscillator 88E1112 PHY SGMII MAC Device SMA Marvell 88E1112 , interoperability tests between a LatticeECP2MTM device and the Marvell 88E1111/88E1112 devices. Specifically, this , 88E1111/ 88E1112 devices. · SGMII Physical Layer Interoperability testing of the LatticeECP2M and Marvell , 88E1112 64 QFN Evaluation Board The Marvell 88E1112 64 QFN evaluation board includes: · An 88E1111 , Marvell 88E1111/ 88E1112 devices. The purpose of these tests is to confirm the correct processing of |
Lattice Semiconductor Original |
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sgmii specification ieee 88e1111 SGMII mode 88E1111 "mdio registers" 88E1111 register SFP EVAL BOARD 88e1112 sgmii SFP EVALUATION BOARD TN1133 |
Marvell 88e1111 register mapAbstract: MV-S100649-00 Transceiver â'¢ â'¢ The 88E1111 device incorporates the Marvell Virtual Cable Testerâ"¢ (VCTâ , . 113 MARVELL CONFIDENTIAL 2.24 88E1111 Device Boundary Scan Chain Order , 03 c. TI ar AL ve , U ll S ND em ER ic NDond A# uc 02 tor, 13 In 03 c. MARVELL CONFIDENTIAL 88E1111 Datasheet Doc. No. MV-S100649-00, Rev. F December 3, 2004 7vu31zzfnua-e4681dge * Marvell Semiconductor, Inc. * UNDER NDA# 021303 Integrated 10/100/1000 Ultra Gigabit Ethernet |
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Marvell 88e1111 register map Marvell PHY 88E1111 Marvell PHY 88E1111 application note Marvell 88E1111 application note marvel phy 88e1111 reference design 88E1111 PHY registers map |
88E1111Abstract: 88E1118 interoperability test between a LatticeECP2MTM device and the Marvell® Alaska® Ultra 88E1111/ 88E1112 devices. The , /Marvell Gigabit Ethernet Physical Layer Interoperability Lattice Semiconductor The 88E1111/88E1112 , LatticeECP2M/Marvell Gigabit Ethernet Physical Layer Interoperability Lattice Semiconductor Figure 6. Phy , Marvell 88E1112 Evaluation Board (with the 88E1111/88E1112 devices) · The LatticeECP2M SERDES Evaluation , : LFE2M35-FF672 RJ45 MDIO 1000BASE-X 1000BASE-T TX RX 2 2 RJ45 88E1111 PHY On-board Oscillator |
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Alaska Ultra 88E1111 Gigabit 88E1118 Marvell PHY 88E1112 Alaska Ultra 88E1111 Integrated Gigabit Ethernet Marvell PHY 88E1111 alaska 88E1118 RGMII TN1163 88E1111/ |
88E1111Abstract: Marvell PHY 88E1111 layout (Marvell 88E1111), which can be programmed via two-wire interface with the device address 0xAC. For details of PHY IC registers in 88E1111, see Marvell document "Alaska Ultra 88E1111 Integrated Gigabit , Gigabit PHY device is integrated internally Internal PHY IC is configurable by host system software via , configure the PHY device inner LCP-1250RJ3SR-S via SFP two-wire-interface. Dec. 18. 2006 Rev. 1.01 , PHY within the SFP. 2. This part uses the SFP's Rx-Los pin for link indication and 1000 Base-T |
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88E1111 schematic sgmii marvell 88E1111 88E1111 GBIC SGMII Marvell PHY 88E1111 schematic Marvell PHY 88E1111 footprint 88E1111 mac address 10/100/1000M RJ-45 1000B LCP-1250RJ3SR GBIC-1250RJ3SR 1250M |
88E111* HWCFG_MODEAbstract: sgmii marvell 88e1111 -1250RJ3SR is internally designed of physical layer IC (Marvell 88E1111), which can be programmed via two-wire interface with the device address 0xA6. For details of PHY IC registers in 88E1111, see Marvell document , . www.atmel.com 4. "Alaska Ultra 88E1111 Integrated 10/100/1000 Gigabit Ethernet Transceiver", Marvell Corporation , . It can operate in 10/100/1000 Base-T with SGMII interface by reconfiguration of the PHY within the , Configuration (PHY Two-Wire Address 0xA6) Register 27 Bits 3:0 Field HWCFG_ MODE Mode R/W Description Changes |
Delta Electronics Original |
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88E111* HWCFG_MODE Marvell+PHY+88E1111+schematic LCP-1250RJ3SR-L AT24C01A/02/04/08/16 |
Alaska Ultra 88E1111 Integrated Gigabit EthernetAbstract: 88E1111 0xA6) LCP-1250RJ3SR is internally designed of physical layer IC (Marvell 88E1111), which can be programmed via two-wire interface with the device address 0xA6. For details of PHY IC registers in 88E1111, see Marvell document "Alaska Ultra 88E1111 Integrated Gigabit Ethernet Transceiver , with SGMII interface by reconfiguration of the PHY within the SFP. 2. This part uses the SFP's Rx-Los , can operate in 10/100/1000 Base-T with SGMII interface by reconfiguration of the PHY within the SFP |
Delta Electronics Original |
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88e1111 Power Current Marvell PHY 88E1111 Datasheet footprint 88E1111 current 88E1111 registers 88E1111 symbol 88E1111 SFP |
Marvell 88E1111Abstract: internally designed of physical layer IC (Marvell 88E1111), which can be programmed via two-wire interface with the device address 0xA6. For details of PHY IC registers in 88E1111, see Marvell document , 4. â'Alaska Ultra 88E1111 Integrated 10/100/1000 Gigabit Ethernet Transceiverâ', Marvell , Rev. 1.00 www.deltaww.com LCP-1250RJ3SR SFP Transceiver Electrical Pad Layout Pin Function , tied to ground. TX disable is an input that is used to reset the chip of Gigabit Ethernet PHY inside |
Delta Electronics Original |
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MIL-STD-883E R50032471 E239394 |
| Abstract: (Marvell 88E1111), which can be programmed via two-wire interface with the device address 0xAC. For details of PHY IC registers in 88E1111, see Marvell document â'Alaska Ultra 88E1111 Integrated Gigabit , PHY device is integrated internally Operating with single +3.3 V power supply Compatible to both shielded and unshielded twisted pair Cat5 cable Internal PHY IC is configurable by host system software , enhance, the software can configure the PHY device inner LCP-1250RJ3SR-S via SFP two-wire-interface |
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IEEE802 |
Marvell 88E1111 layout guideAbstract: Marvell PHY 88E1111 errata BaseT RJ-45 interface using Marvell 88E1111 PHY - USB 2.0 port-High-speed host and device - USB , Marvell 88E1111 PHY. Phy address was assigned to 0x3. Used the same IRQ3 number as the L2 switch. · Added resistor option for RGMII signals route to either L2 switch or Marvell 88E1111 PHY. · Added SGMII support for eTSEC1 if using the added Marvell 88E1111 PHY. (SGMII for eTSEC2 was already , Update the power management driver · Remove bug fix code for Marvell 88E1111 PHY · Add OCF + IPSEC |
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Marvell 88E1111 layout guide Marvell PHY 88E1111 errata 88E1111 errata 88E1101 88E1111 uboot SKB 8250 AN3947 MPC8313ERDB MPC8313E MPC8313E-RDB |
88E1111 layoutAbstract: 88E1111 register -1250RJ3SR is internally designed of physical layer IC (Marvell 88E1111), which can be programmed via two-wire interface with the device address 0xA6. For details of PHY IC registers in 88E1111, see Marvell document , . www.atmel.com 4. "Alaska Ultra 88E1111 Integrated 10/100/1000 Gigabit Ethernet Transceiver", Marvell Corporation , . It can operate in 10/100/1000 Base-T with SGMII interface by reconfiguration of the PHY within the , Configuration (PHY Two-Wire Address 0xA6) Register 27 Bits 3:0 Field HWCFG_ MODE Mode R/W Description Changes |
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rj45 120 ohm connector |
88E111* HWCFG_MODEAbstract: Marvell PHY 88E1111 schematic of physical layer IC (Marvell 88E1111), which can be programmed via two-wire interface with the device address 0xAC. For details of PHY IC registers in 88E1111, see Marvell document "Alaska Ultra , -1250RJ3SR-S supports the SGMII interface without clock on MAC side. Gigabit PHY device is integrated internally Internal PHY IC is configurable by host system software via SFP 2-wire-interface. Description The LCP , configure the PHY device inner LCP-1250RJ3SR-S via SFP two-wire-interface. The SGMII interface without clock |
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88E1111 PHY register 24 Marvell PHY 88E1111 0xac marvell ethernet switch sgmii MARV 88e1111 registers 0xac sgmii mode sfp 1000M/ |
Marvell PHY 88E1111 layoutAbstract: Marvell PHY 88E1111 schematic (Two-Wire Address 0xAC) LCP-1250RJ3SR-L is internally designed of physical layer IC (Marvell 88E1111 , registers in 88E1111, see Marvell document "Alaska Ultra 88E1111 Integrated Gigabit Ethernet Transceiver , -1250RJ3SR-L supports RX_LOS enabled Internal PHY IC is configurable by host system software via SFP 2 , software to configure MAC on host system. At enhance, the software can configure the PHY device inner LCP , by reconfiguration of the PHY within the SFP. 2. This part uses the SFP's Rx-Los pin for link |
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sfp autonegotiation 88E1111 full |
| Abstract: (Marvell 88E1111), which can be programmed via two-wire interface with the device address 0xAC. For details of PHY IC registers in 88E1111, see Marvell document â'Alaska Ultra 88E1111 Integrated Gigabit , at 1.25 Gbit/s: up to 100m per IEEE802.3 Gigabit PHY device is integrated internally Operating , LCP-1250RJ3SR-L supports RX_LOS enabled Internal PHY IC is configurable by host system software via , configure the PHY device inner LCP-1250RJ3SR-L via SFP two-wire-interface. LCP-1250RJ3SR-L can also be |
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88E1111 schematicAbstract: Marvell PHY 88E1111 layout internally designed of physical layer IC (Marvell 88E1111), which can be programmed via two-wire interface with the device address 0xAC. For details of PHY IC registers in 88E1111, see Marvell document "Alaska , software can configure the PHY device inner LCP-1250RJ3SR-L via SFP two-wire-inter- face. LCP , Internal PHY IC is configurable by host system software via SFP 2-wire-interface Applications Gigabit , by reconfiguration of the PHY within the SFP. 3. This part supports the 10/100/1000 Base-T with SGMII |
Delta Electronics Original |
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sgmii 88E1111 88E1111 marvell |
88E6185Abstract: marvell 88E6185 . 5-21 Marvell 88E1111 Ethernet PHY Configuration , . 5-20 Marvell 88E1145 Quad PHY , port of the Ethernet switch is connected to a front plane Ethernet port through a Marvell 88E1111. Due , 88E6185 Marvell 88E1111 MDIO_PHY MDC_PHY SMI=0x10 RJ45 SMI=0x6 Front Panel DSP1 , Marvell 88E1145 Quad PHY device connecting to each of the four ports. Table 5-4 describes the signals |
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marvell 88E6185 Tsi578 marvell 88e1145 88e1145 config 88E1111 RGMII tsi578 hardware manual MSC8144AMC-S MSC8144AMCSUM EL516 MSC8144 TSI578 88EE6185 |
r338Abstract: 88E1111 marvell RGMII or SGMII: one 10/100/1000 BaseT RJ-45 interface using Marvell 88E1111 PHY â'" USB 2.0 port , Marvellâ"¢ 88E1111 PHY in REVC board PowerQUICCâ"¢ MPC8313E Reference Design Board (RDB), Rev. 6 2 , PCI Bus eTSEC1 RGMII/ RGMII/SGMII Marvell PHY System Clock and USB Clock 128 Mbyte , Vitesse L2 Switch Test Points Marvell PHY USB mini-AB SD card DAC for IEEE1588 Clock , MPC8313E L2 Switch Marvell PHY Reset config logic 3.3 V MAX811 PORESET to MPC8313E MR NOR |
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r338 MPC8313ERDBUG C8313ERDBUG |
Marvell PHY 88E1111 DatasheetAbstract: 88E1111 -45 interface using Marvell 88E1111 PHY - USB 2.0 port: high-speed host/device - USB interface: selectable , L2 switch, or selectable one 10/100/1000 BaseT RJ-45 interface using MarvellTM 88E1111 PHY in REVC , Slot 3.3 V 32-Bit PCI Slot 33/66 MHz PCI Bus eTSEC1 RGMII/ RGMII/SGMII Marvell PHY , NAND Flash Memory Thermal Sensor Vitesse L2 Switch Test Points Marvell PHY USB , MPC8313E L2 Switch Marvell PHY Reset config logic 3.3 V MAX811 PORESET to MPC8313E MR NOR |
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VSC7385 Marvell rgmii layout guide 88e1111 mii Marvell PHY 88E1111 printed board Marvell PHY 88E1111 MDIO read write 88E1111 register map PC8313ERDBUG |
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