MX10E8050I MX10E8050X MX10E8050IA MX10E8050IPC MX10E8050IQC MX10E8050IUC - Datasheet Archive

 

MX10E8050I MX10E8050X MX10E8050IA Major Difference Feature Product Default ISP IAP Package Clock mode MX10E8050IPC MX10E8050IQC

 

PRELIMINARY MX10E8050I MX10E8050I MX10E8050X MX10E8050X MX10E8050IA MX10E8050IA Major Difference Feature Product Default ISP IAP Package Clock mode MX10E8050IPC MX10E8050IPC MX10E8050IQC MX10E8050IQC 40 Pin PDIP x 12 YES YES 44 Pin PLCC MX10E8050IUC MX10E8050IUC 44 Pin LQFP MX10E8050XPC MX10E8050XPC 40 Pin PDIP MX10E8050XQC MX10E8050XQC x 6 NO NO MX10E8050XUC MX10E8050XUC MX10E8050IAQC MX10E8050IAQC P/N:PM0887 PM0887 44 Pin PLCC 44 Pin LQFP x 12 Yes Yes 44 Pin PLCC Specifications subject to change without notice, contact your sales representatives for the most update information. REV. 1.3, JUL. 21, 2003 1 PRELIMINARY MX10E8050I MX10E8050I / X MX10E8050IA MX10E8050IA FEATURES - 80C51 80C51 CPU core - 3.0 ~ 3.6V voltage range - On-chip Flash program memory with in-system programming (ISP) - Operating frequency up to 40MHz (12x),20MHz(6x) - 64K bytes Flash memory for code memory - 1280 bytes internal data RAM - Low power consumption - Code and data memory expandable to 64K Bytes - Four 8 bit and one 4 bit general purpose I/O ports - Three standard 16-bit Timers - In - Application Programming(IAP) capability - On-chip Watch Dog Timer - Four channel PWM outputs/4bit general purpose I/O ports (PLCC & LQFP only) - UART - 7 interrupt sources with four priority level - 5 volt tolerant input - 400kb/s I2C - 6x / 12x clock mode PIN Configurations 6 1 40 7 39 PLCC44 PLCC44 17 29 18 Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 P/N:PM0887 PM0887 Function P4.2/PWM2 P1.0/T2 P1.1/T2EX P1.2 P1.3 P1.4 P1.5 P1.6/SCL P1.7/SDA RST P3.0/RxD P4.3/PWM3 P3.1/TxD P3.2/INT0 P3.3/INT1 Pin 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 28 Function P3.4/T0 P3.5/T1 P3.6/WR P3.7/RD XTAL2 XTAL1 VSS P4.0/PWM0 P2.0/A8 P2.1/A9 P2.2/A10 2/A10 P2.3/A11 3/A11 P2.4/A12 4/A12 P2.5/A13 5/A13 P2.6/A14 6/A14 Pin 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Function P2.7/A15 7/A15 PSEN ALE P4.1/PWM1 EA P0.7/AD7 P0.6/AD6 P0.5/AD5 P0.4/AD4 P0.3/AD3 P0.2/AD2 P0.1/AD1 P0.0/AD0 VCC Specifications subject to change without notice, contact your sales representatives for the most update information. REV. 1.3, JUL. 21, 2003 2 PRELIMINARY MX10E8050I MX10E8050I / X MX10E8050IA MX10E8050IA 34 1 33 LQFP44 LQFP44 11 23 12 Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Function P1.5 P1.6/SCL P1.7/SDA RST P3.0/RxD P4.3/PWM3 P3.1/TxD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 P3.6/WR P3.7/RD XTAL2 XTAL1 22 Pin 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Function P0.6/AD6 P0.5/AD5 P0.4/AD4 P0.3/AD3 P0.2/AD2 P0.1/AD1 P0.0/AD0 VCC P4.2/PWM2 P1.0/T2 P1.1/T2EX P1.2 P1.3 P1.4 (T2) P1.0 (T2EX) P1.1 P1.2 P1.3 P1.4 P1.5 (SCL)P1.6 (SDA)P1.7 RESET (RXD) P3.0 (TXD)P3.1 (INT0) P3.2 (INT1) P3.3 (T0) P3.4 (T1) P3.5 (WR) P3.6 (RD) P3.7 XTAL2 XTAL1 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 PDIP 40 44 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VCC P0.0 (AD0) P0.1 (AD1) P0.2 (AD2) P0.3 (AD3) P0.4 (AD4) P0.5 (AD5) P0.6 (AD6) P0.7 (AD7) EA ALE PSEN P2.7 (A15) P2.6 (A14) P2.5 (A13) P2.4 (A12) P2.3 (A11) P2.2 (A10) P2.1 (A9) P2.0 (A8) Pin 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Function VSS P4.0/PWM0 P2.0/A8 P2.1/A9 P2.2/A10 2/A10 P2.3/A11 3/A11 P2.4/A12 4/A12 P2.5/A13 5/A13 P2.6/A14 6/A14 P2.7/A15 7/A15 PSEN ALE P4.1/PWM1 EA P0.7/AD7 PDIP PIN 39-32 21-28 1-8 PLCC PIN 43-36 24-31 2-9 10-17 NA 11,13-19 5,7-13 23,34,1,12 17,28,39,6 DESCRIPTION Port:8-bit open drain bidirectional I/O Port Port: 8-bit quasi-bidirectional I/O Port with internal pull-up Port: 8-bit quasi-bidirectional I/O Port with internal pull-up , except P1.6 and P1.7 Port: 8-bit quasi-bidirectional I/O Port with internal pull-up 4bit Quasi-bidirectional I/O port or PWM 9 40 20 19 18 29 30 31 10 44 22 21 20 32 33 35 reset input Positive power supply Ground XTAL connection input XTAL connection output Program store enable output Address latch enable output External access input Table. 1 Pin Description I/O I/O I/O I/O Package Type SYMBOL P0.0-P0.7 P2.0-P2.7 P1.0-P1.7 I/O P3.0-P3.7 I/O P4.0~P4.3/ PWM0~PWM3 I RESET I VCC I VSS I XTAL1 O XTAL2 O PSEN O ALE I EA P/N:PM0887 PM0887 LQFP PIN 37-30 18-25 40-44,1-3 4 38 16 15 14 26 27 29 Specifications subject to change without notice, contact your sales representatives for the most update information. 3 REV. 1.3, JUL. 21, 2003 PRELIMINARY MX10E8050I MX10E8050I / X MX10E8050IA MX10E8050IA Mnemonic Type Name and Function Vss Vcc Pin Number PDIP PLCC 20 22 40 44 LQFP 16 38 I I P0.0 ~ 0.7 39-32 43-36 37-30 I/O P1.0~1.7 1-8 2-9 40-44 1-3 I/O 1 2 2 3 40 41 I/O I P2.0~2.7 3 4 5 6 7 8 21-28 4 5 6 7 8 9 24-31 42 43 44 1 2 3 18-25 I I/O I/O I/O I/O I/O I/O Ground: 0 volt reference Power Supply: This is the power supply voltage for normal, idle and power-down operation Port 0: Port 0 is an open drain, bi-directional I/O port. Port 0 pins have 1s written to them float and can be used as high impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accessed to external program and data memory. In this application, it uses strong internal pull-ups when emitting 1s. Port1: Port 1 is an 8-bit bi-directional I/O port with internal pull-ups. Port 1 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 1 pins that are externally pulled low will source current because of the internal pull-ups. Note that P1.6 and P1.7 are open drain pins for I2C function. Alternate functions for port 1 include: T2(P1.0): Timer/Counter 2 external count input/clock out T2EX(P1.1): Timer/Counter 2 Reload / Capture / Direction control SDA (P1.7): Data line for I2C SCL (P1.6): Clock line for I2C P3.0~3.7 10-17 11, 13-19 5, 7-13 I/O P/N:PM0887 PM0887 Port 2 : Port 2 is an 8-bit bi-directional I/O port with internal pull-ups. Port2 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 2 pins that are externally pulled low will source current because of the internal pull-ups. Port 2 emits the high ordered address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR). In this application, it uses strong internal pull-ups when emitting 1s. During accesses to external data memory using 8-bit addresses (MOVX@RI), port 2 emits the contents of P2 special `function register. Port 3: Port 3 is an 8-bit bi-directional I/O port with internal pull-ups. Port 3 pins that have 1s written to them are pulled high with the internal pull-ups and can be used as inputs. As Specifications subject to change without notice, contact your sales representatives for the most update information. 4 REV. 1.3, JUL. 21, 2003 PRELIMINARY MX10E8050I MX10E8050I / X MX10E8050IA MX10E8050IA 10 11 12 13 14 15 16 17 11 13 14 15 16 17 18 19 5 7 8 9 10 11 12 14 I O I I I I O O I/O P4.0 P4.1 P4.2 P4.3 RST 9 23 34 1 12 10 17 28 39 6 4 I I I I I ALE 30 33 27 O PSEN 29 32 26 O EA 31 35 15 I XTAL 1 19 21 15 I XTAL 2 18 20 14 O P4.0~P4.3 P/N:PM0887 PM0887 inputs, Port 3 pins that are externally pulled low will source current because of the internal pull-ups. Port 3 also serves the special features of MX10E8050I MX10E8050I family, as listed below: RxD (P3.0) : Serial input port TxD (P3.1) : Serial output port INT0 (P3.2) : External interrupt 0 INT1 (P3.3) : External interrupt 1 T0 (P3.4) : Timer 0 external input T1 (P3.5) : Timer 1 external input WR (P3.6) : External data memory write strobe RD (P3.7) : External data memory read strobe Port 4: Port 4 is an 4-bit bi-directional I/O port with internal pull-ups. Port 4 pins that have 1s written to them are pulled high with the internal pull-ups and can be used as inputs. As inputs, Port 4 pins that are externally pulled low will source current because of the internal pull-ups. Port 4 also serves the special features of MX10E8050I MX10E8050I family, as listed below: PWM0 (P4.0) : PWM module output 0 PWM1 (P4.1) : PWM module output 1 PWM2 (P4.2) : PWM module output 2 PWM3 (P4.3) : PWM module output 3 Reset : A high on this pin for eight machine cycles while the oscillator is running, reset the devices. An internal diffused resistor to Vss permits a power-on reset using only an external capacitor to Vcc Address Latch Enable: Output pulse for latching the low byte of the address during an access to external memory. In normal operation, ALE is emitted at constant rate of 1/6 the oscillator frequency in 12x clock mode. 1/3 the oscillator frequency in 6x clock mode, and can be used for external timing or clocking. Note that one ALE pulse is skipped during each access to external data memory. Program Strobe Enable: The read strobe to external program memory. When executing code from external program memory, PSEN is activated twice each machine cycle., except the two PSEN activation are skipped during each access to external data memory. PSEN is not activated during fetch from internal program memory. External Access Enable/ Programming Supply Voltage: EA must be external held low to enable the device to fetch code from external program memory locations 0000H 0000H and FFFFH for 64 K devices. Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator circuits. Crystal 2: Output from the inverting oscillator amplifier. Specifications subject to change without notice, contact your sales representatives for the most update information. 5 REV. 1.3, JUL. 21, 2003 PRELIMINARY MX10E8050I MX10E8050I / X MX10E8050IA MX10E8050IA BLOCK DIAGRAM P4.0-P4.3 P0.0-P0.7 P2.0-P2.7 PORT 0 DRIVERS PORT 2 DRIVERS Vcc PORT 4 DRIVERS RAM ADDR. REGISTER Vss PORT 4 LATCH RAM PWM PORT 0 LATCH PORT 2 LATCH STACK ACC POINTER TMP2 ROM T3 WATCHDOG TIMER BUFFER ALU PC INCREMENTER T0/T1/T2 SFRs TIMERS TIMING EA AND CONTROL RST DPTR PORT 1 LATCH I2C PORT 1 DRIVERS OSC. XTAL1 PORT 3 LATCH Input Filter PORT 3 Output Stage DRIVERS XTAL2 P1.0-P1.7 P/N:PM0887 PM0887 PROGRAM COUNTER INSTRUCTION REGISTER PSW ALE REGISTER TMP1 B REGISTER PSEN PROGRAM ADDR. P3.0-P3.7 Specifications subject to change without notice, contact your sales representatives for the most update information. 6 REV. 1.3, JUL. 21, 2003 PRELIMINARY MX10E8050I MX10E8050I / X MX10E8050IA MX10E8050IA FUNCTIONAL DESCRIPTION General The MX10E8050I MX10E8050I Serial is a stand-alone high-performance and low power microcontroller designed for use in many applications which need code programmability. The Flash EPROM offers customers to program the device themselves. This feature increases the flexibility in many applications, not only in development stage, but also in mass production stage. In addition to the 80C51 80C51 standard functions, the MX10E8050I MX10E8050I Serial provides a number of dedicated hardware functions. MX10E8050I MX10E8050I Serial is a control-oriented CPU with on-chip program and data memory. It can execute program with internal memory up to 64k bytes. MX10E8050I MX10E8050I Serial has two software selectable modes of reduced activity for power reduction Idle, and Power-down. The idle mode freezes the CPU while allowing the RAM, Timers, serial ports, interrupt system and other peripherals to continue functioning. The Power-down mode saves the RAM contents but freezes the oscillator causing all other chip functions to be inoperative. Power-down mode can be terminated by an external reset ,and in addition , by either of the two external interrupts can be terminated as the power down mode does. MEMORY ORGANIZATION The Central Processing Unit (CPU) manipulates operands in three memory spaces; these are the 256 bytes internal data memory (RAM), 1k byte auxiliary data memory (AUX-RAM) and 64k byte internal MTP program memory ( FLASH ROM ). Program Memory The program memory address space of the MX10E8050I MX10E8050I Serial comprises an internal and an external memory space. The MX10E8050I MX10E8050I Serial has 64k byte of program memory on-chip. Program Protection If the user choose to set security lock in MTP memory, the program content is protected from reading out of chip. Internal Data Memory The internal data memory is divided into three physically separated parts: 256 byte of RAM, 1k bytes of AUX-RAM, and 128 bytes special function register area (SFR). These parts can be addressed as follows (see Fig.1 and Table. 2) - RAM 0 to 127 can be addressed directly and indirectly as in the 80C51 80C51. Address pointers are R0 and R1 of the selected register bank. - RAM 128 to 255 can only be addressed indirectly . Address pointers are R0 and R1 of the selected register bank. - AUX-RAM 0 to 1023 is indirectly addressable as the external data memory locations 0 to 1023 by the MOVX instructions. Address pointers are R0 and R1 of the selected register bank and DPTR. SFRs can only be addressed directly in the address range from 128 to 255. P/N:PM0887 PM0887 Specifications subject to change without notice, contact your sales representatives for the most update information. 7 REV. 1.3, JUL. 21, 2003 PRELIMINARY MX10E8050I MX10E8050I / X MX10E8050IA MX10E8050IA Table. 2 Internal data memory access LOCATION RAM 0 to 127 RAM 128 to 255 AUX-RAM 0 to 1023 Special Function Register (SFR) 128 to 255 ADDRESSED DIRECT and INDIRECT INDIRECT only INDIRECT only with MOVX DIRECT only Fig. 1 shows the internal memory address space. Table 3 shows the Special Function Register (SFR) memory map. Location 0 to 31 at the lower RAM area can be devided into four 8-bit register banks. Only one of these banks may be enabled at a time. The next 16 bytes, locations 32 through 47, contain 128 directly addressable bit locations. The stack can be located anywhere in the internal 256 byte RAM. The stack depth is only limited by the available internal RAM space of 256 bytes. All registers except the Program Counter and the four 8-byte register banks reside in the SFR address space. Five methods to access memory space are as floww : - Register - Direct - Register-Indirect - Immediate - Base-Register plus Index-Register-Indirect. The first three methods can be used for addressing destination operands. Most instructions have a 'destination / source' field that specifies the data type, addressing methods and operands involved. For operations other than MOVs, the destination operand is also a source operand. Access to memory addresses is as follows: - Register in one of the four 8-byte register banks through Direct or Register-Indirect addressing. - 256 bytes of internal RAM through Direct or Register-Indirect addressing. Bytes 0-127 of internal RAM may be only be addressed indirectly as data RAM. - SFR through direct addressing at address location 128-255. OVERLAPPED SPACE with different access schemes 255 64k 1023 Indirect Only FLASH memory SFRs direct only AUXILIARY RAM through MOVX access 127 Direct and Indirect 0 0 MAIN RAM INTERNAL PROGRAM MEMORY SFRs AUX-RAM INTERNAL DATA MEMORY Fig.1 Internal program and data memory address space P/N:PM0887 PM0887 Specifications subject to change without notice, contact your sales representatives for the most update information. 8 REV. 1.3, JUL. 21, 2003 PRELIMINARY MX10E8050I MX10E8050I / X MX10E8050IA MX10E8050IA Table. 3 SFR Register Map HIGH NIBBLE OF SFR ADDRESS LOW 0 1 2 3 8 P0% 11111111 SP 00000111 DPL 00000000 9 P1% 11111111 A P2% 11111111 B P3% 11111111 C P4% 11111111 D PSW% 00000000 E ACC% 00000000 AUXR1 00000000 DPH 00000000 4 FMCON 00000001 FMDATA 00000000 5 6 7 8 9 A B C D E PCON 00000000 TCON% 00000000 TMOD 00000000 TL0 00000000 TL1 00000000 TH0 00000000 TH1 00000000 AUXR 00000000 F B% 00000000 PWMC 10000000 SCON% 00000000 SBUF XXXXXXXX IE% 00000000 SADDR 00000000 IPH 00000000 IP% 00000000 SADEN 00000000 F T2CON% 00000000 T2MOD 11111110 RCAP2L 00000000 RCAP2H 00000000 TL2 00000000 TH2 00000000 S1CON 00000000 S1STA 11111000 S1DAT 00000000 S1ADR 00000000 PWMP3 00000000 PWM2 00000000 PWM3 00000000 PWMP2 00000000 PDCON 00000000 EBTCON PWMP1 XXXXXX1X 00000000 PWM0 00000000 PWM1 00000000 PWMP0 00000000 T3 11111111 NOTES : % = Bit addressable register x = Undefined P/N:PM0887 PM0887 Specifications subject to change without notice, contact your sales representatives for the most update information. 9 REV. 1.3, JUL. 21, 2003 PRELIMINARY MX10E8050I MX10E8050I / X MX10E8050IA MX10E8050IA Special Function Registers Symbol Description Direct Address ACC Accumulator E0H AUXR Auxiliary 8EH AUXR1 Auxiliary1 A2H B B register F0H DPTR Data pointer(2-byte) Data pointer high DPH Data pointer low 83H DPL 82H EBTCON Enable T3 EBH FMCON Flash control E4H FMDATA Flash data E5H IE Interrupt Enable A8H IP Interrupt priority B8H IPH Interrupt priority high B7H P0 Port 0 80H P1 Port 1 90H P2 Port 2 A0H P3 Port 3 B0H P4 Port4 C0H PCON Power Control 87H PDCON ROM enable code F8H Bit Address, Symbol, or Alternative Port Function MSB LSB E7 E6 E5 E4 E3 E2 E1 E0 EXTRAM AO ENBOOT 0 DPS F7 F6 F5 F4 F3 F2 F1 F0 PPARAM PALE PCEB POEB Bit7 AF EA BF B7 - Bit6 AE ET2 BE PT2 B6 Bit5 AD ES1 BD PS1 B5 Bit4 AC ES BC PS B4 87 AD7 97 P17 A7 AD15 B7 RD 86 AD6 96 P16 A6 AD14 B6 WR - - PT2H PS1H PSH 85 AD5 95 P15 A5 AD13 B5 T1 Reset Function 00H 00000000B 00000000B 00000000B 00000000B 00H 00H 00H EB xxxxxx1xB PWEB PREADYB 00000001B 00000001B Bit3 Bit2 Bit1 Bit0 00000000B 00000000B AB AA A9 A8 ET1 EX1 ET0 EX0 00000000B 00000000B BB BA B9 B8 PT1 PX1 PT0 PX0 x0000000B B3 B2 B1 B0 PT1H PX1H PT0H PX0H x0000000B 84 AD4 94 P14 A4 AD12 B4 T0 83 AD3 93 P13 A3 AD11 B3 INT1 C3 82 AD2 92 P12 A2 AD10 B2 INT0 C2 81 AD1 91 P11 A1 AD9 B1 TxD C1 80 AD0 90 P10 A0 AD8 B0 RxD C0 WLE Bit4 D4 RS1 PWM3 PWM2 PWM1 PWM0 FFH FFH FFH FFH PWMP3 Prescaler vector 3 F2H P/N:PM0887 PM0887 PWMP PWMP PWMP PWMP PWMP PWMP PWMP 0.6 PWMP PWMP PWMP PWMP PWMP PWMP PWMP PWMP 1.6 PWMP PWMP PWMP PWMP PWMP PWMP PWMP PWMP 2.7 PWMP2 Prescaler vector 2 F6H DSCB PWMP 1.7 PWMP1 Prescaler vector 1 FBH PWMD 0.7 PSW Program Status Word D0H PWMC PWM control F1H PWMP0 Prescaler vector 0 FEH Bit7 D7 CY SMOD0 Bit6 Bit5 D6 D5 AC F0 2.6 PWMP PWMP PWMP PWMP PWMP PWMP PWMPPWMP 00000000B 00000000B SMOD1 GF1 Bit3 D3 RS0 0.5 1.5 2.5 0.4 1.4 2.4 0.3 1.3 2.3 PD Bit1 D1 - DSCA PWM3E PWM2E GF2 Bit2 D2 OV PWM1E PWM0E 0.2 1.2 2.2 0.1 1.1 2.1 IDL Bit0 D0 P 000000x0B 1000x000B 00000000B 00000000B 0.0 00000000B 00000000B 1.0 00000000B 00000000B 2.0 Specifications subject to change without notice, contact your sales representatives for the most update information. 10 FH 00xx0000B 00000000B 00000000B REV. 1.3, JUL. 21, 2003 PRELIMINARY MX10E8050I MX10E8050I / X MX10E8050IA MX10E8050IA 3.7 PWM0 PWM0 ratio FCH 3.6 3.5 3.4 3.3 3.2 3.1 3.0 PWM2 PWM2 ratio FDH F4H PWM PWM PWM PWM PWM PWM 0.6 0.5 0.4 0.3 0.2 0.1 PWM PWM PWM PWM PWM PWM PWM PWM 1.6 1.5 1.4 1.3 1.2 1.1 1.0 F5H PWM PWM PWM PWM PWM PWM PWM 2.6 2.5 2.4 2.3 2.2 2.1 PWM PWM PWM PWM PWM PWM PWM PWM 3.6 3.5 3.4 3.3 3.2 3.1 9F 98H 81H S1CON S1STA S1DAT S1ADR TCON I2C Control I2C Status I2C data I2C address Timer Control D8H D9H DAH DBH 88H T2CON T2MOD TH0 TH1 TH2 TL0 TL1 TL2 TMOD T3 Timer 2 Control P/N:PM0887 PM0887 C8H Timer 2 Mode Control C9H Timer High 0 8CH Timer High 1 8DH Timer High 2 CDH Timer Low 0 8AH Timer Low 1 8BH Timer Low 2 CCH Timer Mode 89H Timer 3 FFH 00000000B 00000000B 00H 00H 00H 00H xxxxxxxxB CAH SADDR Slave Address A9H SADEN Slave address Mask B9H SBUF Serial Data Buffer 99H RACAP2L Timer 2 Capture Low Serial Control Stack Pointer 00000000B 00000000B 3.0 RACAP2H Timer 2 Capture High CBH SCON SP 00000000B 00000000B 2.0 3.7 PWM3 ratio PWM 2.7 PWM3 00000000B 00000000B 0.0 1.7 PWM1 ratio PWM 0.7 PWM1 PWM 9E SM0/FE SM1 DF CR2 9D SM2 9C REN 9B TB8 9A RB8 99 TI 98 RI DE DD ENS1 STA DC STO DB SI DA AA D9 CR1 D8 CR0 00H 07H S1STA.7 S1STA.6 S1STA.5 S1STA.4 S1STA.3 S1DAT.7 S1DAT.6 S1DAT.5 S1DAT.4 S1DAT.3 S1DAT.2 S1DAT.1 S1DAT.0 S1ADR.7 S1ADR.6 S1ADR.5 S1ADR.4 S1ADR.3 S1ADR.2 S1ADR.1 GC TF1 CF TF2 - TR1 CE EXF2 - GATE C/T TF0 CD RCLK - TR0 IE1 CC CB TCLK EXEN2 - M1 M0 IT1 CA TR2 - GATE C/T IE0 C9 C/T2 T2OE M1 IT0 C8 CP/RL 00H DCEN xxxxxx00B 00H 00H 00H 00H 00H 00H M0 00H FFH Specifications subject to change without notice, contact your sales representatives for the most update information. 11 00H 00H 00H 00H 00H REV. 1.3, JUL. 21, 2003 PRELIMINARY MX10E8050I MX10E8050I / X MX10E8050IA MX10E8050IA AUXR (8EH) EXTRAM A0 - EXTRAM : External RAM Select Switch. Set 1 to select (MOVX) the external RAM when the address is larger than 256. Default is 0 to switch (MOVX) to external RAM only when the address is larger than 1k. - AO : Turn off ALE output in internal execution mode. Watchdog Timer/WDT/T3 (FFH) - WDT consists of an 11-bit prescaler and an 8-bit timer formed by SFR T3. EBTCON (EBH) /EW - /EW: After reset, /EW bit is set, and WDT is disable. POWER CONTROL Register/PCON (87H) SMOD1 SMOD0 X WLE GF1 GF0 PD IDL - SMOD1: Double baud rate bit for UART. - SMOD0: Frame error detection bit. - WLE: Watchdog load enable. This flag must be set prior to loading WDT and is cleared when WDT is loaded. - GF1/GF0: general-purpose flag bit. - PD: Power-down bit. Setting it activates power-down mode. - IDL: Idle mode bit. Setting it activates idle mode. - The CPU & Peripheral status during 2 power saving mode: CPU Int,Timer. Oscillator ckt P/N:PM0887 PM0887 Idle mode OFF ON ON Power-down mode OFF OFF OFF Specifications subject to change without notice, contact your sales representatives for the most update information. 12 REV. 1.3, JUL. 21, 2003 PRELIMINARY MX10E8050I MX10E8050I / X MX10E8050IA MX10E8050IA I/O facilities MX10E8050I MX10E8050I has one 8 bits port, port 0, which is open drain, three 8 bits ports, port1/2/3 and a four-bits port port 4 . They are quasi bi-directional ports except P1.6 and P1.7. These five ports are fully compatible to standard 80C51 80C51's port 0/1/2/3/4. - Port3: pins can be configured individually to provide: external interrupt inputs (external interrupt 0/1); external inputs for Timer/ counter 0 and Timer /counter1, and UART receive / transmit. - Port 1.6, Port 1.7 : pins are used to be I2C clock and data I/O, which are open drain Port pins which are not used for alternate functions may be used as normal bidirectional I/O pins. The generation or use of a Port 1 or Port 3 pin as an alternate function is carried out automatically by writing the associated SFR bit with proper value. +3V 2 oscillator penods strong pull-up P2 P1 P3 I/O PORT 1,2,3,4 exclude P1.6,P1.7 O from port latch n input data read port pin INPUT BUFFER I/O buffers in the MX10E8050I MX10E8050I (Ports 1,2,3,4) P/N:PM0887 PM0887 Specifications subject to change without notice, contact your sales representatives for the most update information. 13 REV. 1.3, JUL. 21, 2003 PRELIMINARY MX10E8050I MX10E8050I / X MX10E8050IA MX10E8050IA Timer/Counter MX10E8050I MX10E8050I Serial Timer/Counter 0 and 1 are fully compatible to standard 80C51 80C51's. The MX10E8050I MX10E8050I Serial contains two 16-bit Timer/counters, Timer 0 and Timer 1. Timer 0 and Timer 1 may be programmed to carry out the following functions: - measure time intervals and pulse durations - count events - generate interrupt requests. Timer 0 and Timer 1 Timers 0 and 1 each have a control bit in TMOD SFR that selects the Timer or counter function of the corresponding Timer. In the Timer function, the register is incremented every machine cycle. Thus, one can think of it as counting machine cycles. Since a machine cycle consists of 12 oscillator periods, the count rate is 1/12 of the oscillator frequency. In the counter function, the register is incremented in response to a HIGH-to-LOW transition at the corresponding samples, when the transition shows a HIGH in one cycle and a LOW in the next cycle, the counter is incremented. Thus, it takes two machine cycles (24 oscillator periods) to recognize a HIGH-to-LOW transition. There are no restrictions on the duty cycle of the external input signal, but to ensure that a given level is sampled at least once before it changes, it should be held for at least one full machine cycle. Timer 0 and Timer 1 can be programmed independently to operate in one of four modes (refer to table 5) : - Mode 0 : 8-bit Timer/counter with devided-by-32 prescaler - Mode 1 : 16-bit Timer/counter - Mode 2 : 8-bit Timer/counter with automatic reload - Mode 3 : Timer 0 :one 8-bit Timer/counter and one 8-bits Timer. Timer 1 :stopped. When Timer 0 is in Mode 3, Timer 1 can be programmed to operate in Modes 0, 1 or 2 but cannot set an interrupt request flag and generate an interrupt. However, the overflow from Timer 1 can be used to pulse the Serial Port transmission-rgate generator. With a 16 MHz crystal, the counting frequency of these Timer/counters is as follows: - in the Timer function, the Timer is incremented at a frequency of 1.33 MHz (oscillator frequency divided by 12). - in the counter function, the frequency handling range for external inputs is 0 Hz to 0.66 MHz (oscillator frequency divided by 24). Both internal and external inputs can be gated to the Timer by a second external source for directly measuring pulse duration. The Timers are started and stopped under software control. Each one sets its interrupt request flag when it overflows from all logic 1's to all logic 0's (respectively, the automatic reload value), with the exception of Mode 3 as previously described. TMOD : TIMER/COUNTER MODE CONTROL REGISTER This register is located at address 89H. Table. 4 TMOD SFR (89H) 7 6 GATE C/ T (MSB) TIMER 1 5 M1 4 M0 3 GATE 2 C/ T 1 M1 0 M0 (LSB) TIMER 0 keep the above table with the following table P/N:PM0887 PM0887 Specifications subject to change without notice, contact your sales representatives for the most update information. 14 REV. 1.3, JUL. 21, 2003 PRELIMINARY MX10E8050I MX10E8050I / X MX10E8050IA MX10E8050IA Table. 5 Description of TMOD bits MNEMONIC TIMER 1 GATE POSITION FUNCTION TMOD.7 C/T TMOD.6 M1 M0 TIMER 0 GATE TMOD.5 TMOD.4 Timer 1 gating control : when set, Timer/counter '1' is enabled only while 'Int1' pin is high and 'tr1' control bit is set. when cleared, Timer/counter '1' is enabled whenever 'tr1' control bit is set. Timer or counter selector: cleared for Timer operation (input from internal system clock). set for counter operation (input from 'T1' input pin). Operation mode: see table 6. Operation mode: see table 6. C/T TMOD.2 M1 M0 TMOD.1 TMOD.0 TMOD.3 Timer 0 gating control: when set, Timer/Counter '0' is enabled only while 'Int0' pin is high and 'tr0' control bit is set. when cleared, Timer/counter '0' is enabled whenever 'tr0' control bit is set. Timer or counter selector: cleared for Timer operation (input from internal system clock). set for counter operation (input from 'T0' input pin). Operation mode: see table 6. Operation mode: see table 6. Table. 6 TMOD M1 and M0 operating modes M1 M0 FUNCTION 0 0 8-bit Timer/counter : 'THx' with 5-bit prescaler. 0 1 16-bit Timer/counter : 'THx' and 'TLx' are cascaded, there is no prescaler. 1 0 8-bit autoload Timer/counter : 'THx' holds a value which is to be reloaded into 'TLx' each time it overflows. 1 1 Timer 0: TL0 is an 8-bit Timer/counter controlled by the standard Timer 0 control bits. TH0 is an 8bit Timer controlled by Timer 1 control bits. 1 1 Timer 1 : Timer/counter 1 stopped. TCON : TIMER/COUNTER CONTROL REGISTER This register is located at address 88H. Notes : Symbol Description Direct Bit Address, Symbol, or Alternative Port Function Address MSB LSB TMOD Timer Mode 89H GATE C/T M1 M0 GATE C/T M1 M0 Table. 7 TCON SFR (88H) 7 6 TF1 TR1 (MSB) 5 TF0 4 TR0 3 IE1 2 IT1 1 IE0 Reset Function 00H 0 IT0 (LSB) keep the above table with the following table P/N:PM0887 PM0887 Specifications subject to change without notice, contact your sales representatives for the most update information. 15 REV. 1.3, JUL. 21, 2003 PRELIMINARY MX10E8050I MX10E8050I / X MX10E8050IA MX10E8050IA Table. 8 Description of TCON bits MNEMONIC POSITION FUNCTION TF1 TCON.7 Timer 1 overflow flag : set by hardware on Timer/Counter overflow. Cleared when interrupt is processed. TR1 TCON.6 Timer 1 control bit : set/cleared by software to turn Timer/counter ON/OFF. TF0 TCON.5 Timer 0 overflow flag: set by hardware on Timer/Counter overflow. Cleared when interrupt is processed. TR0 TCON.4 Timer 0 control bit : set/cleared by software to turn Timer/counter ON/OFF. IE1 TCON.3 Interrupt 1 edge flag: set by hardware when external interrupt is detected. Cleared when interrupt is processed. IT1 TCON.2 Interrupt 1 type control bit : set/cleared by software to specify falling edge/LOW level triggered external interrupt. IE0 TOCN.1 Interrupt 0 edge flag: set by hardware when external interrupt is detected. Cleared when interrupt is processed. IT0 TOCN.0 Interrupt 0 type control bit: set/cleared by software tospecify falling edge/LOW level triggered external interrupt. P/N:PM0887 PM0887 Specifications subject to change without notice, contact your sales representatives for the most update information. 16 REV. 1.3, JUL. 21, 2003 PRELIMINARY MX10E8050I MX10E8050I / X MX10E8050IA MX10E8050IA TIMER 2 OPERATION Timer 2 Timer 2 is a 16-bit Timer/Counter which can operate as either an event timer or an event counter, as selected by C/ T2* in the special function register T2CON (see Figure 2). Timer 2 has three operating modes: Capture, Auto-reload (up or down counting), and Baud Rate Generator, which are selected by bits in the T2CON as shown in Table 9. Capture Mode In the capture mode there are two options which are selected by bit EXEN2 in T2CON. If EXEN2=0, then timer 2 is a 16-bit timer or counter (as selected by C/T2* in T2CON) which, upon overflowing sets bit TF2, the timer 2 overflow bit. This bit can be used to generate an interrupt (by enabling the Timer 2 interrupt bit in the IE register). If EXEN2= 1, Timer 2 operates as described above, but with the added feature that a 1- to -0 transition at external input T2EX causes the current value in the Timer 2 registers, TL2 and TH2, to be captured into registers RCAP2L and RCAP2H, respectively. In addition, the transition at T2EX causes bit EXF2 in T2CON to be set, and EXF2 like TF2 can generate an interrupt (which vectors to the same location as Timer 2 overflow interrupt. The Timer 2 interrupt service routine can interrogate TF2 and EXF2 to determine which event caused the interrupt). The capture mode is illustrated in Figure B (There is no reload value for TL2 and TH2 in this mode. Even when a capture event occurs from T2EX, the counter keeps on counting T2EX pin transitions or osc/6 pulses (osc/12 in 12 clock mode).). Auto-Reload Mode (Up or Down Counter) In the 16-bit auto-reload mode, Timer 2 can be configured (as either a timer or counter [C/T2* in T2CON]) then programmed to count up or down. The counting direction is determined by bit DCEN (Down Counter Enable) which is located in the T2MOD register (see Figure 4). When reset is applied the DCEN=0 which means Timer 2 will default to counting up. If DCEN bit is set, Timer 2 can count up or down depending on the value of the T2EX pin. Figure 5 shows Timer 2 which will count up automatically since DCEN=0. In this mode there are two options selected by bit EXEN2 in T2CON register. If EXEN2=0, then Timer 2 counts up to 0FFFFH and sets the TF2 (Overflow Flag) bit upon overflow. This causes the Timer 2 registers to be reloaded with the 16-bit value in RCAP2L and RCAP2H. The values in RCAP2L and RCAP2H are preset by software means. If EXEN2=1, then a 16-bit reload can be triggered either by an overflow or by a 1-to-0 transition at input T2EX. This transition also sets the EXF2 bit. The Timer 2 interrupt, if enabled, can be generated when either TF2 or EXF2 are 1. In Figure 6 DCEN=1 which enables Timer 2 to count up or down. This mode allows pin T2EX to control the direction of count. When a logic 1 is applied at pin T2EX Timer 2 will count up. Timer 2 will overflow at 0FFFFH and set the TF2 flag, which can then generate an interrupt, if the interrupt is enabled. This timer overflow also causes the 16-bit value in RCAP2L and RCAP2H to be reloaded into the timer registers TL2 and TH2. When a logic 0 is applied at pin T2EX this causes Timer 2 to count down. The timer will underflow when TL2 and TH2 become equal to the value stored in RCAP2L and RCAP2H. Timer 2 underflow sets the TF2 flag and causes 0FFFFH to be reloaded into the timer registers TL2 and TH2. The external flag EXF2 toggles when Timer 2 underflows or overflows. This EXF2 bit can be used as a 17th bit of resolution if needed. The EXF2 flag does not generate an interrupt in this mode of operation. P/N:PM0887 PM0887 Specifications subject to change without notice, contact your sales representatives for the most update information. 17 REV. 1.3, JUL. 21, 2003 PRELIMINARY MX10E8050I MX10E8050I / X MX10E8050IA MX10E8050IA (MSB) (LSB) TF2 Symbol Position TF2 T2CON.7 EXF2 T2CON.6 RCLK T2CON.5 TCLK T2CON.4 EXEN2 T2CON.3 TR2 C/T2 T2CON.2 T2CON.1 CP/RL2 T2CON.0 EXF2 RCLK TCLK EXEN2 TR2 C/T2 CP/RL2 Name and Significance Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software. TF2 will not be set when either RCLK or TCLK = 1. Timer 2 external flag set when either a capture or reload is caused by a negative transition on T2EX and EXEN2 = 1. When Timer 2 interrupt is enabled, EXF2 = 1 will cause the CPU to vector to the Timer 2 interrupt routine. EXF2 must be cleared by software. EXF2 does not cause an interrupt in up/down counter mode (DCEN = 1). Receive clock flag. When set, causes the serial port to use Timer 2 overflow pulses for its receive clock in modes 1 and 3. RCLK = 0 causes Timer 1 overflow to be used for the receive clock. Transmit clock flag. When set, causes the serial port to use Timer 2 overflow pulses for its transmit clock in modes 1 and 3. TCLK = 0 causes Timer 1 overflows to be used for the transmit clock. Timer 2 external enable flag. When set, allows a capture or reload to occur as a result of a negative transition on T2EX if Timer 2 is not being used to clock the serial port. EXEN2 = 0 causes Timer 2 to ignore events at T2EX. Start/stop control for Timer 2. A logic 1 starts the timer. Timer or counter select. (Timer 2) 0 = Internal timer (OSC/6 in 6 clock mode or OSC/12 OSC/12 in 12 clock mode) 1 = External event counter (falling edge triggered). Capture/Reload flag. When set, captures will occur on negative transitions at T2EX if EXEN2 = 1. When cleared, auto-reloads will occur either with Timer 2 overflows or negative transitions at T2EX when EXEN2 = 1. When either RCLK = 1 or TCLK = 1, this bit is ignored and the timer is forced to auto-reload on Timer 2 overflow. Figure 2. Timer/Counter 2 (T2CON) Control Register Table 9 : Timer 2 Operation Modes RCLK + TCLK 0 CP / RL2 0 TR2 1 MODE 16-bit Auto-reload 0 1 X 1 X X 1 1 0 16-bit Capture Baud rate generator (off) P/N:PM0887 PM0887 Specifications subject to change without notice, contact your sales representatives for the most update information. 18 REV. 1.3, JUL. 21, 2003 PRELIMINARY MX10E8050I MX10E8050I / X MX10E8050IA MX10E8050IA OSC ÷ n* C/T2 = 0 TL2 (8-bits) TH2 (8-bits) TF2 C/T2 = 1 T2 Pin Control TR2 Capture Transition Detector Timer 2 Interrupt RCAP2L RCAP2H T2EX Pin EXF2 Control EXEN2 * n = 12 in 12 clock mode. n = 6 in 6 clock mode. Figure 3 : Timer 2 in Capture Mode T2MOD Address = 0C9H Reset Value = XXXX XX00B XX00B Not Bit Addressable T2OE Bit 7 6 5 4 3 2 DCEN 1 0 Symbol T2OE DCEN * Function Not implemented, reserved for future use.* Timer 2 Output Enable bit. Down Count Enable bit. When set, this allows Timer 2 to be configured as an up/down counter. User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate. Figure 4 : Timer 2 Mode (T2MOD) Control Register P/N:PM0887 PM0887 Specifications subject to change without notice, contact your sales representatives for the most update information. 19 REV. 1.3, JUL. 21, 2003 PRELIMINARY MX10E8050I MX10E8050I / X MX10E8050IA MX10E8050IA ÷ n* OSC C/T2 = 0 TL2 (8-BITS) TH2 (8-BITS) C/T2 = 1 T2 PIN CONTROL TR2 RELOAD TRANSITION DETECTOR RCAP2L RCAP2H TF2 TIMER 2 INTERRUPT T2EX PIN EXF2 CONTROL EXEN2 * n = 12 in 12 clock mode. n = 6 in 6 clock mode. Figure 5 : Timer 2 in Auto-Reload Mode (DCEN = 0) (DOWN COUNTING RELOAD VALUE) FFH FFH TOGGLE EXF2 OSC ÷ n* C/T2 = 0 OVERFLOW TL2 T2 PIN TH2 TF2 INTERRUPT C/T2 = 1 CONTROL TR2 COUNT DIRECTION 1 = UP 0 = DOWN RCAP2L * n = 12 in 12 clock mode. n = 6 in 6 clock mode. RCAP2H (UP COUNTING RELOAD VALUE) T2EX PIN Figure 6 : Timer 2 Auto-Reload Mode (DCEN = 1) P/N:PM0887 PM0887 Specifications subject to change without notice, contact your sales representatives for the most update information. 20 REV. 1.3, JUL. 21, 2003 PRELIMINARY MX10E8050I MX10E8050I / X MX10E8050IA MX10E8050IA Timer 1 Overflow ÷2 "0" OSC "1" C/T2 = 0 SMOD TL2 (8-bits) "1" TH2 (8-bits) "0" RCLK C/T2 = 1 T2 Pin Control ÷ 16 "1" TR2 Transition Detector RCAP2L T2EX Pin EXF2 RX Clock "0" Reload RCAP2H TCLK ÷ 16 TX Clock Timer 2 Interrupt Control EXEN2 Note availability of additional external interrupt. Figure 7. Timer 2 in Baud Rate Generator Mode Table 10 : Timer 2 Generated Commonly Used Baud Rates Baud Rate Timer 2 12 clock mode Osc Freq 375 k 9.6 k 2.8 k 2.4 k 1.2 k 300 110 300 110 12 MHz 12 MHz 12 MHz 12 MHz 12 MHz 12 MHz 12 MHz 6 MHz 6 MHz RCAP2H RCAP2L FF FF FF FF FE FB F2 FD F9 FF D9 B2 64 C8 1E AF 8F 57 Baud Rate Generator Mode Bits TCLK and / or RCLK in T2CON (Table 10) allow the serial port transmit and receive baud rates to be derived from either Timer 1 or Timer 2. When TCLK = 0, Timer 1 is used as the serial port transmit baud rate generator. When TCLK = 1, Timer 2 is used as the serial port transmit baud rate generator. RCLK has the same effect for the serial port receive baud rate. With there two bits, the serial port can have different receive and transmit baud rates - one generated by Timer1, the other by Timer2. Figure 7 shows the Timer2 in baud rate generation mode. The baud rate generation mode is like the auto-reload mode, in that a rollover in TH2 causes the Timer 2 registers to be reloaded with the 16-bit value in registers RCAP2H and RCAP2L, which are preset by software. The baud rates in modes 1 and 3 are determined by Timer 2's overflow rate given below : Modes 1 and 3 Baud Rates = Timer 2 Overflow Rate 16 P/N:PM0887 PM0887 Specifications subject to change without notice, contact your sales representatives for the most update information. 21 REV. 1.3, JUL. 21, 2003 PRELIMINARY MX10E8050I MX10E8050I / X MX10E8050IA MX10E8050IA The Timer can be configured for either "timer" or "counter" operation. In many applications, it is configured for "timer" operation ( C/T 2* = 0). Timer operation is different for Timer 2 when it is being used as a baud rate generator. Usually, as a timer it would increment every machine cycle ( i.e., 1/6 the oscillator frequency in 6 clock mode, 1/ 12 the oscillator frequency in 12 clock mode). As a baud rate generator, it increments at the oscillator frequency in 6 clock mode (OSC/2 in 12 clock mode). Thus the baud rate formula is as follows : Oscillator Frequency Modes 1 and 3 Baud Rates = [ n * x [65536 - (RCAP2H, RCAP2L)]] *n = 32 in 12 clock mode or 16 in 6 clock mode Where : (RCAP2h, RCAP2L) = The content of RCAP2H and RCAP2L taken as a 16-bit unsigned integer. The Timer 2 as a baud rate generator mode shown in Figure7, is valid only if RCLK and / or TCLK = 1in T2CON register. Note that a rollover in TH2 does not set TF2, and Will not generate an interrupt. Thus, the Timer 2 interrupt does not have to be disabled when Timer 2 is in the baudrate generator mode. Also if the EXEN2 (T2 external enable flag) is set, a 1-to-0 transition in T2EX (Timer / counter 2 trigger input) will set EXF2 (T2 external flag) but will not cause a reload from (RCAP2H, RCAP2L) to (TH2, TL2). Therefore when Timer 2 is in use as a baud rate generator, T2EX can be used as an additional external interrupt, if needed. When Timer 2 is in the baud rate generator mode, one should not try to read or write TH2 and TL2. As a baud rate generator, Timer 2 is accurate. The RCAP2 registers may be read, but should not be written to, because a write might overlap a reload and cause write and / or reload errors. The timer should be turned off (clear TR2) before accessing the Timer 2 or RCAP2 registers. Table 10 shows commonly used baud rates and how they can be obtained from Timer 2. Summary Of Baud Rate Equations Timer 2 is in baud rate generating mode. If Timer 2 is being clocked through pin T2(P1.0) the baud rate is : Timer 2 Overflow Rate Baud Rate = 16 If Timer 2 is being clocked internally, The baud rate is : Baud Rate = fOSC [ n * x [65536 - (RCAP2H, RCAP2L)]] *n = 32 in 12 clock mode or 16 in 6 clock mode Where fOSC = Oscillator Frequency To obtain the reload value for RCAP2H and RCAP2L, the above equation can be rewritten as : RCAP2H, RCAP2L = 65536 - ( fOSC n * x Baud Rate ) Timer / Counter 2 Set-up Except for the baud rate generator mode, the values given for T2CON do not include the setting of the TR2 bit. Therefore, bit TR2 must be set, separately, to turn the timer on. see Table 11 for set-up of Timer 2 as a timer. Also see Table 12 for set-up of Timer 2 as a counter. P/N:PM0887 PM0887 Specifications subject to change without notice, contact your sales representatives for the most update information. 22 REV. 1.3, JUL. 21, 2003 PRELIMINARY MX10E8050I MX10E8050I / X MX10E8050IA MX10E8050IA Table 11 : Timer 2 as a Timer T2CON INTERNAL CONTROL EXTERNAL CONTROL (Note 1) (Note 2) 00H 08H 01H 09H 34H 36H 24H 26H 14H 16H MODE 16-bit Auto-Reload 16-bit Capture Baud rate generator receive and transmit same baud rate Receive only Transmit only Table 12 : Timer 2 as a Counter TMOD MODE INTERNAL CONTROL (Note 1) 16-bit Auto-Reload 02H 03H EXTERNAL CONTROL (Note 2) 0AH 0BH NOTES : 1. Capture / reload occurs only on timer / counter overflow. 2. Capture / reload occurs on timer / counter overflow and a 1-to-0 transition on T2EX (P1.1) pin except when Timer 2 is used in the baud rate generatior mode. P/N:PM0887 PM0887 Specifications subject to change without notice, contact your sales representatives for the most update information. 23 REV. 1.3, JUL. 21, 2003 PRELIMINARY MX10E8050I MX10E8050I / X MX10E8050IA MX10E8050IA Interrupt system The MX10E8050I MX10E8050I Serial contains a 7-source (2 external interrupts, Timer 0, Timer1, Timer2, I2C and UART) with four priority levels interrupt structure. Each External interrupts INT0 and INT1, can be either level-activated or transition-activated depending on bits IT0 and IT1 in TCON SFR. The flags that actually generate these interrupts are bits IE0, IE1 in TCON. When an external interrupt is generated, the corresponding request flag is cleared by the hardware where the service routine is vectored to, if the interrupt is transition-activated. If the interrupt is level-activated the external source has to hold the request active until the requested interrupt is actually generated. Then it has to deactive the request before the interrupt service routine is completed, otherwise another interrupt will be generated. The Timer 0 and Timer 1 Interrupts are generated by TF0 and TF1, which are set by a rollover in their respective Timer/counter register (except for Timer 0 in Mode 3 of the serial interface). When a Timer interrupt is generated, the flag that generated it is cleared by the on-chip hardware when the service routine is vectored to. IE : INTERRUPT ENABLE REGISTER This register is located at address A8H. Table. 13 IE SFR (A8H) 7 6 5 4 3 EA ET2 ES1 ES ET1 (MSB) keep the above table with the following table 2 EX1 1 ET0 0 EX0 (LSB) Table. 14 Description of IE bits MNEMONIC POSITION FUNCTION EA IE.7 Disable all interrupt - Low, all disabled. - High, each interrupt source is individually enabled or disabled by setting or clearing its enable bit. ET2 IE.6 Enable / Disable Timer2 interrupt. - Low, disabled - High, enabled ES1 IE.5 Enable / Disable l2C Interrupt. - Low, disabled - High, enabled ES IE.4 Enable / Disable UART interrupt. - Low, disabled - High, enabled ET1 IE.3 Enable / Disable Timer1 overflow interrupt. EX1 IE.2 Enable / Disable External interrupt 1. - Low, disabled - High, enabled ET0 IE.1 Enable / disable Timer0 overflow interrupt. EX0 IE.0 Enable / Disable External interrupt 0. - Low, disabled - High, enabled P/N:PM0887 PM0887 Specifications subject to change without notice, contact your sales representatives for the most update information. 24 REV. 1.3, JUL. 21, 2003 PRELIMINARY MX10E8050I MX10E8050I / X MX10E8050IA MX10E8050IA IP : INTERRUPT PRIORITY REGISTER This register is located at address B8H. Table. 15 IP SFR (B8H) 7 6 5 PT2H PS1H 4 PSH 3 PT1H 2 PX1H 1 PT0H 0 PX0H (LSB) keep the above table with the following table Table. 16 Description of IP bits MNEMONIC POSITION FUNCTION IP.7 RESERVED PT2H IP.6 Define Timer2 interrupt priority level. - High, assign a high priority level. PS1H IP.5 Define I2C interrupt priority level. - High, assign a high priority level. PSH IP.4 Define interrupt priority level of UART. PT1H IP.3 Define Timer1 overflow interrupt priority level. PX1H IP.2 Define External interrupt 1 interrupt priority level. - High, assign a high priority level. PT0H IP.1 Define Timer0 overflow interrupt priority level. PX0H IP.0 Define External interrupt 0 interrupt priority level. - High, assign a high priority level. P/N:PM0887 PM0887 Specifications subject to change without notice, contact your sales representatives for the most update information. 25 REV. 1.3, JUL. 21, 2003 PRELIMINARY MX10E8050I MX10E8050I / X MX10E8050IA MX10E8050IA IPH : INTERRUPT HIGH PRIORITY REGISTER This register is located at address B7H. Table. 17 IPH SFR (B7H) 7 6 5 PT2H PS1H 4 PSH 3 PT1H 2 PX1H 1 PT0H 0 PX0H ( LSB ) keep the above table with the following table Table. 18 Description of IPH bits MNEMONIC POSITION FUNCTION IPH.7 RESERVED PT2H IPH.6 Define Timer2 interrupt priority level. - High, assign a high priority level. PS1H IPH.5 Define I2C interrupt priority level. - High, assign a high priority level. PSH IPH.4 Define interrupt priority level of UART. PT1H IPH.3 Define Timer1 overflow interrupt priority level. PX1H IPH.2 Define External interrupt 1 interrupt priority level. - High, assign a high priority level. PT0H IPH.1 Define Timer0 overflow interrupt priority level. PX0H IPH.0 Define External interrupt 0 interrupt priority level. - High, assign a high priority level. NAME IE0 I2C TF0 IE1 TF1 RI + TI TF2 + EXF2 P/N:PM0887 PM0887 PRIORITY WITHIN LEVEL (HIGHEST) 1 2 3 4 5 6 (LOWEST) 7 VECTOR ADDRESS 0003H 0003H 002BH 002BH 000BH 000BH 0013H 0013H 001BH 001BH 0023H 0023H 0033H 0033H Specifications subject to change without notice, contact your sales representatives for the most update information. 26 REV. 1.3, JUL. 21, 2003 PRELIMINARY MX10E8050I MX10E8050I / X MX10E8050IA MX10E8050IA Watchdog Timer The Watchdog Timer (WDT) see Fig.8 , consists of an 11-bit prescaler and an 8-bit Timer formed by SFR T3. The Timer is incremented every 1.5 ms, derived from the system clock frequency of 16 MHz by the following formula : fTimer = fclk / (12 x (2048). The 8-bit Timer increments every 12 x 2048 cycles of the on-chip oscillator. When a Timer overflow occurs, the microcontroller is reset. The internal RESET signal is not inhibited when the external RST pin is kept 0 into high impedance, no matter if the XTAL-clock is running or not. To prevent a system reset the Timer must be reloaded in time by the application software. If the processor suffers a hardware / software malfunction, the software will fail to reload the Timer. This failure will result in an overflow thus prevent the processor from running out of control. This time interval is determined by the 8-bit reload value that is written into register T3. Watchdog time interval = [ 100 - T3 ] x 12 x 2048 / oscillator frequency (12x mode) [ 100 - T3 ] x 6 x 2048 / oscillator frequency ( 6x mode) The watch-dog Timer can only be reloaded if the condition flag WLE (SFR PCON bit 4) has been previously set high by software. At the moment the counter is loaded WLE is automatically cleared. In the idle state the watchdog Timer and reset circuitry remain active. The watchdog Timer is controlled by the watchdog enable signal EW (SFR EBTCON bit 1). A LOW level enables the watchdog Timer. A HIGH level disable the watchdog Timer. Internal Bus Prescaler (11-bit) Timer T3 (8-bit) Clear fCLK/12 LOAD LOADEN to reset circuitry Write T3 Clear WLE PD LOADEN PCON. 4 PCON. 1 EW Internal Bus Fig. 8 Watchdog Timer T3 P/N:PM0887 PM0887 Specifications subject to change without notice, contact your sales representatives for the most update information. 27 REV. 1.3, JUL. 21, 2003 PRELIMINARY MX10E8050I MX10E8050I / X MX10E8050IA MX10E8050IA Pulse Width Modulated Outputs The MX10E8050I MX10E8050I contains four pulse width modulated output channels. These channels generate pulses of programmable length and interval. Two kinds of user modes are available. One is to use two channels as a pair of PWM output with one prescaler and four channels as two pairs of PWM outputs with each own single prescaler. The operation thus is like two set of independently PWM modules. The repetition frequency is defined by an 8-bit prescaler, which supplies the clock for the counter. The prescaler and counter are common to the both PWM channels in each set. The 8-bit counter counts modulo 255, i.e., from 0 to 254 inclusive. The value of the 8-bit counter is compared to the contents of two registers: PWM0 and PWM1 or PWM2 and PWM3. Provided the contents of either of these registers is greater than the counter value, the corresponding PWM0 or PWM1 or PWM2 or PWM3 output is set LOW. If the contents of these registers are equal to, or less than the counter value, the output will be HIGH. The pulse-width-ratio is therefore defined by the contents of the registers PWM0 and PWM1 or PWM2 and PWM3. The pulse-width-ratio is in the range of 0 to 1 and may be programmed in increments of 1/255. The other one operation is that to use four channels as four independently PWM outputs with each own prescaler. fPWM = fOSC 2 x (1 + PWMP) x 255 This gives a repetition frequency range of 123Hz to 31.4KHz (fOSC = 16MHz). At fOSC = 24MHz, the frequency range is 184Hz to 47.1KHz. By loading the PWM registers with either 00H or FFH, the PWM channels will output a constant HIGH or LOW level, respectively. Since the 8-bit counter counts modulo 255, it can never actually reach the value of the PWM registers when they are loaded with FFH. When a compare register (PWM0 or PWM1 or PWM2 or PWM3) is loaded with a new value, the associated output is updated immediately. It does not have to wait until the end of the current counter period. Every PWMn output pins are driven by push-pull drivers. These pins are not used for any other purpose. The PWM function is enabled by setting SFR PWMC. SFR PWMC also controls operational mode and enable out. After reset, P4.0 to P4.3 are used to as the PWM output. P/N:PM0887 PM0887 Specifications subject to change without notice, contact your sales representatives for the most update information. 28 REV. 1.3, JUL. 21, 2003 PRELIMINARY MX10E8050I MX10E8050I / X MX10E8050IA MX10E8050IA P/N:PM0887 PM0887 Specifications subject to change without notice, contact your sales representatives for the most update information. 29 REV. 1.3, JUL. 21, 2003 PRELIMINARY MX10E8050I MX10E8050I / X MX10E8050IA MX10E8050IA DSCA/DSCB = 1 PWM0/2 8-BIT COMPARATOR Internal Bus fCKL PRESCALE (PWMP 0/2) OUTPUT BUFFER PWM 0/2 OUTPUT BUFFER PWM 1/3 8-BIT COUNTER 1/2 PRESCALE (PWMP 1/3) 8-BIT COUNTER 8-BIT COMPARATOR PWM1/3 DSCA/DSCB = 0 PWM0/2 8-BIT COMPARATOR OUTPUT BUFFER PWM 0/2 OUTPUT BUFFER PWM 1/3 Internal Bus fCKL 1/2 PRESCALE (PWMP 0,1) (PWMP 2,3) 8-BIT COUNTER 8-BIT COMPARATOR PWM1/3 Fig. 9 Functional Diagram of Pulse Width Modulated Outputs P/N:PM0887 PM0887 Specifications subject to change without notice, contact your sales representatives for the most update information. 30 REV. 1.3, JUL. 21, 2003 PRELIMINARY MX10E8050I MX10E8050I / X MX10E8050IA MX10E8050IA UART Enhanced UART In addition to the standard operation the UART can perform framing error detect by looking for missing stop bits, and automatic address recognition. The UART also fully supports multiprocessor communication as does the standard 80C51 80C51 UART. When used for framing error detect the UART looks for missing stop bits in the communication. A missing bit will set the FE bit in the SCON register. The FE bit shares the SCON.7 bit with SM0 and the function of SCON.7 is determined by PCON.6 (SMOD0) (see Figure 10). If SMOD0 is set then SCON.7 functions as FE. SCON.7 functions as SM0 when SMOD0 is cleared. When used as FE SCON.7 can only be cleared by software. Automatic Address Recognition Automatic Address Recognition is a feature which allows the UART to recognize certain addresses in the serial bit stream by using hardware to make the comparisons. This feature saves a great deal of software overhead by eliminating the need for the software to examine every serial address which passes by the serial port. This feature is enabled by setting the SM2 bit in SCON. In the 9 bit UART modes, mode 2 and mode 3, the Receive Interrupt flag (RI) will be automatically set when the received byte contains either the "Given" address or the "Broadcast" address. The 9-bit mode requires that the 9th information bit is a 1 to indicate that the received information is an address and not data. Automatic address recogintion is shown in figure 12. The 8 bit mode is called Mode 1. In this mode the RI flag will be set if SM2 is enabled and the information received has a valid stop bit following the 8 address bits and the information is either a Given or Broadcast address. Mode 0 is the Shift Register mode and SM2 is ignored. Using the Automatic Address Recognition feature allows a master to selectively communicate with one or more slaves by invoking the Given slave address or addresses. All of the slaves may be contacted by using the Broadcast address. Two special Function Registers are used to define the slave's address, SADDR, and the address mask, SADEN. SADEN is used to define which bits in the SADDR are to b used and which bits are "don't care". The SADEN mask can be logically ANDed with the SADDR to create the "Given" address which the master will use for addressing each of the slaves. Use of the Given address allows multiple slaves to be recognized while excluding others. The following examples will help to show the versatility of this scheme: Slave 0 SADDR = 1100 0000 SADEN = 1111 1101 Given = 1100 00X0 Slave 1 SADDR = 1100 0000 SADEN = 1111 1110 Given = 1100 000X In the above example SADDR is the same and the SADEN data is used to differentiate between the two slaves. Slave 0 requires a 0 in bit 0 and it ignores bit 1. Slave 1 requires a 0 in bit 1 and bit 0 is ignored. A unique address for Slave 0 would be 1100 0010 since slave 1 requires a 0 in bit 1. A unique address for slave 1 would be 1100 0001 since a 1 in bit 0 will exclude slave 0. Both slaves can be selected at the same time by an address which has bit 0 = 0 (for slave 0) and bit 1 = 0 (for slave 1). Thus, both could be addressed with 1100 0000. In a more complex system the following could be used to select slaves 1 and 2 while excluding slave 0: P/N:PM0887 PM0887 Specifications subject to change without notice, contact your sales representatives for the most update information. 31 REV. 1.3, JUL. 21, 2003 PRELIMINARY MX10E8050I MX10E8050I / X MX10E8050IA MX10E8050IA Slave 0 SADDR = 1100 0000 SADEN = 1111 1001 Given = 1100 0XX0 Slave 1 SADDR = 1110 0000 SADEN = 1111 1010 Given = 1110 0X0X Slave 2 SADDR = 1110 0000 SADEN = 1111 1100 Given = 1110 00XX In the above example the differentiation among the 3 slaves is in the lower 3 address bits. Slave 0 requires that bit 0 = 0 and it can be uniquely addressed by 1110 0110. Slave 1 requires that bit 1 = 0 and it can be uniquely addressed by 1110 and 0101. Slave 2 requires that bit 2 = 0 and its unique address is 1110 0011. To select Slaves 0 and 1 and exclude Slave 2 use address 1110 0100, since it is necessary to make bit 2 = 1 to exclude slave 2. The Broadcast Address for each slave is created by taking the logical OR of SADDR and SADEN. Zeros in this result are trended as don't-cares. In most cases, interpreting the don't-cares as ones, the broadcast address will be FF hexadecimal. Upon reset SADDR (SFR address 0A9H) and SADEN (SFR address 0B9H) are leaded with 0s. This produces a given address of all "don't cares" as well as a Broadcast address of all "don't cares". This effectively disables the Automatic Addressing mode and allows the microcontroller to use standard 80C51 80C51 type UART drivers which do not make use of this feature. P/N:PM0887 PM0887 Specifications subject to change without notice, contact your sales representatives for the most update information. 32 REV. 1.3, JUL. 21, 2003 PRELIMINARY MX10E8050I MX10E8050I / X MX10E8050IA MX10E8050IA SCON Address = 98H Reset Value = 0000 0000B 0000B Bit Addressable SM0/FE Bit: SM1 SM2 REN TB8 RB8 Tl Rl 5 7 6 (SMOD0 = 0/1)* 4 3 2 1 0 Symbol Function FE Framing Error bit. This bit is set by the receiver when an invalid stop bit is detected. The FE bit is not cleared by valid frames but should be cleared by software. The SMOD0 bit must be set to enable access to the FE bit. SM0 Serial Port Mode Bit 0, (SMOD0 must = 0 to access bit SM0) SM1 Serial Port Mode Bit 1 SM0 SM1 Mode Description Baud Rate* 0 0 1 0 1 0 0 1 2 shift register 8-bit UART 9-bit UART 1 1 3 9-bit UART fOSC/6 (6-clock mode) or fOSC/12 (12-clock mode) variable fOSC/32 or fOSC/16 (6-clock mode) or fOSC/64 or fOSC/32 (12-clock mode) variable SM2 Enables the Automatic Address Recognition feature in Modes 2 or 3. If SM2 = 1 then Rl will not be set unless the received 9th data bit (RB8) is 1, indicating an address, and the received byte is a Given or Broadcast Address. In Mode 1, if SM2 = 1 then Rl will not be activated unless a valid stop bit was received, and the received byte is a Given or Broadcast Address. In Mode 0, SM2 should be 0. REN Enables serial reception. Set by software to enable reception. Clear by software to disable reception. TB8 The 9th data bit that will be transmitted in Modes 2 and 3. Set or clear by software as desired. RB8 In modes 2 and 3, the 9th data bit that was received. In Mode 1, if SM2 = 0, RB8 is the stop bit that was received. In Mode 0, RB8 is not used. Tl Transmit interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or at the beginning of the stop bit in the other modes, in any serial transmission. Must be cleared by software. Rl Receive interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or halfway through the stop bit time in the other modes, in any serial reception (except see SM2). Must be cleared by software. NOTE: *SMOD0 is located at PCON6. *fOSC = oscillator frequency Figure 10. SCON : Serial Port Control Register P/N:PM0887 PM0887 Specifications subject to change without notice, contact your sales representatives for the most update information. 33 REV. 1.3, JUL. 21, 2003 PRELIMINARY MX10E8050I MX10E8050I / X MX10E8050IA MX10E8050IA D0 D1 D2 D3 D4 D5 D6 D7 D8 DATA BYTE START BIT ONLY IN MODE 2, 3 STOP BIT SET FE BIT IF STOP BIT IS 0 (FRAMING ERROR) SM0 TO UART MODE CONTROL SM0 / FE SM1 SM2 REN SMOD1 SMOD0 ± POF RB8 TB8 LVF TI RI SCON (98H) GF0 GF1 IDL PCON (87H) 0 : SCON.7 = SM0 1 : SCON.7 = FE Figure 11. UART Framing Error Detection D0 D1 D2 D3 D4 SM0 SM1 1 1 1 0 D5 SM2 1 D6 D7 D8 REN TB8 RB8 1 X TI RI SCON (98H) RECEIVED ADDRESS D0 TO D7 COMPARATOR PROGRAMMED ADDRESS IN UART MODE 2 OR MODE 3 AND SM2 = 1: INTERRUPT IF REN=1, RB8=1 AND ªRECEIVED ADDRESSº = ªPROGRAMMED ADDRESSº ± WHEN OWN ADDRESS RECEIVED, CLEAR SM2 TO RECEIVE DATA BYTES ± WHEN ALL DATA BYTES HAVE BEEN RECEIVED: SET SM2 TO WAIT FOR NEXT ADDRESS. Figure 12. UART Multiprocessor Communication, Automatic Address Recognition P/N:PM0887 PM0887 Specifications subject to change without notice, contact your sales representatives for the most update information. 34 REV. 1.3, JUL. 21, 2003 PRELIMINARY MX10E8050I MX10E8050I / X MX10E8050IA MX10E8050IA Serial I/O The MX10E8050I MX10E8050I Serial is equipped with two independent serial ports : SIO0 and SIO1. SIO0 is a full duplex UART port and is identical to the 80C51 80C51 serial port. SIO0 : SIO0 is a full duplex serial I/O port identical to that on the 80C51 80C51. It's operation is the same, including the use of timer 1 as a baud rate generator. SIO1, I2C Serial I/O : The I2C bus uses two wires (SDA and SCL) to transfer information between devices connected to the bus. The main features of the bus are : - Bidirectional data transfer between masters and slaves - Multimaster bus (no central master) - Arbitration between simultaneously transmitting masters without corruption of serial data on the bus - Serial clock synchronization allows devices with different bit rates to communicate via one serial bus - Serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer - The I2C bus may be used for test and diagnostic purposes The output latches of P1.6 and P1.7 must be set to logic 1 in order to enable SIO1. The MX10E8050I MX10E8050I Serial on-chip I2C logic provides a serial interface that meets the I2C bus specification and supports all transfer modes (other than the low-speed mode) from and to the I2C bus. The SIO1 logic handles bytes transfer autonomously. It also keeps track of serial transfers, and a status register (S1STA) reflects the status of SIO1 and the I2C bus. The CPU interfaces to the I2C logic via the following four special function register : S1CON (SIO1 control register), S1STA (SIO1 status register), S1DAT (SIO1 data register), and S1ADR (SIO1 slave address register). The SIO1 logic interfaces to the external I2C bus via two port 1 pins : P1.6/SCL (serial clock line) and P1.7/SDA (serial data line). A typical I2C bus configuration is shown in Figure 13, and Figure 14 shows how a data transfer is accomplished on the bus. Depending on the state of the direction bit (R/W), two types of data transfers are possible on the I2C bus: 1. Data transfer from a master transmitter to a slave receiver. The first byte transmitted by the master is the slave address. Next follows a number of data bytes. The slave returns an acknowledge bit after each received byte. 2. Data transfer from a slave transmitter to a master receiver. The first byte (the slave address) is transmitted by the master. The slave then returns an acknowledge bit. Next follows the data bytes transmitted by the slave to the master. The master returns an acknowledge bit after all received bytes other than the last byte. At the end of the last received byte, a "not acknowledge" is returned. The master device generates all of the serial clock pulses and the START and STOP conditions. A transfer is ended with a STOP condition or with a repeated START condition. Since a repeated START condition is also the beginning of the next serial transfer, the I2C bus will not be released. P/N:PM0887 PM0887 Specifications subject to change without notice, contact your sales representatives for the most update information. 35 REV. 1.3, JUL. 21, 2003 PRELIMINARY MX10E8050I MX10E8050I / X MX10E8050IA MX10E8050IA Modes of Operation: The on-chip SIO1 logic may operate in the following four modes: 1. Master Transmitter Mode: Serial data output through P1.7/SDA while P1.6/SCL outputs the serial clock. The first byte transmitted contains the slave address of the receiving device (7 bits) and the data direction bit. In this case the data direction bit (R/W) will be logic 0, and we say that a "W" is transmitted. Thus the first byte transmitted is SLA+W. Serial data is transmitted 8 bits at a time. After each byte is transmitted, an acknowledge bit is received. START and STOP conditions are output to indicate the beginning and the end of a serial transfer. 2. Master Receiver Mode: The first byte transmitted contains the slave address of the transmitting device (7 bits) and the data direction bit. In this case the data direction bit (R/W) will be logic 1, and we say that an "R" is transmitted. Thus the first byte transmitted is SLA+R. Serial data is received via P1.7/SDA while P1.6/SCL outputs the serial clock. Serial data is received 8 bits at a time. After each byte is received, an acknowledge bit is transmitted. START and STOP conditions are output to indicate the beginning and end of a serial transfer. 3. Slave Receiver Mode: Serial data and the serial clock are received through P1.7/SDA and P1.6/SCL. After each byte is received, an acknowledge bit is transmitted. START and STOP conditions are recognized as the beginning and end of a serial transfer. Address recognition is performed by hardware after reception of the slave address and direction bit. 4. Slave Transmitter Mode: The first byte is received and handled as in the slave receiver mode. However, in this mode, the direction bit will indicate that the transfer direction is reversed. Serial data is transmitted via P1.7/SDA while the serial clock is input through P1.6/SCL. START and STOP conditions are recognized as the beginning and end of a serial transfer. In a given application, SIO1 may operate as a master and as a slave. In the slave mode, the SIO1 hardware looks for its own slave address and the general call address. If one of these addresses is detected, an interrupt is requested. When the microcontroller wishes to become the bus master, the hardware waits until the bus is free before the master mode is entered so that a possible slave action is not interrupted. If bus arbitration is lost in the master mode, SIO1 switches to the slave mode immediately and can detect its own slave address in the same serial transfer. SIO1 Implementation and Operation: Figure 15 shows how the on-chip I2C bus interface is implemented, and the following text describes the individual blocks. INPUT FILTERS AND OUTPUT STAGES The input filters have I2C compatible input levels. If the input voltage is less than 1.5V, the input logic level is interpreted as 0; if the input voltage is greater than 3.0V, the input logic level is interpreted as 1. Input signals are synchronized with the internal clock (fOSC/4), and spikes shorter than three oscillator periods are filtered out. The output stages consist of open drain transistors that can sink 3mA at VOUT < 0.4V. These open drain outputs do not have clamping diodes to VDD. Thus, if the device is connected to the I2C bus and VDD is switched off, the I2C bus is not affected. P/N:PM0887 PM0887 Specifications subject to change without notice, contact your sales representatives for the most update information. 36 REV. 1.3, JUL. 21, 2003 PRELIMINARY MX10E8050I MX10E8050I / X MX10E8050IA MX10E8050IA ADDRESS REGISTER, S1ADR This 8-bit special function register may be loaded with the 7-bit slave address (7 most significant bits) to which SIO1 will respond when programmed as a slave transmitter or receiver. The LSB (GC) is used to enable general call address (00H) recognition. COMPARATOR The comparator compares the received 7-bit slave address with its own slave address (7 most significant bits in S1ADR). It also compares the first received 8-bit byte with the general call address (00H). If an equality is found, the appropriate status bits are set and an interrupt is requested. SHIFT REGISTER, S1DAT This 8-bit special function register contains a byte of serial data to be transmitted or a byte which has just been received. Data in S1DAT is always shifted from right to left; the first bit to be transmitted is the MSB (bit 7) and, after a byte has been received, the first bit of received data is located at the MSB of S1DAT. While data is being shifted out, data on the bus is simultaneously being shifted in; S1DAT always contains the last byte present on the bus. Thus, in the event of lost arbitration, the transition from master transmitter to slave receiver is made with the correct data in S1DAT. P/N:PM0887 PM0887 Specifications subject to change without notice, contact your sales representatives for the most update information. 37 REV. 1.3, JUL. 21, 2003 PRELIMINARY MX10E8050I MX10E8050I / X MX10E8050IA MX10E8050IA VDD RP RP SDA I2C bus SCL P1.7/SDA P1.6/SCL Other Device with I2C Interface MX10E8050I/X MX10E8050I/X Other Device with I2C Interface Figure 13. Typical I2C Bus Configuration Stop Condition SDA Repeated Start Condition MSB Slave Address R/W Direction Bit Acknowledgment Signal from Receiver Acknowledgment Signal from Receiver SCL 1 S 2 7 8 9 ACK Clock Line Held Low While Interrupts Are Serviced 1 2 3±8 9 ACK P/S Repeated if more bytes are transferred Start Condition Figure 14. Data Transfer on the I2C Bus P/N:PM0887 PM0887 Specifications subject to change without notice, contact your sales representatives for the most update information. 38 REV. 1.3, JUL. 21, 2003 PRELIMINARY MX10E8050I MX10E8050I / X MX10E8050IA MX10E8050IA 8 S1ADR Address Register P1.7 Comparator Input Filter P1.7/SDA Output Stage S1DAT Shift Register ACK Arbitration & Sync Logic Input Filter P1.6/SCL Internal Bus 8 Timing & Control Logic fOSC/4 Serial Clock Generator Output Stage Interrupt Timer 1 Overflow Control Register S1CON P1.6 8 Status Bits Status Decoder S1STA Status Register 8 Figure 15. I2C Bus Serial Interface Block Diagram P/N:PM0887 PM0887 Specifications subject to change without notice, contact your sales representatives for the most update information. 39 REV. 1.3, JUL. 21, 2003 PRELIMINARY MX10E8050I MX10E8050I / X MX10E8050IA MX10E8050IA (3) (1) (1) (2) SDA SCL 2 1 3 4 8 9 ACK 1. Another device transmits identical serial data. 2. Another device overrules a logic 1 (dotted line) transmitted by SIO1 (master) by pulling the SDA line low. Arbitration is lost, and SIO1 enters the slave receiver mode. 3. SIO1 is in the slave receiver mode but still generates clock pulses until the current byte has been transmitted. SIO1 will not generate clock pulses for the next byte. Data on SDA originates from the new master once it has won arbitration. Figure 16. Arbitration Procedure SDA (1) (3) (1) SCL (2) Mark Duration Space Duration 1. Another service pulls the SCL line low before the SIO1"mark" duration is complete. The serial clock generator is immediately reset and commences with the "space" duration by pulling SCL low. 2. Another device still pulls the SCL line low after SIO1 releases SCL. The serial clock generator is forced into the wait state until the SCL line is released. 3. The SCL line is released, and the serial clock generator commences with the mark duration. Figure 17. Serial Clock Synchronization P/N:PM0887 PM0887 Specifications subject to change without notice, contact your sales representatives for the most update information. 40 REV. 1.3, JUL. 21, 2003 PRELIMINARY MX10E8050I MX10E8050I / X MX10E8050IA MX10E8050IA ARBITRATION AND SYNCHRONIZATION LOGIC In the master transmitter mode, the arbitration logic checks that every transmitted logic 1 actually appears as a logic 1 on the I2C bus. If another device on the bus overrules a logic 1 and pulls the SDA line low, arbitration is lost, and SIO1 immediately changes from master transmitter to slave receiver. SIO1 will continue to output clock pulses (on SCL) until transmission of the current serial byte is complete. Arbitration may also be lost in the master receiver mode. Loss of arbitration in this mode can only occur while SIO1 is returning a "not acknowledge: (logic 1) to the bus. Arbitration is lost when another device on the bus pulls this signal LOW. Since this can occur only at the end of a serial byte, SIO1 generates no further clock pulses. Figure 16 shows the arbitration procedure. The synchronization logic will synchronize the serial clock generator with the clock pulses on the SCL line from another device. If two or more master devices generate clock pulses, the "mark" duration is determined by the device that generates the shortest "marks," and the "space" duration is determined by the device that generates the longest "spaces." Figure 17 shows the synchronization procedure. A slave may stretch the space duration to slow down the bus master. The space duration may also be stretched for handshaking purposes. This can be done after each bit or after a complete byte transfer. SIO1 will stretch the SCL space duration after a byte has been transmitted or received and the acknowledge bit has been transferred. The serial interrupt flag (SI) is set, and the stretching continues until the serial interrupt flag is cleared. SERIAL CLOCK GENERATOR This programmable clock pulse generator provides the SCL clock pulses when SIO1 is in the master transmitter or master receiver mode. It is switched off when SIO1 is in a slave mode. The programmable output clock frequencies are: fOSC/120, fOSC/9600, and the Timer 1 overflow rate divided by eight. The output clock pulses have a 50% duty cycle unless the clock generator is synchronized with other SCL clock sources as described above. TIMING AND CONTROL The timing and control logic generates the timing and control signals for serial byte handling. This logic block provides the shift pulses for S1DAT, enables the comparator, generates and detects start and stop conditions, receives and transmits acknowledge bits, controls the master and slave modes, contains interrupt request logic, and monitors the I2C bus status. CONTROL REGISTER, S1CON This 7-bit special function register is used by the microcontroller to control the following SIO1 functions: start and restart of a serial transfer, termination of a serial transfer, bit rate, address recognition, and acknowledgment. STATUS DECODER AND STATUS REGISTER The status decoder takes all of the internal status bits and compresses them into a 5-bit code. This code is unique for each I2C bus status. The 5-bit code may be used to generate vector addresses for fast processing of the various service routines. Each service routine processes a particular bus status. There are 26 possible bus states if all four modes of SIO1 are used. The 5-bit status code is latched into the five most significant bits of the status register when the serial interrupt flag is set (by hardware) and remains stable until the interrupt flag is cleared by software. The three least significant bits of the status register are always zero. If the status code is used as a vector to service routines, then the routines are displaced by eight address locations. Eight bytes of code is sufficient for most of the service routines (see the software example in this section). The Four SIO1 Special Function Registers: The microcontroller interfaces to SIO1 via four special function registers. These four SFRs (S1ADR, S1DAT, S1CON, and S1STA) are described individually in the following sections. P/N:PM0887 PM0887 Specifications subject to change without notice, contact your sales representatives for the most update information. 41 REV. 1.3, JUL. 21, 2003 PRELIMINARY MX10E8050I MX10E8050I / X MX10E8050IA MX10E8050IA The Address Register, S1ADR: The CPU can read from and write to this 8-bit, directly addressable SFR. S1ADR is not affected by the SIO1 hardware. The contents of this register are irrelevant when SIO1 is in a master mode. In the slave modes, the seven most significant bits must be loaded with the microcontroller' s own slave address, and, if the least significant bit is set, the general call address (00H) is recognized; otherwise it is ignored. 7 S1ADR (DBH) 6 5 4 3 2 1 0 X X X X X X X GC own slave address The most significant bit corresponds to the first bit received from the I2C bus after a start condition. A logic 1 in S1ADR corresponds to a high level on the I2C bus, and a logic 0 corresponds to a low level on the bus. The Data Register, S1DAT: S1DAT contains a byte of serial data to be transmitted or a byte which has just been received. The CPU can read from and write to this 8-bit, directly addressable SFR while it is not in the process of shifting a byte. This occurs when SIO1 is in a defined state and the serial interrupt flag is set. Data in S1DAT remains stable as long as SI is set. Data in S1DAT is always shifted from right to left: the first bit to be transmitted is the MSB (bit 7), and, after a byte has been received, the first bit of received data is located at the MSB of S1DAT. While data is being shifted out, data on the bus is simultaneously being shifted in; S1DAT always contains the last data byte present on the bus. Thus, in the event of lost arbitration, the transition from master transmitter to slave receiver is made with the correct data in S1DAT. 7 S1ADR (DAH) 6 5 4 3 SD7 SD6 SD5 SD4 2 SD3 1 SD2 SD1 0 SD0 shift direction SD7 - SD0: Eight bits to be transmitted or just received. A logic 1 in S1DAT corresponds to a high level on the I2C bus, and a logic 0 corresponds to a low level on the bus. Serial data shifts through S1DAT from right to left. Figure 18 shows how data in S1DAT is serially transferred to and from the SDA line. S1DAT and the ACK flag form a 9-bit shift register which shifts in or shifts out an 8-bit byte, followed by an acknowledge bit. The ACK flag is controlled by the SIO1 hardware and cannot be accessed by the CPU. Serial data is shifted through the ACK flag into S1DAT on the rising edges of serial clock pulses on the SCL line. When a byte has been shifted into S1DAT, the serial data is available in S1DAT, and the acknowledge bit is returned by the control logic during the ninth clock pulse. Serial data is shifted out from S1DAT via a buffer (BSD7) on the falling edges of clock pulses on the SCL line. When the CPU writes to S1DAT, BSD7 is loaded with the content of S1DAT.7, which is the first bit to be transmitted to the SDA line (see Figure 19). After nine serial clock pulses, the eight bits in S1DAT will have been transmitted to the SDA line, and the acknowledge bit will be present in ACK. Note that the eight transmitted bits are shifted back into S1DAT. P/N:PM0887 PM0887 Specifications subject to change without notice, contact your sales representatives for the most update information. 42 REV. 1.3, JUL. 21, 2003 PRELIMINARY MX10E8050I MX10E8050I / X MX10E8050IA MX10E8050IA Internal Bus SDA 8 BSD7 S1DAT ACK SCL Shift Pulses Figure 18. Serial Input/Output Configuration The Control Register, S1CON: The CPU can read from and write to this 8-bit, directly addressable SFR. Two bits are affected by the SIO1 hardware: the SI bit is set when a serial interrupt is requested, and the STO bit is cleared when a STOP condition is present on the I2C bus. The STO bit is also cleared when ENS1 = "0". 7 S1CON (D8H) 6 5 4 3 2 CR2 ENS1 STA STO SI AA 1 CR1 0 CR0 ENS1, THE SIO1 ENABLE BIT ENS1 = "0": When ENS1 is "0", the SDA and SCL outputs are in a high impedance state. SDA and SCL input signals are ignored, SIO1 is in the "not addressed" slave state, and the STO bit in S1CON is forced to "0". No other bits are affected. P1.6 and P1.7 may be used as open drain I/O ports. ENS1 = "1": When ENS1 is "1", SIO1 is enabled. The P1.6 and P1.7 port latches must be set to logic 1. ENS1 should not be used to temporarily release SIO1 from the I2C bus since, when ENS1 is reset, the I2C bus status is lost. The AA flag should be used instead (see description of the AA flag in the following text). In the following text, it is assumed that ENS1 = "1". STA, THE START FLAG STA = "1": When the STA bit is set to enter a master mode, the SIO1 hardware checks the status of the I2C bus and generates a START condition if the bus is free. If the bus is not free, then SIO1 waits for a STOP condition (which will free the bus) and generates a START condition after a delay of a half clock period of the internal serial clock generator. If STA is set while SIO1 is already in a master mode and one or more bytes are transmitted or received, SIO1 transmits a repeated START condition. STA may be set at any time. STA may also be set when SIO1 is an addressed slave. STA = "0": When the STA bit is reset, no START condition or repeated START condition will be generated. STO, THE STOP FLAG STO = "1": When the STO bit is set while SIO1 is in a master mode, a STOP condition is transmitted to the I2C bus. When the STOP condition is detected on the bus, the SIO1 hardware clears the STO flag. In a slave mode, the STO flag may be set to recover from an error condition. In this case, no STOP condition is transmitted to the I2C bus. However, the SIO1 hardware behaves as if a STOP condition has been received and switches to the defined "not addressed" slave receiver mode. The STO flag is automatically cleared by hardware. P/N:PM0887 PM0887 Specifications subject to change without notice, contact your sales representatives for the most update information. 43 REV. 1.3, JUL. 21, 2003 PRELIMINARY MX10E8050I MX10E8050I / X MX10E8050IA MX10E8050IA If the STA and STO bits are both set, the a STOP condition is transmitted to the I2C bus if SIO1 is in a master mode (in a slave mode, SIO1 generates an internal STOP condition which is not transmitted). SIO1 then transmits a START condition. STO = "0": When the STO bit is reset, no STOP condition will be generated. SI, THE SERIAL INTERRUPT FLAG SI = "1": When the SI flag is set, then, if the EA and ES1 (interrupt enable register) bits are also set, a serial interrupt is requested. SI is set by hardware when one of 25 of the 26 possible SIO1 states is entered. The only state that does not cause SI to be set is state F8H, which indicates that no relevant state information is available. While SI is set, the low period of the serial clock on the SCL line is stretched, and the serial transfer is suspended. A high level on the SCL line is unaffected by the serial interrupt flag. SI must be reset by software. SI = "0": When the SI flag is reset, no serial interrupt is requested, and there is no stretching of the serial clock on the SCL line. AA, THE ASSERT ACKNOWLEDGE FLAG AA = "1": If the AA flag is set, an acknowledge (low level to SDA) will be returned during the acknowledge clock pulse on the SCL line when: - The "own slave address" has been received - The general call address has been received while the general call bit (GC) in S1ADR is set - A data byte has been received while SIO1 is in the master receiver mode - A data byte has been received while SIO1 is in the addressed slave receiver mode AA = "0": if the AA flag is reset, a not acknowledge (high level to SDA) will be returned during the acknowledge clock pulse on SCL when: - A data has been received while SIO1 is in the master receiver mode - A data byte has been received while SIO1 is in the addressed slave receiver mode When SIO1 is in the addressed slave transmitter mode, state C8H will be entered after the last serial is transmitted (see Figure 23). When SI is cleared, SIO1 leaves state C8H, enters the not addressed slave receiver mode, and the SDA line remains at a high level. In state C8H, the AA flag can be set again for future address recognition. When SIO1 is in the not addressed slave mode, its own slave address and the general call address are ignored. Consequently, no acknowledge is returned, and a serial interrupt is not requested. Thus, SIO1 can be temporarily released from the I2C bus while the bus status is monitored. While SIO1 is released from the bus, START and STOP conditions are detected, and serial data is shifted in. Address recognition can be resumed at any time by setting the AA flag. If the AA flag is set when the part's own slave address or the general call address has been partly received, the address will be recognized at the end of the byte transmission. CR0, CR1, AND CR2, THE CLOCK RATE BITS These three bits determine the serial clock frequency when SIO1 is in a master mode. The various serial rates are shown in Table 19. A 12.5kHz bit rate may be used by devices that interface to the I2C bus via standard I/O port lines which are software driven and slow. 100kHz is usually the maximum bit rate and can be derived from a 16MHz, 12MHz, or a 6MHz oscillator. A variable bit rate (0.5kHz to 62.5kHz) may also be used if Timer 1 is not required for any other purpose while SIO1 is in a master mode. The frequencies shown in Table 19 are unimportant when SIO1 is in a slave mode. In the slave modes, SIO1 will automatically synchronize with any clock frequency up to 100kHz. P/N:PM0887 PM0887 Specifications subject to change without notice, contact your sales representatives for the most update information. 44 REV. 1.3, JUL. 21, 2003 PRELIMINARY MX10E8050I MX10E8050I / X MX10E8050IA MX10E8050IA The Status Register, S1STA: S1STA is an 8-bit read-only special function register. The three least significant bits are always zero. The five most significant bits contain the status code. There are 26 possible status codes. When S1STA contains F8H, no relevant state information is available and no serial interrupt is requested. All other S1STA values correspond to defined SIO1 states. When each of these states is entered, a serial interrupt is requested (SI = "1"). A valid status code is present in S1STA one machine cycle after SI is set by hardware and is still present one machine cycle after SI has been reset by software. More Information on SIO1 Operating Modes: The four operating modes are: - Master Transmitter - Master Receiver - Slave Receiver - Slave Transmitter Data transfers in each mode of operation are shown in Figures 20~28. These figures contain the following abbreviations: Abbreviation S SLA R W A A Data P Explanation Start condition 7-bit slave address Read bit (high level at SDA) Write bit (low level at SDA) Acknowledge bit (low level at SDA) Not acknowledge bit (high level at SDA) 8-bit data byte Stop condition In Figures 20~28, circles are used to indicate when the serial interrupt flag is set. The numbers in the circles show the status code held in the S1STA register. At these points, a service routine must be executed to continue or complete the serial transfer. These service routines are not critical since the serial transfer is suspended until the serial interrupt flag is cleared by software. When a serial interrupt routine is entered, the status code in S1STA is used to branch to the appropriate service routine. For each status code, the required software action and details of the following serial transfer are given in Table 20~24. Master Transmitter Mode: In the master transmitter mode, a number of data bytes are transmitted to a slave receiver (see Figure 20). Before the master transmitter mode can be entered, S1CON must be initialized as follows: 7 6 5 4 3 2 1 0 S1CON (D8H) CR2 bit rate ENS1 1 STA STO SI AA 0 0 0 x CR1 CR0 bit rate CR0, CR1, and CR2 define the serial bit rate. ENS1 must be set to logic 1 to enable SIO1. If the AA bit is reset, SIO1 will not acknowledge its own slave address or the general call address in the event of another device becoming master of the bus. In other words, if AA is reset, SIO0 cannot enter a slave mode. STA, STO, and SI must be reset. The master transmitter mode may now be entered by setting the STA bit using the SETB instruction. The SIO1 logic will now test the I2C bus and generate a start condition as soon as the bus becomes free. When a START condition is transmitted, the serial interrupt flag (SI) is set, and the status code in the status register (S1STA) will be 08H. This status code must be used to vector to an interrupt service routine that loads S1DAT with the slave address and the data direction bit (SLA+W). The SI bit in S1CON must then be reset before the serial transfer can continue. P/N:PM0887 PM0887 Specifications subject to change without notice, contact your sales representatives for the most update information. 45 REV. 1.3, JUL. 21, 2003 PRELIMINARY MX10E8050I MX10E8050I / X MX10E8050IA MX10E8050IA When the slave address and the direction bit have been transmitted and an acknowledgment bit has been received, the serial interrupt flag (SI) is set again, and a number of status codes in S1STA are possible. There are 18H, 20H, or 38H for the master mode and also 68H, 78H, or B0H if the slave mode was enabled (AA = logic 1). The appropriate action to be taken for each of these status codes is detailed in Table 20. After a repeated start condition (state 10H). SIO1 may switch to the master receiver mode by loading S1DAT with SLA+R). SDA D7 D6 D5 D4 D3 D2 D1 D0 A SCL Shift ACK & S1DAT Shift In ACK S1DAT (2) (2) (2) (2) (2) (2) (2) A (2) (1) (2) (2) (2) (2) (2) (2) (2) (2) (1) Shift BSD7 Shift Out BSD7 D7 D6 D5 D4 D3 D2 D1 D0 (3) Loaded by the CPU (1) Valid data in S1DAT (2) Shifting data in S1DAT and ACK (3) High level on SDA Figure 19. Shift-in and Shift-out Timing Table 19 : Serial Clock Rates CR2 0 0 0 0 1 1 1 1 P/N:PM0887 PM0887 CR1 0 0 1 1 0 0 1 1 CR0 0 1 0 1 0 1 0 1 BIT FREQUENCY (kHz) AT fOSC 6MHz 12MHz 16MHz 23 47 63 27 54 71 31 63 83 37 75 100 6.25 12.5 17 50 100 100 0.25