MT88E41 GR-30-CORE SR-TSV-002476 MT88E41AE MT88E41AS MT88E41AN MP036S - Datasheet Archive

 

Extended Voltage Calling Number Identification Circuit (ECNIC) Features · · · · · ·

 

CMOS MT88E41 MT88E41 Extended Voltage Calling Number Identification Circuit (ECNIC) Features · · · · · · · · · · ISSUE 3 1200 baud BELL 202 and CCITT V.23 Frequency Shift Keying (FSK) demodulation Compatible with Bellcore GR-30-CORE GR-30-CORE and SR-TSV-002476 SR-TSV-002476 High input sensitivity: -36dBm minimum FSK Detection Level Simple serial 3-wire data interface eliminating the need for a UART Power down mode Internal gain adjustable amplifier Carrier detect status output Uses 3.579545 MHz crystal 2.7 - 5.5V operation Low power CMOS technology Applications · · · · · · · Calling Number Delivery (CND), Calling Name Delivery (CNAM) and Calling Identity on Call Waiting (CIDCW) features of Bellcore CLASSSM service Feature phones Phone sets, adjunct boxes FAX machines Telephone answering machines Database query systems Battery powered applications February 1998 Ordering Information MT88E41AE MT88E41AE 16 Pin Plastic DIP MT88E41AS MT88E41AS 16 Pin SOIC MT88E41AN MT88E41AN 20 Pin SSOP -40 °C to +85 °C Description The MT88E41 MT88E41 Extended Voltage Calling Number Identification Circuit (ECNIC) is a CMOS integrated circuit providing an interface to various calling line information delivery services that utilize 1200 baud BELL 202 or CCITT V.23 FSK voiceband data transmission schemes. The ECNIC receives and demodulates the signal and outputs data into a simple 3-wire serial interface. Typically, the FSK modulated data containing information on the calling line is sent before alerting the called party or during the silent interval between the first and second ring using either CCITT V.23 recommendations or Bell 202 specifications. The ECNIC accepts and demodulates both CCITT V.23 and BELL 202 signals. Along with serial data and clock, the ECNIC provides a data ready signal to indicate the reception of every 8-bit character sent from the Central Office. The received data can be processed externally by a microcontroller, stored in memory, or displayed as is, depending on the application. GS DATA IN- - IN+ Receive Bandpass Filter + Data and Timing Recovery FSK Demodulator DR DCLK CAP VRef Bias Generator Carrier Detector Clock Generator PWDN OSC1 OSC2 CD to other circuits VSS VDD IC1 IC2 Figure 1 - Functional Block Diagram CLASS SM is a service mark of Bellcore 5-21 MT88E41 MT88E41 IN+ INGS VRef CAP OSC1 OSC2 VSS 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 IN+ INGS VRef CAP NC OSC1 NC OSC2 VSS VDD IC2 IC1 PWDN CD DR DATA DCLK 16 PIN PLASTIC DIP/SOIC 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VDD IC2 NC NC IC1 PWDN CD DR DATA DCLK 20 PIN SSOP Figure 2 - Pin Connections Pin Description Pin # Name Description 16 20 1 1 IN+ Non-inverting Op-Amp (Input). 2 2 IN- Inverting Op-Amp (Input). 3 3 GS Gain Select (Output). Gives access to op-amp output for connection of feedback resistor. 4 4 VRef Voltage Reference (Output). Nominally VDD/2. This is used to bias the op-amp inputs. 5 5 CAP Capacitor. Connect a 0.1µF capacitor to VSS. 6 7 OSC1 Oscillator (Input). Crystal connection. This pin can be driven directly from an external clocking source. 7 9 OSC2 Oscillator (Output). Crystal connection. When OSC1 is driven by an external clock, this pin should be left open. 8 10 9 11 VSS Power supply ground. DCLK Data Clock (Output). Outputs a clock burst of 8 low going pulses at 1202.8Hz (3.5795MHz divided by 2976). Every clock burst is initiated by the DATA stop bit start bit sequence. When the input DATA is 1202.8 baud, the positive edge of each DCLK pulse coincides with the middle of the data bits output at the DATA pin. No DCLK pulses are generated during the start or stop bits. Typically, DCLK is used to clock the eight data bits from the 10 bit data word into a serialto-parallel converter. 10 12 DATA Data (Output). Serial data output corresponding to the FSK input and switching at the input baud rate. Mark frequency at the input corresponds to a logic high, while space frequency corresponds to a logic low at the DATA output. With no FSK input, DATA is at logic high. This output stays high until CD has become active. 11 13 DR Data Ready (Open Drain Output). This output goes low after the last DCLK pulse of each word. This can be used to identify the data (8-bit word) boundary on the serial output stream. Typically, DR is used to latch the eight data bits from the serial-to-parallel converter into a microcontroller. 12 14 CD Carrier Detect (Open Drain Output). A logic low indicates that a carrier has been present for a specified time on the line. A time hysteresis is provided to allow for momentary discontinuity of carrier. 13 15 PWDN Power Down (Input). Active high, Schmitt Trigger input. Powers down the device including the input op-amp and the oscillator. 14 16 IC1 Internal Connection 1. Connect to VSS. 15 19 IC2 Internal Connection 2. Internally connected, leave open circuit. 16 20 VDD Positive power supply voltage. 6,8 17, 18 NC No Connection. 5-22 MT88E41 MT88E41 Functional Description IN+ The MT88E41 MT88E41 Extended Voltage Calling Number Identification Circuit (ECNIC) is a device compatible with the Bellcore proposal (GR-30-CORE GR-30-CORE) on generic requirements for transmitting asynchronous voiceband data to Customer Premises Equipment (CPE) from a serving Stored Program Controlled Switching System (SPCS) or a Central Office (CO). This data transmission technique is applicable in a variety of services like Calling Number Delivery (CND), Calling Name Delivery (CNAM) or Calling Identity Delivery on Call Waiting (CIDCW) as specified in Custom Local Area Signalling Service (CLASSSM) calling information delivery features by Bellcore. With CND, CNAM and CIDCW service, the called subscriber has the capability to display or to store the information on the calling party which is sent by the CO and received by the ECNIC. In the CND service, information about a calling party is embedded in the silent interval between the first and second ring. During this period, the ECNIC receives and demodulates the 1200 baud FSK signal (compatible with Bell-202 specification) and outputs data into a 3-wire serial interface. In the CIDCW service, information about a second calling party is sent to the subscriber, (while the subscriber is engaged in another call). During this period, the ECNIC receives and demodulates the FSK signal as in the CND case. C IN- RIN RF VOLTAGE GAIN (AV) = RF / RIN GS VRef MT88E41 MT88E41 Figure 4 - Single-Ended Input Configuration at the called subscriber location either in the on-hook case as in CND, or the off-hook case, as in CIDCW. The functional block diagram of the ECNIC is shown in Figure 1. Note however, for CIDCW applications, a separate CAS (CPE Alerting Signal) detector is required. In Europe, Caller ID and CIDCW services are being proposed. These schemes may be different from their North American counterparts. In most cases, 1200 baud CCITT V.23 FSK is used instead of Bell 202. Because the ECNIC can also demodulate 1200 baud CCITT V.23 with the same performance, it is suitable for these applications. Although the main application of the ECNIC is to support CND and CIDCW service, it may also be used in any application where 1200 baud Bell 202 and/or CCITT V.23 FSK data reception is required. Input Configuration The ECNIC is designed to provide the data transmission interface required for the above service C1 R1 IN+ IN- C2 R4 The input arrangement of the MT88E41 MT88E41 provides an operational amplifier, as well as a bias source (VRef) which is used to bias the inputs at VDD/2. Provision is made for connection of a feedback resistor to the opamp output (GS) for adjustment of gain. In a singleended configuration, the input pins are connected as shown in Figure 4. R5 GS VRef R3 Figure 3 shows the necessary connections for a differential input configuration. User Interface R2 DIFFERENTIAL INPUT AMPLIFIER MT88E41 MT88E41 C1 = C2 = 10 nF R1 = R4 = R5 = 100 k R2 = 60k, R3 = 37.5 k R3 = (R2R5) / (R2 + R5) INPUT IMPEDANCE VOLTAGE GAIN (AVdiff) = R5/R1 (ZINdiff) = 2 R12 + (1/C)2 Figure 3 - Differential Input Configuration The ECNIC provides a powerful 3-pin interface which can reduce the external hardware and software requirements. The ECNIC receives the FSK signal, demodulates it, and outputs the extracted data to the DATA pin. For each received stop bit start bit sequence, the ECNIC outputs a fixed frequency clock string of 8 pulses at the DCLK pin. Each clock 5-23 MT88E41 MT88E41 rising edge corresponds to the centre of each DATA bit cell (providing the incoming baud rate matches the DCLK rate). DCLK is not generated for the stop and start bits. Consequently, DCLK will clock only valid data into a peripheral device such as a serial to parallel shift register or a micro-controller. The ECNIC also outputs an end of word pulse (data ready) at the DR pin. The data ready signal indicates the reception of every 10-bit word sent from the Central Office. This output is typically used to interrupt a micro-controller. The three outputs together, eliminate the need for a UART (Universal Asynchronous Receiver Transmitter) or the high software overhead of performing the UART function (asynchronous serial data reception). Note that the 3-pin interface may also output data generated by voice since these frequencies are in the input frequency detection band of the device. The user may choose to ignore these outputs when FSK data is not expected, or force the ECNIC into its powerdown mode. Power Down Mode For applications requiring reduced power consumption, the ECNIC can be forced into power down when it is not needed to receive FSK data. This is done by pulling the PWDN pin high. In powerdown mode, the crystal oscillator, op-amp and internal circuitry are all disabled and the ECNIC will not react to the input signal. DATA and DCLK are at logic high, and DR and CD are at high impedance or at logic high when pulled up with resistors.The ECNIC can be awakened for reception of the FSK signal by pulling the PWDN pin to ground (see Figure 9). Carrier Detect The presence of the FSK signal is indicated by a logic low at the carrier detect (CD) output. This output has built in hysteresis to prevent toggling when the received signal is shortly interrupted. Note that the CD output is also activated by voice since these frequencies are in the input frequency detection band of the device. The user may choose to ignore this output when FSK data is not expected, or force the ECNIC into its powerdown mode. 5-24 MT88E41 MT88E41 OSC1 OSC2 MT88E41 MT88E41 OSC1 OSC2 MT88E41 MT88E41 OSC1 OSC2 to the next MT88E41 MT88E41 3.579545 MHz Figure 5 - Common Crystal Connection Crystal Oscillator The ECNIC uses a crystal oscillator as the master timing source for filters and the FSK demodulator. The crystal specification is as follows: Frequency: Frequency tolerance: Resonance mode: Load capacitance: Maximum series resistance: Maximum drive level (mW): e.g. CTS MP036S MP036S 3.579545 MHz ±0.1%(-40°C+85°C) Parallel 18 pF 150 ohms 2 mW A number of MT88E41 MT88E41 devices can be connected as shown in Figure 5 such that only one crystal is required. The connection between OSC2 and OSC1 can be D.C. coupled as shown, or A.C. coupled using 30pF capacitors. Alternatively, the OSC1 inputs on all devices can be driven from a CMOS buffer (dc coupled) with the OSC2 outputs left unconnected. VRef and CAP Inputs VRef is the output of a low impedance voltage source equal to VDD/2 and is used to bias the input op-amp. A 0.1µF capacitor is required between CAP and VSS to suppress noise on VRef. MT88E41 MT88E41 Applications The circuit shown in Figure 6 illustrates the use of the MT88E41 MT88E41 device in a typical FSK receiver system. Bellcore Special Report SR-TSV-002476 SR-TSV-002476 specifies that the FSK receiver should be able to receive FSK signal levels as follows: Received Signal Level at 1200Hz: -32dBm to -12dBm Received Signal Level at 2200Hz: -36dBm to -12dBm This condition can be attained by choosing suitable values of R1 and R2. The MT88E41 MT88E41 configured in a unity gain mode as shown in Fig. 6 meets the above level requirements. For applications requiring detection of lower FSK signal level, the input op amp may be configured to provide adequate gain. VDD MT88E41 MT88E41 C1 IN + GS R2 IC2 IC1 Notes: R1, R2 = 100 k 1% R3, R4 = 100 k 10% C1, C2, C3 = 0.1µF 20% X-tal = 3.579545 MHz DR DATA VSS R4 CD OSC1 R3 PWDN OSC2 X-tal VRef CAP C2 C3 VDD IN - R1 DCLK To Controller Figure 6 - Application Circuit (Single-Ended Input) 5-25 MT88E41 MT88E41 Absolute Maximum Ratings* - Voltages are with respect to VSS unless otherwise stated. Parameter Symbol Min Max Units 1 DC Power Supply Voltage VDD to VSS VDD -0.3 6 V 2 Voltage on any pin VP -0.3 VDD+0.3 V 3 Current at any pin (except VDD and VSS) I I/O ±10 mA 4 Storage Temperature TST +150 °C 5 Package Power Dissipation PD 500 mW -65 * Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. Recommended Operating Conditions - Voltages are with respect to ground (VSS) unless otherwise stated Characteristics Sym Min 1 DC Power Supply Voltage VDD 2.7 2 Clock Frequency fOSC 3 Tolerance on Clock Frequency fc 4 Operating Temperature Typ Max Units 5.5 Test Conditions V MHz 3.579545 ±0.1 % +85 °C -40 DC Electrical Characteristics Characteristics 1 2 3 4 S U P P L Y Sym Standby Supply Current VDD=2.7V VDD=5.5V IDDQ Operating Supply Current VDD=2.7V VDD=5.5V Min Typ* Max Units 7 15 14 28 µA µA IDD 1 3 2 5 mA mA 0.4 Test Conditions PWDN=VDD PWDN=VSS DR CD 5 Low Level Output Voltage High Level Output Voltage VOL VOH VDD-0.4 V V IOL=2.5mA IOH=0.8mA Sink Current IOL 2.5 mA VOL=0.4V Schmitt Input High Threshold Schmitt Input Low Threshold DATA DCLK VT+ VT- 0.48*VDD 0.28*VDD VHYS 0.2 0.68*VDD 0.48*VDD V V PWDN 6 Schmitt Hysterisis 7 Input Current 8 10 µA VSS VIN VDD 0.5VDD + 0.05 V No Load 2 k IIN Output Voltage VRef Output Resistance RRef VRef 9 V 0.5VDD - 0.05 DC Electrical Characteristics are over recommended operating conditions unless otherwise stated. * Typical figures are at 25°C and are for design aid only. 5-26 MT88E41 MT88E41 Electrical Characteristics - Gain Setting Amplifier Characteristics Sym Min Typ Max Units 1 Test Conditions µA VSS VIN VDD 1 Input Leakage Current IIN 2 Input Resistance Rin 3 Input Offset Voltage VOS 4 Power Supply Rejection Ratio PSRR 30 40 dB 1kHz ripple on VDD 5 Common Mode Rejection CMRR 30 40 dB VCMmin VIN VCMmax 6 DC Open Loop Voltage Gain AVOL 30 32 dB 7 Unity Gain Bandwidth fC .2 0.3 MHz 8 Output Voltage Swing VO 0.5 9 Maximum Capacitive Load (GS) CL 5 M 25 mV RL VCM 1.0 pF 50 11 Common Mode Range Voltage Load 50k Vpp 100 10 Maximum Resistive Load (GS) VDD-0.5 k VDD-1.0 V Electrical characteristics are over recommended operating conditions, unless otherwise stated. Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. AC Electrical Characteristics - FSK Detection Characteristics Sym Min Typ Max Units Notes* -9 275 dBm mV 1, 2, 3 1, 2, 3 7 1 Input Detection Level -36 12.3 2 Input Baud Rate 1188 1200 1212 baud 3 Input Frequency Detection Bell 202 1 (Mark) Bell 202 0 (Space) 1188 2178 1200 2200 1212 2222 Hz Hz }7 BELL 202 Frequencies Hz Hz }7 CCITT V.23 Frequencies dB 2, 3, 4, 5 CCITT V.23 1 (Mark) CCITT V.23 0 (Space) 4 Input Noise Tolerance 20 log( signal) noise 1280.5 1300 1319.5 2068.5 2100 2131.5 SNR 20 AC Electrical Characteristics are over recommended operating conditions, unless otherwise stated. Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. 5-27 MT88E41 MT88E41 AC Electrical Characteristics - Timing Characteristics 1 2 CD 5 6 Min Typ Max Units Power-up time tPU 35 50 Power-down time tPD 100 1000 µs tIAL 25 ms Input FSK to CD high delay tIAH Rate 8 11 ms 8 Hysteresis DATA Notes* ms Input FSK to CD low delay PWDN OSC1 3 4 Sym ms 1188 1200 1212 bps 1 5 ms 7 Input FSK to DATA delay 8 Rise time tR 200 ns 8 Fall time tF 200 ns 8 9 DATA DCLK tIDD 6,12 DATA to DCLK delay tDCD 6 416 µs 6, 7, 10 11 DCLK to DATA delay tCDD 6 416 µs 6, 7, 10 12 Frequency 1200 1202.8 1205 Hz 7 10 13 15 16 17 DR 18 415 416 417 µs 7 tCL 415 416 417 µs 7 DCLK to DR delay tCRD 415 416 417 µs 7 tRR 10 µs 9 Fall time tFF 200 ns 9 Low time DCLK DR tCH Rise time 14 High time Low time DCLK tRL 417 µs 7 415 416 AC Electrical Characteristics are over recommended operating conditions unless otherwise stated. Typical figures are at 25°C and are for design aid only, not guaranteed and not subject to production testing. *Notes: 1. dBm=decibels above or below a reference power of 1mW into 600. 2. Using unity gain test circuit shown in Figure 6. 3. Mark and Space frequencies have the same amplitude. 4. Band limited random noise (200-3200Hz). 5. Referenced to the minimum input detection level. 6. FSK input data at 1200 ±12 baud. 7. OSC1 at 3.579545 MHz ±0.2%. 8. 10k to VSS, 50pF to VSS. 9. 10k to VDD, 50pF to VSS. 10. Function of signal condition. 11. The device will stop functioning within this time, but more time may be required to reach I DDQ. 12. For a repeating mark space sequence, the data stream will typically have equal 1 and 0 bit durations. tDCD tCDD tR tF DATA DCLK tCL tR tCH tF Figure 7 - DATA and DCLK Output Timing 5-28 MT88E41 MT88E41 tRR tFF DR tRL Figure 8 - DR Output Timing channel seizure 2 sec TIP/RING checksum Mark state Input FSK Second Ringing First Ringing 500ms (min) Data 200ms (min) PWDN tPU tPD OSC2 CD * tIAL tIAH DATA High (Input Idle) High (Input Idle) DCLK DR * * with external pull-up resistor Figure 9 - Input and Output Timing (Bellcore CND Service) 5-29 MT88E41 MT88E41 start stop start stop TIP/RING b7 1 0 b0 b1 b2 b3 b4 b5 b6 b7 1 0 start stop b0 b1 b2 b3 b4 b5 b6 b7 1 0 b0 b1 b2 tIDD start DATA start b0 b1 b2 b3 b4 b5 b6 b7 b7 stop start b0 b1 b2 b3 b4 b5 b6 b7 stop DCLK tCRD DR * * with external pull-up resistor Figure 10 - Serial Data Interface Timing 5-30 b0 b1 b2 stop Package Outlines 3 2 1 E1 E n-2 n-1 n D A2 A L C eA b2 e eC eB b Notes: D1 1) Not to scale 2) Dimensions in inches 3) (Dimensions in millimeters) Plastic Dual-In-Line Packages (PDIP) - E Suffix 8-Pin 18-Pin 20-Pin Plastic DIM 16-Pin Plastic Plastic Plastic Min A Max Min 0.210 (5.33) Max Min 0.210 (5.33) Max Min 0.210 (5.33) Max 0.210 (5.33) A2 0.115 (2.92) 0.195 (4.95) 0.115 (2.92) 0.195 (4.95) 0.115 (2.92) 0.195 (4.95) 0.115 (2.92) 0.195 (4.95) b 0.014 (0.356) 0.022 (0.558) 0.014 (0.356) 0.022 (0.558) 0.014 (0.356) 0.022 (0.558) 0.014 (0.356) 0.022 (0.558) b2 0.045 (1.14) 0.070 (1.77) 0.045 (1.14) 0.070 (1.77) 0.045 (1.14) 0.070 (1.77) 0.045 (1.14) 0.070 (1.77) C 0.008 (0.203) 0.014 (0.356) 0.008 (0.203) 0.014(0.356) 0.008 (0.203) 0.014 (0.356) 0.008 (0.203) 0.014 (0.356) D 0.355 (9.02) 0.400 (10.16) 0.780 (19.81) 0.800 (20.32) 0.880 (22.35) 0.920 (23.37) 0.980 (24.89) 1.060 (26.9) D1 0.005 (0.13) E 0.300 (7.62) 0.325 (8.26) 0.300 (7.62) 0.325 (8.26) 0.300 (7.62) 0.325 (8.26) 0.300 (7.62) 0.325 (8.26) E1 0.240 (6.10) 0.280 (7.11) 0.240 (6.10) 0.280 (7.11) 0.240 (6.10) 0.280 (7.11) 0.240 (6.10) 0.280 (7.11) 0.005 (0.13) 0.005 (0.13) 0.005 (0.13) e 0.100 BSC (2.54) 0.100 BSC (2.54) 0.100 BSC (2.54) 0.100 BSC (2.54) eA 0.300 BSC (7.62) 0.300 BSC (7.62) 0.300 BSC (7.62) 0.300 BSC (7.62) L 0.115 (2.92) eB eC 0.150 (3.81) 0.115 (2.92) 0.430 (10.92) 0 0.060 (1.52) 0.150 (3.81) 0.430 (10.92) 0 0.060 (1.52) NOTE: Controlling dimensions in parenthesis ( ) are in millimeters. General-8 0.115 (2.92) 0.150 (3.81) 0.115 (2.92) 0.430 (10.92) 0 0.060 (1.52) 0.150 (3.81) 0.430 (10.92) 0 0.060 (1.52) Package Outlines 3 2 1 E1 E n-2 n-1 n D A2 A L C eA b2 e eB b Notes: D1 1) Not to scale 2) Dimensions in inches 3) (Dimensions in millimeters) Plastic Dual-In-Line Packages (PDIP) - E Suffix 22-Pin 28-Pin 40-Pin Plastic DIM 24-Pin Plastic Plastic Plastic Min A Max Min 0.210 (5.33) Max Min 0.250 (6.35) Max Min 0.250 (6.35) Max 0.250 (6.35) A2 0.125 (3.18) 0.195 (4.95) 0.125 (3.18) 0.195 (4.95) 0.125 (3.18) 0.195 (4.95) 0.125 (3.18) 0.195 (4.95) b 0.014 (0.356) 0.022 (0.558) 0.014 (0.356) 0.022 (0.558) 0.014 (0.356) 0.022 (0.558) 0.014 (0.356) 0.022 (0.558) b2 0.045 (1.15) 0.070 (1.77) 0.030 (0.77) 0.070 (1.77) 0.030 (0.77) 0.070 (1.77) 0.030 (0.77) 0.070 (1.77) C 0.008 (0.204) 0.015 (0.381) 0.008 (0.204) 0.015 (0.381) 0.008 (0.204) 0.015 (0.381) 0.008 (0.204) 0.015 (0.381) D 1.050 (26.67) 1.120 (28.44) 1.150 (29.3) 1.290 (32.7) 1.380 (35.1) 1.565 (39.7) 1.980 (50.3) 2.095 (53.2) D1 0.005 (0.13) E 0.390 (9.91) 0.005 (0.13) 0.430 (10.92) 0.380 (9.65) E1 0.670 (17.02) 0.485 (12.32) 0.580 (14.73) 0.005 (0.13) .330 (8.38) 0.246 (6.25) 0.330 (8.39) 0.600 (15.24) 0.290 (7.37) E E1 0.005 (0.13) 0.600 (15.24) 0.670 (17.02) 0.600 (15.24) 0.670 (17.02) 0.485 (12.32) 0.580 (14.73) 0.485 (12.32) 0.580 (14.73) 0.254 (6.45) e 0.100 BSC (2.54) 0.100 BSC (2.54) 0.100 BSC (2.54) 0.100 BSC (2.54) eA 0.400 BSC (10.16) 0.600 BSC (15.24) 0.600 BSC (15.24) 0.600 BSC (15.24) eA 0.300 BSC (7.62) eB L 0.430 (10.92) 0.115 (2.93) 0.160 (4.06) 0.115 (2.93) 0.200 (5.08) 15° Shaded areas for 300 Mil Body Width 24 PDIP only 15° 0.115 (2.93) 0.200 (5.08) 15° 0.115 (2.93) 0.200 (5.08) 15° Package Outlines Pin 1 E A C L H e D L 4 mils (lead coplanarity) Notes: 1) Not to scale 2) Dimensions in inches 3) (Dimensions in millimeters) 4) A & B Maximum dimensions include allowable mold flash A1 B DIM 16-Pin 18-Pin 20-Pin 24-Pin 28-Pin Min Max Min Max Min Max Min Max Min Max A 0.093 (2.35) 0.104 (2.65) 0.093 (2.35) 0.104 (2.65) 0.093 (2.35) 0.104 (2.65) 0.093 (2.35) 0.104 (2.65) 0.093 (2.35) 0.104 (2.65) A1 0.004 (0.10) 0.012 (0.30) 0.004 (0.10) 0.012 (0.30) 0.004 (0.10) 0.012 (0.30) 0.004 (0.10) 0.012 (0.30) 0.004 (0.10) 0.012 (0.30) B 0.013 (0.33) 0.020 (0.51) 0.013 (0.33) 0.030 (0.51) 0.013 (0.33) 0.020 (0.51) 0.013 (0.33) 0.020 (0.51) 0.013 (0.33) 0.020 (0.51) C 0.009 (0.231) 0.013 (0.318) 0.009 (0.231) 0.013 (0.318) 0.009 (0.231) 0.013 (0.318) 0.009 (0.231) 0.013 (0.318) 0.009 (0.231) 0.013 (0.318) D 0.398 (10.1) 0.413 (10.5) 0.447 (11.35) 0.4625 (11.75) 0.496 (12.60) 0.512 (13.00) 0.5985 (15.2) 0.614 (15.6) 0.697 (17.7) 0.7125 (18.1) E 0.291 (7.40) 0.299 (7.40) 0.291 (7.40) 0.299 (7.40) 0.291 (7.40) 0.299 (7.40) 0.291 (7.40) 0.299 (7.40) 0.291 (7.40) 0.299 (7.40) e 0.050 BSC (1.27 BSC) 0.050 BSC (1.27 BSC) 0.050 BSC (1.27 BSC) 0.050 BSC (1.27 BSC) 0.050 BSC (1.27 BSC) H 0.394 (10.00) 0.419 (10.65) 0.394 (10.00) 0.419 (10.65) 0.394 (10.00) 0.419 (10.65) 0.394 (10.00) 0.419 (10.65) 0.394 (10.00) 0.419 (10.65) L 0.016 (0.40) 0.050 (1.27) 0.016 (0.40) 0.050 (1.27) 0.016 (0.40) 0.050 (1.27) 0.016 (0.40) 0.050 (1.27) 0.016 (0.40) 0.050 (1.27) Lead SOIC Package - S Suffix NOTES: 1. Controlling dimensions in parenthesis ( ) are in millimeters. 2. Converted inch dimensions are not necessarily exact. General-7 Package Outlines Pin 1 E A C L H e Notes: 1) Not to scale 2) Dimensions in inches 3) (Dimensions in millimeters) 4) Ref. JEDEC Standard M0-150/M0118 M0-150/M0118 for 48 Pin 5) A & B Maximum dimensions include allowable mold flash D A2 A1 B 20-Pin 24-Pin 28-Pin 48-Pin Dim Min A1 0.0087 (0.22) Max - 0.079 (2) 0.002 (0.05) B Min 0.079 (2) A Max C 0.002 (0.05) 0.013 (0.33) 0.0087 (0.22) 0.008 (0.21) Min Max Min Max 0.079 (2) 0.095 (2.41) 0.110 (2.79) 0.008 (0.2) 0.016 (0.406) 0.008 (0.2) 0.0135 (0.342) 0.002 (0.05) 0.013 (0.33) 0.0087 (0.22) 0.008 (0.21) 0.013 (0.33) 0.008 (0.21) 0.010 (0.25) D 0.27 (6.9) 0.295 (7.5) 0.31 (7.9) 0.33 (8.5) 0.39 (9.9) 0.42 (10.5) 0.62 (15.75) 0.63 (16.00) E 0.2 (5.0) 0.22 (5.6) 0.2 (5.0) 0.22 (5.6) 0.2 (5.0) 0.22 (5.6) 0.291 (7.39) 0.299 (7.59) e 0.025 BSC (0.635 BSC) 0.025 BSC (0.635 BSC) 0.025 BSC (0.635 BSC) 0.025 BSC (0.635 BSC) A2 0.065 (1.65) 0.073 (1.85) 0.065 (1.65) 0.073 (1.85) 0.065 (1.65) 0.073 (1.85) 0.089 (2.26) 0.099 (2.52) H 0.29 (7.4) 0.32 (8.2) 0.29 (7.4) 0.32 (8.2) 0.29 (7.4) 0.32 (8.2) 0.395 (10.03) 0.42 (10.67) L 0.022 (0.55) 0.037 (0.95) 0.022 (0.55) 0.037 (0.95) 0.022 (0.55) 0.037 (0.95) 0.02 (0.51) 0.04 (1.02) Small Shrink Outline Package (SSOP) - N Suffix General-11 For more information about all Zarlink products visit our Web Site at www.zarlink.com Information relating to products and services furnished herein by Zarlink Semiconductor Inc. trading as Zarlink Semiconductor or its subsidiaries (collectively "Zarlink") is believed to be reliable. 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