MT16HTF12864H MT16HTF25664H PC2-3200 PC2-4200 PC2-5300 PC2-6400 MO-224 DDR2-800 - Datasheet Archive

 

Features DDR2 SDRAM SODIMM MT16HTF12864H ­ 1GB MT16HTF25664H ­ 2GB For component data sheets, refer to Micron's Web site:

 

1GB, 2GB (x64, DR) 200-Pin DDR2 SDRAM SODIMM Features DDR2 SDRAM SODIMM MT16HTF12864H MT16HTF12864H ­ 1GB MT16HTF25664H MT16HTF25664H ­ 2GB For component data sheets, refer to Micron's Web site: www.micron.com Features Figure 1: · 200-pin, small outline dual in-line memory module (SODIMM) · Fast data transfer rates: PC2-3200 PC2-3200, PC2-4200 PC2-4200, PC2-5300 PC2-5300, or PC2-6400 PC2-6400. · 1GB (128 Meg x 64), 2GB (256 Meg x 64) · VDD = VDDQ = +1.8V · VDDSPD = +1.7V to +3.6V · JEDEC standard 1.8V I/O (SSTL_18-compatible) · Differential data strobe (DQS, DQS#) option · 4n-bit prefetch architecture · Multiple internal device banks for concurrent operation · Programmable CAS# latency (CL) · Posted CAS# additive latency (AL) · WRITE latency = READ latency - 1 tCK · Programmable burst lengths: 4 or 8 · Adjustable data-output drive strength · 64ms, 8,192-cycle refresh · On-die termination (ODT) · Serial presence detect (SPD) with EEPROM · Gold edge contacts · Dual rank PCB height: 30mm (1.18in) 200-Pin SODIMM (MO-224 MO-224 R/C E) Options Marking Operating temperature1 Commercial (0°C TC +70°C) Industrial (­40°C TC +85°C) Package ­ 200-pin DIMM (Pb-free) · Frequency/CAS latency ­ 2.5ns @ CL = 5 (DDR2-800 DDR2-800) ­ 2.5ns @ CL = 6 (DDR2-800 DDR2-800) ­ 3ns @ CL = 5 (DDR2-667 DDR2-667) ­ 3.75ns @ CL = 4 (DDR2-533 DDR2-533) ­ 5.0ns @ CL = 3 (DDR2-400 DDR2-400)2 · PCB height ­ 30mm (1.18in) · · · · None I Y -80E -800 -667 -53E -40E Notes: 1. Contact Micron for industrial temperature module offerings. 2. Not recommended for new designs. Table 1: Key Timing Parameters Data Rate (MT/s) Speed Grade Industry Nomenclature CL = 6 CL = 5 CL = 4 CL = 3 (ns) tRP (ns) tRC (ns) -80E -800 -667 -53E -40E PC2-6400 PC2-6400 PC2-6400 PC2-6400 PC2-5300 PC2-5300 PC2-4200 PC2-4200 PC2-3200 PC2-3200 ­ 800 ­ ­ ­ 800 667 667 533 533 533 533 400 ­ ­ 400 400 400 12.5 15 15 15 15 12.5 15 15 15 15 55 55 55 55 55 PDF: 09005aef818e4054/Source: 09005aef818e40d2 HTF16C128 HTF16C128_256x64H.fm - Rev. C 6/07 EN 1 tRCD Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice. 1GB, 2GB (x64, DR) 200-Pin DDR2 SDRAM SODIMM Features Table 2: Addressing Parameter 1GB 8K 16K (A0­A13) 4 (BA0, BA1) 1KB 512Mb (64 Meg x 8) 1K (A0­A9) 2 (S0#, S1#) Refresh count Row address Device bank address Device page size per bank Device configuration Column address Module rank address Table 3: 2GB 8K 16K (A0­A13) 8 (BA0­BA2) 1KB 1Gb (128 Meg x 8) 1K (A0­A9) 2 (S0#, S1#) Part Numbers and Timing Parameters ­ 1GB Modules Base device: MT47H64M8 MT47H64M8,1 512Mb DDR2 SDRAM Module Density Part Number2 MT16HTF12864HY-80E MT16HTF12864HY-80E_ MT16HTF12864HY-800 MT16HTF12864HY-800_ MT16HTF12864HY-667 MT16HTF12864HY-667_ MT16HTF12864HY-53E MT16HTF12864HY-53E_ MT16HTF12864HY-40E MT16HTF12864HY-40E_ Table 4: Configuration Module Bandwidth Memory Clock/ Data Rate Clock Cycles (CL-tRCD-tRP) 1GB 1GB 1GB 1GB 1GB 128 Meg x 64 128 Meg x 64 128 Meg x 64 128 Meg x 64 128 Meg x 64 6.4 GB/s 6.4 GB/s 5.3 GB/s 4.3 GB/s 3.2 GB/s 2.5ns/800 MT/s 2.5ns/800 MT/s 3.0ns/667 MT/s 3.75ns/533 MT/s 5.0ns/400 MT/s 5-5-5 6-6-6 5-5-5 4-4-4 3-3-3 Part Numbers and Timing Parameters ­ 2GB Modules Base device: MT47H128M8 MT47H128M8,1 1Gb DDR2 SDRAM Module Density Part Number2 MT16HTF25664HY-80E MT16HTF25664HY-80E_ MT16HTF25664HY-800 MT16HTF25664HY-800_ MT16HTF25664HY-667 MT16HTF25664HY-667_ MT16HTF25664HY-53E MT16HTF25664HY-53E_ MT16HTF25664HY-40E MT16HTF25664HY-40E_ Notes: PDF: 09005aef818e4054/Source: 09005aef818e40d2 HTF16C128 HTF16C128_256x64H.fm - Rev. C 6/07 EN Configuration Module Bandwidth Memory Clock/ Data Rate Clock Cycles (CL-tRCD-tRP) 2GB 2GB 2GB 2GB 2GB 256 Meg x 64 256 Meg x 64 256 Meg x 64 256 Meg x 64 256 Meg x 64 6.4 GB/s 6.4 GB/s 5.3 GB/s 4.3 GB/s 3.2 GB/s 2.5ns/800 MT/s 2.5ns/800 MT/s 3.0ns/667 MT/s 3.75ns/533 MT/s 5.0ns/400 MT/s 5-5-5 6-6-6 5-5-5 4-4-4 3-3-3 1. Data sheets for the base devices can be found on Micron's Web site. 2. All part numbers end with a two-place code (not shown) designating component and PCB revisions. Consult factory for current revision codes. Example: MT16HTF12864HY-40ED3 MT16HTF12864HY-40ED3. 2 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved. 1GB, 2GB (x64, DR) 200-Pin DDR2 SDRAM SODIMM Module Pin Assignments and Descriptions Module Pin Assignments and Descriptions Table 5: Pin Assignments 200-Pin SODIMM Front 200-Pin SODIMM Back Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 VREF VSS DQ0 DQ1 VSS DQS0# DQS0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1# DQS1 VSS DQ10 DQ11 VSS VSS DQ16 DQ17 VSS DQS2# 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 851 87 89 91 93 95 97 99 DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DM3 NC VSS DQ26 DQ27 VSS CKE0 VDD NC NC/BA2 VDD A12 A9 A8 VDD A5 A3 Notes: PDF: 09005aef818e4054/Source: 09005aef818e40d2 HTF16C128 HTF16C128_256x64H.fm - Rev. C 6/07 EN 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 A1 VDD A10 BA0 WE# VDD CAS# S1# VDD ODT1 VSS DQ32 DQ33 VSS DQS4# DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DM5 VSS 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 DQ42 DQ43 VSS DQ48 DQ49 VSS NC VSS DQS6# DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DM7 VSS DQ58 DQ59 VSS SDA SCL VDDSPD 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 VSS DQ4 DQ5 VSS DM0 VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1 VSS CK0 CK0# VSS DQ14 DQ15 VSS VSS DQ20 DQ21 VSS NC 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 DM2 VSS DQ22 DQ23 VSS DQ28 DQ29 VSS DQS3# DQS3 VSS DQ30 DQ31 VSS CKE1 VDD NC NC VDD A11 A7 A6 VDD A4 A2 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 A0 VDD BA1 RAS# S0# VDD ODT0 A13 VDD NC VSS DQ36 DQ37 VSS DM4 VSS DQ38 DQ39 VSS DQ44 DQ45 VSS DQS5# DQS5 VSS 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 DQ46 DQ47 VSS DQ52 DQ53 VSS CK1 CK1# VSS DM6 VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DQS7# DQS7 VSS DQ62 DQ63 VSS SA0 SA1 1. Pin 85 is NC for 1GB and BA2 for 2GB. 3 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved. 1GB, 2GB (x64, DR) 200-Pin DDR2 SDRAM SODIMM Module Pin Assignments and Descriptions Table 6: Pin Descriptions Symbol Type Description ODT0, ODT1 Input On-die termination: ODT (registered HIGH) enables termination resistance internal to the (SSTL_18) DDR2 SDRAM. When enabled, ODT is only applied to each of the following pins: DQ, DQS, DQS#, and DM. The ODT input will be ignored if disabled via the LOAD MODE command. CK0, CK0# Input Clock: CK and CK# are differential clock inputs. All address and control input signals are CK1, CK1# (SSTL_18) sampled on the crossing of the positive edge of CK and the negative edge of CK#. Output data (DQs and DQS/DQS#) is referenced to the crossings of CK and CK#. CKE0, CKE1 Input Clock enable: CKE (registered HIGH) activates and CKE (registered LOW) deactivates clocking (SSTL_18) circuitry on the DDR2 SDRAM. S0#, S1# Input Chip select: S# enables (registered LOW) and disables (registered HIGH) the command decoder. (SSTL_18) All commands are masked when S# is registered HIGH. S# provides for external rank selection on systems with multiple ranks. S# is considered part of the command code. RAS#, CAS#, Input Command inputs: RAS#, CAS#, and WE# (along with S#) define the command being entered. WE# (SSTL_18) BA0­BA2 Input Bank address inputs: BA0­BA1/BA2 define to which device bank an ACTIVE, READ, WRITE, or (SSTL_18) PRECHARGE command is being applied. BA0­BA1/BA2 define which mode register, including MR, EMR, EMR(2), and EMR(3), is loaded during the LOAD MODE command. BA0, BA0 (1GB), BA0­BA2 (2GB) A0­A13 Input Address inputs: Provide the row address for ACTIVE commands and the column address and (SSTL_18) auto precharge bit (A10) for READ/WRITE commands, to select one location out of the memory array in the respective bank. A10 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one device bank (A10 LOW, device bank selected by BA0­BA1/BA2) or all device banks (A10 HIGH). The address inputs also provide the op-code during a LOAD MODE command. DM0­DM7 Input Input data mask: DM is an input mask signal for write data. Input data is masked when DM is (DQS9­DQS17 DQS17) (SSTL_18) sampled HIGH along with that input data during a WRITE access. DM is sampled on both edges of DQS. Although DM pins are input-only, the DM loading is designed to match that of DQ and DQS pins. If RDQS is disabled, DQS9­DQS17 DQS17 become DM0­DM8 and DQS9#­DQS17 DQS17# are not used. SCL Input Serial clock for presence-detect: SCL is used to synchronize the presence-detect data transfer (SSTL_18) to and from the module. SA0­SA1 Input Presence-detect address inputs: These pins are used to configure the presence-detect device. (SSTL_18) DQ0­DQ63 I/O Data input/output: Bidirectional data bus. (SSTL_18) DQS0­DQS7, I/O Data strobe: Output with read data, input with write data for source synchronous operation. DQS0#­DQS7# (SSTL_18) Edge-aligned with read data, center-aligned with write data. DQS# is only used when differential data strobe mode is enabled via the LOAD MODE command. SDA I/O Serial presence-detect data: SDA is a bidirectional pin used to transfer addresses and data (SSTL_18) into and out of the presence-detect portion of the module. Supply Power supply: +1.8V ±0.1V. VDD Supply SSTL_18 reference voltage. VDD/2. VREF Supply Ground. VSS Supply Serial EEPROM positive power supply: +1.7V to +3.6V. VDDSPD NC ­ No connect: These pins should be left unconnected. PDF: 09005aef818e4054/Source: 09005aef818e40d2 HTF16C128 HTF16C128_256x64H.fm - Rev. C 6/07 EN 4 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved. 1GB, 2GB (x64, DR) 200-Pin DDR2 SDRAM SODIMM Functional Block Diagram Functional Block Diagram Figure 2: Functional Block Diagram S1# S0# DQS0# DQS0 DM0 DQS4# DQS4 DM4 DM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ DQ DQ DQ DQ DQ DQ DQ CS# DQS DQS# U2 DM DQ DQ DQ DQ DQ DQ DQ DQ CS# DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 U14 DQS1# DQS1 DM1 DQ DQ DQ DQ DQ DQ DQ DQ CS# DQS DQS# U6 DM DQ DQ DQ DQ DQ DQ DQ DQ CS# DQS DQS# DM DQ DQ DQ DQ DQ DQ DQ DQ CS# DQS DQS# U12 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 U18 DQ DQ DQ DQ DQ DQ DQ DQ CS# DQS DQS# DM DQ DQ DQ DQ DQ DQ DQ DQ U8 CS# DQS DQS# U16 DQS6# DQS6 DM6 DM DQ DQ DQ DQ DQ DQ DQ DQ CS# DQS DQS# U3 DM DQ DQ DQ DQ DQ DQ DQ DQ CS# DM DQS DQS# DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 U13 DQS3# DQS3 DM3 DQ DQ DQ DQ DQ DQ DQ DQ CS# DQS DQS# DM DQ DQ DQ DQ DQ DQ DQ DQ U5 CS# DQS DQS# U11 DQS7# DQS7 DM7 DM DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 CS# U4 DM DQS DQS# DQS2# DQS2 DM2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ DQ DQ DQ DQ DQ DQ DQ DQS5# DQS5 DM5 DM DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DM DQS DQS# DQ DQ DQ DQ DQ DQ DQ DQ BA0­BA1/BA2 A0­A13 RAS# CAS# WE# CKE0 CKE1 ODT0 ODT1 CS# DQS DQS# U7 DM DQ DQ DQ DQ DQ DQ DQ DQ BA0­BA1/BA2: DDR2 SDRAM A0­A13: DDR2 SDRAM RAS#: DDR2 SDRAM CAS#: DDR2 SDRAM WE#: DDR2 SDRAM CKE0: Rank 0 CKE1: Rank 1 ODT0: Rank 0 ODT1: Rank 1 CS# DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 U17 SCL U1 SPD EEPROM WP A0 A1 DQ DQ DQ DQ DQ DQ DQ DQ CS# VDDSPD DQS DQS# SDA DM DQ DQ DQ DQ DQ DQ DQ DQ U9 CS# DQS DQS# U15 Rank 0 = U2­U9 Rank 1 = U11­U18 A2 SA0 SA1 VSS CK0 CK0# U2, U3, U6, U7 U13, U14, U17, U18 CK1 CK1# U4, U5, U8, U9 U11, U12, U15, U16 SPD EEPROM VDD DDR2 SDRAM VREF DDR2 SDRAM VSS PDF: 09005aef818e4054/Source: 09005aef818e40d2 HTF16C128 HTF16C128_256x64H.fm - Rev. C 6/07 EN DM DQS DQS# 5 DDR2 SDRAM, EEPROM Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved. 1GB, 2GB (x64, DR) 200-Pin DDR2 SDRAM SODIMM General Description General Description The MT16HTF12864H MT16HTF12864H and MT16HTF25664H MT16HTF25664H DDR2 SDRAM modules are high-speed, CMOS, dynamic random-access 1GB and 2GB memory modules organized in a x64 configuration. These DDR2 SDRAM modules use internally configured 4-bank (512Mb) or 8-bank (1Gb) DDR2 SDRAM devices. DDR2 SDRAM modules use double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 4n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the DDR2 SDRAM module effectively consists of a single 4n-bit-wide, one-clock-cycle data transfer at the internal DRAM core and four corresponding n-bit-wide, one-half-clock-cycle data transfers at the I/O pins. A bidirectional data strobe (DQS, DQS#) is transmitted externally, along with data, for use in data capture at the receiver. DQS is a strobe transmitted by the DDR2 SDRAM device during reads and by the memory controller during writes. DQS is edge-aligned with data for reads and center-aligned with data for writes. DDR2 SDRAM modules operate from a differential clock (CK and CK#); the crossing of CK going HIGH and CK# going LOW will be referred to as the positive edge of CK. Commands are registered at every positive edge of CK. Input data is registered on both edges of DQS, and output data is referenced to both edges of DQS, as well as to both edges of CK. Serial Presence-Detect Operation DDR2 SDRAM modules incorporate serial presence-detect (SPD). The SPD function is implemented using a 2,048-bit EEPROM. This nonvolatile storage device contains 256 bytes. The first 128 bytes are programmed by Micron to identify the module type and various SDRAM organizations and timing parameters. The remaining 128 bytes of storage are available for use by the customer. System READ/WRITE operations between the master (system logic) and the slave EEPROM device occur via a standard I2C bus using the DIMM's SCL (clock) and SDA (data) signals, together with SA (1:0), which provide four unique DIMM/EEPROM addresses. Write protect (WP) is tied to VSS on the module, permanently disabling hardware write protect. PDF: 09005aef818e4054/Source: 09005aef818e40d2 HTF16C128 HTF16C128_256x64H.fm - Rev. C 6/07 EN 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved. 1GB, 2GB (x64, DR) 200-Pin DDR2 SDRAM SODIMM Electrical Specifications Electrical Specifications Stresses greater than those listed in Table 7 may cause permanent damage to the module. This is a stress rating only, and functional operation of the module at these or any other conditions outside those indicated in the device data sheet are not implied. Exposure to absolute maximum rating conditions for extended periods may adversely affect reliability. Table 7: Absolute Maximum Ratings Symbol Parameter Min Max Units VDD VIN, VOUT II VDD supply voltage relative to VSS Voltage on any pin relative to VSS Address inputs, Input leakage current; Any input 0V VIN VDD; VREF input 0V VIN 0.95V (All other pins not under RAS#, CAS#, WE# test = 0V) S#, CKE, ODT, CK, CK# DM Output leakage current; 0V VOUT; DQs and ODT DQ, DQS, DQS# are disabled VREF leakage current; VREF = valid VREF level Module ambient operating temperature Commercial Industrial DDR2 SDRAM component case operating Commercial temperature2 Industrial ­1.0 ­0.5 ­80 +2.3 +2.3 +80 V V µA ­40 ­10 ­10 +40 +10 +10 µA ­32 0 ­40 0 ­40 +32 +70 +85 +85 +95 µA °C °C °C °C Ioz IVREF TA TC1 Notes: 1. The refresh rate is required to double when 85°C < TC 95°C. 2. For further information, refer to technical note TN-00-08 TN-00-08: Thermal Applications, available on Micron's Web site. Input Capacitance Micron encourages designers to simulate the performance of the module to achieve optimum values. Simulations are significantly more accurate and realistic than a gross estimation of module capacitance when inductance and delay parameters associated with trace lengths are used in simulations. JEDEC modules are currently designed using simulations to close timing budgets. AC Timing and Operating Conditions Recommended AC operating conditions are given in the DDR2 component data sheets. Component specifications are available on Micron's Web site. Module speed grades correlate with component speed grades, as shown in Table 8. Table 8: Module and Component Speed Grades Module Speed Grade Component Speed Grade -80E -800 -667 -53E -40E -25E -25 -3 -37E -53E PDF: 09005aef818e4054/Source: 09005aef818e40d2 HTF16C128 HTF16C128_256x64H.fm - Rev. C 6/07 EN 7 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved. 1GB, 2GB (x64, DR) 200-Pin DDR2 SDRAM SODIMM Electrical Specifications IDD Specifications Table 9: DDR2 IDD Specifications and Conditions ­ 1GB Values shown for MT47H64M8 MT47H64M8 DDR2 SDRAM only and are computed from values specified in the 512Mb (64 Meg x 8) component data sheet -80E/ -80E/ Symbol -800 -667 Parameter/Condition t t Operating one bank active-precharge current: CK = CK (IDD), RC = tRC (IDD), tRAS = tRAS MIN (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching Operating one bank active-read-precharge current: IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS MIN (IDD), tRCD = tRCD (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data pattern is same as IDD4W Precharge power-down current: All device banks idle; tCK = tCK (IDD); CKE is LOW; Other control and address bus inputs are stable; Data bus inputs are floating Precharge quiet standby current: All device banks idle; tCK = tCK (IDD); CKE is HIGH, S# is HIGH; Other control and address bus inputs are stable; Data bus inputs are floating Precharge standby current: All device banks idle; tCK = tCK (IDD); CKE is HIGH, S# is HIGH; Other control and address bus inputs are switching; Data bus inputs are switching Active power-down current: All device banks open; Fast PDN exit tCK = tCK (IDD); CKE is LOW; Other control and address bus MR[12] = 0 inputs are stable; Data bus inputs are floating Slow PDN exit MR[12] = 1 tCK = tCK (IDD), Active standby current: All device banks open; tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Other control and address bus inputs are switching; Data bus inputs are switching Operating burst write current: All device banks open; continuous burst writes; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching Operating burst read current: All device banks open; continuous burst reads; IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), t RAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching Burst refresh current: tCK = tCK (IDD); REFRESH command at every t RFC (IDD) interval; CKE is HIGH, S# is HIGH between valid commands; Other control and address bus inputs are switching; Data bus inputs are switching Self refresh current: CK and CK# at 0V; CKE 0.2V; Other control and address bus inputs are floating; Data bus inputs are floating Operating bank interleave read current: All device banks interleaving reads; IOUT = 0mA; BL = 4, CL = CL (IDD), AL = tRCD (IDD) - 1 × tCK (IDD); tCK = tCK (IDD), tRC = tRC (IDD), tRRD = tRRD (IDD), tRCD = tRCD (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are stable during deselects; Data bus inputs are switching -53E -40E Units 776 696 696 mA 976 896 816 776 mA IDD2P2 112 112 112 112 mA IDD2Q2 800 720 640 560 mA IDD2N2 880 800 720 640 mA IDD3P2 640 560 480 400 mA 192 192 192 192 mA 880 720 mA 1 IDD0 856 IDD11 IDD11 t Notes: PDF: 09005aef818e4054/Source: 09005aef818e40d2 HTF16C128 HTF16C128_256x64H.fm - Rev. C 6/07 EN IDD3N2 1,120 1,040 IDD4W1 1,616 1,416 1,176 976 mA IDD4R1 1,696 1,496 1,216 976 mA IDD52 IDD52 IDD62 IDD62 IDD71 IDD71 3,680 2,880 2,720 2,640 112 112 112 112 2,456 1,976 1,856 1,816 mA mA mA 1. Value calculated as one module rank in this operating condition; all other module ranks in IDD2P (CKE LOW) mode. 2. Value calculated reflects all module ranks in this operating condition. 8 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved. 1GB, 2GB (x64, DR) 200-Pin DDR2 SDRAM SODIMM Electrical Specifications Table 10: DDR2 IDD Specifications and Conditions ­ 2GB Values shown for MT47H128M8 MT47H128M8 DDR2 SDRAM only and are computed from values specified in the 1Gb (128 Meg x 8) component data sheet -80E/ -80E/ Symbol -800 -667 Parameter/Condition t t Operating one bank active-precharge current: CK = CK (IDD), RC = tRC (IDD), tRAS = tRAS MIN (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching Operating one bank active-read-precharge current: IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS MIN (IDD), t RCD = tRCD (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data pattern is same as IDD4W Precharge power-down current: All device banks idle; tCK = tCK (IDD); CKE is LOW; Other control and address bus inputs are stable; Data bus inputs are floating Precharge quiet standby current: All device banks idle; tCK = tCK (IDD); CKE is HIGH, S# is HIGH; Other control and address bus inputs are stable; Data bus inputs are floating Precharge standby current: All device banks idle; tCK = tCK (IDD); CKE is HIGH, S# is HIGH; Other control and address bus inputs are switching; Data bus inputs are switching Active power-down current: All device banks open; Fast PDN exit tCK = tCK (IDD); CKE is LOW; Other control and address bus MR[12] = 0 inputs are stable; Data bus inputs are floating Slow PDN exit MR[12] = 1 tCK = tCK (IDD), Active standby current: All device banks open; tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Other control and address bus inputs are switching; Data bus inputs are switching Operating burst write current: All device banks open; continuous burst writes; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching Operating burst read current: All device banks open; continuous burst reads; IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching Burst refresh current: tCK = tCK (IDD); REFRESH command at every t RFC (IDD) interval; CKE is HIGH, S# is HIGH between valid commands; Other control and address bus inputs are switching; Data bus inputs are switching Self refresh current: CK and CK# at 0V; CKE 0.2V; Other control and address bus inputs are floating; Data bus inputs are floating Operating bank interleave read current: All device banks interleaving reads; IOUT = 0mA; BL = 4, CL = CL (IDD), AL = tRCD (IDD) - 1 × tCK (IDD); tCK = tCK (IDD), tRC = tRC (IDD), tRRD = tRRD (IDD), tRCD = tRCD (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are stable during deselects; Data bus inputs are switching -53E -40E Units 736 616 616 mA 936 856 816 776 mA IDD2P2 112 112 112 112 mA IDD2Q2 800 640 640 560 mA IDD2N2 800 640 640 560 mA IDD3P2 640 480 480 480 mA 160 160 160 160 mA 960 880 720 640 mA IDD4W1 1,336 1,136 1,056 896 mA IDD4R1 896 mA 1 776 IDD11 IDD11 IDD0 t Notes: PDF: 09005aef818e4054/Source: 09005aef818e40d2 HTF16C128 HTF16C128_256x64H.fm - Rev. C 6/07 EN IDD3N2 IDD52 IDD52 IDD62 IDD62 IDD71 IDD71 1,336 1,136 1,056 3,760 3,440 3,360 3,280 112 112 112 112 2,736 2,296 2,216 2,136 mA mA mA 1. Value calculated as one module rank in this operating condition; all other module ranks in IDD2P (CKE LOW) mode. 2. Value calculated reflects all module ranks in this operating condition. 9 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved. 1GB, 2GB (x64, DR) 200-Pin DDR2 SDRAM SODIMM Serial Presence-Detect Serial Presence-Detect Table 11: Serial Presence-Detect EEPROM DC Operating Conditions All voltages referenced to VSS Parameter/Condition Symbol Supply voltage Input high voltage: Logic 1; All inputs Input low voltage: Logic 0; All inputs Output low voltage: IOUT = 3mA Input leakage current: VIN = GND to VDD Output leakage current: VOUT = GND to VDD Standby current Power supply current, READ: SCL clock frequency = 100 kHz Power supply current, WRITE: SCL clock frequency = 100 kHz Table 12: Min Max Units VDDSPD VIH VIL VOL ILI ILO ISB ICCR ICCW 1.7 VDDSPD × 0.7 ­0.6 ­ 0.10 0.05 1.6 0.4 2 3.6 VDDSPD + 0.5 VDDSPD × 0.3 0.4 3 3 4 1 3 V V V V µA µA µA mA mA Serial Presence-Detect EEPROM AC Operating Conditions All voltages referenced to VSS Parameter/Condition Symbol SCL LOW to SDA data-out valid Time the bus must be free before a new transition can start Data-out hold time SDA and SCL fall time Data-in hold time Start condition hold time Clock HIGH period Noise suppression time constant at SCL, SDA inputs Clock LOW period SDA and SCL rise time SCL clock frequency Data-in setup time Start condition setup time Stop condition setup time WRITE cycle time Notes: PDF: 09005aef818e4054/Source: 09005aef818e40d2 HTF16C128 HTF16C128_256x64H.fm - Rev. C 6/07 EN Min Max Units Notes tAA 0.2 1.3 200 ­ 0 0.6 0.6 ­ 1.3 ­ ­ 100 0.6 0.6 ­ 0.9 ­ ­ 300 ­ ­ ­ 50 ­ 0.3 400 ­ ­ ­ 10 µs µs ns ns µs µs µs ns µs µs kHz ns µs µs ms 1 tBUF tDH tF tHD:DAT tHD:STA tHIGH tI tLOW tR fSCL tSU:DAT tSU:STA t SU:STO tWRC 2 2 3 4 1. To avoid spurious start and stop conditions, a minimum delay is placed between SCL = 1 and the falling or rising edge of SDA. 2. This parameter is sampled. 3. For a restart condition, or following a WRITE cycle. 4. The SPD EEPROM WRITE cycle time (tWRC) is the time from a valid stop condition of a write sequence to the end of the EEPROM internal ERASE/PROGRAM cycle. During the WRITE cycle, the EEPROM bus interface circuit is disabled, SDA remains HIGH due to pull-up resistance, and the EEPROM does not respond to its slave address. 10 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved. 1GB, 2GB (x64, DR) 200-Pin DDR2 SDRAM SODIMM Serial Presence-Detect Table 13: Byte Serial Presence-Detect Matrix Description 0 1 2 3 4 5 6 7 8 9 Number of SPD bytes used by Micron Total Number of bytes in SPD device Fundamental memory type Number of row addresses on assembly Number of column addresses on assembly DIMM height and module ranks Module data width Reserved Module voltage interface levels SDRAM cycle time, tCK (CL = maximum value, see byte 18) 10 SDRAM access from clock,tAC (CL = maximum value, see byte 18) 11 12 13 14 15 16 17 18 Module configuration type Refresh rate/type SDRAM device width (primary SDRAM) Error-checking SDRAM data width Reserved Burst lengths supported Number of banks on SDRAM device CAS latencies supported 19 20 21 22 23 Module thickness DDR2 DIMM type SDRAM module attributes SDRAM device attributes: Weak driver (01) and 50 ODT (03) SDRAM cycle time, tCK, MAX CL - 1 24 SDRAM access from CK, tAC, MAX CL - 1 25 SDRAM cycle time, tCK, MAX CL - 2 26 SDRAM access from CK, tAC, MAX CL - 2 PDF: 09005aef818e4054/Source: 09005aef818e40d2 HTF16C128 HTF16C128_256x64H.fm - Rev. C 6/07 EN Entry (Version) 1GB 2GB 128 256 DDR2 SDRAM 14 10 30mm, dual rank 64 0 SSTL 1.8V -80E/-800 -80E/-800 -667 -53E -40E -80E/-800 -80E/-800 -667 -53E -40E Non-ECC 7.81µs/SELF 8 n/a 0 4, 8 4 or 8 -80E (5, 4) -800 (6, 5, 4) -667 (5, 4, 3) -53E/-40E -53E/-40E (4, 3) 80 08 08 0E 0A 61 40 00 05 25 30 3D 50 40 45 50 60 00 82 08 00 00 0C 04 30 70 38 18 01 04 00 03 01 3D 30 50 40 45 50 60 00 3D 50 00 00 40 45 00 80 08 08 0E 0A 61 40 00 05 25 30 3D 50 40 45 50 60 00 82 08 00 00 0C 08 30 70 38 18 01 04 00 03 01 3D 30 50 40 45 50 60 00 3D 50 00 00 40 45 00 SODIMM No PLL or Reg -800/-80E/-667 -800/-80E/-667 -53E/-40E -53E/-40E -80E/-667 -80E/-667 -800 -53E/-40E -53E/-40E -80E/-800 -80E/-800 -667 -53E -40E -80E -800 -667 -53E/-40E -53E/-40E -80E -800 -667 -53E/-40E -53E/-40E 11 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved. 1GB, 2GB (x64, DR) 200-Pin DDR2 SDRAM SODIMM Serial Presence-Detect Table 13: Byte Serial Presence-Detect Matrix (continued) Description tRP 27 MIN row precharge time, 28 29 MIN row active-to-row active, tRRD MIN RAS#-to-CAS# delay, tRCD 30 MIN active-to-active precharge time, tRAS 31 32 Module rank density Address and command setup time, tISb 33 Address and command hold time, tIHb 34 Data/data mask input setup time, tDSb 35 Data/data mask input hold time, tDHb 36 37 Write recovery time, tWR WRITE-to-READ command delay, tWTR 38 39 40 READ-to-PRECHARGE command delay, tRTP Memory analysis probe Extension for bytes 41 and 42 41 MIN active-to-active/refresh time, tRC1 42 Entry (Version) 1GB 2GB -80E -800/-667-53E/-40E -800/-667-53E/-40E 32 3C 1E 32 3C 2D 28 80 17 20 25 35 25 27 37 47 05 10 15 12 17 22 27 3C 1E 28 1E 00 30 00 39 3C 37 69 32 3C 1E 32 3C 2D 28 01 17 20 25 35 25 27 37 47 05 10 15 12 17 22 27 3C 1E 28 1E 00 36 06 39 3C 37 7F 80 14 18 1E 23 1E 22 28 2D 00 00 12 80 14 18 1E 23 1E 22 28 2D 00 00 12 MIN AUTO REFRESH to ACTIVE/ AUTO REFRESH command period, tRFC SDRAM device MAX cycle time, tCK (MAX) SDRAM device MAX DQS-DQ skew time, tDQSQ 43 44 45 46 47­61 62 -80E -800/-667-53E/-40E -800/-667-53E/-40E -800/-80E/-667/-53E -800/-80E/-667/-53E -40E 512MB 512MB, 1GB -800/-80E -800/-80E -667 -53E -40E -800/-80E -800/-80E -667 -53E -40E -800/-80E -800/-80E -667/-53E -667/-53E -40E -800-80E -800-80E -667 -53E -40E -80E/-667/-53E -80E/-667/-53E -800/-40E -800/-40E -80E -800/-667/-53E/-40E -800/-667/-53E/-40E -80E -800/-667/-53E -800/-667/-53E -40E -800/-80E -800/-80E -667 -53E -40E -800/-80E -800/-80E -667 -53E -40E n/a SDRAM device MAX read data hold skew factor, t QHS PLL relock time Optional features, not supported SPD revision PDF: 09005aef818e4054/Source: 09005aef818e40d2 HTF16C128 HTF16C128_256x64H.fm - Rev. C 6/07 EN Release 1.2 12 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved. 1GB, 2GB (x64, DR) 200-Pin DDR2 SDRAM SODIMM Serial Presence-Detect Table 13: Serial Presence-Detect Matrix (continued) Byte 63 64 65­71 72 73­90 91 92 93 94 95­98 99­127 128­255 Description Entry (Version) 1GB 2GB -80E -800 -667 -53E -40E MICRON (continued) 1­12 ­ 1­9 0 ­ ­ ­ 92 33 4E F9 60 2C 00 01­0C Variable data 01­09 00 Variable data Variable data Variable data 00 FF 33 D4 EF 9A 01 2C 00 01­0C Variable data 01­09 00 Variable data Variable data Variable data 00 FF Checksum for bytes 0­62 Manufacturer's JEDEC ID code Manufacturer's JEDEC ID code Manufacturing location Module part number (ASCII) PCB identification code Identification code (continued) Year of manufacture in BCD Week of manufacture in BCD Module serial number Reserved for manufacturer-specific data Reserved for customer-specific data Notes: PDF: 09005aef818e4054/Source: 09005aef818e40d2 HTF16C128 HTF16C128_256x64H.fm - Rev. C 6/07 EN 1. The tRC SPD values shown are JEDEC DDR2 device specification values. The actual Micron DDR2 device specification is tRC = 55ns for all speed grades. 13 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved. 1GB, 2GB (x64, DR) 200-Pin DDR2 SDRAM SODIMM Module Dimensions Module Dimensions Figure 3: 200-Pin DDR2 SODIMM Front view 3.80 (0.150) MAX 67.75 (2.667) 67.45 (2.656) 2.0 (0.079) R (2X) U1 U2 U3 U4 U5 30.15 (1.187) 29.85 (1.175) 1.80 (0.071) (2X) U6 U7 U8 U9 20.0 (0.787) TYP 6.00 (0.236) TYP Pin 1 16.25 (0.64) TYP 2.00 (0.079) TYP 0.0197 (0.50) R 0.45 (0.018) TYP 0.60 (0.024) TYP 63.60 (2.504) TYP Pin 199 1.10 (0.043) 0.90 (0.035) Back view U11 U12 U13 U14 U15 U16 U17 U18 3.50 (0.138) TYP Pin 200 Notes: 4.2 (0.165) TYP Pin 2 47.4 (1.87) TYP 11.4 (0.45) TYP 1. All dimensions are in millimeters (inches); MAX/MIN or typical (TYP) where noted. 2. The dimensional diagram is for reference only. Refer to the MO document for complete design dimensions. ® 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 prodmktg@micron.com www.micron.com Customer Comment Line: 800-932-4992 Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. This data sheet contains minimum and maximum limits specified over the complete power supply and temperature range for production devices. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. PDF: 09005aef818e4054/Source: 09005aef818e40d2 HTF16C128 HTF16C128_256x64H.fm - Rev. C 6/07 EN 14 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved.